Pixel circuit, pixel driving method and display apparatus

Abstract

Provided in the present disclosure are a pixel circuit, a pixel driving method and a display apparatus. The pixel circuit comprises a drive circuit, a compensation control circuit, a first energy storage circuit, an on-off control circuit and a data write circuit. A display period comprises a write phase and a compensation phase. In the compensation phase, the compensation control circuit controls, under the control of a compensation control signal, a first node connect to a third node, and the on-off control circuit controls, under the control of an on-off control signal, the first node connect to a first end of the first energy storage circuit; and in the write phase, the data write circuit writes, under the control of a scan signal, a data voltage into a second end of the first energy storage circuit. By means of the present disclosure, data voltage writing and threshold voltage compensation can be separated, such that the threshold voltage compensation time is not limited by resolution and frequency, and thus high-frequency driving in large-sized panels can be realized.

Description

Pixel circuit, pixel driving method and display device

[0001] Cross-reference to Related Applications

[0002] This application claims priority to Chinese Patent Application No. 202410985406.3, filed on July 22, 2024, the contents of which are incorporated herein by reference in its entirety. TECHNICAL FIELD

[0003] The present disclosure relates to the technical field of display, and in particular, to a pixel circuit, a pixel driving method and a display device. BACKGROUND

[0004] With the improvement of product specifications, there is an urgent need for a circuit that can simultaneously solve the problem of the influence of high frequency and process fluctuation on picture quality. The related pixel circuit cannot separate threshold voltage compensation and data voltage writing, cannot make threshold voltage compensation time not limited by resolution and frequency, and cannot realize high-frequency driving under large size. SUMMARY

[0005] The main purpose of the present disclosure is to provide a pixel circuit, a pixel driving method and a display device, which solve the problem that the prior art cannot separate threshold voltage compensation and data voltage writing, cannot make threshold voltage compensation time not limited by resolution and frequency, and cannot realize high-frequency driving under large size.

[0006] In one aspect, the embodiments of the present disclosure provide a pixel circuit, comprising a driving circuit, a compensation control circuit, a first energy storage circuit, a on-off control circuit and a data writing circuit; a display period of the pixel circuit comprises a writing stage and a compensation stage;

[0007] The control end of the driving circuit is electrically connected with the first node, the first end of the driving circuit is electrically connected with the second node, and the second end of the driving circuit is electrically connected with the third node; the driving circuit is used for generating a driving current under the control of the potential of the first node;

[0008] The compensation control circuit is electrically connected with a compensation control line, the first node and the third node respectively, and is used for controlling the communication between the first node and the third node under the control of a compensation control signal provided by the compensation control line in the compensation stage;

[0009] The on-off control circuit is electrically connected with an on-off control line, the first node and the first end of the first energy storage circuit respectively, and is used for controlling the communication between the first node and the first end of the first energy storage circuit under the control of an on-off control signal provided by the on-off control line;

[0010] The data writing circuit is electrically connected with the scan end, the data line and the second end of the first energy storage circuit respectively, and is configured to write, under control of a scan signal provided by the scan end, a data voltage provided by the data line to the second end of the first energy storage circuit in the writing stage.

[0011] Optionally, the transistor included in the compensation control circuit is an oxide transistor.

[0012] Optionally, the pixel circuit further includes a first initialization circuit.

[0013] The first initialization circuit is electrically connected with an initial control line, a first reset voltage end and the second end of the first energy storage circuit respectively, and is configured to write, under control of an initial control signal provided by the initial control line, a first reset voltage provided by the first reset voltage end to the second end of the first energy storage circuit.

[0014] Optionally, the pixel circuit further includes a second initialization circuit.

[0015] The second initialization circuit is electrically connected with a first reset control line, a second reset voltage end and the first end of the first energy storage circuit respectively, and is configured to write, under control of a first reset control signal provided by the first reset control line, a second reset voltage provided by the second reset voltage end to the first end of the first energy storage circuit.

[0016] Optionally, the display cycle further includes a light emitting stage, which is arranged after the writing stage and the compensation stage.

[0017] The first initialization circuit is configured to write, under control of the initial control signal, the first reset voltage to the second end of the first energy storage circuit in the light emitting stage.

[0018] The on-off control circuit is configured to control the communication between the first node and the first end of the first energy storage circuit under control of the on-off control signal in the light emitting stage.

[0019] Optionally, the display cycle further includes an initialization stage, which is arranged before the writing stage and the compensation stage.

[0020] The first initialization circuit is configured to write, under control of the initial control signal, the first reset voltage to the second end of the first energy storage circuit in the initialization stage.

[0021] Optionally, the second initialization circuit is configured to write, under control of the first reset control signal, the second reset voltage to the first end of the first energy storage circuit in the writing stage.

[0022] The compensation control circuit is further configured to control, under control of the compensation control signal, communication between the first node and the third node during the writing stage.

[0023] 8. The pixel circuit of claim 4, wherein the transistor included in the compensation control circuit is an n-type transistor, the transistor included in the on-off control circuit is a p-type transistor, and the compensation control line and the on-off control line are the same control line; or,

[0024] the transistor included in the compensation control circuit is a p-type transistor, the transistor included in the on-off control circuit is an n-type transistor, and the compensation control line and the on-off control line are the same control line.

[0025] Optionally, the pixel circuit further comprises a light emitting element, a first light emitting control circuit, a second light emitting control circuit and a second energy storage circuit.

[0026] The first light emitting control circuit is electrically connected with a first light emitting control line, the third node and a first electrode of the light emitting element, respectively, and is configured to control, under control of a first light emitting control signal provided by the first light emitting control line, communication between the third node and the first electrode of the light emitting element.

[0027] The second light emitting control circuit is electrically connected with a second light emitting control line, a power voltage terminal and the second node, respectively, and is configured to control, under control of a second light emitting control signal provided by the second light emitting control line, communication between the power voltage terminal and the second node.

[0028] The second energy storage circuit is electrically connected with the first node, and is configured to maintain the potential of the first node.

[0029] A second electrode of the light emitting element is electrically connected with a first voltage terminal.

[0030] Optionally, the pixel circuit further comprises a third initialization circuit; the third initialization circuit is electrically connected with a second reset control line, the second node and a third initial voltage terminal, respectively, and is configured to write, under control of a second reset control signal provided by the second reset control line, a third initial voltage provided by the third initial voltage terminal into the second node; or,

[0031] The pixel circuit further comprises a fourth initialization circuit; the fourth initialization circuit is electrically connected with a second reset control line, a second initial voltage terminal and a first electrode of the light emitting element, respectively, and is configured to write, under control of a second reset control signal provided by the second reset control line, a second initial voltage provided by the second initial voltage terminal into the first electrode of the light emitting element; or,

[0032] The pixel circuit further comprises a fifth initialization circuit; the fifth initialization circuit is electrically connected with the first reset control line and the first initial voltage terminal respectively, and the fifth initialization circuit is further electrically connected with the third node or the first node, for writing the first initial voltage provided by the first initial voltage terminal into the third node or the first node under the control of the first reset control signal provided by the first reset control line.

[0033] Optionally, the driving circuit comprises a driving transistor, the compensation control circuit comprises a first transistor, the first energy storage circuit comprises a first capacitor, the on-off control circuit comprises a second transistor, and the data writing circuit comprises a third transistor.

[0034] The gate of the driving transistor is electrically connected with the first node, the first pole of the driving transistor is electrically connected with the second node, and the second pole of the driving transistor is electrically connected with the third node.

[0035] The gate of the first transistor is electrically connected with the compensation control line, the first pole of the first transistor is electrically connected with the first node, and the second pole of the first transistor is electrically connected with the third node.

[0036] The gate of the second transistor is electrically connected with the on-off control line, the first pole of the second transistor is electrically connected with the first node, and the second pole of the second transistor is electrically connected with the first end of the first capacitor.

[0037] The gate of the third transistor is electrically connected with the scanning terminal, the first pole of the third transistor is electrically connected with the data line, and the second pole of the third transistor is electrically connected with the second end of the first capacitor.

[0038] Optionally, the first initialization circuit comprises a fourth transistor.

[0039] The gate of the fourth transistor is electrically connected with the initial control line, the first pole of the fourth transistor is electrically connected with the first reset voltage terminal, and the second pole of the fourth transistor is electrically connected with the second end of the first energy storage circuit.

[0040] Optionally, the second initialization circuit comprises a fifth transistor.

[0041] The gate of the fifth transistor is electrically connected with the first reset control line, the first pole of the fifth transistor is electrically connected with the second reset voltage terminal, and the second pole of the fifth transistor is electrically connected with the first end of the first energy storage circuit.

[0042] Optionally, the first light-emitting control circuit comprises a sixth transistor, and the second light-emitting control circuit comprises a seventh transistor.

[0043] a gate of the sixth transistor is electrically connected with the first light-emitting control line, a first electrode of the sixth transistor is electrically connected with the third node, and a second electrode of the sixth transistor is electrically connected with the first electrode of the light-emitting element;

[0044] a gate of the seventh transistor is electrically connected with the second light-emitting control line, a first electrode of the seventh transistor is electrically connected with the power supply voltage terminal, and a second electrode of the seventh transistor is electrically connected with the second node.

[0045] Optionally, when the pixel circuit comprises a third initialization circuit, the third initialization circuit comprises an eighth transistor; a gate of the eighth transistor is electrically connected with the second reset control line, a first electrode of the eighth transistor is electrically connected with the second node, and a second electrode of the eighth transistor is electrically connected with the third initial voltage terminal.

[0046] When the pixel circuit comprises a fourth initialization circuit, the fourth initialization circuit comprises a ninth transistor; a gate of the ninth transistor is electrically connected with the second reset control line, a first electrode of the ninth transistor is electrically connected with the second initial voltage terminal, and a second electrode of the ninth transistor is electrically connected with the first electrode of the light-emitting element.

[0047] When the pixel circuit comprises a fifth initialization circuit, the fifth initialization circuit comprises a tenth transistor; a gate of the tenth transistor is electrically connected with the first reset control line, a first electrode of the tenth transistor is electrically connected with the first initial voltage terminal, and a second electrode of the tenth transistor is electrically connected with the third node or the first node.

[0048] In a second aspect, the embodiments of the present disclosure provide a pixel driving method applied to the pixel circuit described above, a display period comprising a writing stage, a compensation stage and a light-emitting stage; the light-emitting stage is arranged after the writing stage and the compensation stage; the pixel driving method comprises:

[0049] In the writing stage, the data writing circuit writes the data voltage provided by the data line into the second terminal of the first energy storage circuit under the control of the scanning signal;

[0050] In the compensation stage, the compensation control circuit controls the communication between the first node and the third node under the control of the compensation control signal;

[0051] In the light-emitting stage, the first initialization circuit writes the first reset voltage into the second terminal of the first energy storage circuit under the control of the initial control signal, and the on-off control circuit controls the communication between the first node and the first terminal of the first energy storage circuit under the control of the on-off control signal.

[0052] Optionally, the pixel circuit further comprises a second initialization circuit; and the pixel driving method further comprises:

[0053] In the writing stage, the second initialization circuit writes a second reset voltage to the first terminal of the first energy storage circuit under the control of a first reset control signal; and the compensation control circuit controls the communication between the first node and the third node under the control of the compensation control signal.

[0054] In a third aspect, the embodiments of the present disclosure provide a display device comprising the pixel circuit.

[0055] The embodiments of the present disclosure can separate the writing of the data voltage and the threshold voltage compensation, so that the threshold voltage compensation time is not limited by the resolution and the frequency, and high-frequency driving under large size can be achieved. BRIEF DESCRIPTION OF DRAWINGS

[0056] FIG. 1 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0057] FIG. 2 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0058] FIG. 3 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0059] FIG. 4 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0060] FIG. 5 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0061] FIG. 6 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0062] FIG. 7 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0063] FIG. 8 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0064] FIG. 9 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0065] FIG. 10A is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0066] FIG. 10B is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0067] FIG. 11 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0068] FIG. 12 is a timing diagram of the operation of the pixel circuit of FIG. 11 according to at least one embodiment of the present disclosure;

[0069] FIG. 13 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0070] FIG. 14 is a timing diagram of operation of at least one embodiment of the pixel circuit of FIG. 13 according to the present disclosure;

[0071] FIG. 15 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0072] FIG. 16 is a timing diagram of operation of at least one embodiment of the pixel circuit of FIG. 15 according to the present disclosure;

[0073] FIG. 17 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0074] FIG. 18 is a timing diagram of operation of at least one embodiment of the pixel circuit of FIG. 17 according to the present disclosure;

[0075] FIG. 19 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0076] FIG. 20 is a timing diagram of operation of at least one embodiment of the pixel circuit of FIG. 19 according to the present disclosure. DETAILED DESCRIPTION

[0077] The technical solutions in the embodiments of the present disclosure will be clearly and completely described below with reference to the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, rather than all the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by a person of ordinary skill in the art without creative work fall within the scope of protection of the present disclosure.

[0078] The transistors used in all the embodiments of the present disclosure can be thin film transistors or field effect transistors or other devices with the same characteristics. In the embodiments of the present disclosure, to distinguish the two poles of the transistor other than the gate, one pole is referred to as the first pole and the other pole is referred to as the second pole.

[0079] In actual operation, when the transistor is a thin film transistor or a field effect transistor, the first pole can be a drain and the second pole can be a source, or the first pole can be a source and the second pole can be a drain.

[0080] The pixel circuit according to the embodiments of the present disclosure includes a driving circuit, a compensation control circuit, a first energy storage circuit, a on-off control circuit and a data writing circuit; the display period of the pixel circuit includes a writing stage and a compensation stage;

[0081] The control end of the driving circuit is electrically connected with the first node, the first end of the driving circuit is electrically connected with the second node, the second end of the driving circuit is electrically connected with the third node, and the driving circuit is used to generate a driving current under the control of the potential of the first node.

[0082] The compensation control circuit is electrically connected with a compensation control line, the first node and the third node respectively, and is configured to, in a compensation phase, control the first node and the third node to be in communication under control of a compensation control signal provided by the compensation control line;

[0083] The on-off control circuit is electrically connected with an on-off control line, the first node and a first terminal of the first energy storage circuit respectively, and is configured to, under control of an on-off control signal provided by the on-off control line, control the first node and the first terminal of the first energy storage circuit to be in communication;

[0084] The data write-in circuit is electrically connected with a scan end, a data line and a second terminal of the first energy storage circuit respectively, and is configured to, in a write-in phase, write a data voltage provided by the data line into the second terminal of the first energy storage circuit under control of a scan signal provided by the scan end. In the working process of the pixel circuit, in a compensation phase, the compensation control circuit controls the first node and the third node to be in communication under control of a compensation control signal, so as to perform threshold voltage compensation; and in a write-in phase, the data write-in circuit writes a data voltage into the second terminal of the first energy storage circuit under control of a scan signal, so as to perform data voltage write-in. The pixel circuit can separate data voltage write-in and threshold voltage compensation, so that threshold voltage compensation time is not limited by resolution and frequency, and high-frequency driving under large size can be realized. The pixel circuit can be used in LTPO (low temperature poly-silicon oxide) technology, and product diversification demand can be realized through low-frequency driving. The pixel circuit can meet high and low frequency product demand, and realize 1Hz to 360Hz full frequency change.

[0085] In the working process of the pixel circuit, a display period can include a write-in phase, a compensation phase and a light-emitting phase.

[0086] In the write-in phase, the data write-in circuit writes a data voltage into the second terminal of the first energy storage circuit under control of a scan signal, and at this time, the data voltage is not written into the first node but written into the second terminal of the first energy storage circuit.

[0087] In the compensation phase, the compensation control circuit controls the first node and the third node to be in communication under control of the compensation control signal, so as to perform threshold voltage compensation.

[0088] In the light-emitting stage, the potential of the second end of the first energy storage circuit is reset to a first initial voltage, and the on-off control circuit controls the communication between the first node and the first end of the first energy storage circuit under the control of the on-off control signal, so that the first node is related to the data voltage, thereby enabling the data voltage to be written separately from the threshold voltage compensation, so that the threshold voltage compensation time is not limited by the resolution and the frequency, and high-frequency driving under large size can be realized.

[0089] As shown in FIG. 1, the pixel circuit according to the embodiment of the present disclosure includes a driving circuit 10, a compensation control circuit 11, a first energy storage circuit 12, an on-off control circuit 13 and a data writing circuit 14; the display period of the pixel circuit includes a writing stage and a compensation stage;

[0090] The control end of the driving circuit 10 is electrically connected with the first node N1, the first end of the driving circuit 10 is electrically connected with the second node N2, the second end of the driving circuit 10 is electrically connected with the third node N3, and the driving circuit 10 is used for generating a driving current under the control of the potential of the first node N1.

[0091] The compensation control circuit 11 is electrically connected with a compensation control line GT2, the first node N1 and the third node N3 respectively, and is used for controlling the communication between the first node N1 and the third node N3 under the control of a compensation control signal provided by the compensation control line GT2 in the compensation stage.

[0092] The on-off control circuit 13 is electrically connected with an on-off control line ST, the first node N1 and the first end of the first energy storage circuit 12 respectively, and is used for controlling the communication between the first node N1 and the first end of the first energy storage circuit 12 under the control of an on-off control signal provided by the on-off control line ST.

[0093] The data writing circuit 14 is electrically connected with a scanning end GT, a data line DL and the second end of the first energy storage circuit 12 respectively, and is used for writing a data voltage Vdata provided by the data line DL into the second end of the first energy storage circuit 12 under the control of a scanning signal provided by the scanning end GT in the writing stage.

[0094] In at least one embodiment of the present disclosure, the on-off control line can be a compensation control line GT2, or the on-off control line can be an N+1th compensation control line GT2(N+1); N can be a positive integer, and the compensation control line GT2 can be an Nth compensation control line.

[0095] In at least one embodiment of the present disclosure, the compensation control circuit includes an oxide transistor, so as to reduce the leakage current and facilitate the maintenance of the potential of the first node.

[0096] The pixel circuit in at least one embodiment of the present disclosure further comprises a first initialization circuit;

[0097] The first initialization circuit is electrically connected with an initial control line, a first reset voltage terminal and the second terminal of the first energy storage circuit respectively, and is configured to write a first reset voltage provided by the first reset voltage terminal into the second terminal of the first energy storage circuit under control of an initial control signal provided by the initial control line.

[0098] In a specific implementation, the pixel circuit can further comprise a first initialization circuit configured to write a first reset voltage into the second terminal of the first energy storage circuit under control of an initial control signal, so as to reset the potential of the second terminal of the first energy storage circuit. As shown in FIG. 2, the pixel circuit in at least one embodiment of the present disclosure further comprises a first initialization circuit 21 based on the pixel circuit in at least one embodiment of the present disclosure shown in FIG. 1.

[0099] The first initialization circuit 21 is electrically connected with an initial control line RST0, a first reset voltage terminal VR1 and the second terminal of the first energy storage circuit 12 respectively, and is configured to write a first reset voltage provided by the first reset voltage terminal VR1 into the second terminal of the first energy storage circuit 12 under control of an initial control signal provided by the initial control line RST0.

[0100] In operation, the first initialization circuit 21 writes the first reset voltage into the second terminal of the first energy storage circuit 12 under control of the initial control signal in the light-emitting stage, so as to reset the potential of the second terminal of the first energy storage circuit 12, so that the potential of the first node is related to the data voltage.

[0101] Optionally, the initial control line can be the same control line as the first light-emitting control line.

[0102] The pixel circuit in at least one embodiment of the present disclosure further comprises a second initialization circuit;

[0103] The second initialization circuit is electrically connected with a first reset control line, a second reset voltage terminal and the first terminal of the first energy storage circuit respectively, and is configured to write a second reset voltage provided by the second reset voltage terminal into the first terminal of the first energy storage circuit under control of a first reset control signal provided by the first reset control line.

[0104] In a specific implementation, the pixel circuit can comprise a second initialization circuit configured to write a second reset voltage into the first terminal of the first energy storage circuit under control of a first reset control signal, so as to reset the potential of the first terminal of the first energy storage circuit.

[0105] As shown in FIG. 3, on the basis of at least one embodiment of the pixel circuit shown in FIG. 2 of the present disclosure, the pixel circuit in at least one embodiment of the present disclosure further comprises a second initialization circuit 31.

[0106] The second initialization circuit 31 is electrically connected with the first reset control line RST1, the second reset voltage terminal VR2 and the first end of the first energy storage circuit 12 respectively, and is configured to write the second reset voltage provided by the second reset voltage terminal VR2 into the first end of the first energy storage circuit 12 under the control of the first reset control signal provided by the first reset control line RST1.

[0107] In at least one embodiment of the present disclosure, the transistor included in the compensation control circuit is an n-type transistor, the transistor included in the on-off control circuit is a p-type transistor, and the compensation control line and the on-off control line are the same control line; or,

[0108] The transistor included in the compensation control circuit is a p-type transistor, the transistor included in the on-off control circuit is an n-type transistor, and the compensation control line and the on-off control line are the same control line.

[0109] In specific implementation, when the transistor included in the compensation control circuit and the transistor included in the on-off control circuit are transistors of different types, the compensation control line and the on-off control line can be the same control line, thereby reducing the number of control lines used by the display panel containing the pixel circuit.

[0110] In at least one embodiment of the present disclosure, the display period further comprises a light emitting stage, and the light emitting stage is arranged after the writing stage and the compensation stage;

[0111] The first initialization circuit is configured to write the first reset voltage into the second end of the first energy storage circuit under the control of the initial control signal in the light emitting stage.

[0112] The on-off control circuit is configured to control the communication between the first node and the first end of the first energy storage circuit under the control of the on-off control signal in the light emitting stage.

[0113] In specific implementation, the light emitting stage is arranged after the writing stage and the compensation stage, in the light emitting stage, the first initialization circuit writes the first reset voltage into the second end of the first energy storage circuit under the control of the initial control signal, and the on-off control circuit controls the communication between the first node and the first end of the first energy storage circuit under the control of the on-off control signal, so that the potential of the first node is related to the data voltage.

[0114] In at least one embodiment of the present disclosure, the display period further comprises an initialization stage, which is arranged before the write stage and the compensation stage;

[0115] The first initialization circuit is configured to write the first reset voltage to the second terminal of the first energy storage circuit under the control of the initial control signal during the initialization stage.

[0116] In specific implementation, the initialization stage can be further arranged before the write stage and the compensation stage, in which the first initialization circuit writes the first reset voltage to the second terminal of the first energy storage circuit under the control of the initial control signal to initialize the potential of the second terminal of the first energy storage circuit.

[0117] In at least one embodiment of the present disclosure, the second initialization circuit is configured to write the second reset voltage to the first terminal of the first energy storage circuit under the control of the first reset control signal during the write stage.

[0118] The compensation control circuit is further configured to control the communication between the first node and the third node under the control of the compensation control signal during the write stage.

[0119] In specific implementation, during the write stage, the second initialization circuit writes the second reset voltage to the first terminal of the first energy storage circuit under the control of the first reset control signal, and the compensation control circuit controls the communication between the first node and the third node under the control of the compensation control signal, so that the potential of the first node is initialized to the first initial voltage when the potential of the third node is initialized to the first initial voltage. The pixel circuit according to at least one embodiment of the present disclosure further comprises a light emitting element, a first light emitting control circuit, a second light emitting control circuit and a second energy storage circuit.

[0120] The first light emitting control circuit is electrically connected with a first light emitting control line, the third node and a first electrode of the light emitting element, respectively, and is configured to control the communication between the third node and the first electrode of the light emitting element under the control of a first light emitting control signal provided by the first light emitting control line.

[0121] The second light emitting control circuit is electrically connected with a second light emitting control line, a power voltage terminal and the second node, respectively, and is configured to control the communication between the power voltage terminal and the second node under the control of a second light emitting control signal provided by the second light emitting control line.

[0122] The second energy storage circuit is electrically connected with the first node, and is configured to maintain the potential of the first node.

[0123] The second electrode of the light emitting element is electrically connected with the first voltage terminal.

[0124] In a specific implementation, the pixel circuit can further include a light emitting element, a first light emitting control circuit and a second light emitting control circuit; the first light emitting control circuit controls the communication between the third node and the first electrode of the light emitting element under the control of a first light emitting control signal; and the second light emitting control circuit controls the communication between the power voltage terminal and the second node under the control of a second light emitting control signal to perform light emitting control.

[0125] In at least one embodiment of the present disclosure, the initial control line can be a first light emitting control line, so as to reduce the number of control lines used by the display panel.

[0126] As shown in FIG. 4, based on at least one embodiment of the pixel circuit shown in FIG. 2 of the present disclosure, the pixel circuit according to at least one embodiment of the present disclosure further includes a light emitting element E1, a first light emitting control circuit 41, a second light emitting control circuit 42 and a second energy storage circuit 40.

[0127] The first light emitting control circuit 41 is electrically connected with a first light emitting control line EM1, the third node N3 and the first electrode of the light emitting element E1, respectively, and is configured to control the communication between the third node N3 and the first electrode of the light emitting element E1 under the control of a first light emitting control signal provided by the first light emitting control line EM1.

[0128] The second light emitting control circuit 42 is electrically connected with a second light emitting control line EM2, a power voltage terminal VDD and the second node N2, respectively, and is configured to control the communication between the power voltage terminal VDD and the second node N2 under the control of a second light emitting control signal provided by the second light emitting control line EM2.

[0129] The second energy storage circuit 40 is electrically connected with the first node N1, and is configured to maintain the potential of the first node N1.

[0130] The second electrode of the light emitting element E1 is electrically connected with a first voltage terminal V1.

[0131] Optionally, the first voltage terminal can be a low voltage terminal.

[0132] As shown in FIG. 5, based on at least one embodiment of the pixel circuit shown in FIG. 3 of the present disclosure, the pixel circuit according to at least one embodiment of the present disclosure further includes a light emitting element E1, a first light emitting control circuit 41, a second light emitting control circuit 42 and a second energy storage circuit 40.

[0133] The first light emitting control circuit 41 is electrically connected with the first light emitting control line EM1, the third node N3 and the first electrode of the light emitting element E1, respectively, for controlling the communication between the third node N3 and the first electrode of the light emitting element E1 under the control of the first light emitting control signal provided by the first light emitting control line EM1.

[0134] The second light emitting control circuit 42 is electrically connected with the second light emitting control line EM2, the power voltage terminal VDD and the second node N2, respectively, for controlling the communication between the power voltage terminal VDD and the second node N2 under the control of the second light emitting control signal provided by the second light emitting control line EM2.

[0135] The second energy storage circuit 40 is electrically connected with the first node N1 for maintaining the potential of the first node N1.

[0136] The second electrode of the light emitting element E1 is electrically connected with the first voltage terminal V1.

[0137] The pixel circuit in at least one embodiment of the present disclosure further comprises a third initialization circuit.

[0138] The third initialization circuit is electrically connected with the second reset control line, the second node and the third initial voltage terminal, respectively, for writing the third initial voltage provided by the third initial voltage terminal into the second node under the control of the second reset control signal provided by the second reset control line.

[0139] In specific implementation, the pixel circuit can further comprise a third initialization circuit, which writes the third initial voltage into the second node under the control of the second reset control signal, thereby improving the hysteresis of the driving transistor included in the driving circuit.

[0140] As shown in FIG. 6, the pixel circuit in at least one embodiment of the present disclosure further comprises a third initialization circuit 43 on the basis of the pixel circuit in at least one embodiment shown in FIG. 4.

[0141] The third initialization circuit 43 is electrically connected with the second reset control line RST2, the second node N2 and the third initial voltage terminal I3, respectively, for writing the third initial voltage Vinit3 provided by the third initial voltage terminal I3 into the second node N2 under the control of the second reset control signal provided by the second reset control line RST2.

[0142] As shown in FIG. 7, the pixel circuit in at least one embodiment of the present disclosure further comprises a third initialization circuit 43 on the basis of the pixel circuit in at least one embodiment shown in FIG. 5.

[0143] The third initialization circuit 43 is electrically connected with the second reset control line RST2, the second node N2 and the third initial voltage terminal I3 respectively, and is configured to write a third initial voltage Vinit3 provided by the third initial voltage terminal I3 into the second node N2 under control of a second reset control signal provided by the second reset control line RST2.

[0144] The pixel circuit according to at least one embodiment of the present disclosure further comprises a fourth initialization circuit.

[0145] The fourth initialization circuit is electrically connected with the second reset control line, the second initial voltage terminal and the first electrode of the light emitting element respectively, and is configured to write a second initial voltage provided by the second initial voltage terminal into the first electrode of the light emitting element under control of a second reset control signal provided by the second reset control line.

[0146] In a specific implementation, the pixel circuit can further comprise a fourth initialization circuit configured to write a second initial voltage into the first electrode of the light emitting element under control of a second reset control signal, and clear the residual charge in the first electrode of the light emitting element.

[0147] The pixel circuit according to at least one embodiment of the present disclosure further comprises a fifth initialization circuit.

[0148] The fifth initialization circuit is electrically connected with the first reset control line, the first initial voltage terminal and the third node respectively, and is configured to write a first initial voltage provided by the first initial voltage terminal into the third node under control of a first reset control signal provided by the first reset control line.

[0149] In a specific implementation, the pixel circuit can further comprise a fifth initialization circuit configured to write a first initial voltage into the third node under control of a first reset control signal, and reset the potential of the third node.

[0150] As shown in FIG. 8, on the basis of at least one embodiment of the pixel circuit shown in FIG. 6, the pixel circuit according to at least one embodiment of the present disclosure further comprises a fourth initialization circuit 44 and a fifth initialization circuit 45.

[0151] The fourth initialization circuit 44 is electrically connected with the second reset control line RST2, the second initial voltage terminal I2 and the first electrode of the light emitting element E1 respectively, and is configured to write a second initial voltage Vinit2 provided by the second initial voltage terminal I2 into the first electrode of the light emitting element E1 under control of a second reset control signal provided by the second reset control line RST2.

[0152] The fifth initialization circuit 45 is electrically connected with the first reset control line RST1, the first initial voltage terminal I1 and the third node N3 respectively, and is configured to write the first initial voltage Vinit1 provided by the first initial voltage terminal I1 into the third node N3 under the control of a first reset control signal provided by the first reset control line RST1.

[0153] As shown in FIG. 9, based on at least one embodiment of the pixel circuit shown in FIG. 7, the pixel circuit provided by at least one embodiment of the present disclosure further includes a fourth initialization circuit 44 and a fifth initialization circuit 45.

[0154] The fourth initialization circuit 44 is electrically connected with the second reset control line RST2, the second initial voltage terminal I2 and the first electrode of the light emitting element E1 respectively, and is configured to write the second initial voltage Vinit2 provided by the second initial voltage terminal I2 into the first electrode of the light emitting element E1 under the control of a second reset control signal provided by the second reset control line RST2.

[0155] The fifth initialization circuit 45 is electrically connected with the first reset control line RST1, the first initial voltage terminal I1 and the third node N3 respectively, and is configured to write the first initial voltage Vinit1 provided by the first initial voltage terminal I1 into the third node N3 under the control of a first reset control signal provided by the first reset control line RST1.

[0156] As shown in FIG. 10A, based on at least one embodiment of the pixel circuit shown in FIG. 7, the pixel circuit provided by at least one embodiment of the present disclosure further includes a fourth initialization circuit 44.

[0157] The fourth initialization circuit 44 is electrically connected with the second reset control line RST2, the second initial voltage terminal I2 and the first electrode of the light emitting element E1 respectively, and is configured to write the second initial voltage Vinit2 provided by the second initial voltage terminal I2 into the first electrode of the light emitting element E1 under the control of a second reset control signal provided by the second reset control line RST2.

[0158] The pixel circuit provided by at least one embodiment of the present disclosure can further include a fifth initialization circuit.

[0159] The fifth initialization circuit is electrically connected with the first reset control line, the first initial voltage terminal and the first node respectively, and is configured to write the first initial voltage provided by the first initial voltage terminal into the first node under the control of a first reset control signal provided by the first reset control line.

[0160] In a specific implementation, when the pixel circuit includes a fifth initialization circuit electrically connected to the first node, the transistor included in the compensation control circuit and the transistor included in the fifth initialization circuit can be oxide transistors to reduce leakage current and facilitate maintaining the potential of the first node.

[0161] As shown in FIG. 10B, on the basis of at least one embodiment of the pixel circuit shown in FIG. 7, the pixel circuit according to at least one embodiment of the present disclosure further includes a fourth initialization circuit 44 and a fifth initialization circuit 45.

[0162] The fourth initialization circuit 44 is electrically connected to a second reset control line RST2, a second initial voltage terminal I2, and a first electrode of the light emitting element E1, respectively, and is configured to write a second initial voltage Vinit2 provided by the second initial voltage terminal I2 into the first electrode of the light emitting element E1 under the control of a second reset control signal provided by the second reset control line RST2.

[0163] The fifth initialization circuit 45 is electrically connected to a first reset control line RST1, a first initial voltage terminal I1, and the first node N1, respectively, and is configured to write a first initial voltage Vinit1 provided by the first initial voltage terminal I1 into the first node N1 under the control of a first reset control signal provided by the first reset control line RST1.

[0164] Optionally, the driving circuit includes a driving transistor, the compensation control circuit includes a first transistor, the first energy storage circuit includes a first capacitor, the on-off control circuit includes a second transistor, and the data writing circuit includes a third transistor.

[0165] The gate of the driving transistor is electrically connected to the first node, the first electrode of the driving transistor is electrically connected to the second node, and the second electrode of the driving transistor is electrically connected to the third node.

[0166] The gate of the first transistor is electrically connected to the compensation control line, the first electrode of the first transistor is electrically connected to the first node, and the second electrode of the first transistor is electrically connected to the third node.

[0167] The gate of the second transistor is electrically connected to the on-off control line, the first electrode of the second transistor is electrically connected to the first node, and the second electrode of the second transistor is electrically connected to a first terminal of the first capacitor.

[0168] The gate of the third transistor is electrically connected to the scanning terminal, the first electrode of the third transistor is electrically connected to the data line, and the second electrode of the third transistor is electrically connected to a second terminal of the first capacitor.

[0169] Optionally, the first initialization circuit comprises a fourth transistor.

[0170] The gate of the fourth transistor is electrically connected with the initial control line, the first pole of the fourth transistor is electrically connected with the first reset voltage terminal, and the second pole of the fourth transistor is electrically connected with the second terminal of the first energy storage circuit.

[0171] Optionally, the second initialization circuit comprises a fifth transistor.

[0172] The gate of the fifth transistor is electrically connected with the first reset control line, the first pole of the fifth transistor is electrically connected with the second reset voltage terminal, and the second pole of the fifth transistor is electrically connected with the first terminal of the first energy storage circuit.

[0173] Optionally, the first light-emitting control circuit comprises a sixth transistor, and the second light-emitting control circuit comprises a seventh transistor.

[0174] The gate of the sixth transistor is electrically connected with the first light-emitting control line, the first pole of the sixth transistor is electrically connected with the third node, and the second pole of the sixth transistor is electrically connected with the first pole of the light-emitting element.

[0175] The gate of the seventh transistor is electrically connected with the second light-emitting control line, the first pole of the seventh transistor is electrically connected with the power voltage terminal, and the second pole of the seventh transistor is electrically connected with the second node.

[0176] The second energy storage circuit comprises a second capacitor.

[0177] The first terminal of the second capacitor is electrically connected with the first node, and the second terminal of the second capacitor is electrically connected with the direct current voltage terminal.

[0178] Optionally, the direct current voltage terminal can be a power voltage terminal.

[0179] Optionally, the third initialization circuit comprises an eighth transistor.

[0180] The gate of the eighth transistor is electrically connected with the second reset control line, the first pole of the eighth transistor is electrically connected with the second node, and the second pole of the eighth transistor is electrically connected with the third initial voltage terminal.

[0181] Optionally, the fourth initialization circuit comprises a ninth transistor.

[0182] The gate of the ninth transistor is electrically connected with the second reset control line, the first pole of the ninth transistor is electrically connected with the second initial voltage terminal, and the second pole of the ninth transistor is electrically connected with the first pole of the light-emitting element.

[0183] Optionally, the fifth initialization circuit comprises a tenth transistor;

[0184] The gate of the tenth transistor is electrically connected with the first reset control line, the first pole of the tenth transistor is electrically connected with the first initial voltage terminal, and the second pole of the tenth transistor is electrically connected with the third node.

[0185] As shown in FIG. 11, on the basis of at least one embodiment of the pixel circuit shown in FIG. 8, the light emitting element is an organic light emitting diode O1;

[0186] The driving circuit comprises a driving transistor T0, the compensation control circuit comprises a first transistor T1, the first energy storage circuit comprises a first capacitor C1, the on-off control circuit comprises a second transistor T2, and the data writing circuit comprises a third transistor T3.

[0187] The gate of the driving transistor T0 is electrically connected with the first node N1, the source of the driving transistor T0 is electrically connected with the second node N2, and the drain of the driving transistor T0 is electrically connected with the third node N3.

[0188] The gate of the first transistor T1 is electrically connected with a compensation control line GT2, the source of the first transistor T1 is electrically connected with the first node N1, and the drain of the first transistor T1 is electrically connected with the third node N3.

[0189] The gate of the second transistor T2 is electrically connected with an N+1th compensation control line GT2(N+1), the source of the second transistor T2 is electrically connected with the first node N1, and the drain of the second transistor T2 is electrically connected with the first end of the first capacitor C1.

[0190] The gate of the third transistor T3 is electrically connected with a scanning terminal GT, the source of the third transistor T3 is electrically connected with the data line DL, and the drain of the third transistor T3 is electrically connected with the second end of the first capacitor C1.

[0191] The first initialization circuit comprises a fourth transistor T4.

[0192] The gate of the fourth transistor T4 is electrically connected with a first light emitting control line EM1, the source of the fourth transistor T4 is electrically connected with a first initial voltage terminal I1, and the drain of the fourth transistor T4 is electrically connected with the second end of the first capacitor C1.

[0193] The first light emitting control circuit comprises a sixth transistor T6, and the second light emitting control circuit comprises a seventh transistor T7.

[0194] The gate of the sixth transistor T6 is electrically connected with the first light-emitting control line EM1, the source of the sixth transistor T6 is electrically connected with the third node N3, and the drain of the sixth transistor T6 is electrically connected with the anode of the organic light-emitting diode O1;

[0195] The gate of the seventh transistor T7 is electrically connected with the second light-emitting control line EM2, the source of the seventh transistor T7 is electrically connected with the power voltage terminal VDD, and the drain of the seventh transistor T7 is electrically connected with the second node N2;

[0196] The third initialization circuit comprises an eighth transistor T8.

[0197] The gate of the eighth transistor T8 is electrically connected with the second reset control line RST2, the source of the eighth transistor T8 is electrically connected with the second node N2, and the drain of the eighth transistor T8 is electrically connected with the third initial voltage terminal I3.

[0198] The fourth initialization circuit comprises a ninth transistor T9.

[0199] The gate of the ninth transistor T9 is electrically connected with the second reset control line RST2, the source of the ninth transistor T92 is electrically connected with the second initial voltage terminal I2, and the drain of the ninth transistor T9 is electrically connected with the anode of O1.

[0200] The fifth initialization circuit comprises a tenth transistor T10.

[0201] The gate of the tenth transistor T10 is electrically connected with the first reset control line RST1, the source of the tenth transistor T10 is electrically connected with the first initial voltage terminal I1, and the drain of the tenth transistor T10 is electrically connected with the third node N3.

[0202] The second energy storage circuit comprises a second capacitor C2.

[0203] The first end of the second capacitor C2 is electrically connected with the first node N1, and the second end of the second capacitor C2 is electrically connected with the power voltage terminal VDD.

[0204] In at least one embodiment of the pixel circuit shown in FIG. 11, the first reset voltage terminal is the first initial voltage terminal I1.

[0205] T1 is an n-type transistor, and T1 is an oxide transistor; the transistors other than T1 are p-type transistors, and the transistors other than T1 are low-temperature polysilicon transistors.

[0206] As shown in FIG. 12, at least one embodiment of the pixel circuit shown in FIG. 11 of the present disclosure works as follows: the display period includes reset stage S1, write stage S2, compensation stage S3 and light-emitting stage S4 arranged in sequence.

[0207] In the reset stage S1, RST1 provides a high voltage signal, RST2 provides a low voltage signal, GT2 provides a low voltage signal, EM1 provides a low voltage signal, EM2 provides a high voltage signal, GT provides a high voltage signal, T8 and T9 are open, I2 provides a second initial voltage Vinit2 to the anode of O1, and the residual charge of the anode of O1 is cleared, I3 provides a third initial voltage Vinit3 to N2, T4 is open, and I1 provides a first initial voltage Vinit1 to the second end of C1;

[0208] In the write stage S2, RST1 provides a low voltage signal, RST2 provides a high voltage signal, GT2 provides a high voltage signal, EM1 provides a high voltage signal, EM2 provides a high voltage signal, GT provides a low voltage signal, GT2(N+1) provides a low voltage signal, T3 is open, DL provides a data voltage Vdata to the second end of C1, T10 is open, T1 is open, T2 is open, and I1 provides a first initial voltage Vinit1 to N1 and the first end of C1;

[0209] In the compensation stage S3, RST1 provides a high voltage signal, RST2 provides a high voltage signal, GT2 provides a high voltage signal, EM1 provides a high voltage signal, EM2 provides a low voltage signal, GT provides a high voltage signal, GT2(N+1) provides a high voltage signal, T1 is open, and T7 is open;

[0210] At the beginning of the compensation stage S3, T0 is open, VDD provides a power voltage signal to charge C2 and change the potential of N1 until the potential of N1 becomes Vdd+Vth, and then T0 is closed; Vdd is the voltage value of the power voltage signal provided by VDD, and Vth is the threshold voltage of T0;

[0211] In the light-emitting stage S4, RST1 provides a high voltage signal, RST2 provides a high voltage signal, GT2 provides a low voltage signal, EM1 provides a low voltage signal, EM2 provides a low voltage signal, GT provides a high voltage signal, GT2(N+1) provides a low voltage signal, T2 is open, T4 is open, and I1 provides a first initial voltage Vinit1 to the first end of C1, at this time, the potential of N1 jumps to Vdd+Vth+Vinit1-Vdata, T6 and T7 are open, and T0 drives O1 to emit light.

[0212] The difference between at least one embodiment of the pixel circuit shown in FIG. 13 of the present disclosure and at least one embodiment of the pixel circuit shown in FIG. 11 of the present disclosure is as follows: a second initialization circuit is further included;

[0213] The second initialization circuit comprises a fifth transistor T5;

[0214] The gate of the fifth transistor T5 is electrically connected with the first reset control line RST1, the source of the fifth transistor T5 is electrically connected with the first initial voltage terminal I1, and the drain of the fifth transistor T5 is electrically connected with the first end of the first capacitor C1.

[0215] The gate of T2 is electrically connected with the compensation control line GT2.

[0216] In at least one embodiment of the pixel circuit shown in FIG. 13, the second reset voltage terminal is a second initial voltage terminal, and T5 is a p-type transistor.

[0217] In at least one embodiment of the pixel circuit shown in FIG. 13, the gate of T1 and the gate of T2 are both electrically connected with GT2, so as to reduce the number of control lines used.

[0218] As shown in FIG. 14, in at least one embodiment of the pixel circuit shown in FIG. 13 of the present disclosure, during operation, the display period comprises a reset stage S1, a write stage S2, a compensation stage S3 and an emitting stage S4 arranged in sequence.

[0219] In the reset stage S1, RST1 provides a high voltage signal, RST2 provides a low voltage signal, GT2 provides a low voltage signal, EM1 provides a low voltage signal, EM2 provides a high voltage signal, GT provides a high voltage signal, T8 and T9 are turned on, I2 provides a second initial voltage Vinit2 to the anode of O1, and the residual charges at the anode of O1 are cleared, I3 provides a third initial voltage Vinit3 to N2, T4 is turned on, and I1 provides a first initial voltage Vinit1 to the second end of C1.

[0220] In the write stage S2, RST1 provides a low voltage signal, RST2 provides a high voltage signal, GT2 provides a high voltage signal, EM1 provides a high voltage signal, EM2 provides a high voltage signal, GT provides a low voltage signal, T3 is turned on, DL provides a data voltage Vdata to the second end of C1, T10 is turned on, T1 is turned on, T5 is turned on, and I1 provides a first initial voltage Vinit1 to N1 and the first end of C1.

[0221] In the compensation stage S3, RST1 provides a high voltage signal, RST2 provides a high voltage signal, GT2 provides a high voltage signal, EM1 provides a high voltage signal, EM2 provides a low voltage signal, GT provides a high voltage signal, T1 is turned on, and T7 is turned on.

[0222] At the beginning of the compensation stage S3, T0 is turned on, the power voltage signal provided by VDD charges C2, changes the potential of N1, until the potential of N1 becomes Vdd+Vth, T0 is turned off; Vdd is the voltage value of the power voltage signal provided by VDD, Vth is the threshold voltage of T0;

[0223] In the light-emitting stage S4, RST1 provides a high voltage signal, RST2 provides a high voltage signal, GT2 provides a low voltage signal, EM1 provides a low voltage signal, EM2 provides a low voltage signal, GT provides a high voltage signal, T5 is turned on, T4 is turned on, I1 provides the first initial voltage Vinit1 to the first end of C1, at this time, the potential of N1 jumps to Vdd+Vth+Vinit1-Vdata, T6 and T7 are turned on, T0 drives O1 to emit light.

[0224] As shown in FIG. 15, on the basis of at least one embodiment of the pixel circuit shown in FIG. 10A, the light-emitting element is an organic light-emitting diode O1;

[0225] The driving circuit comprises a driving transistor T0, the compensation control circuit comprises a first transistor T1, the first energy storage circuit comprises a first capacitor C1, the on-off control circuit comprises a second transistor T2, and the data writing circuit comprises a third transistor T3;

[0226] The gate of the driving transistor T0 is electrically connected with the first node N1, the source of the driving transistor T0 is electrically connected with the second node N2, and the drain of the driving transistor T0 is electrically connected with the third node N3;

[0227] The gate of the first transistor T1 is electrically connected with the compensation control line GT2, the source of the first transistor T1 is electrically connected with the first node N1, and the drain of the first transistor T1 is electrically connected with the third node N3;

[0228] The gate of the second transistor T2 is electrically connected with the compensation control line GT2, the source of the second transistor T2 is electrically connected with the first node N1, and the drain of the second transistor T2 is electrically connected with the first end of the first capacitor C1;

[0229] The gate of the third transistor T3 is electrically connected with the scanning end GT, the source of the third transistor T3 is electrically connected with the data line DL, and the drain of the third transistor T3 is electrically connected with the second end of the first capacitor C1;

[0230] The first initialization circuit comprises a fourth transistor T4;

[0231] The gate of the fourth transistor T4 is electrically connected with the first light-emitting control line EM1, the source of the fourth transistor T4 is electrically connected with the second initial voltage terminal I2, and the drain of the fourth transistor T4 is electrically connected with the second terminal of the first capacitor C1;

[0232] The second initialization circuit comprises a fifth transistor T5;

[0233] The gate of the fifth transistor T5 is electrically connected with the first reset control line RST1, the source of the fifth transistor T5 is electrically connected with the second initial voltage terminal I2, and the drain of the fifth transistor T5 is electrically connected with the first terminal of the first capacitor C1;

[0234] The first light-emitting control circuit comprises a sixth transistor T6, and the second light-emitting control circuit comprises a seventh transistor T7;

[0235] The gate of the sixth transistor T6 is electrically connected with the first light-emitting control line EM1, the source of the sixth transistor T6 is electrically connected with the third node N3, and the drain of the sixth transistor T6 is electrically connected with the anode of the organic light-emitting diode O1;

[0236] The gate of the seventh transistor T7 is electrically connected with the second light-emitting control line EM2, the source of the seventh transistor T7 is electrically connected with the power voltage terminal VDD, and the drain of the seventh transistor T7 is electrically connected with the second node N2;

[0237] The third initialization circuit comprises an eighth transistor T8;

[0238] The gate of the eighth transistor T8 is electrically connected with the second reset control line RST2, the source of the eighth transistor T8 is electrically connected with the second node N2, and the drain of the eighth transistor T8 is electrically connected with the third initial voltage terminal I3;

[0239] The fourth initialization circuit comprises a ninth transistor T9;

[0240] The gate of the ninth transistor T9 is electrically connected with the second reset control line RST2, the source of the ninth transistor T92 is electrically connected with the second initial voltage terminal I2, and the drain of the ninth transistor T9 is electrically connected with the anode of O1;

[0241] The fifth initialization circuit comprises a tenth transistor T10;

[0242] The gate of the tenth transistor T10 is electrically connected with the first reset control line RST1, the source of the tenth transistor T10 is electrically connected with the first initial voltage terminal I1, and the drain of the tenth transistor T10 is electrically connected with the anode of O1;

[0243] The second energy storage circuit comprises a second capacitor C2;

[0244] A first end of the second capacitor C2 is electrically connected with the first node N1, and a second end of the second capacitor C2 is electrically connected with the power voltage terminal VDD.

[0245] In at least one embodiment of the pixel circuit shown in FIG. 15, T1 is an n-type transistor, and T1 is an oxide transistor; the transistors other than T1 are p-type transistors, and the transistors other than T1 are low-temperature polysilicon transistors.

[0246] In at least one embodiment of the pixel circuit shown in FIG. 15, the first reset voltage terminal and the second reset voltage terminal are both the second initial voltage terminal I2, so as to reduce the number of initial voltage terminals used.

[0247] In at least one embodiment of the pixel circuit shown in FIG. 15, T10 is not used, and the potential of N1 is reset by T2 and T5.

[0248] As shown in FIG. 16, in at least one embodiment of the pixel circuit shown in FIG. 15, during operation, the display period can include a reset stage S1, a write stage S2, a compensation stage S3 and a light-emitting stage S4 arranged in sequence.

[0249] In the reset stage S1, RST1 provides a high voltage signal, RST2 provides a low voltage signal, GT2 provides a high voltage signal, EM1 provides a low voltage signal, EM2 provides a high voltage signal, GT provides a high voltage signal, T8 is turned on, T9 is turned on, I3 provides the third initial voltage Vinit3 to N2, I2 provides the second initial voltage Vinit2 to the anode of O1, and the residual charge of the anode of O1 is cleared; T4 is turned on, and I2 provides the second initial voltage Vinit2 to the second end of C1.

[0250] In the write stage S2, RST1 provides a low voltage signal, RST2 provides a high voltage signal, GT2 provides a high voltage signal, EM1 provides a high voltage signal, EM2 provides a high voltage signal, GT provides a low voltage signal, T3 is turned on, DL provides the data voltage Vdata to the second end of C1, T5 is turned on, and I2 provides the second initial voltage Vinit2 to the first end of C1.

[0251] In the compensation stage S3, RST1 provides a high voltage signal, RST2 provides a high voltage signal, GT2 provides a high voltage signal, EM1 provides a high voltage signal, EM2 provides a low voltage signal, GT provides a high voltage signal, T1 is turned on, and T7 is turned on.

[0252] At the beginning of the compensation stage S3, T0 is turned on, the power voltage signal provided by VDD charges C2, changes the potential of N1, until the potential of N1 becomes Vdd+Vth, T0 is turned off; Vdd is the voltage value of the power voltage signal provided by VDD, Vth is the threshold voltage of T0;

[0253] In the light-emitting stage S4, RST1 provides a high voltage signal, RST2 provides a high voltage signal, GT2 provides a low voltage signal, EM1 provides a low voltage signal, EM2 provides a low voltage signal, GT provides a high voltage signal, T4 is turned on, I2 provides a second initial voltage Vinit2, T2 is turned on, the potential of N1 jumps to Vdd+Vth+Vinit1-Vdata, T6 and T7 are turned on, T0 drives O1 to emit light.

[0254] At least one embodiment of the pixel circuit shown in FIG. 17 of the present disclosure is different from at least one embodiment of the pixel circuit shown in FIG. 15 of the present disclosure as follows:

[0255] The eighth transistor T8 is not included.

[0256] FIG. 18 is a working timing diagram of at least one embodiment of the pixel circuit shown in FIG. 17 of the present disclosure.

[0257] At least one embodiment of the pixel circuit shown in FIG. 19 is different from at least one embodiment of the pixel circuit shown in FIG. 11 as follows:

[0258] At least one embodiment of the pixel circuit shown in FIG. 19 further includes a fifth initialization circuit.

[0259] The fifth initialization circuit includes a tenth transistor T10.

[0260] The gate of the tenth transistor T10 is electrically connected to the first reset control line RST1, the source of the tenth transistor T10 is electrically connected to the first initial voltage terminal I1, and the drain of the tenth transistor T10 is electrically connected to the first node N1.

[0261] In at least one embodiment of the pixel circuit shown in FIG. 19, T1 and T10 are oxide transistors, T1 and T10 are n-type transistors, and the other transistors are p-type transistors.

[0262] As shown in FIG. 20, at least one embodiment of the pixel circuit shown in FIG. 19 of the present disclosure works, and the display period includes, in sequence, a reset stage S1, a write stage S2, a compensation stage S3, and a light-emitting stage S4.

[0263] In the reset stage S1, RST1 provides a low voltage signal, RST2 provides a low voltage signal, GT2 provides a low voltage signal, EM1 provides a low voltage signal, EM2 provides a high voltage signal, GT provides a high voltage signal, T8 and T9 are open, I2 provides a second initial voltage Vinit2 to the anode of O1, the residual charge of the anode of O1 is cleared, I3 provides a third initial voltage Vinit3 to N2, T4 is open, and I1 provides a first initial voltage Vinit1 to the second end of C1;

[0264] In the write stage S2, RST1 provides a high voltage signal, RST2 provides a high voltage signal, GT2 provides a high voltage signal, EM1 provides a high voltage signal, EM2 provides a high voltage signal, GT provides a low voltage signal, GT2(N+1) provides a low voltage signal, T3 is open, DL provides a data voltage Vdata to the second end of C1, T10 is open, T1 is open, T2 is open, and I1 provides a first initial voltage Vinit1 to the first end of N1 and C1;

[0265] In the compensation stage S3, RST1 provides a low voltage signal, RST2 provides a high voltage signal, GT2 provides a high voltage signal, EM1 provides a high voltage signal, EM2 provides a low voltage signal, GT provides a high voltage signal, and GT2(N+1) provides a high voltage signal, T1 is open, and T7 is open;

[0266] At the beginning of the compensation stage S3, T0 is open, VDD provides a power voltage signal to charge C2 and change the potential of N1 until the potential of N1 becomes Vdd+Vth, and T0 is closed; Vdd is the voltage value of the power voltage signal provided by VDD, and Vth is the threshold voltage of T0;

[0267] In the light-emitting stage S4, RST1 provides a low voltage signal, RST2 provides a high voltage signal, GT2 provides a low voltage signal, EM1 provides a low voltage signal, EM2 provides a low voltage signal, GT provides a high voltage signal, GT2(N+1) provides a low voltage signal, T2 is open, T4 is open, and I1 provides a first initial voltage Vinit1 to the first end of C1, at this time, the potential of N1 jumps to Vdd+Vth+Vinit1-Vdata, T6 and T7 are open, and T0 drives O1 to emit light.

[0268] The pixel driving method provided in the embodiments of the present disclosure is applied to the pixel circuit described above, and a display cycle includes a write stage, a compensation stage, and a light-emitting stage; the light-emitting stage is arranged after the write stage and the compensation stage; and the pixel driving method includes:

[0269] In the write stage, the data writing circuit writes the data voltage provided by the data line to the second end of the first energy storage circuit under the control of the scanning signal;

[0270] In the compensation phase, the compensation control circuit controls the communication between the first node and the third node under the control of the compensation control signal to perform threshold voltage compensation.

[0271] In the light-emitting phase, the first initialization circuit writes the first reset voltage to the second end of the first energy storage circuit under the control of the initial control signal, and the on-off control circuit controls the communication between the first node and the first end of the first energy storage circuit under the control of the on-off control signal, so that the first node is related to the data voltage, thereby enabling the data voltage to be written separately from the threshold voltage compensation, so that the threshold voltage compensation time is not limited by the resolution and the frequency, and high-frequency driving under large size can be realized.

[0272] In at least one embodiment of the present disclosure, the pixel circuit further comprises a second initialization circuit; and the pixel driving method further comprises:

[0273] In the writing phase, the second initialization circuit writes the second reset voltage to the first end of the first energy storage circuit under the control of the first reset control signal; and the compensation control circuit controls the communication between the first node and the third node under the control of the compensation control signal.

[0274] In specific implementation, in the writing phase, the second initialization circuit writes the second reset voltage to the first end of the first energy storage circuit and the first node under the control of the first reset control signal; and the compensation control circuit controls the communication between the first node and the third node under the control of the compensation control signal, and when the potential of the third node is initialized to the first initial voltage, the potential of the first node is initialized to the first initial voltage.

[0275] The display device provided in the embodiments of the present disclosure comprises the pixel circuit described above.

[0276] The above describes the preferred embodiments of the present disclosure. It should be noted that, for those skilled in the art, without departing from the principles of the present disclosure, a number of improvements and refinements can be made, which should also be considered as the protection scope of the present disclosure.

Claims

1. A pixel circuit comprising a driving circuit, a compensation control circuit, a first energy storage circuit, a pass control circuit and a data writing circuit; a display period of the pixel circuit comprising a writing stage and a compensation stage; a control end of the driving circuit being electrically connected with a first node, a first end of the driving circuit being electrically connected with a second node, a second end of the driving circuit being electrically connected with a third node, the driving circuit being configured to generate a driving current under the control of a potential of the first node; the compensation control circuit being electrically connected with a compensation control line, the first node and the third node respectively, and being configured to control a communication between the first node and the third node under the control of a compensation control signal provided by the compensation control line in the compensation stage; the pass control circuit being electrically connected with a pass control line, the first node and a first end of the first energy storage circuit respectively, and being configured to control a communication between the first node and the first end of the first energy storage circuit under the control of a pass control signal provided by the pass control line; the data writing circuit being electrically connected with a scanning end, a data line and a second end of the first energy storage circuit respectively, and being configured to write a data voltage provided by the data line into the second end of the first energy storage circuit under the control of a scanning signal provided by the scanning end in the writing stage.

2. The pixel circuit of claim 1, wherein, The transistor included in the compensation control circuit is an oxide transistor.

3. The pixel circuit of claim 1, wherein, Further comprising a first initialization circuit; the first initialization circuit being electrically connected with an initial control line, a first reset voltage end and the second end of the first energy storage circuit respectively, and being configured to write a first reset voltage provided by the first reset voltage end into the second end of the first energy storage circuit under the control of an initial control signal provided by the initial control line.

4. The pixel circuit of claim 3, wherein, Further comprising a second initialization circuit; the second initialization circuit being electrically connected with a first reset control line, a second reset voltage end and the first end of the first energy storage circuit respectively, and being configured to write a second reset voltage provided by the second reset voltage end into the first end of the first energy storage circuit under the control of a first reset control signal provided by the first reset control line.

5. The pixel circuit of claim 3, wherein, The display period further comprises a light emitting stage, the light emitting stage being arranged after the writing stage and the compensation stage; the first initialization circuit being configured to write the first reset voltage into the second end of the first energy storage circuit under the control of the initial control signal in the light emitting stage; the pass control circuit being configured to control the communication between the first node and the first end of the first energy storage circuit under the control of the pass control signal in the light emitting stage.

6. The pixel circuit of claim 5, wherein, The display period further comprises an initialization stage, the initialization stage being arranged before the writing stage and the compensation stage; the first initialization circuit being configured to write the first reset voltage into the second end of the first energy storage circuit under the control of the initial control signal in the initialization stage.

7. The pixel circuit of claim 4, wherein, the second initialization circuit being configured to write the second reset voltage into the first end of the first energy storage circuit under the control of the first reset control signal in the writing stage; The compensation control circuit is further configured to control, under control of the compensation control signal, communication between the first node and the third node during the writing stage.

8. The pixel circuit of claim 4, wherein, The compensation control circuit includes an n-type transistor, the on-off control circuit includes a p-type transistor, and the compensation control line and the on-off control line are the same control line; or, The compensation control circuit includes a p-type transistor, the on-off control circuit includes an n-type transistor, and the compensation control line and the on-off control line are the same control line.

9. The pixel circuit of any one of claims 1 to 8, wherein, The pixel circuit further includes a light-emitting element, a first light-emitting control circuit, a second light-emitting control circuit, and a second energy storage circuit. The first light-emitting control circuit is electrically connected with a first light-emitting control line, the third node, and a first electrode of the light-emitting element, respectively, and is configured to control communication between the third node and the first electrode of the light-emitting element under control of a first light-emitting control signal provided by the first light-emitting control line. The second light-emitting control circuit is electrically connected with a second light-emitting control line, a power voltage terminal, and the second node, respectively, and is configured to control communication between the power voltage terminal and the second node under control of a second light-emitting control signal provided by the second light-emitting control line. The second energy storage circuit is electrically connected with the first node, and is configured to maintain the potential of the first node. The second electrode of the light-emitting element is electrically connected with a first voltage terminal.

10. The pixel circuit of claim 9, wherein, The pixel circuit further includes a third initialization circuit; the third initialization circuit is electrically connected with a second reset control line, the second node, and a third initial voltage terminal, respectively, and is configured to write a third initial voltage provided by the third initial voltage terminal into the second node under control of a second reset control signal provided by the second reset control line; or, The pixel circuit further includes a fourth initialization circuit; the fourth initialization circuit is electrically connected with a second reset control line, a second initial voltage terminal, and a first electrode of the light-emitting element, respectively, and is configured to write a second initial voltage provided by the second initial voltage terminal into the first electrode of the light-emitting element under control of a second reset control signal provided by the second reset control line; or, The pixel circuit further includes a fifth initialization circuit; the fifth initialization circuit is electrically connected with a first reset control line and a first initial voltage terminal, and is further electrically connected with the third node or the first node, and is configured to write a first initial voltage provided by the first initial voltage terminal into the third node or the first node under control of a first reset control signal provided by the first reset control line.

11. The pixel circuit of claim 1, wherein, The driving circuit includes a driving transistor, the compensation control circuit includes a first transistor, the first energy storage circuit includes a first capacitor, the on-off control circuit includes a second transistor, and the data writing circuit includes a third transistor. The gate of the driving transistor is electrically connected with the first node, the first electrode of the driving transistor is electrically connected with the second node, and the second electrode of the driving transistor is electrically connected with the third node. The gate of the first transistor is electrically connected with the compensation control line, the first pole of the first transistor is electrically connected with the first node, and the second pole of the first transistor is electrically connected with the third node; The gate of the second transistor is electrically connected with the on-off control line, the first pole of the second transistor is electrically connected with the first node, and the second pole of the second transistor is electrically connected with the first end of the first capacitor; The gate of the third transistor is electrically connected with the scanning end, the first pole of the third transistor is electrically connected with the data line, and the second pole of the third transistor is electrically connected with the second end of the first capacitor.

12. The pixel circuit of claim 3, wherein, The first initialization circuit comprises a fourth transistor; The gate of the fourth transistor is electrically connected with the initial control line, the first pole of the fourth transistor is electrically connected with the first reset voltage end, and the second pole of the fourth transistor is electrically connected with the second end of the first energy storage circuit.

13. The pixel circuit of claim 4, wherein, The second initialization circuit comprises a fifth transistor; The gate of the fifth transistor is electrically connected with the first reset control line, the first pole of the fifth transistor is electrically connected with the second reset voltage end, and the second pole of the fifth transistor is electrically connected with the first end of the first energy storage circuit.

14. The pixel circuit of claim 6, wherein, The first light-emitting control circuit comprises a sixth transistor, and the second light-emitting control circuit comprises a seventh transistor; The gate of the sixth transistor is electrically connected with the first light-emitting control line, the first pole of the sixth transistor is electrically connected with the third node, and the second pole of the sixth transistor is electrically connected with the first pole of the light-emitting element; The gate of the seventh transistor is electrically connected with the second light-emitting control line, the first pole of the seventh transistor is electrically connected with the power voltage end, and the second pole of the seventh transistor is electrically connected with the second node.

15. The pixel circuit of claim 7, wherein, When the pixel circuit comprises a third initialization circuit, the third initialization circuit comprises an eighth transistor; the gate of the eighth transistor is electrically connected with the second reset control line, the first pole of the eighth transistor is electrically connected with the second node, and the second pole of the eighth transistor is electrically connected with the third initial voltage end; When the pixel circuit comprises a fourth initialization circuit, the fourth initialization circuit comprises a ninth transistor; the gate of the ninth transistor is electrically connected with the second reset control line, the first pole of the ninth transistor is electrically connected with the second initial voltage end, and the second pole of the ninth transistor is electrically connected with the first pole of the light-emitting element; When the pixel circuit comprises a fifth initialization circuit, the fifth initialization circuit comprises a tenth transistor; the gate of the tenth transistor is electrically connected with the first reset control line, the first pole of the tenth transistor is electrically connected with the first initial voltage end, and the second pole of the tenth transistor is electrically connected with the third node or the first node.

16. A pixel driving method applied to the pixel circuit according to any one of claims 1 to 15, wherein The display period comprises a writing stage, a compensation stage and a light-emitting stage; The light-emitting stage is arranged after the writing stage and the compensation stage; The pixel driving method comprises: In the writing stage, the data writing circuit writes the data voltage provided by the data line into the second end of the first energy storage circuit under the control of the scanning signal; In the compensation stage, the compensation control circuit controls the first node and the third node to be in communication under the control of a compensation control signal; In the light-emitting stage, the first initialization circuit writes a first reset voltage into the second terminal of the first energy storage circuit under the control of an initial control signal, and the on-off control circuit controls the first node and the first terminal of the first energy storage circuit to be in communication under the control of an on-off control signal.

17. The pixel driving method of claim 16, wherein, The pixel circuit further comprises a second initialization circuit; and the pixel driving method further comprises: In the writing stage, the second initialization circuit writes a second reset voltage into the first terminal of the first energy storage circuit under the control of a first reset control signal; and the compensation control circuit controls the first node and the third node to be in communication under the control of the compensation control signal.

18. A display device comprising the pixel circuit according to any one of claims 1 to 15.

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