Display substrate and preparation method therefor, and display device

Abstract

The embodiments of the present disclosure relate to, but are not limited to, the technical field of display. Disclosed are a display substrate and a preparation method therefor, and a display device. By means of forming an undercut structure (52) and a first trench (100) in a partition structure (50), the display substrate can increase the contact area between the partition structure (50) and an encapsulation layer and improve the adhesion of the encapsulation layer, thereby reducing the risk of detachment of the encapsulation layer, and can also improve an encapsulation effect and reduce the risk of water, oxygen, etc., seeping in through a gap between the partition structure (50) and the encapsulation layer, thereby improving the reliability of a light-emitting device.

Description

Display substrate and its preparation method, display device

[0001] This application claims priority to Chinese Patent Application No. 202410993473.X, filed on July 23, 2024, entitled "Display Substrate and Method for Preparing the Same, Display Device", the contents of which shall be construed as incorporated herein by reference. Technical Field

[0002] This disclosure relates to, but is not limited to, the field of display technology, specifically to a display substrate and its preparation method, and a display device. Background Technology

[0003] With the development of display technology, the application of Active Matrix Organic Light Emitting Diode (AMOLED) panels, known as the next-generation display technology, is becoming increasingly important. AMOLED uses Organic Light Emitting Diodes (OLEDs) as its light-emitting devices. Driven by the AMOLED driving circuit, the OLED emits light when current flows through it. Summary of the Invention

[0004] The following is an overview of the subject matter described in detail in this disclosure. This overview is not intended to limit the scope of the claims.

[0005] This disclosure provides a display substrate, including:

[0006] Substrate;

[0007] The first electrode is disposed on the substrate.

[0008] A pixel definition layer is disposed on the side of the first electrode away from the substrate, the pixel definition layer defining a pixel opening that exposes at least a portion of the first electrode;

[0009] A partition structure is disposed on the side of the pixel definition layer away from the substrate.

[0010] The partition structure includes a first partition structure layer and a second partition structure layer located between the first partition structure layer and the substrate, wherein the orthographic projection width of the first partition structure layer on the substrate is greater than the orthographic projection width of the second partition structure layer on the substrate.

[0011] The first partition structure layer has a first trench, the first trench having a first width on the side away from the substrate, and the first trench having a second width on the side closer to the substrate, the first width being greater than the second width.

[0012] In some embodiments of the display substrate, the first partition structure layer has a first surface away from the substrate and a second surface close to the substrate, wherein the orthographic projection width of the first surface on the substrate is smaller than the orthographic projection width of the second surface on the substrate.

[0013] In some embodiments of the display substrate, the orthographic projection of the first trench on the substrate is within the range of the orthographic projection of the second partition structure layer on the substrate.

[0014] In some embodiments of the display substrate, the second isolation structure layer has a second trench, the first trench communicates with the second trench, the second trench has a third width on the side away from the substrate, and the second trench has a fourth width on the side closer to the substrate, the third width being greater than the fourth width.

[0015] In some embodiments of the display substrate, the third width is greater than the second width.

[0016] In some embodiments of the display substrate, the second partition structure layer has a third surface away from the substrate and a fourth surface close to the substrate, wherein the orthographic projection width of the third surface on the substrate is greater than or less than the orthographic projection width of the fourth surface on the substrate.

[0017] In some embodiments of the display substrate, the partition structure further includes a third partition structure layer, which is disposed between the first partition structure layer and the second partition structure layer, and the orthographic projection width of the third partition structure layer on the substrate is smaller than the orthographic projection width of the first partition structure layer on the substrate.

[0018] In some embodiments of the display substrate, the orthographic projection of the first trench on the substrate is within the range of the orthographic projection of the third partition structure layer on the substrate.

[0019] In some embodiments of the display substrate, the number of the first trenches is two.

[0020] In some embodiments of the display substrate, the third partition structure layer has a third trench, the first trench is connected to the third trench, the third trench has a fifth width on the side away from the substrate, the third trench has a sixth width on the side close to the substrate, and the fifth width is greater than the sixth width.

[0021] In some embodiments of the display substrate, the fifth width is greater than the second width.

[0022] In some embodiments of the display substrate, there are two first trenches and two third trenches that correspond one-to-one with and are connected to the two first trenches.

[0023] In some embodiments of the display substrate, the partition structure further includes a fourth partition structure layer, which is disposed between the second partition structure layer and the third partition structure layer. The orthographic projection width of the fourth partition structure layer on the substrate is greater than the orthographic projection width of the second partition structure layer on the substrate, and the orthographic projection width of the fourth partition structure layer on the substrate is greater than the orthographic projection width of the third partition structure layer on the substrate.

[0024] In some embodiments of the display substrate, the fourth partition structure layer has a seventh surface away from the substrate and an eighth surface close to the substrate, wherein the orthographic projection width of the seventh surface on the substrate is smaller than the orthographic projection width of the eighth surface on the substrate.

[0025] In some embodiments of the display substrate, the second isolation structure layer has a third surface remote from the substrate, and the distance from the periphery of the orthographic projection of the fourth isolation structure layer on the substrate to the periphery of the orthographic projection of the third surface on the substrate is 0.1 μm to 0.5 μm.

[0026] In some embodiments of the display substrate, the partition structure further includes a third partition structure layer, which is disposed between the first partition structure layer and the second partition structure layer. The orthographic projection width of the third partition structure layer on the substrate is greater than the orthographic projection width of the second partition structure layer on the substrate, and the orthographic projection width of the third partition structure layer on the substrate is less than the orthographic projection width of the first partition structure layer on the substrate.

[0027] The third partition structure layer has a third groove, which is connected between the first groove and the third groove;

[0028] The third trench has a fifth width on the side away from the substrate and a sixth width on the side closer to the substrate, wherein the fifth width is greater than the sixth width.

[0029] In some embodiments of the display substrate, the fifth width is greater than the second width;

[0030] The third width is greater than the sixth width.

[0031] In some embodiments of the display substrate, the third partition structure layer has a fifth surface away from the substrate and a sixth surface close to the substrate, wherein the orthographic projection width of the fifth surface on the substrate is smaller than the orthographic projection width of the sixth surface on the substrate.

[0032] In some embodiments of the display substrate, the second isolation structure layer has a third surface remote from the substrate, and the distance from the periphery of the orthographic projection of the first isolation structure layer on the substrate to the periphery of the orthographic projection of the third surface on the substrate is 0.2 μm to 1.2 μm.

[0033] In some embodiments of the display substrate, the third isolation structure layer has a fifth surface remote from the substrate, and the distance from the periphery of the orthographic projection of the first isolation structure layer on the substrate to the periphery of the orthographic projection of the fifth surface on the substrate is 0.1 μm to 0.8 μm.

[0034] In some embodiments of the display substrate, the pixel definition layer includes a first definition layer and a second definition layer, wherein the first definition layer is disposed on the substrate and the second definition layer is disposed on the side of the first definition layer away from the substrate.

[0035] The first defining layer is made of organic material, and the second defining layer is made of inorganic material.

[0036] In some embodiments of the display substrate, the partition structure has a mesh-like structure.

[0037] In some embodiments of the display substrate, the partition structure is located between the pixel openings and is disposed around the pixel openings.

[0038] In some embodiments of the display substrate, one or more of the aforementioned partition structures are present between the pixel openings.

[0039] In some embodiments of the display substrate, the mesh structure has mesh openings, the mesh openings having the same shape as the pixel openings, and the orthographic projection of the pixel openings on the substrate is located within the orthographic projection of the mesh openings on the substrate and does not overlap.

[0040] In some embodiments of the display substrate, at least one of the partition structures is present at the intersection of the geometric center lines connecting four adjacent pixel openings.

[0041] In some embodiments of the display substrate, the display substrate further includes a light-emitting functional layer located within the pixel opening;

[0042] The second electrode is located on the side of the light-emitting functional layer away from the substrate, and the second electrode is coupled to the second isolation structure layer of the isolation structure.

[0043] An encapsulation layer is located on the side of the second electrode away from the substrate, and the encapsulation layer covers the pixel opening and the partition structure;

[0044] An etch barrier layer is disposed on the side of the encapsulation layer away from the substrate, and the etch barrier layer is made of a transparent material.

[0045] In some embodiments of the display substrate, the pixel opening includes a first color pixel opening and a second color pixel opening, and the etching barrier layer includes a first color etching barrier layer and a second color etching barrier layer. The orthogonal projection of the first color etching barrier layer on the substrate at least covers the first color pixel opening, and the orthogonal projection of the second color etching barrier layer on the substrate at least covers the orthogonal projection of the second color pixel opening on the substrate.

[0046] In some embodiments of the display substrate, the first color etching barrier layer and the second color etching barrier layer are made of different materials.

[0047] In some embodiments of the display substrate, the first color etch stop layer and the second color etch stop layer have different thicknesses.

[0048] In some embodiments of the display substrate, the pixel opening further includes a third color pixel opening, and the etching barrier layer is not disposed above the third color pixel opening.

[0049] In some embodiments of the display substrate, the orthogonal projection of the etch barrier layer on the substrate also covers the orthogonal projection of the pixel definition layer on the substrate between the first color pixel opening and the second color pixel opening.

[0050] In some embodiments of the display substrate, the second electrode includes a cathode layer and an auxiliary cathode layer.

[0051] This disclosure also provides a display device, including the display substrate described above.

[0052] This disclosure also provides a method for preparing a display substrate, including:

[0053] A first electrode is formed on a substrate.

[0054] A pixel definition layer is formed on the side of the first electrode away from the substrate, the pixel definition layer defining a pixel opening that exposes at least a portion of the first electrode;

[0055] A partition structure is formed on the side of the pixel definition layer away from the substrate.

[0056] The partition structure includes a first partition structure layer and a second partition structure layer located between the first partition structure layer and the substrate, wherein the orthographic projection width of the first partition structure layer on the substrate is greater than the orthographic projection width of the second partition structure layer on the substrate.

[0057] The first partition structure layer has a first trench, the first trench having a first width on the side away from the substrate, and the first trench having a second width on the side closer to the substrate, the first width being greater than the second width.

[0058] In some embodiments of the method for preparing the display substrate, the method further includes:

[0059] Before forming a partition structure on the side of the pixel definition layer away from the substrate, an anode protection layer is formed on the side of the pixel definition layer away from the substrate, the anode protection layer being made of an inorganic material.

[0060] In some embodiments of the method for preparing the display substrate, the second partition structure layer has a second trench, and the first trench communicates with the second trench.

[0061] In some embodiments of the method for fabricating the display substrate, forming a partition structure on the side of the pixel definition layer away from the substrate includes:

[0062] A third partition structure layer is formed between the first partition structure layer and the second partition structure layer, wherein the orthographic projection width of the third partition structure layer on the substrate is smaller than the orthographic projection width of the first partition structure layer on the substrate.

[0063] The third partition structure layer has a third groove, and the first groove is connected to the third groove.

[0064] In some embodiments of the method for fabricating the display substrate, forming a partition structure on the side of the pixel definition layer away from the substrate further includes:

[0065] A fourth partition structure layer is formed between the second partition structure layer and the third partition structure layer. The orthographic projection width of the fourth partition structure layer on the substrate is greater than the orthographic projection width of the second partition structure layer on the substrate, and the orthographic projection width of the fourth partition structure layer on the substrate is greater than the orthographic projection width of the third partition structure layer on the substrate.

[0066] In some embodiments of the method for fabricating the display substrate, forming a pixel definition layer on the side of the first electrode away from the substrate includes:

[0067] A first defining layer is formed on the side of the first electrode away from the substrate.

[0068] A second definition layer is formed on the side of the first definition layer away from the substrate.

[0069] The first defining layer is made of organic material, and the second defining layer is made of inorganic material.

[0070] In some embodiments of the method for preparing the display substrate, the method further includes:

[0071] A light-emitting functional layer is formed on the side of the partition structure away from the substrate, and the light-emitting functional layer is located inside the pixel opening;

[0072] A second electrode is formed on the side of the light-emitting functional layer away from the substrate, and the second electrode is coupled to the second isolation structure layer of the isolation structure.

[0073] An encapsulation layer is formed on the side of the second electrode away from the substrate, the encapsulation layer covering the pixel opening and the partition structure;

[0074] An etch barrier layer is formed on the side of the encapsulation layer away from the substrate, and the etch barrier layer is made of a transparent material.

[0075] In some embodiments of the method for fabricating the display substrate, forming a second electrode on the side of the light-emitting functional layer away from the substrate includes:

[0076] A cathode layer on the side of the light-emitting functional layer away from the substrate;

[0077] An auxiliary cathode layer is formed on the side of the cathode layer away from the substrate.

[0078] This disclosure provides an exemplary embodiment of a display substrate and its fabrication method, as well as a display device. The partition structure of the display substrate includes a first partition structure layer and a second partition structure layer located between the first partition structure layer and a substrate. The orthographic projection width of the first partition structure layer on the substrate is greater than the orthographic projection width of the second partition structure layer on the substrate, enabling the partition structure to form an undercut structure around the pixel opening. The first partition structure layer has a first trench. Thus, the undercut structure and the first trench increase the contact area between the partition structure and the encapsulation layer, enhance the adhesion of the encapsulation layer, reduce the risk of encapsulation layer peeling, and also enhance the encapsulation effect, reducing the risk of water and oxygen intruding from the gap between the partition structure and the encapsulation layer, thereby enhancing the reliability of the light-emitting device.

[0079] After reading and understanding the accompanying diagrams and detailed descriptions, the other aspects can be understood. Attached Figure Description

[0080] The accompanying drawings are used to provide an understanding of the technical solutions of this disclosure and form part of the specification. They are used together with the embodiments of this disclosure to explain the technical solutions of this disclosure and do not constitute a limitation on the technical solutions of this disclosure.

[0081] Figure 1 is a schematic diagram of a display device;

[0082] Figure 2 is a schematic diagram of a planar structure of a display substrate;

[0083] Figure 3 is a cross-sectional structural diagram of a display substrate according to an embodiment of the present disclosure;

[0084] Figure 4a is a schematic diagram of the fabrication process of the display substrate according to an embodiment of the present disclosure after the formation of the driving circuit layer, the first electrode and the first definition layer;

[0085] Figure 4b is a schematic diagram of the fabrication process of the display substrate according to an embodiment of the present disclosure after the formation of the second pixel definition film;

[0086] Figure 4c is a schematic diagram of the fabrication process of the display substrate after the formation of the second defining layer according to an embodiment of the present disclosure;

[0087] Figure 4d is a schematic diagram of the substrate fabrication process after the formation of the anode protective layer in an embodiment of this disclosure;

[0088] Figure 4e is a schematic diagram of the fabrication process of the display substrate according to an embodiment of the present disclosure after the formation of the second conductive film and the barrier structure film;

[0089] Figures 4f to 4k are schematic diagrams showing the fabrication process of the display substrate according to the embodiments of the present disclosure after the formation of the second partition structure layer, the partition structure layer and the trench;

[0090] Figure 41 is a schematic diagram of the fabrication process of the display substrate according to an embodiment of the present disclosure after the formation of the light-emitting functional layer, the second electrode, the encapsulation layer and the etch barrier layer;

[0091] Figure 5 is a schematic diagram showing the formation of the light-emitting functional layer, the second electrode, and the encapsulation layer by a thermal evaporation coating process during the fabrication of the display substrate according to an embodiment of this disclosure.

[0092] Figures 6a to 6d are schematic planar views of the positional relationship between pixel arrangement and partition structure in the display substrate according to the embodiments of this disclosure;

[0093] Figures 7a and 7b are schematic plan views of the second partition structure layer in the display substrate according to an embodiment of the present disclosure;

[0094] Figure 8 is a scanning electron microscope image of the substrate fabrication process of the present disclosure after the formation of the second partition structure layer, the partition structure layer and the trench;

[0095] Figure 9a is a scanning electron microscope image of the patterned second color encapsulation film during the fabrication process of an existing display substrate;

[0096] Figure 9b is a scanning electron microscope image of the patterned second color encapsulation film during the fabrication process of the display substrate according to an embodiment of this disclosure.

[0097] Explanation of reference numerals in the attached drawings: 101, Substrate; 102, Driving circuit layer; 103, Second pixel definition film; 104, Anode protective layer; 105, Second conductive film; 106, First isolation structure film; 107, Third isolation structure film; 11, First color anode; 12, Second color anode; 13, Third color anode; 21, First color cathode; 22, Second color cathode; 23, Third color cathode; 31, First light-emitting functional layer; 32, Second light-emitting functional layer; 33, Third light-emitting functional layer; 41, First color encapsulation layer; 42, Second color encapsulation layer; 43, Third color encapsulation layer; 44, Encapsulation structure layer; 50, Isolation structure; 51, Second isolation structure layer; 511, Third surface; 512, Fourth surface; 513, Second isolation structure layer portion; 52. Undercut structure; 53. First partition structure layer; 531. First surface; 532. Second surface; 533. First partition structure layer portion; 54. Third partition structure layer; 541. Fifth surface; 542. Sixth surface; 543. Third partition structure layer portion; 55. Fourth partition structure layer; 551. Seventh surface; 552. Eighth surface; 61. First definition layer; 62. Second definition layer; 70. Open mask; 81. First color etching barrier layer; 82. Second color etching barrier layer; 90. Evaporation source; 100. First trench; 200. Second trench; 300. Third trench; 400. Mesh opening. Detailed Implementation

[0098] To make the objectives, technical solutions, and advantages of this disclosure clearer, embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. Note that the implementation methods can be carried out in many different forms. Those skilled in the art will readily understand that the methods and content can be varied in various forms without departing from the spirit and scope of this disclosure. Therefore, this disclosure should not be construed as limited to the content described in the following embodiments. Without conflict, the embodiments and features in the embodiments of this disclosure can be arbitrarily combined with each other.

[0099] The scale of the figures in this disclosure can be used as a reference in actual manufacturing processes, but is not limited thereto. For example, the aspect ratio of the channel, the thickness and spacing of each film layer, and the width and spacing of each signal line can be adjusted according to actual needs. The number of pixels in the display substrate and the number of sub-pixels in each pixel are not limited to the quantities shown in the figures. The figures described in this disclosure are only schematic diagrams of the structure, and one aspect of this disclosure is not limited to the shapes or values ​​shown in the figures.

[0100] The ordinal numbers “first,” “second,” and “third” used in this specification are used to avoid confusion among the constituent elements, not to limit their quantity.

[0101] In this specification, for convenience, terms such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer" are used to indicate orientation or positional relationships in conjunction with the accompanying drawings. This is solely for the purpose of facilitating the description and simplification, and does not imply that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this disclosure. The positional relationships of the constituent elements may be appropriately varied depending on the orientation of each constituent element being described. Therefore, the use of terms not limited to those described in the specification may be appropriately replaced as needed.

[0102] In this specification, unless otherwise expressly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they may refer to a fixed connection, a detachable connection, or an integral connection; a mechanical connection or an electrical connection; a direct connection, an indirect connection via an intermediate component, or a connection within two components. Those skilled in the art will understand the specific meaning of these terms in this disclosure based on the specific circumstances.

[0103] In this specification, a transistor is a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain electrode) and the source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to the region through which current primarily flows.

[0104] In this specification, the first electrode can be the drain electrode and the second electrode can be the source electrode, or vice versa. In cases where transistors with opposite polarities are used or the current direction changes during circuit operation, the functions of the "source electrode" and "drain electrode" are sometimes interchanged. Therefore, in this specification, the "source electrode" and "drain electrode" can be interchanged, and the "source terminal" and "drain terminal" can be interchanged.

[0105] In this specification, "electrical connection" includes the situation where components are connected together by elements that have a certain electrical function. There are no particular limitations on what constitutes an "electrical function," as long as it allows for the transmission and reception of electrical signals between the connected components. Examples of "electrical functions" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements with various functions.

[0106] In this specification, "parallel" refers to the state where the angle formed by two straight lines is greater than or equal to -10° and less than 10°, and therefore also includes the state where the angle is greater than or equal to -5° and less than 5°. Similarly, "perpendicular" refers to the state where the angle formed by two straight lines is greater than or equal to 80° and less than 100°, and therefore also includes the state where the angle is greater than or equal to 85° and less than 95°.

[0107] In this specification, the terms "film" and "layer" may be interchanged. For example, "conductive layer" may sometimes be replaced with "conductive film." Similarly, "insulating film" may sometimes be replaced with "insulating layer."

[0108] In this specification, circles, ellipses, rectangles, triangles, trapezoids, pentagons, or hexagons are not strictly defined. They can be approximate circles, ellipses, rectangles, triangles, trapezoids, pentagons, or hexagons. Small deformations due to tolerances are possible, as are chamfers, curved edges, and other deformations.

[0109] In this disclosure, “about” means a value that is not strictly limited and allows for process and measurement errors.

[0110] The inventors of this publication have discovered that in the photolithography pixelation process of AMOLED, the light-emitting devices in the atmospheric environment may fail due to the intrusion of water and oxygen. This is because the connection stability between the encapsulation layer and the isolation structure is poor, and water and oxygen can easily intrude from the gaps between the encapsulation layer and the isolation structure, leading to the failure of the light-emitting devices.

[0111] This disclosure provides a display substrate, which may include:

[0112] Substrate 101;

[0113] The first electrode is disposed on the substrate 101;

[0114] A pixel definition layer is disposed on the side of the first electrode away from the substrate 101. The pixel definition layer defines a pixel opening that exposes at least a portion of the first electrode.

[0115] The partition structure 50 is disposed on the side of the pixel definition layer away from the substrate 101;

[0116] The partition structure 50 may include a first partition structure layer 53 and a second partition structure layer 51 located between the first partition structure layer 53 and the substrate 101. The orthographic projection width L1 of the first partition structure layer 53 on the substrate 101 is greater than the orthographic projection width L2 of the second partition structure layer 51 on the substrate 101, such that the first partition structure layer 53 and the second partition structure layer 51 can form an undercut structure 52 around the pixel opening. The orthographic projection width L1 of the first partition structure layer 53 on the substrate 101 refers to the dimension of the orthographic projection of the first partition structure layer 53 on the substrate 101 along the first direction D1. The orthographic projection width L2 of the second partition structure layer 51 on the substrate 101 refers to the dimension of the orthographic projection of the second partition structure layer 51 on the substrate 101 along the first direction D1, as shown in Figure 3.

[0117] The first partition structure layer 53 has a first trench 100. The first trench 100 has a first width W1 on the side away from the substrate 101 and a second width W2 on the side closer to the substrate 101. The first width W1 is greater than the second width W2. The first width W1 refers to the dimension of the first trench 100 along the first direction D1 on the side away from the substrate 101. The second width W2 refers to the dimension of the first trench 100 along the first direction D1 on the side closer to the substrate 101, as shown in Figure 4j.

[0118] Figure 1 is a schematic diagram of a display device. As shown in Figure 1, the display device may include a timing controller, a data signal driver, a scan signal driver, and a pixel array. The pixel array may include multiple scan signal lines (S1 to Sm), multiple data signal lines (D1 to Dn), and multiple sub-pixels Pxij.

[0119] In an exemplary embodiment, the timing controller can provide grayscale values ​​and control signals of specifications suitable for the data signal driver to the data signal driver, and can provide clock signals, scan start signals, etc., of specifications suitable for the scan signal driver to the scan signal driver. The data signal driver can use the grayscale values ​​and control signals received from the timing controller to generate data voltages to be provided to the data signal lines D1, D2, D3, ..., Dn. For example, the data signal driver can sample the grayscale values ​​using a clock signal and apply the data voltage corresponding to the grayscale values ​​to the data signal lines D1 to Dn on a sub-pixel row basis, where n can be a natural number. The scan signal driver can generate scan signals to be provided to the scan signal lines S1, S2, S3, ..., Sm by receiving clock signals, scan start signals, etc., from the timing controller. For example, the scan signal driver can sequentially provide scan signals with on-level pulses to the scan signal lines S1 to Sm. For example, a scan signal driver can be configured as a shift register and can generate scan signals by sequentially transmitting scan start signals, provided in the form of on-level pulses, to the next stage circuit under the control of a clock signal, where m can be a natural number. A sub-pixel array can include multiple sub-pixels PXij. Each sub-pixel PXij can be connected to a corresponding data signal line and a corresponding scan signal line, where i and j can be natural numbers. A sub-pixel PXij can refer to a sub-pixel whose transistor is connected to the i-th scan signal line and to the j-th data signal line.

[0120] Figure 2 is a schematic diagram of a planar structure of a display device. As shown in Figure 2, the display area of ​​the display device may include a plurality of pixel units P arranged in a matrix along a first direction D1 and a second direction D2. At least one of the plurality of pixel units P may include a first sub-pixel P1 emitting a first color light, a second sub-pixel P2 emitting a second color light, and a third sub-pixel P3 emitting a third color light. The first sub-pixel P1 may include a pixel driving circuit and a first color light-emitting device. The second sub-pixel P2 may include a pixel driving circuit and a second color light-emitting device. The third sub-pixel P3 may include a pixel driving circuit and a third color light-emitting device. The pixel driving circuit in the sub-pixel is connected to a scan signal line and a data signal line respectively. The pixel driving circuit is configured to receive the data voltage transmitted by the data signal line under the control of the scan signal line and output a corresponding current to the display light-emitting device. The light-emitting device in the sub-pixel is connected to the pixel driving circuit of the sub-pixel respectively. The light-emitting device is configured to emit light of a corresponding brightness in response to the current output by the pixel driving circuit of the sub-pixel. Wherein, the first direction D1 and the second direction D2 are both parallel to the substrate 101, and the first direction D1 and the second direction D2 intersect each other, for example, the first direction D1 and the second direction D2 are perpendicular to each other.

[0121] In an exemplary embodiment, the first sub-pixel P1 can be a red sub-pixel emitting red (R) light, the second sub-pixel P2 can be a blue sub-pixel emitting blue (B) light, and the third sub-pixel P3 can be a green sub-pixel emitting green (G) light. In an exemplary embodiment, the shape of the sub-pixels can be any one or more of triangles, squares, rectangles, rhombuses, trapezoids, parallelograms, pentagons, hexagons, and other polygons. They can be arranged horizontally, vertically, in an X-shape, a cross shape, a triangular shape, a square shape, a diamond shape, or a delta shape, etc., and this disclosure does not limit the arrangement. The partition structure 50 is disposed in the non-light-emitting area between pixels to ensure that the pixel aperture ratio is not reduced. Different pixel arrangements have corresponding partition structure 50 design schemes, as shown in Figures 6a to 6d.

[0122] In an exemplary embodiment, a pixel unit may include four sub-pixels, which is not limited herein.

[0123] The display substrate of this disclosure will be illustrated by some exemplary embodiments below.

[0124] Figure 3 is a cross-sectional structural diagram of a display substrate according to an embodiment of the present disclosure. As shown in Figure 3, in a direction perpendicular to the display substrate (e.g., third direction D3), the display substrate may include: a substrate 101, a driving circuit layer 102 disposed on the substrate 101, a light-emitting structure layer disposed on the side of the driving circuit layer 102 away from the substrate 101, and an encapsulation structure layer 44 disposed on the side of the light-emitting structure layer away from the substrate 101. In some possible implementations, the display device may include other film layers, such as a color filter structure layer and a touch structure layer disposed on the encapsulation structure layer 44 away from the substrate 101, which is not limited herein.

[0125] In an exemplary embodiment, the substrate 101 can be a flexible substrate, such as polyimide (PI). The driving circuit layer 102 can be fabricated on the substrate 101 using silicon semiconductor processes (e.g., CMOS processes). The driving circuit layer 102 can include a gate driving circuit, an electrostatic discharge (ESD) protection circuit, an initialization circuit, a pixel internal compensation circuit, a pixel driving circuit, and wiring, etc. The wiring can include gate lines, initial signal lines, reference signal lines, data lines, a first power line (VDD), a second power line (VSS), etc. The gate driving circuit, the ESD protection circuit, the pixel internal compensation circuit, and the pixel driving circuit can all include transistors. The transistors can include a control electrode G, a first electrode S, and a second electrode D. The control electrode G, the first electrode S, and the second electrode D can be connected to corresponding connection electrodes through tungsten metal-filled vias (i.e., tungsten vias, W-vias), and can be connected to other electrical structures (such as wirings) through the connection electrodes.

[0126] In an exemplary embodiment, the light-emitting structure layer may include a plurality of light-emitting devices. Each light-emitting device may include at least a first electrode (anode), a light-emitting functional layer, and a second electrode (cathode). The first electrode may be connected to the second electrode D of a transistor via a connecting electrode. The light-emitting functional layer may be connected to the first electrode, and the second electrode may be connected to the light-emitting functional layer. The second electrode may be connected to a second power line (VSS). The light-emitting functional layer emits light under the drive of the first electrode and the second electrode.

[0127] In an exemplary embodiment, the light-emitting functional layer is located within the pixel opening. The second electrode is located on the side of the light-emitting functional layer away from the substrate 101, and the second electrode is coupled to the second isolation structure layer 51 of the isolation structure 50.

[0128] In an exemplary embodiment, the first electrode may include a first color anode 11, a second color anode 12, and a third color anode 13. The second electrode may include a first color cathode 21, a second color cathode 22, and a third color cathode 23. The light-emitting functional layer may include a first light-emitting functional layer 31, a second light-emitting functional layer 32, and a third light-emitting functional layer 33. The first color anode 11, the first light-emitting functional layer 31, and the first color cathode 21 form a first color light-emitting device for a first sub-pixel. The second color anode 12, the second light-emitting functional layer 32, and the second color cathode 22 form a second color light-emitting device for a second sub-pixel. The third color anode 13, the third light-emitting functional layer 33, and the third color cathode 23 form a third color light-emitting device for a third sub-pixel.

[0129] In an exemplary embodiment, the pixel opening may include a first color pixel opening, a second color pixel opening, and a third color pixel opening.

[0130] The first color pixel opening exposes the first color anode 11, and the first light-emitting functional layer 31 is located inside the first color pixel opening and covers the side of the first color anode 11 away from the substrate 101. The first color cathode 21 is located on the side of the first light-emitting functional layer 31 away from the substrate 101 and is coupled to the second isolation structure layer 51.

[0131] The second color pixel opening exposes the second color anode 12, and the second light-emitting functional layer 32 is located within the second color pixel opening and covers the side of the second color anode 12 away from the substrate 101. The second color cathode 22 is located on the side of the second light-emitting functional layer 32 away from the substrate 101 and is coupled to the second isolation structure layer 51.

[0132] The third color pixel opening exposes the third color anode 13, and the third light-emitting functional layer 33 is located within the third color pixel opening and covers the side of the third color anode 13 away from the substrate 101. The third color cathode 23 is located on the side of the third light-emitting functional layer 33 away from the substrate 101 and is coupled to the second isolation structure layer 51.

[0133] In an exemplary embodiment, the first electrode may be a stacked structure of indium tin oxide (ITO) / silver (Ag) / indium tin oxide (ITO).

[0134] In an exemplary embodiment, the first light-emitting functional layer 31 may include at least one first light-emitting layer (EML), and any one or more of the following: hole injection layer (HIL), hole transport layer (HTL), electron blocking layer (EBL), hole blocking layer (HBL), electron transport layer (ETL), electron injection layer (EIL), and charge production layer (CGL). The first light-emitting layer is red.

[0135] In an exemplary embodiment, the second light-emitting functional layer 32 may include at least one second light-emitting layer (EML), and any one or more of the following: hole injection layer (HIL), hole transport layer (HTL), electron blocking layer (EBL), hole blocking layer (HBL), electron transport layer (ETL), electron injection layer (EIL), and charge production layer (CGL). The second light-emitting layer is blue.

[0136] In an exemplary embodiment, the third light-emitting functional layer 33 may include at least one third light-emitting layer (EML), and any one or more of the following: hole injection layer (HIL), hole transport layer (HTL), electron blocking layer (EBL), hole blocking layer (HBL), electron transport layer (ETL), electron injection layer (EIL), and charge production layer (CGL). The third light-emitting layer is green.

[0137] In an exemplary embodiment, the second electrode may include a cathode layer and an auxiliary cathode layer.

[0138] In an exemplary embodiment, the cathode layer can be a co-evaporated metal thin-film cathode with high transparency and low work function. Furthermore, it is ensured that the co-evaporated metal thin-film cathode can be removed by a dry etching process. The material combination of the co-evaporated metal thin film can be, but is not limited to, magnesium (Mg) and aluminum (Al), ytterbium (Yb) and aluminum (Al), and lithium (Li) and aluminum (Al). The volume ratio between the material combinations can be approximately 1:9 to 4:6, for example, approximately 3.5:9. The thickness of the cathode layer can be approximately 0.008 μm to 0.020 μm, for example, approximately 0.014 μm.

[0139] In an exemplary embodiment, the auxiliary cathode layer can be formed by sputtering amorphous indium tin oxide (IZO). Utilizing its good film coverage, electrical connection between the cathode layer and the isolation structure 50 (or the second isolation structure layer 51) is achieved. Furthermore, amorphous indium tin oxide (IZO) can be used as the coupling light-emitting layer of the cathode layer to reduce the surface plasmon polarization (SPP) mode of the metal thin film of the cathode layer, thereby improving the enhancement effect of external light emission from the light-emitting device. The thickness of the auxiliary cathode layer can be approximately 0.05 μm to 0.3 μm. For example, the thickness of the auxiliary cathode layer can be approximately 0.175 μm.

[0140] In an exemplary embodiment, the display substrate may further include an encapsulation layer located on the side of the second electrode away from the substrate 101 and covering the pixel opening and the partition structure 50.

[0141] Due to the requirements of the photolithography process, after each color (R, G, B) light-emitting device is fabricated, it needs to be removed from the vacuum chamber and subjected to subsequent exposure and etching processes in a nitrogen or atmospheric environment. To ensure that the light-emitting devices are adequately and reliably protected during this process, and to minimize the difficulty of subsequent etching processes, a single-layer inorganic thin film can be selected as the encapsulation layer, such as silicon nitride (SiNx) or silicon oxynitride (SiOxNy). The thickness of the encapsulation layer can be approximately 1.5 times the thickness of the second barrier structure layer.

[0142] The encapsulation layer can also be a stacked inorganic film layer, and the thickness of the encapsulation layer can be approximately 0.4 μm to 1.2 μm, such as silicon nitride (SiNx) (TFE CVD) / aluminum oxide (Al2O3) (ALD).

[0143] It can be understood that in other embodiments, the encapsulation layer can also be a more complex structure, for example, it can be a three-layer inorganic thin film; it can achieve better micro-encapsulation characteristics (e.g., better step coverage and foreign matter encapsulation), and finally achieve pixel-level ultra-thin thin film encapsulation, ensuring that the underlying device can be fully protected from damage when the light-emitting device is etched and removed.

[0144] By employing a triple deposition and triple photolithography process, RGB full-color OLED light-emitting devices can be fabricated. This allows for independent pixel fabrication without a high-precision fine metal mask (FMM), achieving higher dimensional accuracy. The effective light-emitting area (aperture ratio) of AMOLED increases from approximately 30% of traditional FMM to around 60%, and pixel density can be increased to over 1500ppi*. This technology can be extended to silicon-based MicroOLED, replacing the existing white light plus color filter (WOLED+CF) solution. Furthermore, it can be combined with dual-layer (tandem) RGB OLED light-emitting devices, achieving six times the lifespan of light-emitting devices or four times the brightness compared to FMM AMOLED. Moreover, by utilizing the inter-pixel separation structure 50, the color mixing problem between sub-pixels and the crosstalk problem between sub-pixels during low-brightness driving can be fundamentally solved, further improving display clarity, color performance (color gamut), uniformity, and other image quality.

[0145] In an exemplary embodiment, the encapsulation structure layer 44 can be encapsulated using a thin film encapsulation (TFE) method, which can ensure that external moisture cannot enter the light-emitting structure layer.

[0146] In an exemplary embodiment, the encapsulation structure layer 44 may include an organic material, such as a resin.

[0147] In an exemplary embodiment, the encapsulation structure layer 44 can be a multi-layer structure. For example, the encapsulation structure layer 44 may include a first inorganic dielectric layer and a second inorganic dielectric layer. The first inorganic dielectric layer is located on the side of the second inorganic dielectric layer near the substrate 101. The first inorganic dielectric layer can be silicon oxide, and the second inorganic dielectric layer can be silicon nitride.

[0148] In an exemplary embodiment, a pixel definition layer is disposed on the side of the first electrode away from the substrate 101, and the pixel definition layer defines a pixel opening that exposes at least a portion of the first electrode.

[0149] In an exemplary embodiment, on a plane perpendicular to the substrate 101, the pixel definition layer may include a first definition layer 61 disposed on the side of the driving circuit layer 102 away from the substrate 101 and a second definition layer 62 disposed on the side of the first definition layer 61 away from the substrate 101.

[0150] In an exemplary embodiment, the first defining layer 61 may be made of an organic material, such as resin. The first defining layer 61 overlaps with the orthographic projection of the first electrode on the substrate 101. The first defining layer 61 may include a first top surface and first side surfaces connected to the first top surface. The first top surface is the surface of the first defining layer 61 away from the substrate 101, and the first side surfaces are located on opposite sides of the first top surface.

[0151] In an exemplary embodiment, the first defining layer 61 can be fabricated by an exposure and development process, and the thickness of the first defining layer 61 can be approximately 1.4 μm to 1.6 μm. For example, the thickness of the first defining layer 61 can be approximately 1.5 μm. Here, the thickness is the dimension along the third direction D3.

[0152] In an exemplary embodiment, the second defining layer 62 may be made of an inorganic material by magnetron sputtering, such as silicon nitride (SiNx), silicon oxide (SiOx), or silicon oxynitride (SiOxNy). The thickness of the second defining layer 62 may be approximately 0.1 μm to 0.3 μm. For example, the thickness of the second defining layer 62 may be approximately 0.2 μm. The thickness is the dimension along the third direction D3. The second defining layer 62 overlaps with the orthographic projection of the first electrode on the substrate 101; the second defining layer 62 also overlaps with the orthographic projection of the first defining layer 61 on the substrate 101. For example, the orthographic projection of the second defining layer 62 on the substrate 101 covers the orthographic projection of the first defining layer 61 on the substrate 101, and the second defining layer 62 covers the first top surface and the first side surface of the first defining layer 61. The second defining layer 62 may include a second top surface and a second side surface connected to the second top surface. The second top surface is the surface of the second defining layer 62 away from the substrate 101, and the second top surface covers the first top surface. The second side surface is located on opposite sides of the second top surface, and the second side surface covers the first side surface. The second defining layer 62 is configured to protect the first defining layer 61.

[0153] In an exemplary embodiment, the first partition structure layer 53 has a first trench 100. The first trench 100 has a first width W1 on the side away from the substrate 101 and a second width W2 on the side closer to the substrate 101. The first width W1 is greater than the second width W2. This results in the first trench 100 having different widths at its two ends along a direction perpendicular to the substrate 101 (third direction D3), i.e., the width of the first trench 100 on the side away from the substrate 101 is greater than the width of the first trench 100 on the side closer to the substrate 101. The first trench 100 has an inverted trapezoidal shape that is wider at the top and narrower at the bottom. This allows the arrangement of the first trench 100 to increase the connection area between the encapsulation layer and the partition structure 50, thereby improving connection stability and sealing.

[0154] In an exemplary embodiment, the number of first trenches 100 can be one or more, which can further increase the connection area between the encapsulation layer and the partition structure 50, improving connection stability and sealing. One or more first trenches 100 can be symmetrically arranged in the middle region of the partition structure 50, and the orthographic projection of the first trench 100 on the substrate 101 lies within the orthographic projection of the partition structure 50 on the substrate 101. In this embodiment, the number of first trenches 100 can be two. The cross-section of the first trench 100 in the direction perpendicular to the substrate 101 can include an inverted trapezoid.

[0155] In an exemplary embodiment, the second barrier structure layer 51 may be made of a conductive material, such as one or more of titanium (Ti), aluminum (Al), molybdenum (Mo), copper (Cu), aluminum-neodymium alloy (AlNd), indium tin oxide (ITO), and indium gallium zinc oxide (IGZO). This ensures high conductivity of the second barrier structure layer 51, while also ensuring that the second barrier structure layer 51 is resistant to corrosion and easy to etch. In an exemplary embodiment, the thickness of the second barrier structure layer 51 is 0.6 μm to 0.8 μm.

[0156] In an exemplary embodiment, the second isolation structure layer 51 is disposed on the side of the pixel definition layer away from the substrate 101 and is electrically connected to the second electrode. For example, the second isolation structure layer 51 is disposed on the side of the second definition layer 62 away from the substrate 101. The orthographic projection of the first trench 100 on the substrate 101 is within the range of the orthographic projection of the second isolation structure layer 51 on the substrate 101.

[0157] The first partition structure layer 53 is disposed on the side of the second partition structure layer 51 away from the substrate 101. The first partition structure layer 53 has a first surface 531 away from the substrate 101 and a second surface 532 close to the substrate 101. The orthographic projection width of the first surface 531 on the substrate 101 is smaller than the orthographic projection width of the second surface 532 on the substrate 101. This allows the cross-section of the first partition structure layer 53 in the direction perpendicular to the substrate 101 to include a trapezoid.

[0158] The sidewall of the first partition structure layer 53 near the pixel opening and the sidewall of the second partition structure layer 51 near the pixel opening form an undercut structure 52.

[0159] The method for preparing the substrate disclosed herein, through the first trench 100 and the undercut structure 52, can increase the contact area between the partition structure 50 and the encapsulation layer, enhance the adhesion of the encapsulation layer, and reduce the risk of encapsulation layer peeling.

[0160] The method for preparing the substrate disclosed herein, through the first trench 100 and the undercut structure 52, can enhance the encapsulation effect, reduce the risk of water, oxygen, etc. entering from the gap between the isolation structure 50 and the encapsulation layer, and enhance the reliability of the light-emitting device.

[0161] In an exemplary embodiment, the second partition structure layer 51 has a second trench 200, which communicates with the first trench 100. The second trench 200 has a third width W3 on the side away from the substrate 101 and a fourth width W4 on the side near the substrate 101, wherein the third width W3 is greater than the fourth width W4. The third width W3 refers to the dimension of the second trench 200 along the first direction D1 on the side away from the substrate 101. The fourth width W4 refers to the dimension of the second trench 200 along the first direction D1 on the side near the substrate 101, as shown in FIG4j. This results in different widths at both ends of the second trench 200 along the direction perpendicular to the substrate 101 (third direction D3), i.e., the width of the second trench 200 on the side away from the substrate 101 is greater than the width of the second trench 200 on the side near the substrate 101, and the second trench 200 has an inverted trapezoidal shape that is wider at the top and narrower at the bottom.

[0162] The first trench 100 penetrates the first partition structure layer 53 and communicates with the second trench 200. The second trench 200 penetrates the second partition structure layer 51 and extends to the side of the pixel definition layer away from the substrate 101, as shown in Figure 4j.

[0163] In an exemplary embodiment, the cross-section of the first trench 100 and the second trench 200 in the direction perpendicular to the substrate 101 may include two connected inverted trapezoids. The third width W3 is greater than the second width W2. This causes the two connected inverted trapezoids to gradually decrease in the direction perpendicular to the substrate 101, abruptly increase at the junction of the first trench 100 and the second trench 200, and then gradually decrease until the pixel definition layer is away from the substrate 101.

[0164] In an exemplary embodiment, the second partition structure layer 51 has a third surface 511 away from the substrate 101 and a fourth surface 512 close to the substrate 101. The orthographic projection width of the third surface 511 on the substrate 101 is greater than or less than the orthographic projection width of the fourth surface 512 on the substrate 101. This allows the cross-section of the second partition structure layer 51 in the direction perpendicular to the substrate 101 to include a trapezoidal or inverted trapezoidal shape.

[0165] In an exemplary embodiment, the distance from the periphery of the orthographic projection of the first partition structure layer 53 on the substrate 101 to the periphery of the orthographic projection of the third surface 511 on the substrate 101 is 0.2 μm to 1.2 μm.

[0166] In an exemplary embodiment, the partition structure 50 may further include a third partition structure layer 54, which is disposed between the first partition structure layer 53 and the second partition structure layer 51. The orthographic projection width L3 of the third partition structure layer 54 on the substrate 101 is smaller than the orthographic projection width L1 of the first partition structure layer 53 on the substrate 101, such that the first partition structure layer 53, the second partition structure layer 51, and the third partition layer 54 can form an undercut structure 52 around the pixel opening. The orthographic projection width L3 of the third partition structure layer 54 on the substrate 101 refers to the dimension of the orthographic projection of the third partition structure layer 54 on the substrate 101 along the first direction D1, as shown in FIG4f.

[0167] In an exemplary embodiment, the orthogonal projection width L3 of the third partition structure layer 54 on the substrate 101 is greater than the orthogonal projection width L2 of the second partition structure layer 51 on the substrate 101.

[0168] In an exemplary embodiment, the third partition structure layer 54 has a fifth surface 541 away from the substrate 101 and a sixth surface 542 close to the substrate 101. The orthographic projection width of the fifth surface 541 on the substrate 101 is smaller than the orthographic projection width of the sixth surface 542 on the substrate 101. This allows the cross-section of the third partition structure layer 54 in the direction perpendicular to the substrate 101 to include a trapezoidal shape.

[0169] In an exemplary embodiment, the distance from the periphery of the orthographic projection of the first partition structure layer 53 on the substrate 101 to the periphery of the orthographic projection of the fifth surface 541 on the substrate 101 is 0.1 μm to 0.8 μm.

[0170] In an exemplary embodiment, the orthographic projection of the first trench 100 onto the substrate 101 is within the range of the orthographic projection of the third partition structure layer 54 onto the substrate 101.

[0171] In an exemplary embodiment, the third partition structure layer 54 has a third trench 300, which is connected to the first trench 100. The third trench 300 has a fifth width W5 on the side away from the substrate 101 and a sixth width W6 on the side near the substrate 101, wherein the fifth width W5 is greater than the sixth width W6. The fifth width W5 refers to the dimension of the third trench 300 along the first direction D1 on the side away from the substrate 101. The sixth width W6 refers to the dimension of the third trench 300 along the first direction D1 on the side near the substrate 101, as shown in FIG. 4g. This results in the third trench 300 having different widths at its two ends along the direction perpendicular to the substrate 101 (third direction D3), i.e., the width of the third trench 300 on the side away from the substrate 101 is greater than the width of the third trench 300 on the side near the substrate 101, and the third trench 300 has an inverted trapezoidal shape that is wider at the top and narrower at the bottom.

[0172] In an exemplary embodiment, the first trench 100 penetrates the first partition structure layer 53 and communicates with the third trench 300. The third trench 300 penetrates the third partition structure layer 54 and extends to the side of the second partition structure layer 51 away from the substrate 101, as shown in FIG4g. The cross-sections of the first trench 100 and the third trench 300 in the direction perpendicular to the substrate 101 may include two connected inverted trapezoids. The fifth width W5 is greater than the second width W2. This causes the two connected inverted trapezoids to gradually decrease in the direction perpendicular to the substrate 101, abruptly increase at the connection point of the first trench 100 and the third trench 300, and then gradually decrease to the side of the second partition structure layer 51 away from the substrate 101.

[0173] In an exemplary embodiment, the number of first trenches 100 can be one or more, and the number of third trenches 300 is the same as the number of first trenches 100 and they are connected in a one-to-one correspondence. This allows the trench structure (first trenches 100 and third trenches 300) of the partition structure 50 to extend along a direction perpendicular to the substrate 101, further increasing the connection area between the encapsulation layer and the partition structure 50, and improving connection stability and sealing. The connection structure of one or more first trenches 100 and second trenches 200 can be symmetrically arranged in the middle region of the partition structure 50. In this embodiment, the number of first trenches 100 can be two. The number of third trenches 300 can be two and they are connected in a one-to-one correspondence with the two first trenches 100. The cross-sections of the first trenches 100 and third trenches 300 in the direction perpendicular to the substrate 101 can include inverted trapezoids, as shown in FIG4i.

[0174] In an exemplary embodiment, the third trench 300 is connected between the first trench 100 and the second trench 200. The first trench 100 penetrates the first partition structure layer 53 and communicates with the third trench 300. The third trench 300 penetrates the third partition structure layer 54 and communicates with the second trench 200. The second trench 200 penetrates the second partition structure layer 51 and extends to the pixel definition layer on the side away from the substrate 101, as shown in FIG4h. The cross-sections of the first trench 100, the second trench 200, and the third trench 300 in the direction perpendicular to the substrate 101 may include three connected inverted trapezoids. The fifth width W5 is greater than the second width W2. The third width W3 is greater than the sixth width W6. This causes the three connected inverted trapezoids to gradually decrease in the direction perpendicular to the substrate 101, then abruptly increase at the connection between the first trench 100 and the third trench 300, and then gradually decrease to the connection between the third trench 300 and the second trench 200, where they abruptly increase again, and then gradually decrease to the side of the pixel definition layer away from the substrate 101.

[0175] In an exemplary embodiment, the number of first trenches 100 can be one or more, and the number of second trenches 200 can be one or more, corresponding one-to-one with the first trenches 100. The number of third trenches 300 is the same as the number of first trenches 100 and second trenches 200, and they are connected one-to-one between the first trenches 100 and the second trenches 200, so that the trench structure (first trench 100, second trench 200 and third trench 300) of the partition structure 50 extends further along the direction perpendicular to the substrate 101, which can further increase the connection area between the encapsulation layer and the partition structure 50, and improve the connection stability and sealing performance. The connecting structure of one or more first trenches 100, second trenches 200 and third trenches 300 can be symmetrically arranged in the middle region of the partition structure 50. In this embodiment, the number of first trenches 100 can be two. The number of second trenches 200 can be two. The number of third trenches 300 can be two, and they are connected one-to-one between the first trenches 100 and the second trenches 200. The cross-sections of the first trench 100, the second trench 200, and the third trench 300 in the direction perpendicular to the substrate 101 may be inverted trapezoidal, as shown in Figure 4h.

[0176] In an exemplary embodiment, the partition structure 50 may further include a fourth partition structure layer 55, which is disposed between the second partition structure layer 51 and the third partition structure layer 54. The orthographic projection width L4 of the fourth partition structure layer 55 on the substrate 101 is greater than the orthographic projection width L2 of the second partition structure layer 51 on the substrate 101, and the orthographic projection width L4 of the fourth partition structure layer 55 on the substrate 101 is greater than the orthographic projection width L3 of the third partition structure layer 54 on the substrate 101, such that the first partition structure layer 53, the second partition structure layer 51, the third partition structure layer 54, and the fourth partition structure layer 55 can form an undercut structure 52 around the pixel opening. The orthographic projection width L4 of the fourth partition structure layer 55 on the substrate 101 refers to the dimension of the orthographic projection of the fourth partition structure layer 55 on the substrate 101 along the first direction D1, as shown in FIG4k.

[0177] In an exemplary embodiment, the fourth partition structure layer 55 has a seventh surface 551 away from the substrate 101 and an eighth surface 552 close to the substrate 101. The orthographic projection width of the seventh surface 551 on the substrate 101 is smaller than the orthographic projection width of the eighth surface 552 on the substrate 101. This allows the cross-section of the fourth partition structure layer 55 in the direction perpendicular to the substrate 101 to include a trapezoidal shape.

[0178] In an exemplary embodiment, the second partition structure layer 51 has a third surface 511 that is away from the substrate 101, and the distance between the periphery of the orthographic projection of the fourth partition structure layer 55 on the substrate 101 and the periphery of the orthographic projection of the third surface 511 on the substrate 101 is 0.1 μm to 0.5 μm.

[0179] In an exemplary embodiment, the first trench 100 can form a first partition structure layer portion 533 on both sides of the first trench 100 in the first partition structure layer 53; in an exemplary embodiment, the second trench 200 can form a second partition structure layer portion 513 on both sides of the second trench 200 in the second partition structure layer 51.

[0180] In an exemplary embodiment, the first isolation structure layer 53 is made of one or more of silicon nitride (SiNx), silicon oxide (SiOx), amorphous silicon (a-Si), indium tin oxide (ITO), indium gallium zinc oxide (IGZO), and titanium (Ti). The first isolation structure layer 53 can be a single-layer structure or a multi-layer structure, and the material of each layer can be the same or different. This results in good film formation characteristics for the first isolation structure layer 53, a large etching selectivity compared to other OLED layers, and a stable and rigid structure.

[0181] The thickness of the first partition structure layer 53 is 0.2 μm to 0.3 μm.

[0182] In an exemplary embodiment, the third isolation structure layer 54 is made of one or more of silicon nitride (SiNx), silicon oxide (SiOx), amorphous silicon (a-Si), indium tin oxide (ITO), indium gallium zinc oxide (IGZO), and titanium (Ti). The third isolation structure layer 54 can be a single-layer or multi-layer structure, and the material of each layer can be the same or different. This results in good film formation characteristics for the third isolation structure layer 54, a large etching selectivity compared to other OLED layers, and a stable and rigid structure.

[0183] In an exemplary embodiment, the thickness of the third partition structure layer 54 is 0.2 μm to 0.3 μm.

[0184] In an exemplary embodiment, the third trench 300 can form third partition structure layer portions 543 on both sides of the third trench 300 in the third partition structure layer 54.

[0185] In an exemplary embodiment, the fourth isolation structure layer 55 is made of one or more of silicon nitride (SiNx), silicon oxide (SiOx), amorphous silicon (a-Si), indium tin oxide (ITO), indium gallium zinc oxide (IGZO), and titanium (Ti). The fourth isolation structure layer 55 can be a single-layer or multi-layer structure, and the material of each layer can be the same or different. This results in good film formation characteristics for the fourth isolation structure layer 55, a large etching selectivity compared to other OLED layers, and a stable and rigid structure.

[0186] In an exemplary embodiment, the thickness of the fourth partition structure layer 55 is 0.2 μm to 0.3 μm.

[0187] The partition structure 50 employs an undercut structure 52, a multi-layer structure, and a trench structure, ensuring a longer pixel encapsulation boundary and a larger contact area between the encapsulation layer and the microstructure of the partition structure 50. This improves the reliability of pixel-level thin-film encapsulation, enhances the pixel-level encapsulation effect, and meets the needs of subsequent photolithography pixel patterning processes. The encapsulation layer can be directly connected to the partition structure 50 or connected to the partition structure 50 through the light-emitting functional layer and the second electrode. Correspondingly, the undercut structure 52 and trench structure on the partition structure 50 can be filled by the encapsulation layer, or by a combination of the encapsulation layer, the light-emitting functional layer, and the second electrode.

[0188] The complexity of the partition structure 50 makes the junction between the encapsulation layer and the partition structure 50 more complex. The junction between the encapsulation layer and the partition structure 50 can serve as a channel for water and oxygen to enter. The more complex the structure, the less likely water and oxygen are to enter.

[0189] It can be understood that in other embodiments, the partition structure 50 may have five or more layers. For example, the partition structure 50 may also include at least one fifth partition structure layer, such that the partition structure 50 may include at least one fifth partition structure layer in addition to the first partition structure layer 53, the third partition structure layer 54 and the fourth partition structure layer 55.

[0190] In an exemplary embodiment, the cross-sections of the first partition structure layer 533, the second partition structure layer 513, and the third partition structure layer 543 in the direction perpendicular to the base 101 may be trapezoidal.

[0191] In an exemplary embodiment, the width of the orthographic projection of the second partition structure layer 51 onto the substrate 101 is less than 4 / 5 of the width of the orthographic projection of the first defining layer 61 onto the substrate 101.

[0192] In an exemplary embodiment, the sum of the widths of the orthographic projections of the second partition structure layer 513 onto the substrate 101 is less than 2 / 5 of the width of the orthographic projection of the first defining layer 61 onto the substrate 101.

[0193] In an exemplary embodiment, the distance between the orthographic projections of two adjacent second partition structure layers 513 on the substrate 101 can be approximately 3 μm to 5 μm.

[0194] In an exemplary embodiment, the width of the orthographic projection of the first partition structure layer 533 onto the substrate 101 can be approximately 5 μm to 10 μm.

[0195] In an exemplary embodiment, the width of the orthographic projection of the third partition structure layer 543 onto the substrate 101 can be approximately 5 μm to 10 μm.

[0196] In an exemplary embodiment, the distance between the orthographic projections of two adjacent first partition structure layers 533 on the substrate 101 can be approximately 2 μm to 5 μm.

[0197] In an exemplary embodiment, the distance between the orthographic projections of two adjacent third partition structure layers 543 on the substrate 101 can be approximately 2 μm to 5 μm.

[0198] The partition structure 50 between adjacent pixels is the key to the pixelation process of photolithography. The partition structure 50 can be used to give full play to the high step coverage of the encapsulation film, significantly increase the width of the pixel-level encapsulation border, and improve the reliability of the thin film encapsulation.

[0199] In an exemplary embodiment, the partition structure 50 has a mesh-like structure. That is, in a plane parallel to the substrate 101, the partition structure 50 has multiple strip-like structures extending along intersecting directions. These multiple strip-like structures can be arranged around the pixel opening to form a mesh-like structure. For example, the partition structure 50 may have multiple strip-like structures extending along intersecting first direction D1 and second direction D2, wherein the first direction D1 and second direction D2 are perpendicular, and the multiple strip-like structures can be arranged around the pixel opening to form a square or rectangular mesh-like structure. It can be understood that in other embodiments, the first direction D1 and second direction D2 may also be non-perpendicular, and the partition structure 50 may also have multiple strip-like structures extending along other directions, such that the multiple strip-like structures are arranged around the pixel opening to form a mesh-like structure in the form of triangles, rhombuses, trapezoids, parallelograms, pentagons, hexagons, and other polygons.

[0200] In an exemplary embodiment, the partition structure 50 is located between and surrounds the pixel openings, allowing it to be positioned in the non-light-emitting area between pixels, thus ensuring that the pixel aperture ratio is not reduced. Furthermore, by utilizing the partition structure 50 between sub-pixels, the color mixing problem between sub-pixels and the crosstalk problem between sub-pixels during low-brightness driving can be fundamentally solved, further improving display clarity, color performance (color gamut), uniformity, and other image quality performance.

[0201] In an exemplary embodiment, there are one or more partition structures 50 between the pixel openings. By increasing the number of partition structures 50 between the pixel openings, the overall connection area between the encapsulation layer and the partition structure 50 can be increased, thereby further improving the overall connection stability between the encapsulation layer and the partition structure 50 and reducing the risk of water and oxygen intrusion into the light-emitting device.

[0202] In an exemplary embodiment, the mesh structure has a mesh opening 400, which has the same shape as the pixel opening. The orthographic projection of the pixel opening on the substrate 101 is located within the orthographic projection of the mesh opening 400 on the substrate 101 and does not overlap, further reducing the impact of the partition structure 50 on the pixel aperture ratio, as shown in Figures 6a to 7b.

[0203] In an exemplary embodiment, the mesh openings 400 of the mesh structure are the same or different sizes to match different pixel openings.

[0204] In an exemplary embodiment, the intersection of the lines connecting the geometric centers of four adjacent pixel openings has at least one partition structure 50.

[0205] In an exemplary embodiment, the first partition structure layer 53, the third partition structure layer 54, and the fourth partition structure layer 55 are made of inorganic materials.

[0206] In an exemplary embodiment, the display substrate may further include an etch barrier layer disposed on the side of the encapsulation layer away from the substrate 101, and the etch barrier layer is made of a transparent material.

[0207] The etch barrier layer will remain in the final light-emitting device structure, therefore it must be made of a transparent material. For example, the visible light transmittance of the etch barrier layer must be greater than 90%.

[0208] In an exemplary embodiment, the orthographic projection of the etch stop layer on the substrate 101 at least covers the orthographic projections of the first color pixel opening and the second color pixel opening on the substrate 101. The etch stop layer may include a first color etch stop layer 81 and a second color etch stop layer 82, wherein the orthographic projection of the first color etch stop layer 81 on the substrate 101 at least covers the first color pixel opening, and the orthographic projection of the second color etch stop layer 82 on the substrate 101 at least covers the orthographic projection of the second color pixel opening on the substrate 101.

[0209] In an exemplary embodiment, the first color etch stop layer and the second color etch stop layer are made of different materials.

[0210] In an exemplary embodiment, the first color etch stop layer and the second color etch stop layer have different thicknesses.

[0211] In an exemplary embodiment, no etching barrier layer is provided above the opening of the third color pixel.

[0212] Since the light-emitting functional layer, the second electrode, and the encapsulation layer can be fabricated using a thermal evaporation coating process, this process employs an open mask coating technique. Subsequent color light-emitting devices deposited on top of the previous color light-emitting device must be completely removed; otherwise, the light emission of the previous color light-emitting device will be affected. Therefore, a certain amount of etching is required. If the difference between the color light-emitting device and the color light-emitting device to be etched away is too small during this process, etching damage can easily occur, leading to the erosion and damage of the previously fabricated color light-emitting device that should be retained. By introducing an etching barrier layer, the first and second color light-emitting devices can be protected separately, preventing etching damage.

[0213] In an exemplary embodiment, the orthogonal projection of the etch barrier layer on the substrate 101 also covers the orthogonal projection of the pixel definition layer on the substrate 101 between the first color pixel opening and the second color pixel opening. The etch barrier layer is a continuous film layer. That is, the etch barrier layer is continuous between the first color pixel opening and the second color pixel opening, forming a complete film layer structure, which can increase the temporary water and oxygen barrier capability of the first color light-emitting device and the second color light-emitting device, preventing water and oxygen from entering the first color light-emitting device and the second color light-emitting device.

[0214] The following description uses the fabrication process of a display substrate as an example. The "patterning process" described in this disclosure includes, for metallic, inorganic, or transparent conductive materials, processes such as photoresist coating, mask exposure, development, etching, and photoresist stripping; for organic materials, it includes processes such as organic material coating, mask exposure, and development. Deposition can be performed using any one or more of sputtering, evaporation, and chemical vapor deposition; coating can be performed using any one or more of spraying, spin coating, and inkjet printing; etching can be performed using any one or more of dry etching and wet etching. This disclosure does not limit the methods used. A "thin film" refers to a thin film of a certain material fabricated on a substrate using deposition, coating, or other processes. If the "thin film" does not require a patterning process during the entire fabrication process, it can also be called a "layer." If the "thin film" requires a patterning process during the entire fabrication process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern." The phrase "A and B are arranged in the same layer" in this disclosure means that A and B are formed simultaneously through the same patterning process, and the "thickness" of the film layer is the dimension of the film layer in the direction perpendicular to the display substrate. In the exemplary embodiments of this disclosure, "the orthographic projection of B is within the range of the orthographic projection of A" or "the orthographic projection of A includes the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary range of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0215] In an exemplary embodiment, the fabrication process of the display substrate may include the following operations.

[0216] 1. Form a driving circuit layer 102, a first electrode, and a first definition layer 61.

[0217] In an exemplary embodiment, forming the driving circuit layer 102, the first electrode, and the first definition layer 61 may include: firstly forming the driving circuit layer 102 on the substrate 101; then, depositing a first conductive film on the side of the driving circuit layer 102 away from the substrate 101, and patterning the first conductive film using a photolithography process to form the first electrode disposed on the side of the driving circuit layer 102 away from the substrate 101; subsequently, depositing a first pixel definition film covering the first electrode on the side of the driving circuit layer 102 away from the substrate 101, and patterning the first pixel definition film using a photolithography process to form the first definition layer 61 disposed on the side of the driving circuit layer 102 away from the substrate 101, wherein the first definition layer 61 overlaps with the orthographic projection of the first electrode on the substrate 101, and the first definition layer 61 exposes the first electrode, the first electrode may include a first color anode 11, a second color anode 12, and a third color anode 13, as shown in FIG4a.

[0218] In an exemplary embodiment, the first color anode 11, the second color anode 12, and the third color anode 13 may be a stacked structure of indium tin oxide (ITO) / silver (Ag) / indium tin oxide (ITO).

[0219] In an exemplary embodiment, the driving circuit layer 102 may include a gate driving circuit, an electrostatic discharge (ESD) protection circuit, an initialization circuit, a pixel internal compensation circuit, a pixel driving circuit, and traces, etc. The traces may include gate lines, initial signal lines, reference signal lines, data lines, a first power supply line (VDD), a second power supply line (VSS), etc. The pixel driving circuit, the gate driving circuit, the ESD protection circuit, the pixel internal compensation circuit, and the pixel driving circuit may all include transistors. The transistors may include a control electrode G, a first electrode S, and a second electrode D. The control electrode G, the first electrode S, and the second electrode D may be connected to corresponding connection electrodes through tungsten metal-filled vias (i.e., tungsten vias, W-vias), and may be connected to other electrical structures (such as traces) through the connection electrodes.

[0220] In an exemplary embodiment, the cross section of the first defining layer 61 in the direction perpendicular to the substrate 101 may be a regular trapezoid. The first defining layer 61 may include a first top surface and a first side surface connected to the first top surface. The first top surface is the surface of the first defining layer 61 away from the substrate 101, and the first side surface is located on opposite sides of the first top surface.

[0221] In an exemplary embodiment, the first defining layer 61 may be made of an organic material, such as a resin.

[0222] In an exemplary embodiment, the thickness of the first defining layer 61 can be approximately 1.4 μm to 1.6 μm. For example, the thickness of the first defining layer 61 can be approximately 1.5 μm.

[0223] 2. Form the second pixel definition film 103.

[0224] In an exemplary embodiment, forming the second pixel definition film 103 may include: depositing a second pixel definition film 103 on the side of the first electrode and the first definition layer 61 away from the substrate 101 on the substrate 101 on which the aforementioned pattern is formed, the second pixel definition film 103 covering the first electrode and the first definition layer 61, and the orthogonal projection of the second pixel definition film 103 on the substrate 101 covering the orthogonal projection of the first electrode and the first definition layer 61 on the substrate 101, as shown in FIG4b.

[0225] In an exemplary embodiment, the second pixel defining film 103 at least covers the first top surface and the first side surface of the first defining layer 61.

[0226] In an exemplary embodiment, the second pixel definition film 103 may be formed by plasma-enhanced chemical vapor deposition (PECVD) or atomic layer deposition (ALD).

[0227] In an exemplary embodiment, the second pixel defining film 103 may be made of an inorganic material, such as silicon nitride (SiNx), silicon oxide (SiOx), or silicon oxynitride (SiOxNy).

[0228] In an exemplary embodiment, the thickness of the second pixel defining film 103 can be approximately 0.1 μm to 0.3 μm. For example, the thickness of the second pixel defining film 103 can be approximately 0.2 μm.

[0229] In the embodiment of this disclosure, during the substrate fabrication process, the first definition layer 61 is covered by the second pixel definition film 103 to protect the first definition layer 61 and avoid damage to the first definition layer 61 in subsequent photolithography processes.

[0230] 3. Form the second definition layer 62.

[0231] In an exemplary embodiment, forming the second defining layer 62 may include: patterning the second pixel defining film 103 on the substrate 101 on which the aforementioned pattern is formed using a photolithography process, thereby forming the second defining layer 62; partially etching away the second pixel defining film 103 on the first electrode, resulting in an overlap between the second defining layer 62 and the orthographic projection of the first electrode on the substrate 101, exposing the first electrode; retaining the second pixel defining film 103 on the first defining layer 61, resulting in an overlap between the second defining layer 62 and the orthographic projection of the first defining layer 61 on the substrate 101, for example, the orthographic projection of the second defining layer 62 on the substrate 101 covers the orthographic projection of the first defining layer 61 on the substrate 101, as shown in FIG4c. The first defining layer 61 and the second defining layer 62 form a pixel defining layer, which defines a pixel opening that exposes at least a portion of a first electrode.

[0232] In an exemplary embodiment, the second defining layer 62 may include a second top surface and second side surfaces connected to the second top surface, wherein the second top surface is the surface of the second defining layer 62 away from the substrate 101. The second side surfaces are located on opposite sides of the second top surface.

[0233] In an exemplary embodiment, the second defining layer 62 may be made of an inorganic material, such as silicon nitride (SiNx), silicon oxide (SiOx), or silicon oxynitride (SiOxNy). The thickness of the second defining layer 62 may be approximately 0.1 μm to 0.3 μm. For example, the thickness of the second pixel defining film 103 may be approximately 0.2 μm.

[0234] 4. Forming the anode protection layer 104 (APL).

[0235] In an exemplary embodiment, forming the anode protection layer 104 may include: depositing an electrode protection film on the substrate 101 on the side of the first electrode and the second defining layer 62 away from the substrate 101 where the aforementioned pattern is formed; the electrode protection film covering the first electrode and the second defining layer 62; the orthographic projection of the electrode protection film on the substrate 101 covering the orthographic projection of the first electrode and the second defining layer 62 on the substrate 101; patterning the electrode protection film using a photolithography process to form the anode protection layer 104; partially etching away the electrode protection film on the second defining layer 62; overlapping of the orthographic projections of the anode protection layer 104, the second defining layer 62, and the first defining layer 61 on the substrate 101; and exposing the second defining layer 62 in the anode protection layer 104; the electrode protection film on the first electrode is retained as shown in FIG4d.

[0236] In an exemplary embodiment, the anode protection layer 104 may include a third top surface and a third side surface connected to the third top surface, wherein the third top surface is the surface of the anode protection layer 104 away from the substrate 101. The third side surfaces are located on opposite sides of the third top surface.

[0237] In an exemplary embodiment, the anode protective layer 104 can be made of an inorganic material, such as silicon nitride (SiNx), silicon oxide (SiOx), or silicon oxynitride (SiOxNy). Choosing an inorganic material for the anode protective layer 104 allows for sufficient protection of the top layer of the first electrode due to its high etching selectivity compared to organic materials in OLEDs. For example, if the first electrode (anode) is an indium tin oxide (ITO) / silver (Ag) / indium tin oxide (ITO) stacked structure, the photolithography process can easily lead to etching damage to the top ITO layer of the first electrode due to the introduction of an auxiliary cathode film. Typically, the process involves thickening the top ITO layer to avoid over-etching and exposure of reflected Ag, which could then corrode. However, since ITO has low transmittance in the visible blue light band, this reduces the luminous efficiency of the OLED device, thus affecting power consumption. Therefore, by introducing an inorganic material to form the anode protective layer 104, sufficient protection of the top ITO layer and the second pixel definition layer can be achieved. The top layer of ITO is protected from over-etching during the auxiliary cathode thin film patterning process, ensuring the efficiency of the OLED light-emitting device. Simultaneously, the inorganic material used to make the anode protective layer 104 has a fast etching rate and a high selectivity compared to ITO, which is beneficial for protecting the ITO and prevents etching carbonization, thus avoiding foreign matter residues on the ITO surface that could affect the subsequent fabrication of the OLED light-emitting device. The reason for not choosing organic materials for the anode protective layer 104 is that the OLED light-emitting device is fabricated using a vacuum evaporation process, requiring all materials on the substrate 101 to be completely cured without gas release and able to withstand the baking temperature of the substrate 101. Furthermore, subsequent etching removal processes are less prone to etching residues (organic materials are prone to carbonization), and the inorganic material has a high selectivity compared to the top layer ITO (organic materials have a low selectivity compared to the top layer ITO).

[0238] In an exemplary embodiment, the thickness of the anode protective layer 104 can be approximately 0.05 μm to 0.1 μm. For example, the thickness of the anode protective layer 104 can be approximately 0.075 μm.

[0239] 5. Form the second conductive film 105 and the barrier structure film.

[0240] In an exemplary embodiment, forming the second conductive film 105 and the barrier structure film may include: depositing a second conductive film 105 and a barrier structure film sequentially on the substrate 101 on the side of the second defining layer 62 and the anode protection layer 104 away from the substrate 101, where the aforementioned pattern is formed. The second conductive film 105 covers the second defining layer 62 and the anode protection layer 104, and the barrier structure film is disposed on the side of the second conductive film 105 away from the substrate 101. The barrier structure film may include a first barrier structure film 106 and a third barrier structure film 107, where the third barrier structure film 107 is disposed on the side of the second conductive film 105 away from the substrate 101, and the first barrier structure film 106 is disposed on the side of the third barrier structure film 107 away from the substrate 101, as shown in FIG4e. Furthermore, the barrier structure film may also include the first barrier structure film 106, which is disposed on the side of the second conductive film 105 away from the substrate 101. Alternatively, the barrier structure film may further include a first barrier structure film 106, a third barrier structure film 107, and a fourth barrier structure film. The fourth barrier structure film is disposed on the side of the second conductive film 105 away from the substrate 101, the third barrier structure film 107 is disposed on the side of the fourth barrier structure film away from the substrate 101, and the first barrier structure film 106 is disposed on the side of the third barrier structure film 107 away from the substrate 101.

[0241] In an exemplary embodiment, the second conductive thin film 105 can be formed by magnetron sputtering.

[0242] In an exemplary embodiment, the second conductive film 105 may be made of a conductive material, such as one or more of titanium (Ti), aluminum (Al), molybdenum (Mo), copper (Cu), aluminum-neodymium alloy (AlNd), indium tin oxide (ITO), and indium gallium zinc oxide (IGZO). The second conductive film 105 may be a single-layer structure or a multi-layer structure, and the material of each layer may be the same or different.

[0243] In an exemplary embodiment, the thickness of the second conductive film 105 can be approximately 0.6 μm to 0.8 μm. For example, the thickness of the second conductive film 105 can be approximately 0.7 μm.

[0244] In an exemplary embodiment, the first isolation structure thin film 106 may be made of one or more of silicon nitride (SiNx), silicon oxide (SiOx), amorphous silicon (a-Si), indium tin oxide (ITO), indium gallium zinc oxide (IGZO), and titanium (Ti). The first isolation structure thin film 106 may be a single-layer structure or a multi-layer structure, and the material of each layer may be the same or different.

[0245] In an exemplary embodiment, the thickness of the first partition structure film 106 can be approximately 0.2 μm to 0.3 μm. For example, the thickness of the first partition structure film 106 can be approximately 0.15 μm.

[0246] In an exemplary embodiment, the third partition structure thin film 107 can be made of one or more of silicon nitride (SiNx), silicon oxide (SiOx), amorphous silicon (a-Si), indium tin oxide (ITO), indium gallium zinc oxide (IGZO), and titanium (Ti). The third partition structure thin film 107 can be a single-layer structure or a multi-layer structure, and the material of each layer can be the same or different.

[0247] In an exemplary embodiment, the thickness of the third partition structure film 107 can be approximately 0.2 μm to 0.3 μm. For example, the thickness of the third partition structure film 107 can be approximately 0.15 μm.

[0248] In an exemplary embodiment, the fourth barrier structure thin film can be made of one or more of silicon nitride (SiNx), silicon oxide (SiOx), amorphous silicon (a-Si), indium tin oxide (ITO), indium gallium zinc oxide (IGZO), and titanium (Ti). The third barrier structure thin film 107 can be a single-layer structure or a multi-layer structure, and the material of each layer can be the same or different.

[0249] In an exemplary embodiment, the thickness of the fourth partition structure film can be approximately 0.2 μm to 0.3 μm. For example, the thickness of the fourth partition structure film can be approximately 0.15 μm.

[0250] In an exemplary embodiment, the first partition structure film 106, the third partition structure film 107, and the fourth partition structure film are made of different materials.

[0251] In an exemplary embodiment, the first partition structure film 106 and the fourth partition structure film are made of the same material and are made of a different material than the third partition structure film 107.

[0252] In an exemplary embodiment, a first isolation structure film 106, a third isolation structure film 107, and a fourth isolation structure film made of silicon nitride (SiNx), silicon oxide (SiOx), or amorphous silicon (a-Si) can be formed by plasma-enhanced chemical vapor deposition (PECVD).

[0253] In an exemplary embodiment, a first isolation structure film 106, a third isolation structure film 107, and a fourth isolation structure film made of indium tin oxide (ITO), indium gallium zinc oxide (IGZO), or titanium (Ti) can be formed by magnetron sputtering.

[0254] 6. Forming a second partition structure layer 51. Partition structure layer and trench structure.

[0255] In an exemplary embodiment, forming the second isolation structure layer 51, the isolation structure layer, and the trench structure may include: first, patterning the isolation structure film on the substrate 101 on which the aforementioned pattern is formed by an etching process, so that the isolation structure film forms an isolation structure layer; then, using the isolation structure layer as a mask, etching the second conductive film 105, so that the second conductive film 105 forms the second isolation structure layer 51, wherein the isolation structure layer and the second isolation structure layer 51 form an isolation structure 50.

[0256] In an exemplary embodiment, the isolation structure film may include a first isolation structure film 106 and a third isolation structure film 107. On the substrate 101 on which the aforementioned pattern is formed, the first isolation structure film 106 and the third isolation structure film 107 are first patterned by an etching process, forming a first isolation structure layer 53 and a third isolation structure layer 54. Subsequently, using the first isolation structure layer 53 and the third isolation structure layer 54 as a mask, a second conductive film 105 is etched, forming a second isolation structure layer 51. Subsequently, the first isolation structure layer 53 is etched to form a first trench 100, exposing the third isolation structure layer 54, as shown in FIG. 4f. The first isolation structure layer 53 may include first isolation structure layer portions 533 located on both sides of the first trench 100. The cross-section of the first trench 100 in the direction perpendicular to the substrate 101 may be an inverted trapezoid.

[0257] The thickness of the second partition structure layer 51 can be approximately 0.6 μm to 0.8 μm, for example, the thickness of the second partition structure layer 51 can be approximately 0.7 μm.

[0258] The first partition structure layer 53, the third partition structure layer 54 and the first trench 100 can be formed simultaneously using the same etching process; or, the first partition structure layer 53, the third partition structure layer 54 and the first trench 100 can be formed respectively using three etching processes.

[0259] The thickness of the first partition structure layer 53 can be approximately 0.2 μm to 0.3 μm. For example, the thickness of the first partition structure layer 53 can be approximately 0.15 μm.

[0260] The thickness of the third partition structure layer 54 can be approximately 0.2 μm to 0.3 μm. For example, the thickness of the third partition structure layer 54 can be approximately 0.15 μm.

[0261] The first partition structure layer 53, the second partition structure layer 51, and the third partition structure layer 54 can form an undercut structure 52 around the pixel opening.

[0262] In an exemplary embodiment, the first partition structure layer 53 has a first surface 531 away from the substrate 101 and a second surface 532 close to the substrate 101. The orthogonal projection width of the first surface 531 on the substrate 101 is smaller than the orthogonal projection width of the second surface 532 on the substrate 101.

[0263] In an exemplary embodiment, the second partition structure layer 51 has a third surface 511 away from the substrate 101 and a fourth surface 512 close to the substrate 101. The orthographic projection width of the third surface 511 on the substrate 101 is greater than or less than the orthographic projection width of the fourth surface 512 on the substrate 101.

[0264] In an exemplary embodiment, the third partition structure layer 54 has a fifth surface 541 away from the substrate 101 and a sixth surface 542 close to the substrate 101. The orthographic projection width of the fifth surface 541 on the substrate 101 is smaller than the orthographic projection width of the sixth surface 542 on the substrate 101.

[0265] In an exemplary embodiment, the distance from the periphery of the orthographic projection of the first partition structure layer 53 onto the substrate 101 to the periphery of the orthographic projection of the third surface 511 onto the substrate 101 can be approximately 0.2 μm to 1.2 μm. For example, the distance from the periphery of the orthographic projection of the first partition structure layer 53 onto the substrate 101 to the periphery of the orthographic projection of the third surface 511 onto the substrate 101 can be approximately 0.7 μm.

[0266] In an exemplary embodiment, the distance from the periphery of the orthographic projection of the first partition structure layer 53 on the substrate 101 to the periphery of the orthographic projection of the fifth surface 541 on the substrate 101 can be approximately 0.1 μm to 0.8 μm. For example, the distance from the periphery of the orthographic projection of the first partition structure layer 53 on the substrate 101 to the periphery of the orthographic projection of the fifth surface 541 on the substrate 101 can be approximately 0.45 μm.

[0267] In an exemplary embodiment, the cross-section of the first trench 100 in the direction perpendicular to the substrate 101 may be an inverted trapezoid. The first trench 100 has a first width W1 on the side away from the substrate 101 and a second width W2 on the side close to the substrate 101. The first width W1 is greater than the second width W2.

[0268] In an exemplary embodiment, the first trench 100 extends from the first surface 531 along a direction close to the substrate 101 and penetrates the first partition structure layer 53.

[0269] In an exemplary embodiment, the width of the orthographic projection of the second partition structure layer 51 onto the substrate 101 is less than 4 / 5 of the width of the orthographic projection of the first defining layer 61 onto the substrate 101.

[0270] In an exemplary embodiment, the width of the orthographic projection of the first partition structure layer 533 onto the substrate 101 can be approximately 5 μm to 10 μm. For example, the width of the orthographic projection of the first partition structure layer 533 onto the substrate 101 can be approximately 7.5 μm.

[0271] The distance between the orthographic projections of the two first partition structure layers 533 on the substrate 101 can be approximately 2 μm to 5 μm. For example, the distance between the orthographic projections of the two first partition structure layers 533 on the substrate 101 can be approximately 3.5 μm.

[0272] In an exemplary embodiment, the isolation structure film may include a first isolation structure film 106 and a third isolation structure film 107. On the substrate 101 on which the aforementioned pattern is formed, the first isolation structure film 106 and the third isolation structure film 107 are first patterned by an etching process, forming a first isolation structure layer 53 and a third isolation structure layer 54. Subsequently, using the first isolation structure layer 53 and the third isolation structure layer 54 as a mask, a second conductive film 105 is etched, forming a second isolation structure layer 51. Subsequently, the first isolation structure layer 53 and the third isolation structure layer 54 are etched to form a first trench 100 and a third trench 300, exposing the second isolation structure layer 51 (Figure 4g). The first isolation structure layer 53 may include first isolation structure layer portions 533 located on both sides of the first trench 100. The third partition structure layer 54 may include third partition structure layer portions 543 located on both sides of the third trench 300. The cross-sections of the first trench 100 and the third trench 300 in the direction perpendicular to the substrate 101 may include inverted trapezoids.

[0273] The thickness of the second partition structure layer 51 can be approximately 0.6 μm to 0.8 μm, for example, the thickness of the second partition structure layer 51 can be approximately 0.7 μm.

[0274] The first partition structure layer 53, the third partition structure layer 54, the first trench 100 and the third trench 300 can be formed simultaneously using the same etching process; or, the first partition structure layer 53, the third partition structure layer 54, the first trench 100 and the third trench 300 can be formed respectively using four etching processes.

[0275] The thickness of the first partition structure layer 53 can be approximately 0.2 μm to 0.3 μm. For example, the thickness of the first partition structure layer 53 can be approximately 0.15 μm.

[0276] The thickness of the third partition structure layer 54 can be approximately 0.2 μm to 0.3 μm. For example, the thickness of the third partition structure layer 54 can be approximately 0.15 μm.

[0277] The first partition structure layer 53, the second partition structure layer 51, and the third partition structure layer 54 can form an undercut structure 52 around the pixel opening.

[0278] In an exemplary embodiment, the first partition structure layer 53 has a first surface 531 away from the substrate 101 and a second surface 532 close to the substrate 101. The orthogonal projection width of the first surface 531 on the substrate 101 is smaller than the orthogonal projection width of the second surface 532 on the substrate 101.

[0279] In an exemplary embodiment, the second partition structure layer 51 has a third surface 511 away from the substrate 101 and a fourth surface 512 close to the substrate 101. The orthographic projection width of the third surface 511 on the substrate 101 is greater than or less than the orthographic projection width of the fourth surface 512 on the substrate 101.

[0280] In an exemplary embodiment, the third partition structure layer 54 has a fifth surface 541 away from the substrate 101 and a sixth surface 542 close to the substrate 101. The orthographic projection width of the fifth surface 541 on the substrate 101 is smaller than the orthographic projection width of the sixth surface 542 on the substrate 101.

[0281] In an exemplary embodiment, the distance from the periphery of the orthographic projection of the first partition structure layer 53 onto the substrate 101 to the periphery of the orthographic projection of the third surface 511 onto the substrate 101 can be approximately 0.2 μm to 1.2 μm. For example, the distance from the periphery of the orthographic projection of the first partition structure layer 53 onto the substrate 101 to the periphery of the orthographic projection of the third surface 511 onto the substrate 101 can be approximately 0.7 μm.

[0282] In an exemplary embodiment, the distance from the periphery of the orthographic projection of the first partition structure layer 53 on the substrate 101 to the periphery of the orthographic projection of the fifth surface 541 on the substrate 101 can be approximately 0.1 μm to 0.8 μm. For example, the distance from the periphery of the orthographic projection of the first partition structure layer 53 on the substrate 101 to the periphery of the orthographic projection of the fifth surface 541 on the substrate 101 can be approximately 0.45 μm.

[0283] In an exemplary embodiment, the cross-sections of the first trench 100 and the third trench 300 in the direction perpendicular to the substrate 101 may include two connected inverted trapezoids. The first trench 100 has a first width W1 on the side away from the substrate 101 and a second width W2 on the side closer to the substrate 101, wherein the first width W1 is greater than the second width W2. The first trench 100 communicates with the third trench 300. The third trench 300 has a fifth width W5 on the side away from the substrate 101 and a sixth width W6 on the side closer to the substrate 101, wherein the fifth width W5 is greater than the sixth width W6. The fifth width W5 is greater than the second width W2. The first trench 100 extends from the first surface 531 along the direction close to the substrate 101 and penetrates the first partition structure layer 53. The third trench 300 extends from the fifth surface 541 along the direction close to the substrate 101 and penetrates the third partition structure layer 54. The two connected inverted trapezoids gradually decrease in the direction perpendicular to the substrate 101, abruptly increase at the connection between the first trench 100 and the third trench 300, and then gradually decrease until the pixel definition layer is away from the substrate 101.

[0284] In an exemplary embodiment, the width of the orthographic projection of the second partition structure layer 51 onto the substrate 101 is less than 4 / 5 of the width of the orthographic projection of the first defining layer 61 onto the substrate 101.

[0285] In an exemplary embodiment, the width of the orthographic projection of the first partition structure layer 533 onto the substrate 101 can be approximately 5 μm to 10 μm. For example, the width of the orthographic projection of the first partition structure layer 533 onto the substrate 101 can be approximately 7.5 μm.

[0286] In an exemplary embodiment, the width of the orthographic projection of the third partition structure layer 543 onto the substrate 101 can be approximately 5 μm to 10 μm. For example, the width of the orthographic projection of the third partition structure layer 543 onto the substrate 101 can be approximately 7.5 μm.

[0287] The distance between the orthographic projections of the two first partition structure layers 533 on the substrate 101 can be approximately 2 μm to 5 μm. For example, the distance between the orthographic projections of the two first partition structure layers 533 on the substrate 101 can be approximately 3.5 μm.

[0288] The distance between the orthographic projections of the two third partition structure layers 543 onto the substrate 101 can be approximately 2 μm to 5 μm. For example, the distance between the orthographic projections of the two second partition structure layers 513 onto the substrate 101 can be approximately 3.5 μm.

[0289] In an exemplary embodiment, the isolation structure film may include a first isolation structure film 106 and a third isolation structure film 107. On the substrate 101 on which the aforementioned pattern is formed, the first isolation structure film 106 and the third isolation structure film 107 are first patterned by an etching process to form a first isolation structure layer 53 and a third isolation structure layer 54. Subsequently, the first isolation structure layer 53 and the third isolation structure layer 54 are etched to form a first trench 100 and a third trench 300. Subsequently, using the first isolation structure layer 53 and the third isolation structure layer 54 as a mask, a second conductive film 105 is etched to form a second isolation structure layer 51. The second isolation structure layer 51 has a second trench 200, and the third trench 300 communicates between the first trench 100 and the second trench 200, and exposes a first defining layer 61 (Figure 4h). The first partition structure layer 53 may include first partition structure layer portions 533 located on both sides of the first trench 100. The third partition structure layer 54 may include third partition structure layer portions 543 located on both sides of the third trench 300. The second partition structure layer 51 may include second partition structure layer portions 513 located on both sides of the second trench 200. The cross-sections of the first trench 100, the second trench 200, and the third trench 300 in the direction perpendicular to the substrate 101 may include an inverted trapezoidal shape.

[0290] The thickness of the second partition structure layer 51 can be approximately 0.6 μm to 0.8 μm, for example, the thickness of the second partition structure layer 51 can be approximately 0.7 μm.

[0291] The first partition structure layer 53, the third partition structure layer 54, the first trench 100 and the third trench 300 can be formed simultaneously using the same etching process; or, the first partition structure layer 53, the third partition structure layer 54, the first trench 100 and the third trench 300 can be formed respectively using four etching processes.

[0292] The thickness of the first partition structure layer 53 can be approximately 0.2 μm to 0.3 μm. For example, the thickness of the first partition structure layer 53 can be approximately 0.15 μm.

[0293] The thickness of the third partition structure layer 54 can be approximately 0.2 μm to 0.3 μm. For example, the thickness of the third partition structure layer 54 can be approximately 0.15 μm.

[0294] The first partition structure layer 53, the second partition structure layer 51, and the third partition structure layer 54 can form an undercut structure 52 around the pixel opening.

[0295] In an exemplary embodiment, the first partition structure layer 53 has a first surface 531 away from the substrate 101 and a second surface 532 close to the substrate 101. The orthogonal projection width of the first surface 531 on the substrate 101 is smaller than the orthogonal projection width of the second surface 532 on the substrate 101.

[0296] In an exemplary embodiment, the second partition structure layer 51 has a third surface 511 away from the substrate 101 and a fourth surface 512 close to the substrate 101. The orthographic projection width of the third surface 511 on the substrate 101 is greater than or less than the orthographic projection width of the fourth surface 512 on the substrate 101.

[0297] In an exemplary embodiment, the third partition structure layer 54 has a fifth surface 541 away from the substrate 101 and a sixth surface 542 close to the substrate 101. The orthographic projection width of the fifth surface 541 on the substrate 101 is smaller than the orthographic projection width of the sixth surface 542 on the substrate 101.

[0298] In an exemplary embodiment, the distance from the periphery of the orthographic projection of the first partition structure layer 53 onto the substrate 101 to the periphery of the orthographic projection of the third surface 511 onto the substrate 101 can be approximately 0.2 μm to 1.2 μm. For example, the distance from the periphery of the orthographic projection of the first partition structure layer 53 onto the substrate 101 to the periphery of the orthographic projection of the third surface 511 onto the substrate 101 can be approximately 0.7 μm.

[0299] In an exemplary embodiment, the distance from the periphery of the orthographic projection of the first partition structure layer 53 on the substrate 101 to the periphery of the orthographic projection of the fifth surface 541 on the substrate 101 can be approximately 0.1 μm to 0.8 μm. For example, the distance from the periphery of the orthographic projection of the first partition structure layer 53 on the substrate 101 to the periphery of the orthographic projection of the fifth surface 541 on the substrate 101 can be approximately 0.45 μm.

[0300] In an exemplary embodiment, the cross-sections of the first trench 100, the second trench 200, and the third trench 300 in the direction perpendicular to the substrate 101 may include three connected inverted trapezoids. The first trench 100 has a first width W1 on the side away from the substrate 101 and a second width W2 on the side closer to the substrate 101, wherein the first width W1 is greater than the second width W2. The first trench 100 is connected to the third trench 300, which has a fifth width W5 on the side away from the substrate 101 and a sixth width W6 on the side closer to the substrate 101, wherein the fifth width W5 is greater than the sixth width W6. The fifth width W5 is greater than the second width W2. The second trench 200 is connected to the third trench 300, which has a third width W3 on the side away from the substrate 101 and a fourth width W4 on the side closer to the substrate 101, wherein the third width W3 is greater than the fourth width W4. The third width W3 is greater than the sixth width W6. The first trench 100 extends from the first surface 531 along the direction close to the substrate 101 and penetrates the first partition structure layer 53. The third trench 300 extends from the fifth surface 541 along the direction close to the substrate 101 and penetrates the third partition structure layer 54. The second trench 200 extends from the third surface 511 along the direction close to the substrate 101 and penetrates the second partition structure layer 51. The three connected inverted trapezoids gradually decrease in size along the direction perpendicular to the substrate 101, abruptly increase at the junction of the first trench 100 and the third trench 300, and then gradually decrease until the junction of the third trench 300 and the second trench 200, where they abruptly increase again, and then gradually decrease until the pixel definition layer on the side away from the substrate 101.

[0301] The sum of the widths of the orthographic projections of the two second partition structure layers 513 onto the substrate 101 is less than 2 / 5 of the width of the orthographic projection of the first defining layer 61 onto the substrate 101.

[0302] The distance between the orthographic projections of the two second partition structure layers 513 on the substrate 101 can be approximately 3 μm to 5 μm. For example, the distance between the orthographic projections of the two second partition structure layers 513 on the substrate 101 can be approximately 4 μm.

[0303] The width of the orthographic projection of the first partition structure layer 533 onto the substrate 101 can be approximately 5 μm to 10 μm. For example, the width of the orthographic projection of the first partition structure layer 533 onto the substrate 101 can be approximately 7.5 μm.

[0304] The width of the orthographic projection of the third partition structure layer 543 onto the substrate 101 can be approximately 5 μm to 10 μm. For example, the width of the orthographic projection of the third partition structure layer 543 onto the substrate 101 can be approximately 7.5 μm.

[0305] The distance between the orthographic projections of the two first partition structure layers 533 on the substrate 101 can be approximately 2 μm to 5 μm. For example, the distance between the orthographic projections of the two first partition structure layers 533 on the substrate 101 can be approximately 3.5 μm.

[0306] The distance between the orthographic projections of the two third partition structure layers 543 on the substrate 101 can be approximately 2 μm to 5 μm. For example, the distance between the orthographic projections of the two third partition structure layers 543 on the substrate 101 can be approximately 3.5 μm.

[0307] Furthermore, in some embodiments, the number of first trenches 100 and third trenches 300 located between adjacent pixel openings can be multiple and interconnected. As shown in FIG4i, the number of first trenches 100 and third trenches 300 located between adjacent pixel openings is two. The two first trenches 100 are spaced apart along a direction parallel to the substrate 101 and are interconnected with the two third trenches 300. The spacing between the orthographic projections of the two first trenches 100 on the substrate 101 can be approximately 2 μm to 5 μm. For example, the spacing between the orthographic projections of the two first trenches 100 on the substrate 101 can be approximately 3.5 μm. The spacing between the orthographic projections of the two third trenches 300 on the substrate 101 can be approximately 2 μm to 5 μm. For example, the spacing between the orthographic projections of the two third trenches 300 on the substrate 101 can be approximately 3.5 μm.

[0308] It can be understood that in other embodiments, the number of the first trench 100, the second trench 200, and the third trench 300 located between adjacent pixel openings can all be two or more.

[0309] In an exemplary embodiment, the isolation structure film may include a first isolation structure film 106. On the substrate 101 on which the aforementioned pattern is formed, the first isolation structure film 106 is first patterned by an etching process to form a first isolation structure layer 53; subsequently, the first isolation structure layer 53 is etched to form a first trench 100; subsequently, using the first isolation structure layer 53 as a mask, a second conductive film 105 is etched to form a second isolation structure layer 51. The second isolation structure layer 51 has a second trench 200, which communicates with the first trench 100 and exposes a second defining layer 62 (Figures 4j and 8). The first isolation structure layer 53 may include first isolation structure layer portions 533 located on both sides of the first trench 100. The second isolation structure layer 51 may include second isolation structure layer portions 513 located on both sides of the second trench 200. The cross-sections of the first trench 100 and the second trench 200 in the direction perpendicular to the substrate 101 may be inverted trapezoidal.

[0310] The thickness of the second partition structure layer 51 can be approximately 0.6 μm to 0.8 μm, for example, the thickness of the second partition structure layer 51 can be approximately 0.7 μm.

[0311] The first partition structure layer 53 and the first trench 100 can be formed simultaneously using the same etching process; or, the first partition structure layer 53 and the first trench 100 can be formed separately using a two-stage etching process.

[0312] The thickness of the first partition structure layer 53 can be approximately 0.2 μm to 0.3 μm. For example, the thickness of the first partition structure layer 53 can be approximately 0.15 μm.

[0313] The first partition structure layer 53 and the second partition structure layer 51 can form an undercut structure 52 around the pixel opening.

[0314] In an exemplary embodiment, the first partition structure layer 53 has a first surface 531 away from the substrate 101 and a second surface 532 close to the substrate 101. The orthogonal projection width of the first surface 531 on the substrate 101 is smaller than the orthogonal projection width of the second surface 532 on the substrate 101.

[0315] In an exemplary embodiment, the second partition structure layer 51 has a third surface 511 away from the substrate 101 and a fourth surface 512 close to the substrate 101. The orthographic projection width of the third surface 511 on the substrate 101 is greater than or less than the orthographic projection width of the fourth surface 512 on the substrate 101.

[0316] In an exemplary embodiment, the distance from the periphery of the orthographic projection of the first partition structure layer 53 onto the substrate 101 to the periphery of the orthographic projection of the third surface 511 onto the substrate 101 can be approximately 0.2 μm to 1.2 μm. For example, the distance from the periphery of the orthographic projection of the first partition structure layer 53 onto the substrate 101 to the periphery of the orthographic projection of the third surface 511 onto the substrate 101 can be approximately 0.7 μm.

[0317] In an exemplary embodiment, the cross-sections of the first trench 100 and the second trench 200 in the direction perpendicular to the substrate 101 may include two connected inverted trapezoids. The first trench 100 has a first width W1 on the side away from the substrate 101 and a second width W2 on the side closer to the substrate 101, wherein the first width W1 is greater than the second width W2. The first trench 100 communicates with the second trench 200. The second trench 200 has a third width W3 on the side away from the substrate 101 and a fourth width W4 on the side closer to the substrate 101, wherein the third width W3 is greater than the second width W2. The first trench 100 extends from the first surface 531 along the direction close to the substrate 101 and penetrates the first partition structure layer 53. The second trench 200 extends from the third surface 511 along the direction close to the substrate 101 and penetrates the second partition structure layer 51. The two connected inverted trapezoids gradually decrease in the direction perpendicular to the substrate 101, abruptly increase at the connection between the first trench 100 and the second trench 200, and then gradually decrease until the pixel definition layer is away from the substrate 101.

[0318] The sum of the widths of the orthographic projections of the two second partition structure layers 513 onto the substrate 101 is less than 2 / 5 of the width of the orthographic projection of the first defining layer 61 onto the substrate 101.

[0319] The distance between the orthographic projections of the two second partition structure layers 513 on the substrate 101 can be approximately 3 μm to 5 μm. For example, the distance between the orthographic projections of the two second partition structure layers 513 on the substrate 101 can be approximately 4 μm.

[0320] In an exemplary embodiment, the isolation structure film may include a first isolation structure film 106, a third isolation structure film 107, and a fourth isolation structure film. On the substrate 101 on which the aforementioned pattern is formed, the first isolation structure film 106, the third isolation structure film 107, and the fourth isolation structure film are first patterned by an etching process to form a first isolation structure layer 53, a third isolation structure layer 54, and a fourth isolation structure layer 55. Subsequently, using the first isolation structure layer 53, the third isolation structure layer 54, and the fourth isolation structure layer 55 as a mask, the second conductive film 105 is etched to form a second isolation structure layer 51. Subsequently, the first isolation structure layer 53 and the third isolation structure layer 54 are etched to form a first trench 100 and a third trench 300, and the fourth isolation structure layer 55 is exposed (Figure 4k). The first partition structure layer 53 may include first partition structure layer portions 533 located on both sides of the first groove 100. The third partition structure layer 54 may include third partition structure layer portions 543 located on both sides of the third groove 300.

[0321] The thickness of the second partition structure layer 51 can be approximately 0.6 μm to 0.8 μm, for example, the thickness of the second partition structure layer 51 can be approximately 0.7 μm.

[0322] The first partition structure layer 53, the third partition structure layer 54, the fourth partition structure layer 55, the first trench 100 and the third trench 300 can be formed simultaneously using the same etching process; or, the first partition structure layer 53, the third partition structure layer 54, the fourth partition structure layer 55, the first trench 100 and the third trench 300 can be formed respectively using five etching processes.

[0323] The thickness of the first partition structure layer 53 can be approximately 0.2 μm to 0.3 μm. For example, the thickness of the first partition structure layer 53 can be approximately 0.15 μm.

[0324] The thickness of the third partition structure layer 54 can be approximately 0.2 μm to 0.3 μm. For example, the thickness of the third partition structure layer 54 can be approximately 0.15 μm.

[0325] The thickness of the fourth partition structure layer 55 can be approximately 0.2 μm to 0.3 μm. For example, the thickness of the fourth partition structure layer 55 can be approximately 0.15 μm.

[0326] The first partition structure layer 53, the second partition structure layer 51, the third partition structure layer 54, and the fourth partition structure layer 55 can form an undercut structure 52 around the pixel opening.

[0327] In an exemplary embodiment, the first partition structure layer 53 has a first surface 531 away from the substrate 101 and a second surface 532 close to the substrate 101. The orthogonal projection width of the first surface 531 on the substrate 101 is smaller than the orthogonal projection width of the second surface 532 on the substrate 101.

[0328] In an exemplary embodiment, the second partition structure layer 51 has a third surface 511 away from the substrate 101 and a fourth surface 512 close to the substrate 101. The orthographic projection width of the third surface 511 on the substrate 101 is greater than or less than the orthographic projection width of the fourth surface 512 on the substrate 101.

[0329] In an exemplary embodiment, the third partition structure layer 54 has a fifth surface 541 away from the substrate 101 and a sixth surface 542 close to the substrate 101. The orthographic projection width of the fifth surface 541 on the substrate 101 is smaller than the orthographic projection width of the sixth surface 542 on the substrate 101.

[0330] In an exemplary embodiment, the fourth partition structure layer 55 has a seventh surface 551 away from the substrate 101 and an eighth surface 552 close to the substrate 101. The orthographic projection width of the seventh surface 551 on the substrate 101 is smaller than the orthographic projection width of the eighth surface 552 on the substrate 101.

[0331] In an exemplary embodiment, the distance from the periphery of the orthographic projection of the first partition structure layer 53 onto the substrate 101 to the periphery of the orthographic projection of the third surface 511 onto the substrate 101 can be approximately 0.2 μm to 1.2 μm. For example, the distance from the periphery of the orthographic projection of the first partition structure layer 53 onto the substrate 101 to the periphery of the orthographic projection of the third surface 511 onto the substrate 101 can be approximately 0.7 μm.

[0332] In an exemplary embodiment, the distance from the periphery of the orthographic projection of the first partition structure layer 53 on the substrate 101 to the periphery of the orthographic projection of the fifth surface 541 on the substrate 101 can be approximately 0.1 μm to 0.8 μm. For example, the distance from the periphery of the orthographic projection of the first partition structure layer 53 on the substrate 101 to the periphery of the orthographic projection of the fifth surface 541 on the substrate 101 can be approximately 0.45 μm.

[0333] In an exemplary embodiment, the distance from the periphery of the orthographic projection of the fourth partition structure layer 55 on the substrate 101 to the periphery of the orthographic projection of the third surface 511 on the substrate 101 can be approximately 0.1 μm to 0.5 μm. For example, the distance from the periphery of the orthographic projection of the fourth partition structure layer 55 on the substrate 101 to the periphery of the orthographic projection of the third surface 511 on the substrate 101 can be approximately 0.3 μm.

[0334] In an exemplary embodiment, the cross-sections of the first trench 100 and the third trench 300 in the direction perpendicular to the substrate 101 may include two connected inverted trapezoids. The first trench 100 has a first width W1 on the side away from the substrate 101 and a second width W2 on the side closer to the substrate 101, wherein the first width W1 is greater than the second width W2. The first trench 100 communicates with the third trench 300. The third trench 300 has a fifth width W5 on the side away from the substrate 101 and a sixth width W6 on the side closer to the substrate 101, wherein the fifth width W5 is greater than the sixth width W6. The fifth width W5 is greater than the second width W2. The first trench 100 extends from the first surface 531 along the direction close to the substrate 101 and penetrates the first partition structure layer 53. The third trench 300 extends from the fifth surface 541 along the direction close to the substrate 101 and penetrates the third partition structure layer 54. The two connected inverted trapezoids gradually decrease in the direction perpendicular to the substrate 101, abruptly increase at the connection between the first trench 100 and the third trench 300, and then gradually decrease to the side of the fourth partition structure layer 55 away from the substrate 101.

[0335] The width of the orthographic projection of the second partition structure layer 51 onto the substrate 101 is less than 4 / 5 of the width of the orthographic projection of the first defining layer 61 onto the substrate 101.

[0336] The width of the orthographic projection of the first partition structure layer 533 onto the substrate 101 can be approximately 5 μm to 10 μm. For example, the width of the orthographic projection of the first partition structure layer 533 onto the substrate 101 can be approximately 7.5 μm.

[0337] The width of the orthographic projection of the third partition structure layer 543 onto the substrate 101 can be approximately 5 μm to 10 μm. For example, the width of the orthographic projection of the third partition structure layer 543 onto the substrate 101 can be approximately 7.5 μm.

[0338] The distance between the orthographic projections of the two first partition structure layers 533 on the substrate 101 can be approximately 2 μm to 5 μm. For example, the distance between the orthographic projections of the two first partition structure layers 533 on the substrate 101 can be approximately 3.5 μm.

[0339] The distance between the orthographic projections of the two third partition structure layers 543 on the substrate 101 can be approximately 2 μm to 5 μm. For example, the distance between the orthographic projections of the two third partition structure layers 543 on the substrate 101 can be approximately 3.5 μm.

[0340] The orthographic projection of the fourth partition structure layer 55 on the substrate 101 covers the orthographic projection of the second partition structure layer 51 on the substrate 101.

[0341] In an exemplary embodiment, the orthographic projection of the second partition structure layer 51 on the substrate 101 is located within the orthographic projection of the partition structure layer on the substrate 101, and the orthographic projections of the second partition structure layer 51 on the substrate 101 overlap with the orthographic projections of the first defining layer 61 and the second defining layer 62 on the substrate 101.

[0342] The method for preparing the substrate disclosed herein uses a trench structure and an undercut structure 52 to increase the contact area between the partition structure 50 and the encapsulation layer, thereby enhancing the adhesion of the encapsulation layer and reducing the risk of encapsulation layer peeling.

[0343] The method for preparing the substrate disclosed herein, through the trench structure and the undercut structure 52, can enhance the encapsulation effect, reduce the risk of water, oxygen, etc. entering through the gap between the isolation structure 50 and the encapsulation layer, and enhance the reliability of the light-emitting device.

[0344] In an exemplary embodiment, the partition structure 50 has a mesh-like structure. The partition structure 50 can be a single, integral structure, as shown in FIG7a. The partition structure 50 can be divided into two second partition structure layers 513 by a groove structure, as shown in FIG7b.

[0345] 7. Form a light-emitting functional layer, a second electrode, an encapsulation layer, and an etching barrier layer.

[0346] In an exemplary embodiment, forming the light-emitting functional layer, the second electrode, the encapsulation layer, and the etch barrier layer may include: on the substrate 101 on which the aforementioned pattern is formed (taking the pattern formed in FIG. 4f after the formation of the second isolation structure layer 51, the isolation structure layer, and the first trench 100 as an example), patterning the anode protection layer 104 by a plasma etching process, at least partially removing the anode protection layer 104 on the first color anode 11, exposing the first color anode 11. Subsequently, on the substrate 101 on which the aforementioned pattern is formed, a first light-emitting functional layer material, a second electrode material, and a first encapsulation film are sequentially deposited by a coating process, such as a thermal evaporation coating process or magnetron sputtering.

[0347] On the substrate 101 on which the aforementioned pattern is formed, a photoresist pattern is formed. Through low-temperature exposure and etching processes, areas not covered by the photoresist are etched away, retaining the first light-emitting functional layer material covering the first color anode 11 to form the first light-emitting functional layer 31. Retaining the second electrode material covering the first light-emitting functional layer 31, a first color cathode 21 is formed. Retaining the first encapsulation film covering the first color cathode 21, a first color encapsulation layer 41 is formed, exposing the anode protection layer 104 covering the second color anode 12 and the third color anode 13. The first color cathode 21 is electrically connected to the second isolation structure layer 51 located on both sides of the first color anode 11.

[0348] On the substrate 101 on which the aforementioned pattern is formed, a first etch barrier film is deposited by a coating process, such as low temperature thin film encapsulation-plasma enhanced chemical vapor deposition (TFE CVD), atomic layer deposition (ALD), or magnetron sputtering; and the first etch barrier film covering the opening of the first color pixel is retained by an etching process to form a first color etch barrier layer 81.

[0349] On the substrate 101 on which the aforementioned pattern is formed, the anode protective layer 104 is patterned by a plasma etching process, at least partially removing the anode protective layer 104 on the second color anode 12, exposing the second color anode 12. Subsequently, on the substrate 101 on which the aforementioned pattern is formed, a second light-emitting functional layer material, a second electrode material, and a second encapsulation film are sequentially deposited by a coating process, such as thermal evaporation coating or magnetron sputtering.

[0350] On the substrate 101 with the aforementioned pattern, a photoresist pattern is formed. Through low-temperature exposure and etching processes, areas not covered by the photoresist are etched away, leaving the second light-emitting functional layer material covering the second color anode 12 intact to form the second light-emitting functional layer 32. The second electrode material covering the second light-emitting functional layer 32 is also intact to form the second color cathode 22. The second encapsulation film covering the second color cathode 22 is retained to form the second color encapsulation layer 42, exposing the anode protection layer 104 covering the third color anode 13. The second color cathode 22 is electrically connected to the second isolation structure layers 51 located on both sides of the second color anode 12.

[0351] On the substrate 101 on which the aforementioned pattern is formed, a second etch barrier film is deposited by a coating process, such as low temperature thin film encapsulation-plasma enhanced chemical vapor deposition (TFE CVD), atomic layer deposition (ALD), or magnetron sputtering; and by an etching process, the second etch barrier film covering the opening of the second color pixel is retained to form a second color etch barrier layer 82.

[0352] On the substrate 101 on which the aforementioned pattern is formed, the anode protective layer 104 is patterned by a plasma etching process, at least partially removing the anode protective layer 104 on the third color anode 13, exposing the third color anode 13. Subsequently, on the substrate 101 on which the aforementioned pattern is formed, a third light-emitting functional layer material, a second electrode material, and a third encapsulation film are sequentially deposited by a coating process, such as thermal evaporation coating or magnetron sputtering.

[0353] The display substrate of this embodiment can protect the surface of the first electrode by introducing an anode protection layer 104, which can ensure that the patterning (etching process) of the previous color light-emitting device has no effect on the color electrode of the subsequent color light-emitting device, and can ensure that the effective injection of holes and the photoelectric efficiency, lifespan and other indicators of the light-emitting device do not decrease.

[0354] On the substrate 101 on which the aforementioned pattern is formed, a photoresist pattern is formed. Through low-temperature exposure and etching processes, the areas not covered by the photoresist are etched away, leaving the third light-emitting functional layer material covering the third color anode 13, forming the third light-emitting functional layer 33. The second electrode material covering the third light-emitting functional layer 33 is also retained, forming the third color cathode 23. Finally, the third encapsulation film covering the third color cathode 23 is retained, forming the third color encapsulation layer 43. The third color cathode 23 is electrically connected to the second isolation structure layer 51 located on both sides of the third color anode 13, as shown in Figure 4l.

[0355] In this design, a first color anode 11, a first light-emitting functional layer 31, and a first color cathode 21 form the light-emitting device of a first sub-pixel. A second color anode 12, a second light-emitting functional layer 32, and a second color cathode 22 form the light-emitting device of a second sub-pixel. A third color anode 13, a third light-emitting functional layer 33, and a third color cathode 23 form the light-emitting device of a third sub-pixel. The light-emitting functional layers may include the first light-emitting functional layer 31, the second light-emitting functional layer 32, and the third light-emitting functional layer 33. The second electrode may include the first color cathode 21, the second color cathode 22, and the third color cathode 23. The encapsulation layer may include a first color encapsulation layer 41, a second color encapsulation layer 42, and a third color encapsulation layer 43. The etch stop layer may include a first color etch stop layer 81 and a second color etch stop layer 82. The orthographic projection of the first color etch stop layer 81 onto the substrate 101 at least covers the opening of the first color pixel, and the orthographic projection of the second color etch stop layer 82 onto the substrate 101 at least covers the orthographic projection of the opening of the second color pixel onto the substrate 101.

[0356] In an exemplary embodiment, the orthographic projection of the first color etch barrier layer 81 and the second color etch barrier layer 82 on the substrate 101 covers the orthographic projection of the pixel definition layer between the first color pixel opening and the second color pixel opening on the substrate 101, and the etch barrier layer is a continuous film layer.

[0357] The first color etch barrier layer 81 and the second color etch barrier layer 82 will be retained in the final light-emitting device structure, thus requiring high visible light transmittance (90%). Furthermore, the fabrication process of the first color etch barrier layer 81 and the second color etch barrier layer 82 is simple and compatible with existing thin-film encapsulation layer processes.

[0358] The first color etching barrier layer 81 and the second color etching barrier layer 82 can also increase the temporary water and oxygen barrier capability of the first color light-emitting device and the second color light-emitting device, preventing water and oxygen from entering the first color film layer and the second color film layer.

[0359] In an exemplary embodiment, the first light-emitting functional layer material, the second light-emitting functional layer material, the third light-emitting functional layer material, the first encapsulation film, the second encapsulation film, and the third encapsulation film can be formed by a thermal evaporation deposition process. Specifically, patterning the anode protection layer 104 using a plasma etching process can prevent damage to the first color anode 11, the second color anode 12, and the third color anode 13.

[0360] In an exemplary embodiment, the orthographic projections of the first light-emitting functional layer 31 and the first color anode 11 on the substrate 101 overlap. For example, the orthographic projections of the first light-emitting functional layer 31 on the substrate 101 and the first color anode 11 on the substrate 101 completely overlap, and the first light-emitting functional layer 31 and the first color anode 11 are in direct contact.

[0361] In an exemplary embodiment, the first light-emitting functional layer 31 may include at least one first light-emitting layer (EML), and any one or more of the following: hole injection layer (HIL), hole transport layer (HTL), electron blocking layer (EBL), hole blocking layer (HBL), electron transport layer (ETL), electron injection layer (EIL), and charge production layer (CGL). In this embodiment, the first light-emitting layer is red.

[0362] In an exemplary embodiment, the first color cathode 21, the second color cathode 22, and the third color cathode 23 may each include a cathode layer and an auxiliary cathode layer. The cathode layer is disposed on the side of the first light-emitting functional layer 31 away from the substrate 101, and the auxiliary cathode layer is disposed on the side of the cathode layer away from the substrate 101. At least a portion of the auxiliary cathode layer covers the surface of the cathode layer on the side away from the substrate 101 and is in direct contact with the cathode layer. At least a portion of the auxiliary cathode layer covers the sidewall of the second isolation structure layer 51 and is in direct contact with the sidewall of the second isolation structure layer 51. The auxiliary cathode layer connects the cathode layer and the second isolation structure layer 51.

[0363] In an exemplary embodiment, the orthogonal projection of the auxiliary cathode layer on the substrate 101 covers the orthogonal projection of the cathode layer on the substrate 101.

[0364] The method for preparing the display substrate in this embodiment connects the cathode layer and the second isolation structure layer 51 through an auxiliary cathode layer, thereby improving the conductivity of the cathode layer and the second isolation structure layer 51. This solves the problem that the unevenness of the isolation structure 50 causes the cathode layer to break during the evaporation process, resulting in an unstable connection between the cathode layer and the second isolation structure layer 51.

[0365] In an exemplary embodiment, the cathode layer can be a highly transparent and low work function co-evaporated metal thin film cathode fabricated by a thermal evaporation deposition process. Furthermore, it is ensured that the co-evaporated metal thin film cathode can be removed by a dry etching process. The material combination of the co-evaporated metal thin film can be, but is not limited to, magnesium (Mg) and aluminum (Al), ytterbium (Yb) and aluminum (Al), and lithium (Li) and aluminum (Al). The volume ratio between the material combinations can be approximately 1:9 to 4:6, for example, approximately 3.5:9. The thickness of the cathode layer can be approximately 0.008 μm to 0.02 μm, for example, approximately 0.014 μm.

[0366] In an exemplary embodiment, the auxiliary cathode layer can be made of a metal oxide by magnetron sputtering, such as at least one of indium tin oxide (ITO), indium zinc oxide (IZO), indium tin zinc oxide (ITZO), and aluminum-doped zinc oxide (AZO). The first color encapsulation layer 41 can be made of an inorganic material, and pixel-level encapsulation can be achieved through ultra-thin inorganic encapsulation.

[0367] The method for preparing the substrate disclosed herein includes an auxiliary cathode layer that may include a metal oxide. The metal oxide has better film coverage, which can ensure electrical contact between the auxiliary cathode layer and the cathode layer, as well as electrical contact between the auxiliary cathode layer and the second isolation structure layer 51.

[0368] In an exemplary embodiment, the orthographic projection of the first light-emitting functional layer 31 on the substrate 101 overlaps with the orthographic projection of the partition structure 50 located on both sides of the first color anode 11 on the substrate 101.

[0369] In an exemplary embodiment, the orthographic projection of the first light-emitting functional layer 31 on the substrate 101 overlaps with the orthographic projection of the second defining layer 62 on the substrate 101.

[0370] In an exemplary embodiment, the orthographic projection of the first color cathode 21 on the substrate 101 overlaps with the orthographic projection of the partition structure 50 located on both sides of the first color anode 11 on the substrate 101.

[0371] In an exemplary embodiment, the orthographic projection of the first color cathode 21 onto the substrate 101 overlaps with the orthographic projection portions of the first defining layer 61 and the second defining layer 62 onto the substrate 101.

[0372] In an exemplary embodiment, the orthographic projection of the first color encapsulation layer 41 on the substrate 101 overlaps with the orthographic projection of the partition structure 50 located on both sides of the first color anode 11 on the substrate 101.

[0373] In an exemplary embodiment, the orthographic projection of the first color encapsulation layer 41 on the substrate 101 overlaps with the orthographic projections of the first definition layer 61 and the second definition layer 62 on the substrate 101.

[0374] In an exemplary embodiment, the orthographic projections of the second light-emitting functional layer 32 and the second color anode 12 on the substrate 101 overlap. For example, the orthographic projections of the second light-emitting functional layer 32 on the substrate 101 and the second color anode 12 on the substrate 101 completely overlap, and the second light-emitting functional layer 32 and the second color anode 12 are in direct contact.

[0375] In an exemplary embodiment, the second light-emitting functional layer 32 may include at least one second light-emitting layer (EML), and any one or more of the following: hole injection layer (HIL), hole transport layer (HTL), electron blocking layer (EBL), hole blocking layer (HBL), electron transport layer (ETL), electron injection layer (EIL), and charge production layer (CGL). In this embodiment, the second light-emitting layer is blue.

[0376] In an exemplary embodiment, the orthographic projection of the second light-emitting functional layer 32 on the substrate 101 overlaps with the orthographic projection of the partition structure 50 located on both sides of the second color anode 12 on the substrate 101.

[0377] In an exemplary embodiment, the orthographic projection of the second light-emitting functional layer 32 on the substrate 101 overlaps with the orthographic projection of the second defining layer 62 on the substrate 101.

[0378] In an exemplary embodiment, the orthographic projection of the second color cathode 22 on the substrate 101 overlaps with the orthographic projection of the partition structure 50 located on both sides of the second color anode 12 on the substrate 101.

[0379] In an exemplary embodiment, the orthographic projection of the second color cathode 22 on the substrate 101 overlaps with the orthographic projection portions of the first defining layer 61 and the second defining layer 62 on the substrate 101.

[0380] In an exemplary embodiment, the orthographic projection of the second color encapsulation layer 42 on the substrate 101 overlaps with the orthographic projection of the partition structure 50 located on both sides of the second color anode 12 on the substrate 101.

[0381] In an exemplary embodiment, the orthographic projection of the second color encapsulation layer 42 on the substrate 101 overlaps with the orthographic projection portions of the first defining layer 61 and the second defining layer 62 on the substrate 101.

[0382] In an exemplary embodiment, the orthographic projections of the third light-emitting functional layer 33 and the third color anode 13 on the substrate 101 overlap. For example, the orthographic projections of the third light-emitting functional layer 33 on the substrate 101 and the orthographic projections of the third color anode 13 on the substrate 101 completely overlap, and the third light-emitting functional layer 33 and the third color anode 13 are in direct contact.

[0383] In an exemplary embodiment, the third light-emitting functional layer 33 may include at least one third light-emitting layer (EML), and any one or more of the following: hole injection layer (HIL), hole transport layer (HTL), electron blocking layer (EBL), hole blocking layer (HBL), electron transport layer (ETL), electron injection layer (EIL), and charge production layer (CGL). In this embodiment, the third light-emitting layer is green.

[0384] In an exemplary embodiment, the orthographic projection of the third light-emitting functional layer 33 on the substrate 101 overlaps with the orthographic projection of the partition structure 50 located on both sides of the third color anode 13 on the substrate 101.

[0385] In an exemplary embodiment, the orthographic projection of the third light-emitting functional layer 33 on the substrate 101 overlaps with the orthographic projection of the second defining layer 62 on the substrate 101.

[0386] In an exemplary embodiment, the orthographic projection of the third color cathode 23 on the substrate 101 overlaps with the orthographic projection of the partition structure 50 located on both sides of the third color anode 13 on the substrate 101.

[0387] In an exemplary embodiment, the orthographic projection of the third color cathode 23 on the substrate 101 overlaps with the orthographic projection portions of the first defining layer 61 and the second defining layer 62 on the substrate 101.

[0388] In an exemplary embodiment, the orthographic projection of the third color encapsulation layer 43 on the substrate 101 overlaps with the orthographic projection of the partition structure 50 located on both sides of the third color anode 13 on the substrate 101.

[0389] In an exemplary embodiment, the orthographic projection of the third color encapsulation layer 43 on the substrate 101 overlaps with the orthographic projection portions of the first defining layer 61 and the second defining layer 62 on the substrate 101.

[0390] Figure 9a is a scanning electron microscope (SEM) image of the patterned second color encapsulation film during the fabrication process of a conventional display substrate. The first color encapsulation layer 41 in the figure is damaged. Figure 9b is a scanning electron microscope (SEM) image of the patterned second color encapsulation film during the fabrication process of a display substrate according to an embodiment of this disclosure. The first color encapsulation layer 41 in the figure is intact.

[0391] In an exemplary embodiment, the pixel aperture may further include a third color pixel aperture, and no etching barrier layer is disposed above the third color pixel aperture.

[0392] In addition, in some embodiments, a third etch barrier film can be deposited on the third color encapsulation layer 43 by a coating process, such as low temperature thin film encapsulation-plasma enhanced chemical vapor deposition (TFE CVD), atomic layer deposition (ALD) or magnetron sputtering; and the third etch barrier film covering the third pixel opening is retained by an etching process to form a third color etch barrier layer to protect the third color encapsulation layer 43.

[0393] In an exemplary embodiment, the materials of the first color etch stop layer 81, the second color etch stop layer 82, and the third color etch stop layer can be aluminum oxide (Al2O3), silicon oxide (SiOx), amorphous indium tin oxide (IZO), and indium tin oxide (ITO). The first color etch stop layer 81, the second color etch stop layer 82, and the third color etch stop layer can be a single-layer structure or a multi-layer structure, and the materials of each layer can be the same or different.

[0394] In an exemplary embodiment, the first color etch barrier layer 81 and the second color etch barrier layer 82 are made of different materials.

[0395] In an exemplary embodiment, the first color etch barrier layer 81 and the second color etch barrier layer 82 have different thicknesses.

[0396] Figure 5 is a schematic diagram showing that during the fabrication process of the display substrate according to an embodiment of the present disclosure, an open mask 70 can be directly used, and an evaporation source 90 can be used to sequentially spray the light-emitting functional layer material, the second electrode material, and the encapsulation layer material onto the substrate 101 with the aforementioned pattern to form the light-emitting functional layer, the second electrode, and the encapsulation layer.

[0397] In an exemplary embodiment, the method for fabricating a display substrate according to this disclosure can simultaneously form a light-emitting functional layer and a second electrode for multiple sub-pixels emitting the same color through the same fabrication process. For example, the method for fabricating a display substrate according to this disclosure can first form a first light-emitting functional layer 31 and a first color cathode 21 for multiple first sub-pixels through a first thermal evaporation coating process; then, through a second thermal evaporation coating process, simultaneously form a second light-emitting functional layer 32 and a second color cathode 22 for multiple second sub-pixels; finally, through a third thermal evaporation coating process, simultaneously form a third light-emitting functional layer 33 and a third color cathode 23 for multiple third sub-pixels. In the above process, the anode protection layer 104 can be patterned by a plasma etching process to expose the corresponding color anode, while retaining the anode protection layer 104 covering the subsequent color anode, so that the current thermal evaporation coating process and patterning (etching process) process have no effect on the color anode of the subsequent color light-emitting device.

[0398] In an exemplary embodiment, the light-emitting device of a sub-pixel can be a multilayer light-emitting device. For example, the first color light-emitting device may include a first color anode 11, a first color cathode 21, and a first light-emitting functional layer 31 disposed between the first color anode 11 and the first color cathode 21. The first light-emitting functional layer 31 may include a hole injection layer disposed on the first color anode 11, a first hole transport layer disposed on the hole injection layer, a first light-emitting layer disposed on the first hole transport layer, a first electron transport layer disposed on the first light-emitting layer, a charge production layer disposed on the first electron transport layer, a second hole transport layer disposed on the charge production layer, a second light-emitting layer disposed on the second hole transport layer, a second electron transport layer disposed on the second light-emitting layer, and an electron injection layer disposed on the second electron transport layer.

[0399] In an exemplary embodiment, the light-emitting device of a sub-pixel can be a single-layer light-emitting device. For example, the first color light-emitting device may include a first color anode 11, a first color cathode 21, and a first light-emitting functional layer 31 disposed between the first color anode 11 and the first color cathode 21. The first light-emitting functional layer 31 may include a hole injection layer disposed on the first color anode 11, a hole transport layer disposed on the hole injection layer, a light-emitting layer disposed on the hole transport layer, an electron transport layer disposed on the light-emitting layer, and an electron injection layer disposed on the electron transport layer.

[0400] Given the extreme sensitivity of OLED light-emitting devices to water and oxygen, all sub-pixels must be completely isolated / independent. Therefore, for each pixel, all its first electrode, light-emitting functional layer, and second electrode are independent. Their thickness can be flexibly adjusted according to the optical and electrical structures of each light-emitting device to achieve the optimal resonant microcavity, ensuring the light emission efficiency and color of the light-emitting device. Furthermore, the independent pixel structure ensures that all film layers are not damaged by etching during the pixelation process.

[0401] 15. Form the encapsulation structure layer 44.

[0402] In an exemplary embodiment, forming the encapsulation structure layer 44 may include: covering an inorganic dielectric film on the substrate 101 on which the aforementioned pattern is formed, to form an encapsulation structure layer 44 covering an etch barrier layer and a third color encapsulation layer 43, as shown in FIG3.

[0403] The display substrate of this embodiment, by introducing an anode protection layer 104, an etching barrier layer, and a partition structure 50 with a trench structure and an undercut structure 52, ensures the effect of pixel-level packaging and protects the first electrode and the encapsulation layer from being damaged during the photolithography patterning process. This allows each sub-pixel to form an independent, stable, and effectively protected microcapsule-like structure, thereby solving the problem that in the photolithography pixelation process, the top layer ITO of the first electrode is etched, causing a change in the work function, affecting the hole injection efficiency, and resulting in low photoelectric efficiency and poor lifespan of the light-emitting device. This further reduces the risk of process defects in the photolithography pixelation process, thereby ensuring the preparation of a high-resolution full-color AMOLED display substrate. This solves the problems of low yield and high requirements for equipment, process environment, and production environment in the photolithography method for OLED pixel preparation, significantly reducing production costs and improving the production yield of the new process.

[0404] Furthermore, by adding an etching barrier layer to the encapsulation layer, the intrusion of water and oxygen caused by encapsulation layer damage due to the etching process during semiconductor photolithography pixelation is avoided, thus protecting the integrity of the encapsulation layer. Moreover, the partition structure 50 with trench structure and undercut structure 52 achieves a pixel-level thin-film encapsulation layer, which can solve the failure of light-emitting devices caused by water and oxygen intrusion in atmospheric environments during photolithography pixelation processes, ensuring the edge sealing of pixel-level thin-film encapsulation and improving the yield of photolithography pixelation processes.

[0405] On the other hand, this disclosure also provides a method for preparing a display substrate, which may include:

[0406] A first electrode is formed on the substrate 101;

[0407] A pixel definition layer is formed on the side of the first electrode away from the substrate 101. The pixel definition layer defines a pixel opening that exposes at least a portion of the first electrode.

[0408] A partition structure 50 is formed on the side of the pixel definition layer away from the substrate 101;

[0409] The partition structure 50 may include a first partition structure layer 53 and a second partition structure layer 51 located between the first partition structure layer 53 and the substrate 101. The orthogonal projection width of the first partition structure layer 53 on the substrate 101 is greater than the orthogonal projection width of the second partition structure layer 51 on the substrate 101.

[0410] The first partition structure layer 53 has a first trench 100, the first trench 100 having a first width W1 on the side away from the substrate 101, and the first trench 100 having a second width W2 on the side close to the substrate 101, the first width W1 being greater than the second width W2.

[0411] The method for preparing a display substrate may further include:

[0412] Before forming the partition structure 50 on the side of the pixel definition layer away from the substrate 101, an anode protection layer 104 is formed on the side of the pixel definition layer away from the substrate 101. The anode protection layer 104 is made of an inorganic material.

[0413] In an exemplary embodiment, the first partition structure layer 53 has a first surface 531 away from the substrate 101 and a second surface 532 close to the substrate 101. The orthogonal projection width of the first surface 531 on the substrate 101 is smaller than the orthogonal projection width of the second surface 532 on the substrate 101.

[0414] In an exemplary embodiment, the orthographic projection of the first trench 100 on the substrate 101 is within the range of the orthographic projection of the second partition structure layer 51 on the substrate 101.

[0415] In an exemplary embodiment, the second partition structure layer 51 has a second trench 200, the first trench 100 is connected to the second trench 200, the second trench 200 has a third width W3 on the side away from the substrate 101, and the second trench 200 has a fourth width W4 on the side close to the substrate 101, the third width W3 being greater than the fourth width W4.

[0416] In an exemplary embodiment, the third width W3 is greater than the second width W2.

[0417] In an exemplary embodiment, the second partition structure layer 51 has a third surface 511 away from the substrate 101 and a fourth surface 512 close to the substrate 101. The orthographic projection width of the third surface 511 on the substrate 101 is greater than or less than the orthographic projection width of the fourth surface 512 on the substrate 101.

[0418] In an exemplary embodiment, forming a partition structure 50 on the side of the pixel definition layer away from the substrate 101 may include:

[0419] A third partition structure layer 54 is formed between the first partition structure layer 53 and the second partition structure layer 51. The orthogonal projection width of the third partition structure layer 54 on the substrate 101 is smaller than the orthogonal projection width of the first partition structure layer 53 on the substrate 101.

[0420] In an exemplary embodiment, the orthographic projection of the first trench 100 onto the substrate 101 is within the range of the orthographic projection of the third partition structure layer 54 onto the substrate 101.

[0421] In an exemplary embodiment, the number of first trenches 100 is two.

[0422] In an exemplary embodiment, the third partition structure layer 54 has a third trench 300, the first trench 100 is connected to the third trench 300, the third trench 300 has a fifth width W5 on the side away from the substrate 101, and the third trench 300 has a sixth width W6 on the side close to the substrate 101, the fifth width W5 being greater than the sixth width W6.

[0423] In an exemplary embodiment, the fifth width W5 is greater than the second width W2.

[0424] In an exemplary embodiment, there are two first grooves 100 and two third grooves 300, which are connected to the two first grooves 100 in a one-to-one correspondence.

[0425] In an exemplary embodiment, forming a partition structure 50 on the side of the pixel definition layer away from the substrate 101 may further include:

[0426] A fourth partition structure layer 55 is formed between the second partition structure layer 51 and the third partition structure layer 54. The orthogonal projection width of the fourth partition structure layer 55 on the substrate 101 is greater than the orthogonal projection width of the second partition structure layer 51 on the substrate 101, and the orthogonal projection width of the fourth partition structure layer 55 on the substrate 101 is greater than the orthogonal projection width of the third partition structure layer 54 on the substrate 101.

[0427] In an exemplary embodiment, the fourth partition structure layer 55 has a seventh surface 551 away from the substrate 101 and an eighth surface 552 close to the substrate 101. The orthographic projection width of the seventh surface 551 on the substrate 101 is smaller than the orthographic projection width of the eighth surface 552 on the substrate 101.

[0428] In an exemplary embodiment, the second partition structure layer 51 has a third surface 511 that is away from the substrate 101, and the distance between the periphery of the orthographic projection of the fourth partition structure layer 55 on the substrate 101 and the periphery of the orthographic projection of the third surface 511 on the substrate 101 is 0.1 μm to 0.5 μm.

[0429] In an exemplary embodiment, forming a partition structure 50 on the side of the pixel definition layer away from the substrate 101 may further include:

[0430] A third partition structure layer 54 is formed between the first partition structure layer 53 and the second partition structure layer 51. The orthographic projection width of the third partition structure layer 54 on the substrate 101 is greater than the orthographic projection width of the second partition structure layer 51 on the substrate 101, and the orthographic projection width of the third partition structure layer 54 on the substrate 101 is less than the orthographic projection width of the first partition structure layer 53 on the substrate 101.

[0431] The third partition structure layer 54 has a third groove 300, which is connected between the first groove 100 and the third groove 300.

[0432] The third trench 300 has a fifth width W5 on the side away from the substrate 101 and a sixth width W6 on the side closer to the substrate 101, wherein the fifth width W5 is greater than the sixth width W6.

[0433] In the exemplary embodiment, the fifth width W5 is greater than the second width W2;

[0434] The third width W3 is greater than the sixth width W6.

[0435] In an exemplary embodiment, the third partition structure layer 54 has a fifth surface 541 away from the substrate 101 and a sixth surface 542 close to the substrate 101. The orthographic projection width of the fifth surface 541 on the substrate 101 is smaller than the orthographic projection width of the sixth surface 542 on the substrate 101.

[0436] In an exemplary embodiment, the second partition structure layer 51 has a third surface 511 that is away from the substrate 101, and the distance between the periphery of the orthographic projection of the first partition structure layer 53 on the substrate 101 and the periphery of the orthographic projection of the third surface 511 on the substrate 101 is 0.2 μm to 1.2 μm.

[0437] In an exemplary embodiment, the third partition structure layer 54 has a fifth surface 541 that is away from the substrate 101, and the distance from the periphery of the orthographic projection of the first partition structure layer 53 on the substrate 101 to the periphery of the orthographic projection of the fifth surface 541 on the substrate 101 is 0.1 μm to 0.8 μm.

[0438] In an exemplary embodiment, forming a pixel definition layer on the side of the first electrode away from the substrate 101 may include:

[0439] A first defining layer 61 is formed on the side of the first electrode away from the substrate 101;

[0440] A second definition layer 62 is formed on the side of the first definition layer 61 away from the substrate 101;

[0441] The first defining layer 61 is made of organic materials, and the second defining layer 62 is made of inorganic materials.

[0442] In an exemplary embodiment, the partition structure 50 has a grid-like structure.

[0443] In an exemplary embodiment, the partition structure 50 is located between the pixel openings and is disposed around the pixel openings.

[0444] In an exemplary embodiment, one or more partition structures 50 are provided between pixel openings.

[0445] In an exemplary embodiment, the mesh structure has a mesh opening 400, which has the same shape as the pixel opening. The orthographic projection of the pixel opening on the substrate 101 is located within the orthographic projection of the mesh opening 400 on the substrate 101 and does not overlap.

[0446] In an exemplary embodiment, the intersection of the lines connecting the geometric centers of four adjacent pixel openings has at least one partition structure 50.

[0447] The method for preparing a display substrate may further include:

[0448] A light-emitting functional layer is formed on the side of the partition structure 50 away from the substrate 101, and the light-emitting functional layer is located inside the pixel opening;

[0449] A second electrode is formed on the side of the light-emitting functional layer away from the substrate 101, and the second electrode is coupled to the second isolation structure layer 51 of the isolation structure 50.

[0450] An encapsulation layer is formed on the side of the second electrode away from the substrate 101, and the encapsulation layer covers the pixel opening and the partition structure 50.

[0451] An etch barrier layer is formed on the side of the encapsulation layer away from the substrate 101. The etch barrier layer is made of a transparent material.

[0452] In an exemplary embodiment, the pixel opening may include a first color pixel opening and a second color pixel opening, and the etch barrier layer may include a first color etch barrier layer 81 and a second color etch barrier layer 82. The orthographic projection of the first color etch barrier layer 81 on the substrate 101 at least covers the first color pixel opening, and the orthographic projection of the second color etch barrier layer 82 on the substrate 101 at least covers the orthographic projection of the second color pixel opening on the substrate 101.

[0453] In an exemplary embodiment, the first color etch barrier layer 81 and the second color etch barrier layer 82 are made of different materials.

[0454] In an exemplary embodiment, the first color etch barrier layer 81 and the second color etch barrier layer 82 have different thicknesses.

[0455] In an exemplary embodiment, the pixel aperture may further include a third color pixel aperture, and no etching barrier layer is disposed above the third color pixel aperture.

[0456] In an exemplary embodiment, the orthogonal projection of the etch barrier layer on the substrate 101 also covers the orthogonal projection of the pixel definition layer between the first color pixel opening and the second color pixel opening on the substrate 101.

[0457] In an exemplary embodiment, forming a second electrode on the side of the light-emitting functional layer away from the substrate 101 may include:

[0458] A cathode layer on the side of the light-emitting functional layer away from the substrate 101;

[0459] An auxiliary cathode layer is formed on the side of the cathode layer away from the substrate 101.

[0460] In an exemplary embodiment, the thickness of the encapsulation layer is 1.5 times the thickness of the second partition structure layer 51.

[0461] This disclosure also provides a display device, which may include the aforementioned display substrate. The display device may be any product or component with display function, such as a mobile phone, wearable device, AR or VR display device, in-vehicle display device, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator, and the embodiments of the present invention are not limited thereto.

[0462] While the embodiments disclosed herein are as described above, the content is merely for the purpose of facilitating understanding of this disclosure and is not intended to limit this disclosure. Any person skilled in the art to which this disclosure pertains may make any modifications and changes in the form and details of the implementation without departing from the spirit and scope disclosed herein; however, the scope of patent protection of this disclosure shall still be determined by the scope defined in the appended claims.

Claims

1. A display substrate, comprising: a substrate substrate; a first electrode disposed on the substrate substrate; a pixel definition layer disposed on a side of the first electrode distal to the substrate substrate, the pixel definition layer defining a pixel opening that exposes at least a portion of the one first electrode; a partition structure disposed on a side of the pixel definition layer distal to the substrate substrate; the partition structure comprising a first partition structure layer and a second partition structure layer between the first partition structure layer and the substrate substrate, a width of a footprint of the first partition structure layer on the substrate substrate being greater than a width of a footprint of the second partition structure layer on the substrate substrate; the first partition structure layer having a first trench, the first trench having a first width on a side distal to the substrate substrate and a second width on a side proximal to the substrate substrate, the first width being greater than the second width. 2.The display substrate of claim 1, wherein, the first partition structure layer having a first surface distal to the substrate substrate and a second surface proximal to the substrate substrate, a width of a footprint of the first surface on the substrate substrate being less than a width of a footprint of the second surface on the substrate substrate. 3.The display substrate of claim 1, wherein, a footprint of the first trench on the substrate substrate is within a footprint of the second partition structure layer on the substrate substrate. 4.The display substrate of claim 1, wherein, the second partition structure layer having a second trench, the first trench and the second trench being in communication, the second trench having a third width on a side distal to the substrate substrate and a fourth width on a side proximal to the substrate substrate, the third width being greater than the fourth width. 5.The display substrate of claim 4, wherein, the third width being greater than the second width. 6.The display substrate according to claim 3 or 4, wherein the second partition structure layer having a third surface distal to the substrate substrate and a fourth surface proximal to the substrate substrate, a width of a footprint of the third surface on the substrate substrate being greater than or less than a width of a footprint of the fourth surface on the substrate substrate. 7.The display substrate of claim 3, wherein, the partition structure further comprising a third partition structure layer disposed between the first partition structure layer and the second partition structure layer, a width of a footprint of the third partition structure layer on the substrate substrate being less than a width of a footprint of the first partition structure layer on the substrate substrate. 8.The display substrate of claim 7, wherein, a footprint of the first trench on the substrate substrate is within a footprint of the third partition structure layer on the substrate substrate. 9.The display substrate of claim 8, wherein, a number of the first trenches is two. 10.The display substrate of claim 7, wherein, the third partition structure layer having a third trench, the first trench and the third trench being in communication, the third trench having a fifth width on a side distal to the substrate substrate and a sixth width on a side proximal to the substrate substrate, the fifth width being greater than the sixth width. 11.The display substrate of claim 10, wherein, the fifth width being greater than the second width. 12.The display substrate of claim 10, wherein, a number of the first trenches is two, a number of the third trenches is two and each of the third trenches is in one-to-one correspondence with one of the first trenches. 13.The display substrate of claim 12, wherein, The partition structure further comprises a fourth partition structure layer, the fourth partition structure layer is arranged between the second partition structure layer and the third partition structure layer, the fourth partition structure layer has a projection width on the substrate which is greater than the projection width of the second partition structure layer on the substrate, and the fourth partition structure layer has a projection width on the substrate which is greater than the projection width of the third partition structure layer on the substrate. 14.The display substrate of claim 13, wherein, The fourth partition structure layer has a seventh surface away from the substrate and an eighth surface close to the substrate, and the projection width of the seventh surface on the substrate is less than the projection width of the eighth surface on the substrate. 15.The display substrate of claim 13, wherein, The second partition structure layer has a third surface away from the substrate, and the distance between the periphery of the projection of the fourth partition structure layer on the substrate and the periphery of the projection of the third surface on the substrate is 0.1-0.5 μm. 16.The display substrate of claim 4, wherein, The partition structure further comprises a third partition structure layer, the third partition structure layer is arranged between the first partition structure layer and the second partition structure layer, the third partition structure layer has a projection width on the substrate which is greater than the projection width of the second partition structure layer on the substrate, and the third partition structure layer has a projection width on the substrate which is less than the projection width of the first partition structure layer on the substrate. The third partition structure layer has a third groove, the third groove is communicated between the first groove and the third groove. The third groove has a fifth width on the side away from the substrate, and has a sixth width on the side close to the substrate, and the fifth width is greater than the sixth width. 17.The display substrate of claim 16, wherein, The fifth width is greater than the second width. The third width is greater than the sixth width. 18.The display substrate according to claim 8 or 10, wherein The third partition structure layer has a fifth surface away from the substrate and a sixth surface close to the substrate, and the projection width of the fifth surface on the substrate is less than the projection width of the sixth surface on the substrate.

19. The display substrate according to any one of claims 1, 7 or 16, wherein, The second partition structure layer has a third surface away from the substrate, and the distance between the periphery of the projection of the first partition structure layer on the substrate and the periphery of the projection of the third surface on the substrate is 0.2-1.2 μm.

20. The display substrate according to any one of claims 7 or 16, wherein, The third partition structure layer has a fifth surface away from the substrate, and the distance between the periphery of the projection of the first partition structure layer on the substrate and the periphery of the projection of the fifth surface on the substrate is 0.1-0.8 μm. 21.The display substrate of claim 1, wherein, The pixel definition layer comprises a first definition layer and a second definition layer, the first definition layer is arranged on the substrate, and the second definition layer is arranged on the side of the first definition layer away from the substrate. The first definition layer is made of organic material, and the second definition layer is made of inorganic material. 22.The display substrate of claim 1, wherein, The partition structure has a grid structure.

23. The display substrate of claim 22, wherein, The partition structure is located between the pixel openings and arranged around the pixel openings.

24. The display substrate of claim 23, wherein, The pixel opening is surrounded by one or more of the partition structures. 25.The display substrate of claim 23, wherein, The grid structure has grid openings, the grid openings have the same shape as the pixel openings, and a normal projection of the pixel openings on the substrate substrate is located within a normal projection of the grid openings on the substrate substrate and does not overlap.

26. The display substrate of claim 23, wherein, The intersection of lines connecting geometric centers of four adjacent pixel openings has at least one partition structure.

27. The display substrate of claim 1, wherein, The display substrate further comprises a light-emitting functional layer, which is located in the pixel opening; A second electrode is located on a side of the light-emitting functional layer away from the substrate substrate, and the second electrode is coupled with a second partition structure layer of the partition structure; An encapsulation layer is located on a side of the second electrode away from the substrate substrate, and the encapsulation layer covers the pixel opening and the partition structure; An etching barrier layer is provided on a side of the encapsulation layer away from the substrate substrate, and the etching barrier layer is made of a transparent material. 28.The display substrate of claim 27, wherein, The pixel opening includes a first color pixel opening and a second color pixel opening, the etching barrier layer includes a first color etching barrier layer and a second color etching barrier layer, a normal projection of the first color etching barrier layer on the substrate substrate at least covers the first color pixel opening, and a normal projection of the second color etching barrier layer on the substrate substrate at least covers a normal projection of the second color pixel opening on the substrate substrate. 29.The display substrate of claim 28, wherein, The first color etching barrier layer and the second color etching barrier layer are made of different materials. 30.The display substrate of claim 28, wherein, The first color etching barrier layer and the second color etching barrier layer have different thicknesses. 31.The display substrate of claim 28, wherein, The pixel opening further includes a third color pixel opening, and no etching barrier layer is provided above the third color pixel opening. 32.The display substrate of claim 28, wherein, The normal projection of the etching barrier layer on the substrate substrate further covers a normal projection of the pixel definition layer on the substrate substrate between the first color pixel opening and the second color pixel opening. 33.The display substrate of claim 27, wherein, The second electrode includes a cathode layer and an auxiliary cathode layer. 34.The display substrate of claim 27, wherein, The thickness of the encapsulation layer is 1.5 times the thickness of the second partition structure layer.

35. A display device comprising the display substrate according to any one of claims 1 to 34.

36. A method for manufacturing a display substrate, comprising: forming a first electrode on a substrate substrate; forming a pixel definition layer on a side of the first electrode away from the substrate substrate, the pixel definition layer defining a pixel opening, the pixel opening exposing at least part of the first electrode; forming a partition structure on a side of the pixel definition layer away from the substrate substrate; the partition structure includes a first partition structure layer and a second partition structure layer between the first partition structure layer and the substrate substrate, a normal projection of the first partition structure layer on the substrate substrate has a width greater than a normal projection of the second partition structure layer on the substrate substrate; the first partition structure layer has a first groove, the first groove has a first width on a side away from the substrate substrate, and the first groove has a second width on a side close to the substrate substrate, the first width being greater than the second width.

37. The manufacturing method of display substrate according to claim 36, further comprising: forming an anode protection layer on the side of the pixel definition layer away from the substrate before forming the partition structure on the side of the pixel definition layer away from the substrate; 38. The method of manufacturing according to claim 36, wherein, the second partition structure layer has a second groove, and the first groove and the second groove are communicated.

39. The method of manufacturing according to claim 36, wherein, the forming the partition structure on the side of the pixel definition layer away from the substrate comprises: forming a third partition structure layer between the first partition structure layer and the second partition structure layer, and a width of a normal projection of the third partition structure layer on the substrate is less than a width of a normal projection of the first partition structure layer on the substrate; the third partition structure layer has a third groove, and the first groove and the third groove are communicated.

40. The method of manufacturing according to claim 39, wherein, the forming the partition structure on the side of the pixel definition layer away from the substrate further comprises: forming a fourth partition structure layer between the second partition structure layer and the third partition structure layer, and a width of a normal projection of the fourth partition structure layer on the substrate is greater than a width of a normal projection of the second partition structure layer on the substrate, and a width of a normal projection of the fourth partition structure layer on the substrate is greater than a width of a normal projection of the third partition structure layer on the substrate.

41. The method of manufacturing according to claim 36, wherein, the forming the pixel definition layer on the side of the first electrode away from the substrate comprises: forming a first definition layer on the side of the first electrode away from the substrate; forming a second definition layer on the side of the first definition layer away from the substrate; the first definition layer is made of organic material, and the second definition layer is made of inorganic material.

42. The manufacturing method according to claim 36, further comprising: forming a light emitting functional layer on the side of the partition structure away from the substrate, and the light emitting functional layer is located in the pixel opening; forming a second electrode on the side of the light emitting functional layer away from the substrate, and the second electrode is coupled with the second partition structure layer of the partition structure; forming an encapsulation layer on the side of the second electrode away from the substrate, and the encapsulation layer covers the pixel opening and the partition structure; forming an etching stop layer on the side of the encapsulation layer away from the substrate, and the etching stop layer is made of transparent material.

43. The method of manufacturing according to claim 42, wherein, the forming the second electrode on the side of the light emitting functional layer away from the substrate comprises: forming a cathode layer on the side of the light emitting functional layer away from the substrate; forming an auxiliary cathode layer on the side of the cathode layer away from the substrate.

Images