Transistor system, resonator and oscillator comprising such a system

Abstract

The invention relates to a transistor electrical system comprising a first transistor (T1) having control, input and output terminals (cd1, e1, s1) configured to be coupled to a bias circuit (10), a second transistor (T2) having control, input and output terminals (cd2, e2, s2) configured to be coupled to the bias circuit (10), an inductive device (2) coupled to the control terminals (cd1, cd2), a first capacitive component (C1) connected in series between the input terminal (e1) of the first transistor (T1) and the output terminal (s2) of the second transistor (T2); and a second capacitive component (C2) connected in series between the input terminal (e2) of the second transistor (T2) and the output terminal (s1) of the first transistor (T1).

Description

[0001] Transistor, resonator and oscillator system comprising such a system

[0002] TECHNICAL FIELD OF THE INVENTION

[0003] The present invention relates to transistor systems, particularly suitable for the realization of resonators and oscillators.

[0004] STATE OF THE ART

[0005] Generally speaking, an electrical system is defined as a system comprising components, known as integrated components, fabricated on a semiconductor substrate, or components, known as discrete components, fabricated on other types of substrates, such as composite substrates. Currently, various electrical systems exist that are capable of resonance, such as piezoelectric resonators and inductance-capacitance resonators. When sufficient energy is supplied to these resonators to compensate for their inherent energy dissipation, they can function as oscillators. Resonators are configured to modify the signals they receive into corresponding output signals with altered characteristics. For example, resonators can be used as filters in signal and image processing.Furthermore, oscillators are configured to generate signals, particularly signals used by electronic circuits in various technical fields such as telecommunications, sensors, radar, measuring devices, etc. Thus, for telecommunications systems, the oscillator's main role is to provide signals to drive external circuits, such as mixers, transmitters, receivers, etc.

[0006] In general, a resonator is an electrical circuit that, at a given frequency, called the resonant frequency or operating frequency, presents an impedance across its terminals. This impedance has a zero imaginary part and a non-zero real part, called pure resistance. In the case of a passive resonator, the real part is positive and represents the inherent losses of the resonator. For an active resonator, that is, one containing transistors, the transistors reduce the value of the real part (and therefore the losses), or even make the real part negative. In the case of active resonators with a negative real part, the resonator is said to be lossless and naturally generates a periodic signal across its terminals. In this case, the resonator is therefore considered an oscillator.An oscillator is a device equipped with a resonator electrically coupled to a transistor circuit, also called a loss compensation circuit, and a biasing circuit to operate the transistors, in order to produce a periodic electrical signal, that is, a signal having a frequency denoted as the oscillation frequency. An oscillator can generate a signal at a fixed frequency or at a variable frequency; in the latter case, it is called a VCO (Voltage Controlled Oscillator).

[0007] One example is the publication: "77.3-GHz Standing-Wave Oscillator Based on an Asymmetrical Tunable Slow-Wave Coplanar Stripline Resonator," by L. Gomes et al., in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 68, no. 8, pp. 3158-3169, Aug. 2021, which presents a loss-compensated oscillator using an active transistor crossover pair. However, such an oscillator's performance drops drastically, and more specifically its power consumption increases and its oscillating capacity decreases, when coupled to an external circuit with low impedance (typically less than 100 ohms). To solve this problem, the authors use buffers (i.e., buffer amplifiers) designed to isolate the oscillator from the external circuit and limit the interference from the external circuit on the oscillator. But adding such buffer amplifiers loads the oscillator capacitively.This results in a reduced operating frequency range when used as a voltage-controlled oscillator, as well as a reduced maximum operating frequency. Furthermore, the buffers require a larger silicon area, increasing manufacturing costs. The structure of such an oscillator is more complex. Finally, the addition of buffers leads to increased power consumption. These buffers therefore impact the oscillator's performance by reducing the maximum operating frequency, increasing power consumption, narrowing the operating frequency range in the case of a voltage-controlled oscillator, and increasing the size and cost of the circuit.

[0008] One example is the publication: “A 64 GHz 5 mW Low Phase Noise gm-Boosted Colpitts CMOS VCO with Self-Switched Biasing Technique,” ​​by TN Nguyen, PP Pande, and D. Heo, in IEEE MTT-S Int. Microw. Symp. Dig., May 2015, pp. 17-22, which describes a voltage-controlled oscillator that uses a technique to improve the efficiency of active compensation by using a transconductance boost effect on the transistors (transconductance is denoted by gm, and the “gm-boost” effect is the transconductance boost effect). The gm-boost effect is achieved by adding two additional transistors. However, this solution is only possible with Colpitts oscillators (that is, oscillators whose oscillation frequency is determined by two capacitors and an inductor).Furthermore, adding transistors in series requires a higher minimum supply voltage than if there were only one transistor.

[0009] An object of the present invention is therefore to propose a transistor system, hereinafter referred to as an active cell, to overcome the disadvantages mentioned above and whose performance is improved compared to prior art transistor systems.

[0010] Another objective is to provide an active cell that can function as a resonator or oscillator.

[0011] Another objective is to provide an active cell that operates with lower power consumption than prior art transistor systems.

[0012] Another objective is to provide an active cell with a higher maximum operating frequency compared to prior art transistor systems. Another objective is to provide a variable frequency active cell with a wider operating frequency range compared to prior art transistor systems.

[0013] Another objective is to provide an active cell that works with external circuits of lower impedance than that permitted by prior art systems.

[0014] Another objective is to provide an oscillator based on an active cell, the size of which is reduced compared to the transistor systems of the prior art.

[0015] SUMMARY OF THE INVENTION

[0016] To achieve these objectives, a transistor-based system is proposed, comprising:

[0017] - the first and second main boundary markers; and

[0018] - an inductive device.

[0019] The system also includes:

[0020] - a first transistor comprising a first terminal, called the control terminal, coupled to the inductive device, a second terminal, called the input terminal, coupled to the first main terminal, and a third terminal, called the output terminal, the control, input and output terminals of the first transistor being configured to be coupled to a biasing circuit; and

[0021] - a second transistor comprising a first terminal, called the control terminal, coupled to the inductive device, a second terminal, called the input terminal, coupled to the second main terminal, and a third terminal, called the output terminal, the control, input and output terminals of the second transistor being configured to be coupled to the biasing circuit;

[0022] - a first capacitive component connected in series between the input terminal of the first transistor and the output terminal of the second transistor; and

[0023] - a second capacitive component coupled in series between the input terminal of the second transistor and the output terminal of the first transistor.

[0024] Thus, a transistor-based system is provided that minimizes losses, increases operating frequency, and consumes little power, while remaining simple, compact, and robust. Such a system is particularly well-suited for use as a loss-compensated resonator or as an oscillator with improved compatibility with external circuits, capable of driving both low-impedance and high-impedance external circuits, similar to oscillators of the prior art.

[0025] According to another aspect, a resonator is proposed, comprising a transistor system as defined above and a biasing circuit coupled to the input, output and control terminals of the first and second transistors of the transistor system, the transistor system being configured to present an impedance having a positive or zero real part so that the transistor system is configured to function as a resonator capable of modifying a current flowing between the first and second main terminals of the transistor system.

[0026] According to another aspect, an oscillator is proposed, comprising a transistor system as defined above and a biasing circuit coupled to the input, output and control terminals of the first and second transistors of the transistor system, the transistor system being configured to present an impedance having a negative real part so that the transistor system is configured to function as an oscillator capable of generating periodic signals on the first and second principal terminals of the transistor system.

[0027] BRIEF DESCRIPTION OF THE FIGURES

[0028] The aims, objects, features and advantages of the invention will be more apparent from the detailed description of an embodiment thereof, which is illustrated by the following accompanying drawings in which: Figures 1 to 20 represent different embodiments of a transistor system, hereinafter referred to as the active cell; and Figures 21 to 23 represent different embodiments of the active cell and a biasing circuit.

[0029] The drawings are given as examples and are not limiting to the invention. They constitute schematic representations of principle intended to facilitate understanding of the invention and are not necessarily to scale with practical applications.

[0030] DETAILED DESCRIPTION OF THE INVENTION

[0031] Before beginning a detailed review of the embodiments of the invention, optional features that may be used in combination or alternatively are stated below.

[0032] According to one example, the transistor system is configured so that, when the input terminals and output terminals receive respective biasing potentials supplied by the biasing circuit, the potential at the output terminal of the first transistor is strictly greater than the potential at the input terminal of the second transistor, and the potential at the output terminal of the second transistor is strictly greater than the potential at the input terminal of the second first transistor.

[0033] According to one example, the first and second transistors are of the field-effect type.

[0034] According to one embodiment of the transistor system, the first and second transistors are of the field-effect type or "FET" in English, the input terminal of each of the first and second transistors is called the source and the output terminal of each of the first and second transistors is called the drain.

[0035] According to one example, the first and second transistors are of the bipolar type.

[0036] According to one embodiment of the transistor system, the first and second transistors are of the bipolar type, the input terminal of each of the first and second transistors is called the emitter and the output terminal of each of the first and second transistors is called the collector.

[0037] According to one example, the transistor system includes first and second secondary terminals configured to be coupled to the biasing circuit, the inductive device includes first and second inductive components each having first and second terminals, the first inductive component having its first terminal coupled to the control terminal of the first transistor and its second terminal coupled to the first secondary terminal, and the second inductive component having its first terminal coupled to the control terminal of the second transistor and its second terminal coupled to the second secondary terminal.

[0038] In one example, each of the first and second inductive components is configured to have a variable inductance.

[0039] According to one example, the inductive device includes at least one inductive component coupled between the respective control terminals of the first and second transistors.

[0040] According to one example, said at least one inductive component is configured to have a variable inductance.

[0041] According to one example, the inductive device includes at least one piezoelectric component coupled between the respective control terminals of the first and second transistors.

[0042] According to one example, the inductive device includes at least one additional capacitive component coupled between the respective control terminals of the first and second transistors.

[0043] According to one example, said at least one additional capacitive component is configured to have a variable capacity.

[0044] According to one example, the system includes first and second reference terminals configured to receive a reference potential supplied by the biasing circuit, and wherein the inductive device includes a third capacitive component coupled between the control terminal of the first transistor and the first reference terminal, and a fourth capacitive component coupled between the control terminal of the second transistor and the second reference terminal.

[0045] In one example, each of the third and fourth capacitive components is configured to have a variable capacitance.

[0046] It is specified that, within the framework of the present invention, the expressions "A coupled to B," "A electrically coupled to B," "A connected to B," or "A electrically connected to B" are synonymous with "A is electrically connected to B" and do not necessarily mean that there is no component between A and B. Thus, these expressions refer to an electrical connection between two elements, this connection being either direct or indirect. This means that it is possible for a current to flow between a first device A and a second device B that are electrically connected, linked, or coupled, at A, at B, and along the path connecting A to B, this path being either or not including other electrical equipment. Device A can be electrically coupled to B, either in series or in parallel.

[0047] Conversely, in the context of the present invention, the term "electrically connected directly" or "directly connected" refers to a direct electrical connection between two elements. This means that between a first device A and a second device B that are electrically connected directly, no other equipment is present, other than an electrical connection or several electrical connections.

[0048] Figures 1 through 23 depict a transistor system, also known as an active cell. Active cell 1 is configured to function as either a resonator or an oscillator. Generally, when configured as a resonator, it modifies the received signal into a corresponding output signal with altered characteristics. For example, in signal processing, active cell 1 can be used to filter the received signal. Conversely, when configured as an oscillator, it generates periodic signals with a specific frequency, known as the oscillation frequency.

[0049] In general, the active cell 1 comprises first and second principal terminals N1, N2 and an inductive device 2. The inductive device 2 is configured to generate a magnetic field when a current flows through it. In particular, the inductive device 2 comprises at least one inductive component 3, L1, L2 configured to generate a magnetic field when a current flows through it.

[0050] More specifically, active cell 1 comprises first and second transistors T1, T2 and first and second capacitive components C1, C2. The first and second capacitive components C1, C2 are also referred to as main capacitive components C1, C2. Generally, a capacitive component C1, C2 can be a capacitor, for example, a discrete chemical, ceramic, tantalum, electrolytic, etc. capacitor. A capacitive component can also be an integrated capacitor of the MOM (Metal-Oxide-Metal), MIM (Metal-Insulator-Metal), or MOS (Metal-Oxide-Semiconductor) type.

[0051] In general, the first transistor T1 includes a first terminal cd1, called the control terminal, coupled to the inductive device 2. The first transistor T1 also includes a second terminal e1, called the input terminal, coupled to the first main terminal N1, and a third terminal s1, called the output terminal. The input terminal e1, output terminal s1, and control terminal cd1 of the first transistor T1 are configured to be coupled to a biasing circuit 10, as illustrated in Figures 21 to 23.

[0052] Furthermore, the second transistor T2 includes a first terminal cd2, called the control terminal, coupled to the inductive device 2. The second transistor T2 also includes a second terminal e2, called the input terminal, coupled to the second main terminal N2, and a third terminal s2, called the output terminal. The input terminal e2, the output terminal s2, and the control terminal cd2 of the second transistor T2 are configured to be coupled to the biasing circuit 10.

[0053] For example, the first and second transistors T1, T2 are of the field-effect type, denoted FET (Field-Effect Transistor), as illustrated in Figures 1 to 23. In this case, the input terminal e1, e2 of a FET is called the source; the output terminal s1, s2 of a FET is called the drain; and the control terminal cd1, cd2 of a FET is called the gate. Alternatively, the first and second transistors T1, T2 could be of the MOSFET type (Metal-Oxide-Semiconductor Field-Effect Transistor). Depletion mode MOSFETs (or "Depletion mode" in English) or inversion mode MOSFETs (or "Enhancement mode" in English) can be used.

[0054] Other transistors can be used. For example, JFETs (Junction Field-Effect Transistors); MESFETs (Metal-Semiconductor Field-Effect Transistors); DMOS transistors (Double-Diffused Metal-Oxide-Semiconductor); GaN FETs (Gallium Nitride Field-Effect Transistors); InP FETs (Indium Phosphide Field-Effect Transistors); and SiC FETs (Silicon Carbide Field-Effect Transistors). HEMT transistors (according to the English acronym for "High Electron Mobility Transistor", i.e., high electronic mobility transistor);HFET transistors (Heterostructure Field-Effect Transistor); MODFET transistors (Modulation-Doped Field-Effect Transistor); FinFET transistors (Fin Field-Effect Transistor); Dual-Gate FET transistors; OFET transistors (Organic Field-Effect Transistor); TFET transistors (Tunnel Field-Effect Transistor); or any type of component classified as a field-effect transistor.

[0055] Alternatively, the first and second transistors T1, T2 are of the bipolar type. In this case, the input terminal e1, e2 of a bipolar transistor is called the emitter; the output terminal s1, s2 of a bipolar transistor is called the collector; and the control terminal cd1, cd2 of a bipolar transistor is called the base.

[0056] For example, one can use BJT transistors (Bipolar Junction transistors); HBT transistors (Heterojunction Bipolar Transistors); or any type of component classified in the category of bipolar transistors.

[0057] According to another variant, hybrid transistors can be used, having a MOSFET-type input and a bipolar-type output. For example, IGBT transistors (Insulated-Gate Bipolar Transistor) can be used.

[0058] In addition, the first capacitive component C1 is coupled in series, preferably directly, between the input terminal e1 of the first transistor T1 and the output terminal s2 of the second transistor T2.

[0059] The second capacitive component C2 is coupled in series, and preferably directly, between the input terminal e2 of the second transistor T2 and the output terminal s1 of the first transistor T1.

[0060] In general, a cross connection is established between the output terminals s1, s2 and the input terminals e1, e2 of the first and second transistors T1, T2.

[0061] In general, the inductive device 2 is coupled to the respective control terminals cd1 and cd2 of the first and second transistors T1 and T2 of the active cell 1. The active cell 1 has an impedance whose real part is Rj n is adjustable via the characteristics of the first and second transistors T1, T2, which makes it active. In addition, the first and second transistors T1, T2 are powered by supply voltages V1, V2 applied respectively to the input terminals e1, e2 and output terminals s1, s2 of the first and second transistors T1, T2, by the biasing circuit 10.

[0062] Specifically, the biasing circuit 10 is designed to bias the first and second transistors, T1 and T2. It is also said that the biasing circuit 10 powers the transistors T1 and T2 of the active cell so that they operate. More precisely, the biasing circuit 10 is configured to bias transistors T1 and T2 so that they operate in active, or linear, mode.

[0063] Thus, when transistors T1, T2 operate in linear mode, transistors T1, T2 function as AC signal amplifiers.

[0064] In other words, the biasing circuit 10 is configured to provide bias potentials Vs1 and Vs2 respectively at the output terminals s1 and s2 of transistors T1 and T2, and to provide bias potentials Ve1 and Ve2 respectively at the input terminals e1 and e2 of transistors T1 and T2. Furthermore, the biasing circuit 10 is configured to provide bias potentials Vcd1 and Vcd2 respectively at the control terminals cd1 and cd2 of transistors T1 and T2. For example, the active cell 1 may include first and second secondary terminals O1 and O2 configured to be coupled to the biasing circuit 10. The secondary terminals O1 and O2 are configured to provide bias potentials Vcd1 and Vcd2 respectively at the control terminals cd1 and cd2 of transistors T1 and T2.For example, the secondary terminals 01, 02 can be coupled either directly to the respective control terminals cd1, cd2 of transistors T1, T2, as illustrated in Figures 7 to 20, or indirectly, as illustrated in Figures 1 to 6, and 21 to 23. It should also be noted that, for each transistor, the supply voltage V1, V2 is equal to the difference between the bias potential Vs1, Vs2 and the bias potential Ve1, Ve2. In general, it is also said that when the biasing circuit 10 supplies, or applies, a bias potential to the input terminals e1, e2, output terminals s1, s2 and control terminals cd1, cd2 of transistors T1, T2, transistors T1, T2 are biased. More specifically, the supply voltages V1, V2, the bias potentials Vs1, Vs2, Ve1, Ve2, Vcd1, Vcd2 are continuous values.

[0065] More specifically, active cell 1 is configured such that when the input terminals e1, e2; the output terminals s1, s2; and the control terminals cd1, cd2 receive the respective DC bias potentials Ve1, Ve2, Vs1, Vs2, and Vcd1, Vcd2 supplied by the biasing circuit 10, the potential Vs1 at the output terminal s1 of the first transistor T1 is strictly greater than the potential Ve2 at the input terminal e2 of the second transistor T2, and the potential Vs2 at the output terminal s2 of the second transistor T2 is strictly greater than the potential Ve1 at the input terminal e1 of the first transistor T1. For example, the DC bias potentials can be applied to the terminals of transistors T1 and T2 respectively via a generator.

[0066] In other words, the main capacitive components C1 and C2 bias the output terminals s1 and s2 of transistors T1 and T2 to a potential level higher than the potential level applied to the input terminals e1 and e2 of transistors T1 and T2. The main capacitive components C1 and C2 act as a short circuit for alternating current, meaning they allow the flow of alternating current or radio frequency signals. More specifically, the main capacitive components C1 and C2 act as a short circuit by electrically coupling, preferably directly, the input terminal e1 and e2 of one transistor T1 and T2 with the output terminal s2 and s1 of the other transistor T1 and T2. The main capacitive components C1 and C2 allow the unimpeded flow of radio frequency signals.In addition, the main capacitive components C1, C2 ensure that the transistors T1, T2 of system 1 function as amplifiers.

[0067] Thus, the active cell 1, equipped with the first and second transistors T1 and T2, is said to be active, and one of its main properties is to compensate for the losses of the inductive device 2. Indeed, the inductive device 2 allows the active cell 1 to function as a resonator or an oscillator. In both cases, the inductive device 2 induces losses that can be compensated by the active cell 1. To clarify the advantages of the invention, equations relating characteristic physical parameters of the components of the active cell 1, as defined according to a preferred embodiment illustrated in Figure 3, will be presented. According to the preferred embodiment, the inductive device 2 comprises first and second inductive components L1 and L2. Other embodiments of the inductive device 2 are envisaged and will be described later.According to the preferred embodiment, the inductive components L1 and L2 each have first and second terminals. The first inductive component L1 has its first terminal coupled to the control terminal cd1 of the first transistor T1 and its second terminal coupled to the first secondary terminal 01. The second inductive component L2 has its first terminal coupled to the control terminal cd2 of the second transistor T2 and its second terminal coupled to the second secondary terminal 02. Optionally, the active cell 1 includes first and second reference terminals R1 and R2 configured to receive a reference potential Vref supplied by the biasing circuit 10, as illustrated in Figures 3 to 5, 15, 20, and 23. In addition, the inductive device 2 may include additional third and fourth capacitive components 03 and 04.The third capacitive component 03 is coupled between the first reference terminal R1 and the first secondary terminal 01, and the fourth capacitive component 04 is coupled between the second reference terminal R2 and the second secondary terminal 02. Such additional capacitive components 03, 04 allow control of the operating frequency value of the active cell 1.

[0068] To simplify the following equations, the elements of active cell 1 will be chosen such that the inductive components L1 and L2 have the same inductance L, and the additional capacitive components O3 and O4 have the same capacitance G. Furthermore, transistors T1 and T2 with identical characteristics will be selected. More specifically, the first and second transistors T1 and T2 will be chosen to have the same transconductance, denoted g. mThe capacitance values ​​of the main capacitive components 01, 02 do not appear in the equation, because, as stated above, the main capacitive components 01, 02 function as a short circuit of alternating currents.

[0069] According to the embodiment illustrated in figure 3, the inductive device 2 has a complex impedance Z, which can be determined by the following equation 1: Z = j(a)L ) (equation 1).

[0070] The impedance Z of the inductive device 2 is said to be complex because it has an imaginary part, with j representing the imaginary unit. In equation 1, the impedance Z corresponds to the complex impedance of the inductive device 2 (whose unit is in Ohms), j is a complex number whose square is -1; œ corresponds to the angular frequency of the active cell 1 (whose unit is in radians per second); L corresponds to the inductance of the inductive components L1, L2 (whose unit is in Henrys); and C corresponds to the capacitance of the additional capacitive components C3, L4 (whose unit is in Farads). It is also noted that the angular frequency œ of the active cell 1 is a function of the operating frequency f of the active cell 1 such that œ = 2 * TT * f.

[0071] By applying Kirchhoff's circuit law, we can determine the complex admittance Yin, at a principal terminal N1, N2 of the active cell 1, according to the following equation 2: with :

[0072] - Yin: the complex admittance at the main terminal N1, N2 of active cell 1 (whose unit is in Ohms) -1 ) ;

[0073] - lo: the current flowing at the main terminal N1, N2 of the active cell 1 (expressed in Amperes);

[0074] - Vo: the bias potential at the main terminal N1, N2 of the active cell 1 (expressed in Volts);

[0075] - Cgd: the intrinsic capacitance between the control terminal cd1, cd2 and the output terminal s1, s2 of a transistor T1, T2 (whose unit is in Farad);

[0076] - Cg S : the intrinsic capacitance between the control terminal cd1, cd2 and the input terminal e1, e2 of a transistor T1, T2 (whose unit is in Farads); and

[0077] - g m : corresponds to the transconductance of a transistor T1, T2 (whose unit is in Ohms) -1 ).

[0078] A specific Gin term can be expressed by the following equation 3:

[0079] Gin (whose unit is in Ohms) -1 ) corresponds to the conductance value of the complex admittance Yj n .

[0080] Thus, we can deduce from equation 3 that the value of the conductance Gin is that of the complex admittance Yi n can be positive or negative.

[0081] Furthermore, it is noted that active cell 1 provides a resistance Ri n , called the input, between its principal terminals N1, N2, which can be expressed by the following equation 4: R in = Re{l / Y in (equation 4).

[0082] That is to say, the input resistance Rj n is equal to the real part of 1 / Yj n that is to say, Rjn is equal to the real part of the complex impedance Zj n = 1 / Yj n at the main terminal N1, N2 of active cell 1 (whose unit is in Ohm).

[0083] In other words, the input resistance Rj n of active cell 1 corresponds to the real part of the complex impedance Zj n at the level of the main terminal N1, N2 of the active cell 1.

[0084] Thus, active cell 1 is configured to provide an input resistance Rj n between its principal bounds N1, N2 which can be either positive or zero, or negative.

[0085] We can also note the following equation 5: (equation ô).

[0086] The frequency fo corresponds to the operating frequency of interest of active cell 1 (whose unit is in Hertz). The operating frequency of interest fo can be either the resonance frequency, when the active cell 1 functions as a resonator, or the oscillation frequency, when the active cell 1 functions as an oscillator.

[0087] It is also noted that the operating pulse of interest co o of active cell 1 is a function of the operating frequency of interest fo of active cell 1 such that CÜO = 2 * TT * fo.

[0088] It can be noted that the operating frequency of interest fo is defined by equation 5 when the imaginary part of the complex admittance Yj n is zero. Thus, according to equation 2 and equation 5, we can note that for a first range of frequencies, the input resistance Rj n is negative, and for a second frequency range, the input resistance Rj n is positive or zero. The upper limit of the first frequency range is less than or equal to the lower limit of the second frequency range. The frequency ranges depend on the value of the inductance L, the characteristics of the first and second transistors T1, T2, and the value of the capacitance C.

[0089] According to equation 5, we can note that the operating frequency of interest, fo, is a function of the characteristics of transistors T1 and T2 of active cell 1, and in particular of the intrinsic capacitances C gs , C g d of said transistors T1, T2.

[0090] Furthermore, at the operating frequency of interest fo, the input resistance Rj can be expressed. n by the following equation 6: (equation 6).

[0091] According to equation 6, it can be noted that, according to the invention, the active cell 1 has, at the operating frequency of interest f0, an input resistance Rj n having a term that is a function of intrinsic capacities C gs , C g d transistors T1, T2, allowing the active cell 1 to be increased to compensate for higher dissipative loads. In other words, the active cell 1 has an input resistance Rj nwhich can have different values ​​depending on the characteristics of the first and second transistors T1, T2, and in particular depending on the intrinsic capacitances C gs , C g d, transistors T1, T2. Because transistors T1, T2 of the system are active, the active cell 1 according to the invention is called an active system. In particular, when the system operates as an oscillator, a differential active oscillator 1 is provided because it has two main terminals N1, N2 to generate two periodic signals. Furthermore, oscillator 1 is configured to generate signals in opposite phase. Generally, transistors T1, T2 compensate for the losses of the inductive device 2, and the active cell 1 is called a self-compensating system. The active cell 1 is also said to operate as a self-contained system.

[0092] Thus, when the input resistance Rj nis positive or zero, at the operating frequency of interest f0, the active cell 1 is configured to function as a resonator. A resonator is a device classified as a receiver (like a resistor, etc.). That is to say, a resonator dissipates energy. It is also noted that the intrinsic capacitances C gs Cgd can be chosen so that Rj n is positive and strictly less than (2 / g m In this case, the active cell 1 compensates for the losses due to the inductive device in a better way compared to a conventional system which has an equivalent internal resistance equal to (2 / g) m Thus, according to the invention, the proposed resonator is said to be low-loss, because it has an input resistance Rj n weaker than a conventional resonator and therefore minimizes losses.

[0093] Furthermore, when active cell 1 is configured to operate as a resonator, it can be connected in series or parallel with an alternating signal generator, which is not shown for simplicity. Specifically, when active cell 1 is connected in series, it receives signals at one of its main terminals, N1, N2 (the input terminal), and outputs signals with modified characteristics at the other main terminal, N2, N1 (the output terminal).

[0094] Furthermore, when active cell 1 is coupled in parallel, active cell 1 receives signals at both main terminals N1 and N2, and active cell 1 emits signals with modified aspects from these two main terminals N1 and N2.

[0095] In general, when active cell 1 is configured to operate as a resonator, active cell 1 is capable of modifying a current flowing between the first and second main terminals N1, N2 of active cell 1.

[0096] Furthermore, when the input resistance Rj nIf the current is negative, at the operating frequency of interest f0, the active cell 1 is configured to function as an oscillator. An oscillator is a device classified as a generator. That is to say, an oscillator provides energy. In addition, an oscillator generates periodic signals at its terminals, called output terminals. In particular, when the active cell 1 functions as an oscillator, it is configured to deliver two periodic signals to the main terminals N1 and N2, respectively. Advantageously, the oscillator according to the invention can compensate for the losses of an external circuit having a lower impedance (typically less than one hundred ohms) than a conventional oscillator can compensate for. Furthermore, the oscillator according to the invention allows an external circuit to be directly coupled to the input terminals N1 and N2 of system 1, without necessarily having to use additional buffers.Furthermore, if buffers coupled to the main terminals N1, N2 of the active cell 1 were used, the energy required to start the oscillations would be very low (for example, an energy reduction of up to 50%), and could provide a very low energy consumption system.

[0097] There are different embodiments of the active cell 1. Generally, when the inductive device 2 comprises two inductive components L1, L2 directly coupled in series, as illustrated in Figures 7, 9, 10, and 20, the two inductive components L1, L2 can be replaced by a single inductive component L1. Similarly, when the inductive device 2 comprises two additional capacitive components C3, C4 directly coupled in series, as illustrated in Figures 6, 8, and 10, the two additional capacitive components C3, C4 can be replaced by a single additional capacitive component C3.

[0098] For example, the additional capacitive components C3, C4 can have a constant capacitance, as illustrated in Figures 3, 5, 6, 8 to 13, 20 and 23, so that the signals emitted by the active cell 1 have a constant frequency depending on the capacitance of the third and fourth capacitive components C3, C4.

[0099] Alternatively, each of the additional capacitive components C3, C4 can have a variable capacitance, as illustrated in Figures 4, 15, and 17, so that the signals emitted by the active cell 1 have a frequency that varies depending on the capacitance of the third and fourth capacitive components C3, C4. A capacitive component with a variable capacitance is defined as a capacitance component whose capacitance can be configured to have different values. In other words, each additional capacitive component C3, C4 can be configured to have a variable capacitance. For example, the additional capacitive components C3, C4 could be variable capacitance diodes (also called varactors or varactor diodes).

[0100] By analogy, the inductive components L1 and L2 can have a constant inductance, and the signals emitted by active cell 1 then have a constant frequency. Alternatively, the inductive components L1 and L2 can have a variable inductance, that is, an inductance configured to have different values. In this case, the signals emitted by active cell 1 then have a variable frequency, that is, a frequency configured to have different values.

[0101] Advantageously, when the active cell 1 functions as an oscillator, the system can be configured so that the two output signals have the same determined frequency, whether constant or variable. For example, when the inductive device 2 includes first and second inductive components L1 and L2, these components have inductances of the same value. Furthermore, when the inductive device 2 includes additional capacitive components C3 and C4, these components have capacitances of the same value.

[0102] According to embodiments illustrated in Figures 1 to 6, the inductive device 2 comprises first and second inductive components L1 and L2, each having first and second terminals. The first inductive component L1 has its first terminal connected to the control terminal cd1 of the first transistor T1 and its second terminal connected to the first secondary terminal 01 of the active cell 1. Furthermore, the second inductive component L2 has its first terminal connected to the control terminal cd2 of the second transistor T2 and its second terminal connected to the second secondary terminal 02 of the active cell 1.

[0103] According to the embodiment illustrated in Figure 2, the first and second inductive components L1, L2 each have a variable inductance so that the signals emitted by the active cell 1 have a variable frequency depending on the inductance of the first and second inductive components L1, L2.

[0104] Advantageously, as illustrated in Figures 3 to 5, the active cell 1 includes the first and second reference terminals R1, R2 configured to receive the reference potential Vref supplied by the biasing circuit 10. In addition, the inductive device 2 includes a third additional capacitive component C3 coupled between the control terminal cd1 of the first transistor T1 and the first reference terminal Ride of the active cell 1, and a fourth additional capacitive component C4 coupled between the control terminal cd2 of the second transistor T2 and the second reference terminal R2 of the active cell 1.

[0105] According to the embodiments illustrated in Figures 3 and 4, the additional capacitive components C3, C4 are coupled, preferably directly, in series with respectively the first and second inductive components L1, L2, between respectively the control terminal cd1, cd2, of a transistor T1, T2 and the first and second reference terminals R1, R2

[0106] According to the embodiment illustrated in Figure 5, the additional capacitive components C3, C4 are coupled, preferably directly, in parallel with respectively the first and second inductive components L1, L2. For example, the additional capacitive components 03, 04 are coupled directly to the respective control terminals cd1, cd2 of the transistors T1, T2.

[0107] According to the embodiment illustrated in Figure 6, the inductive device 2 includes at least one additional capacitive component 03, 04 coupled between the respective control terminals cd1, cd2 of the first and second transistors T1, T2.

[0108] According to other embodiments, illustrated in Figures 7 to 13, the inductive device 2 comprises at least one inductive component L1, L2 coupled between the respective control terminals cd1, cd2 of the first and second transistors T1, T2. Furthermore, the first and second secondary terminals 01, 02 are coupled, preferably directly, respectively to the control terminals cd1, cd2 of transistors T1, T2.

[0109] Advantageously, according to the embodiments illustrated in figures 8 to 13, the inductive device 2 includes at least one additional capacitive component 03, 04 coupled between the respective control terminals cd1, cd2 of the first and second transistors T1, T2.

[0110] For example, according to the embodiment illustrated in Figure 8, the inductive device 2 comprises two inductive components L1, L2 coupled respectively to the control terminals cd1, cd2 of the first and second transistors T1, T2, and two additional capacitive components 03, 04 coupled in series between the two inductive components L1, L2.

[0111] According to the embodiment illustrated in Figure 9, the inductive device 2 comprises two additional capacitive components 03, 04 coupled respectively to the control terminals cd1, cd2 of the first and second transistors T1, T2, and two inductive components L1, L2 coupled in series between the two additional capacitive components 03, 04.

[0112] According to the embodiment illustrated in Figure 10, the inductive device 2 comprises two additional capacitive components C3, C4 coupled in parallel with the control terminals cd1, cd2 respectively of the first and second transistors T1, T2, and two inductive components L1, L2 coupled in parallel with the control terminals cd1, cd2 respectively of the first and second transistors T1, T2.

[0113] According to the embodiment illustrated in Figure 11, the inductive device 2 comprises a first group G1 including a first additional capacitive component C3 coupled in parallel with a first inductive component L1, and a second group G2 including a second additional capacitive component O4 coupled in parallel with a second inductive component L2. The first group G1 and the second group G2 are connected in series between the respective control terminals cd1, cd2 of the first and second transistors T1, T2.

[0114] According to the embodiment illustrated in Figure 12, the inductive device 2 comprises a first group G1 including a first additional capacitive component 03 coupled in parallel with a first inductive component L1. The first group G1 and a second inductive component L2 are coupled in series between the respective control terminals cd1, cd2 of the first and second transistors T1, T2.

[0115] According to the embodiment illustrated in Figure 13, the inductive device 2 comprises a first group G1 including a first additional capacitive component 03 coupled in parallel with a first inductive component L1. The first group G1 and a second additional capacitive component 04 are coupled in series between the respective control terminals cd1, cd2 of the first and second transistors T1, T2.

[0116] According to other embodiments, illustrated in Figures 14 to 19, the inductive device 2 comprises at least one piezoelectric component 3 coupled between the respective control terminals cd1, cd2 of the first and second transistors T1, T2. Furthermore, the first and second secondary terminals 01, 02 are coupled, preferably directly, respectively to the control terminals cd1, cd2 of transistors T1, T2.

[0117] Advantageously, according to the embodiment illustrated in Figure 15, the inductive device 2 includes a third additional capacitive component 03 coupled between the control terminal cd1 of the first transistor T1 and the first reference terminal R1, and a fourth additional capacitive component 04 coupled between the control terminal cd2 of the second transistor T2 and the second reference terminal R2.

[0118] According to the embodiments illustrated in figures 16 to 19, the inductive device 2 comprises at least one inductive component L1, L2 coupled between the respective control terminals cd1, cd2 of the first and second transistors T1, T2.

[0119] For example, according to the embodiment illustrated in Figure 16, the inductive device 2 comprises two inductive components L1, L2 coupled respectively to the control terminals cd1, cd2 of the first and second transistors T1, T2, and a piezoelectric component 3 coupled in series between the two inductive components L1, L2.

[0120] According to the embodiment illustrated in Figure 17, the inductive device 2 comprises two inductive components L1, L2 coupled respectively to the control terminals cd1, cd2 of the first and second transistors T1, T2, two additional capacitive components C3, C4 coupled respectively in series with the first inductive component L1 and a piezoelectric component 3, and with the second inductive component L2 and the piezoelectric component 3.

[0121] According to the embodiment illustrated in Figure 18, the inductive device 2 comprises an additional capacitive component C3, preferably with variable capacitance, coupled in parallel with the control terminals cd1, cd2 respectively of the first and second transistors T1, T2, an inductive component L1 coupled in parallel with the control terminals cd1, cd2 respectively of the first and second transistors T1, T2, and a piezoelectric component 3 coupled in parallel with the control terminals cd1, cd2 respectively of the first and second transistors T1, T2.

[0122] According to the embodiment illustrated in Figure 19, the inductive device 2 comprises a group G1 including an additional capacitive component C3, preferably with variable capacitance, coupled in series with a piezoelectric component 3. The group G1 and an inductive component L1 are coupled in parallel between the control terminals cd1, cd2 respectively of the first and second transistors T1, T2.

[0123] According to another embodiment, illustrated in Figure 20, the inductive device 2 comprises at least one inductive component L1, L2 coupled between the respective control terminals cd1, cd2 of the first and second transistors T1, T2. Furthermore, the first and second secondary terminals O1, O2 are coupled, preferably directly, respectively to the control terminals cd1, cd2 of transistors T1, T2. In addition, the active cell 1 comprises the first and second reference terminals R1, R2 configured to receive the reference potential Vref supplied by the biasing circuit 10.

[0124] Furthermore, the inductive device 2 includes a third capacitive component 03 coupled between the control terminal cd1 of the first transistor T1 and the first reference terminal R1, and a fourth capacitive component 04 coupled between the control terminal cd2 of the second transistor T2 and the second reference terminal R2. Figures 21 to 23 show a biasing circuit 10. In general, the biasing circuit 10 is coupled to the input terminals e1, e2, output terminals s1, s2, and control terminals cd1, cd2 of each of the first and second transistors T1 and T2. In general, the biasing circuit 10 is configured to apply, for each transistor among the first and second transistors T1, T2, the supply voltage V1, V2 between the output terminal s1, s2 and the input terminal e1, e2 of transistor T1, T2 and a current on the output terminal s1, s2 of transistor T1, T2.In addition, the biasing circuit 10 can be configured to supply the biasing potentials Vcd1, Vcd2 on the respective control terminals cd1, cd2 of transistors T1, T2, via the first and second secondary terminals 01, 02.

[0125] There are different ways of implementing the biasing circuit 10.

[0126] Figure 21 shows a biasing circuit 10 comprising a first voltage source 11 coupled to the output terminals s1, s2 of transistors T1, T2, for example via dissipative components 12. The dissipative components 12 may be resistors or inductors. Furthermore, the biasing circuit 10 includes a second voltage source 13 coupled to the input terminals e1, e2 of transistors T1, T2, for example via additional dissipative components 14. The additional dissipative components 14 may be resistors or inductors. The biasing circuit 10 also includes a third voltage source 15 coupled to the first and second inductive components L1, L2, via the first and second secondary terminals 01, 02.For example, the third voltage source 15 can supply the bias potentials Vcd1, Vcd2 on the respective control terminals cd1, cd2 of transistors T1, T2, via the first and second secondary terminals 01, 02.

[0127] Figure 22 shows a biasing circuit 10 comprising a first current source 16 coupled to the output terminals s1, s2 of transistors T1, T2, for example via dissipative components 12. Furthermore, the biasing circuit 10 includes a current-consuming element 17 coupled to the input terminals e1, e2 of transistors T1, T2, for example via additional dissipative components 14. The biasing circuit 10 also includes the third voltage source 15 coupled to the inductive components L1, L2, via the first and second secondary terminals 01, 02.

[0128] In general, the active cell 1 is particularly suitable for being coupled to an external circuit 20 having a low impedance, that is to say typically an impedance of less than one hundred Ohms, for example about 50 Ohms, which corresponds to most of the circuits used in the field of telecommunications, such as transmitter and / or transmitter circuits, and for radio frequency applications.

[0129] The biasing circuit 10 is configured to allow DC currents and signals to pass while blocking AC currents and signals.

[0130] Figure 23 shows a preferred embodiment of an active cell 1 coupled to a biasing circuit 10 and an external circuit 20. According to this preferred embodiment, the external circuit 20 is electrically coupled to the input terminals e1, e2 of transistors T1, T2, via the main terminals N1, N2 of the active cell 1. Thus, the external circuit 20 can be electrically coupled to the output terminals s1, s2 of transistors T1, T2. This is possible because nodes N1, e1, and s2 are electrically coupled to each other. Similarly, nodes N2, e2, and s1 are electrically coupled to each other.

[0131] Furthermore, the third voltage source 15 can supply the bias potentials Vcd1, Vcd2 on the respective control terminals cd1, cd2 of transistors T1, T2, via the first and second secondary terminals 01, 02.

[0132] Advantageously, when the additional capacitive components C3 and C4 each have a constant capacitance, system 1 can output signals at a predetermined frequency, and a fixed-frequency oscillator can be provided. Conversely, when the additional capacitive components C3 and C4 each have a variable capacitance, the active cell 1 can output signals at an adjustable frequency, and a VCO-type oscillator can be provided. The frequency of the output signals is determined by equation 5. More specifically, the active cell 1 has an operating frequency of interest f0 when the inductive device 2 resonates or oscillates in conjunction with the intrinsic capacitances of transistors T1 and T2.

Claims

DEMANDS 1. Transistor system, comprising: • the first and second main boundary markers (N1, N2); and • an inductive device (2), characterized in that the system further comprises: • a first transistor (T1) comprising a first terminal (cd1), called the control terminal, coupled to the inductive device (2), a second terminal (e1), called the input terminal, coupled to the first main terminal (N1), and a third terminal (s1), called the output terminal, the control, input and output terminals (cd1, e1, s1) of the first transistor (T1) being configured to be coupled to a biasing circuit (10); • a second transistor (T2) comprising a first terminal (cd2), called the control terminal, coupled to the inductive device (2), a second terminal (e2), called the input terminal, coupled to the second main terminal (N2), and a third terminal (s2), called the output terminal, the control, input and output terminals (cd2, e2, s2) of the second transistor (T2) being configured to be coupled to the biasing circuit (10); • a first capacitive component (C1) connected in series between the input terminal (e1) of the first transistor (T1) and the output terminal (s2) of the second transistor (T2); and • a second capacitive component (C2) coupled in series between the input terminal (e2) of the second transistor (T2) and the output terminal (s1) of the first transistor (T1).

2. System according to the preceding claim, configured such that, when the input terminals (e1, e2) and the output terminals (s1, s2) receive respective biasing potentials supplied by the biasing circuit (10), the potential (Vs1) at the output terminal (s1) of the first transistor (T1) is strictly greater than the potential (Ve2) at the input terminal (e2) of the second transistor (T2), and the potential (Vs2) at the output terminal (s2) of the second transistor (T2) is strictly greater than the potential (Ve1) at the input terminal (e1) of the second first transistor (T1).

3. A system according to any one of the preceding claims, wherein the first and second transistors (T1, T2) are of the field-effect type, the input terminal (e1, e2) of each of the first and second transistors (T1, T2) being called the source and the output terminal (s1, s2) of each of the first and second transistors (T1, T2) being called the drain.

4. System according to any one of claims 1 to 2, wherein the first and second transistors (T1, T2) are of the bipolar type, the input terminal (e1, e2) of each of the first and second transistors (T1, T2) being called collector and the output terminal (s1, s2) of each of the first and second transistors (T1, T2) being called emitter.

5. System according to any one of the preceding claims, comprising first and second secondary terminals (01, 02) configured to be coupled to the biasing circuit (10), the inductive device (2) comprising first and second inductive components (L1, L2) each having first and second terminals, the first inductive component (L1) having its first terminal coupled to the control terminal (cd1) of the first transistor (T1) and its second terminal coupled to the first secondary terminal (01), and the second inductive component (L2) having its first terminal coupled to the control terminal (cd2) of the second transistor (T2) and its second terminal coupled to the second secondary terminal (02).

6. System according to the preceding claim, wherein each of the first and second inductive components (L1, L2) is configured to have a variable inductance.

7. System according to any one of claims 1 to 4, wherein the inductive device (2) comprises at least one inductive component (L1, L2) coupled between the respective control terminals (cd1, cd2) of the first and second transistors (T1, T2).

8. System according to the preceding claim, wherein said at least one inductive component (L1, L2) is configured to have a variable inductance.

9. System according to any one of claims 1 to 8, wherein the inductive device (2) comprises at least one piezoelectric component (3) coupled between the respective control terminals (cd1, cd2) of the first and second transistors (T1, T2).

10. System according to any one of the preceding claims, wherein the inductive device (2) comprises at least one additional capacitive component (C3, C4) coupled between the respective control terminals (cd1, cd2) of the first and second transistors (T1, T2).

11. System according to the preceding claim, wherein said at least one additional capacitive component (C3, C4) is configured to have a variable capacitance.

12. System according to any one of claims 1 to 9, comprising first and second reference terminals (R1, R2) configured to receive a reference potential (Vref) supplied by the biasing circuit (10), and wherein the inductive device (2) comprises a third capacitive component (C3) coupled between the control terminal (cd1) of the first transistor (T1) and the first reference terminal (R1), and a fourth capacitive component (C4) coupled between the control terminal (cd2) of the second transistor (T2) and the second reference terminal (R2).

13. System according to the preceding claim, wherein each of the third and fourth capacitive components (C3, C4) is configured to have a variable capacitance.

14. Resonator, comprising a transistor system according to any one of the preceding claims and a biasing circuit (10) coupled to the control (cd1, cd2), input (e1, e2) and output (s1, s2) terminals of the first and second transistors (T1, T2) of the transistor system, the transistor system being configured to present an impedance having a real part (Rj n ) positive or zero so that the transistor system is configured to function as a resonator capable of modifying a current flowing between the first and second main terminals (N1, N2) of the transistor system.

15. Oscillator, comprising a transistor system according to any one of claims 1 to 13, and a biasing circuit (10) coupled to the control terminals (cd1, cd2), input terminals (e1, e2) and output terminals (s1, s2) of the first and second transistors (T1, T2) of the transistor system, the transistor system being configured to present an impedance having a real part (Rj n ) negative so that the transistor system is configured to operate as an oscillator capable of generating periodic signals on the first and second principal terminals (N1, N2) of the transistor system.

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