Automotive multiprocessor apparatus and control method thereof

Abstract

The present invention relates to an automotive multiprocessor apparatus comprising a first processor, which is a main processor (Main_uC), a second processor, which is an auxiliary processor (Co_uC) connected to the first processor via a communication (Comm) channel and a GPIO channel using two GPIO (GPIO_M2C, GPIO_C2M) terminals, a power supply device for supplying power to the first processor, and a plurality of switches (Switch1, Switch2) connected in parallel to control the power supplied from the power supply device to the first processor, characterized in that the plurality of switches (Switch1, Switch2) are controlled respectively through switch control signals from the first and second processors, wherein if the switch control signals are all an off-state, the power applied to the first processor is cut off, and if any one of the switch control signals maintains an on-state, the power is continuously supplied to the first processor, and the first and second processors check whether conditions of a signal transmitted using the GPIO channel are satisfied in order to prevent an error signal from being transmitted via the communication (Comm) channel.

Description

[0001] Description

[0002] AUTOMOTIVE MULTIPROCESSOR APPARATUS AND CONTROL METHOD THEREOF

[0003] Technical Field

[0004] The present invention relates to an automotive multiprocessor apparatus and a control method thereof, which diagnose a communication connection status between automotive multiprocessors and ensure that a sleep operation and a wake-up operation are stably performed according to the communication connection status therebetween.

[0005] Background Art of the Invention

[0006] In recent years, there has been an increasing number of automotive systems with multiprocessors (e.g., a main processor, and an auxiliary processor) to improve the stability of the system.

[0007] Typically, communication between connected multiprocessor systems may be blocked due to various reasons, and malfunctions may occur due to communication errors.

[0008] Accordingly, there is a need for a method for detecting whether a communication connection (channel) is blocked, and ensuring that a multiprocessor system can stably operate (i.e. , the system can maintain consistent operation) even when the communication connection (channel) is blocked.

[0009] The background technology of the present invention is disclosed in Korean Patent Registration No. 10-1978323 (2019.05.08).

[0010] Disclosure of the Invention

[0011] Problems to be Solved

[0012] According to an aspect of the present invention, the present invention has been devised to solve the above-described problem, and provides an automotive multiprocessor apparatus and a control method thereof, which diagnose a communication connection status between automotive multiprocessors, and ensure that a sleep operation and a wake-up operation are stably performed according to the communication connection status therebetween.

[0013] Solution to the Problems

[0014] An automotive multiprocessor apparatus according to an aspect of the present invention is characterized by comprising a first processor, which is a main processor (Main_uC), a second processor, which is an auxiliary processor (Co_uC) connected to the first processor via a communication (Comm) channel and a GPIO channel using two GPIO (GPI0_M2C, GPI0_C2M) terminals, a power supply device for supplying power to the first processor, and a plurality of switches (Switchl , Switch2) connected in parallel to control the power supplied from the power supply device to the first processor, wherein the plurality of switches (Switchl , Switch2) are controlled respectively through switch control signals from the first and second processors, wherein if the switch control signals are all an off-state, the power applied to the first processor is cut off, and if any one of the switch control signals maintains an on-state, the power is continuously supplied to the first processor, and the first and second processors check conditions of a signal transmitted using the GPIO channel in order to prevent an error signal from being transmitted via the communication (Comm) channel.

[0015] A method for controlling an automotive multiprocessor apparatus according to another aspect of the present invention is characterized in that in the method for controlling an automotive multiprocessor apparatus, the automotive multiprocessor apparatus comprises a first processor, which is a main processor (Main_uC), a second processor, which is an auxiliary processor (Co_uC) connected to the first processor via a communication (Comm) channel and a GPIO channel using two GPIO (GPI0_M2C, GPI0_C2M) terminals, a power supply device for supplying power to the first processor, and a plurality of switches (Switchl , Switch2) connected in parallel to control the power supplied from the power supply device to the first processor, wherein the first and second processors respectively control the plurality of switches (Switchl , Switch2) through respective switch control signals, wherein the power applied to the first processor is cut off by allowing the switch control signals to all be an off-state, and the power is continuously supplied to the first processor by allowing any one of the switch control signals to maintain an on-state, and the first and second processors check whether conditions of a signal transmitted using the GPIO channel are satisfied in order to prevent an error signal from being transmitted via the communication (Comm) channel.

[0016] Effects of the Invention

[0017] According to an aspect of the present invention, the present invention diagnoses a communication connection status between automotive multiprocessors, and ensures that a sleep operation and a wake-up operation are stably performed.

[0018] Brief Description of the Drawings

[0019] FIG. 1 is an exemplary diagram showing a schematic configuration of an automotive multiprocessor apparatus according to an embodiment of the present invention.

[0020] FIG. 2 is an exemplary diagram showing that in FIG. 1 , three communication (Comm, GPIO*2) channels between a first processor and a second processor are in a normal state.

[0021] FIG. 3 is an exemplary diagram showing that in FIG. 1 , at least one of the three communication (Comm, GPIO*2) channels between the first processor and the second processor is blocked.

[0022] FIGS. 4a and 4b are exemplary diagrams for describing a general purpose input / output (GPIO) operation of an automotive multiprocessor apparatus according to Embodiment 1 of the present invention.

[0023] FIGS. 5a and 5b are exemplary diagrams for describing a GPIO operation of an automotive multiprocessor apparatus according to Embodiment 2 of the present invention.

[0024] FIG. 6 is an exemplary diagram for describing an operation of diagnosing a GPIO terminal of an automotive multiprocessor apparatus according to Embodiment 3 of the present invention.

[0025] FIGS. 7a and 7b are exemplary diagrams for describing an operation of diagnosing a GPIO terminal in a state in which a communication (Comm) channel of an automotive multiprocessor apparatus according to Embodiment 4 of the present invention is blocked.

[0026] FIGS. 8a and 8b are exemplary diagrams for describing an operation of diagnosing that a communication (Comm) channel of an automotive multiprocessor apparatus according to Embodiment 5 of the present invention is blocked and a first GPIO terminal (GPI0_M2C) is in a short-circuited state (i.e. , battery short circuit, ground short circuit).

[0027] FIGS. 9a and 9b are exemplary diagrams for describing an operation of diagnosing that a communication (Comm) channel of an automotive multiprocessor apparatus according to Embodiment 6 of the present invention is blocked and a second GPIO terminal (GPI0_C2M) is in a short-circuited state (i.e., battery short circuit, ground short circuit).

[0028] FIGS. 10a and 10b are exemplary diagrams for describing an operation of switching to a sleep mode when it is diagnosed that a communication (Comm) channel of an automotive multiprocessor apparatus according to Embodiment 7 of the present invention is in a normal state and a first GPIO terminal (GPIO_M2C) is in a short-circuited state (i.e., battery short circuit, ground short circuit).

[0029] FIGS. 11 a and 11 b are exemplary diagrams for describing an operation of switching to a sleep mode when it is diagnosed that a communication (Comm) channel of an automotive multiprocessor apparatus according to Embodiment 8 of the present invention is in a normal state and a second GPIO terminal (GPIO_C2M) is in a short-circuited state (i.e., battery short circuit, ground short circuit).

[0030] FIGS. 12a and 12b are exemplary diagrams for describing a mutual operation of first and second processors 100 and 200 when an error of a communication (Comm) channel of an automotive multiprocessor apparatus according to Embodiment 9 of the present invention is detected.

[0031] FIGS. 13a and 13b are exemplary diagrams for describing a mutual operation of first and second processors 100 and 200 when an error of a communication (Comm) channel of an automotive multiprocessor apparatus according to Embodiment 10 of the present invention and an error of a first GPIO terminal (GPIO_M2C) are detected.

[0032] FIGS. 14a and 14b are exemplary diagrams for describing an operation of monitoring the state of a second processor 200 by a first processor 100 of an automotive multiprocessor apparatus according to Embodiment 11 of the present invention.

[0033] Specific Details for Carrying Out the Invention Hereinafter, with reference to the accompanying drawings, an embodiment of an automotive multiprocessor apparatus and a control method thereof according to the present invention will be described with reference to the accompanying drawings.

[0034] In this process, the thickness of lines and the size of components illustrated in the drawings may be exaggerated for clarity and convenience of description. In addition, the following terms are defined in relation to their functions in the present invention, and may vary depending on the intention of a user or an operator, or on customary practice. Therefore, the definitions of these terms should be made based on the contents throughout this specification.

[0035] Hereinafter, the embodiment of the present invention will be described in detail with reference to the accompanying drawings so that a person having ordinary skill in the art to which the present invention pertains can easily implement the present invention. The present invention may be implemented in various different forms and is not limited to the embodiment described herein. Additionally, in order to clearly describe the present invention, parts irrelevant to the description have been omitted, and similar reference numerals have been assigned to similar parts throughout the specification.

[0036] Throughout the specification, when it is stated that a certain part “includes” a certain component, it means that, unless otherwise specified, the certain part may further include other components, rather than excluding other components.

[0037] It will be understood that terms or words used in the present specification and claims shall not be construed as being limited to having meanings defined in commonly used dictionaries, but should be interpreted as having meanings and concepts consistent with the technical idea of the present invention based on the principle that an inventor may appropriately define concepts of the terms to best explain the invention.

[0038] Therefore, the embodiment described in the present specification and configurations illustrated in the drawings are merely some of the most preferred embodiments of the present invention, and are not intended to limit the technical idea of the present invention. Therefore, it should be understood that there may be various equivalents and modifications that may substitute the embodiments at the time of the present application. In addition, when used herein, the terms "comprise," and "include" and / or "comprising," and “including" specify the presence of the stated shapes, numbers, steps, operations, members, elements and / or groups thereof, and do not preclude the presence or addition of one or more other shapes,, numbers, steps, operations, members, elements and / or groups thereof. In addition, when describing embodiments of the present invention, “can may include “one or more embodiments of the present invention.”

[0039] In addition, in order to facilitate the understanding of the present invention, the accompanying drawings may not be illustrated to scale, but rather, the dimensions of some elements may be exaggerated. In addition, the same reference numbers may be assigned to the same elements in different embodiments.

[0040] The mention that two comparison subjects are ‘identical’ means ‘substantially identical.’ Therefore, being substantially identical may include a case having a deviation which is considered low in the art, for example, a deviation of 5% or less. In addition, the fact that a certain parameter is uniform in a predetermined area may mean that the parameter is uniform from an average perspective.

[0041] Although the terms first, second, and the like are used herein to describe various elements, it should be understood that these elements are not limited by these terms. These terms are only used to distinguish one element from another, and unless otherwise stated, the first element may also be the second element.

[0042] Throughout the specification, unless otherwise specified, each element may be singular or plural.

[0043] When an arbitrary configuration is disposed on an “upper portion (or lower portion)” of an element or “on (or below)” the element, it may mean not only that the configuration is disposed in contact with an upper surface (or lower surface) of the element, but also that another configuration may be interposed between the element and the configuration disposed on (or below) the element.

[0044] In addition, when it is described that a certain element is “connected,” “coupled,” or “linked” to another element, it should be understood that the elements may be directly connected or linked to each other, but that other elements may also be “interposed” between each of the elements, or that each of the elements may be “connected,” “coupled,” or “linked” through the other elements. In addition, when a certain part is referred to as being electrically coupled to another part, it includes not only a case in which the parts are directly coupled to each other, but also a case in which the parts are coupled to each other with another device interposed therebetween.

[0045] Throughout the specification, when it is referred to as “A and / or B,” it means A, B, or A and B unless otherwise specified. That is, “and / or” includes all combinations or any combination of a plurality of items listed. When it is referred to as “C to D,” it means that it is greater than or equal to C and less than or equal to D, unless otherwise specified.

[0046] FIG. 1 is an exemplary figure depicting the schematic configuration of the automotive multiprocessor apparatus according to an embodiment of the present invention. FIG. 2 is an exemplary figure showing the normal state of three communication (Comm, GPIO*2) channels between the first processor and the second processor, in FIG. 1 . FIG. 3 is an exemplary figure showing the state where one of the three communication (Comm, GPIO*2) channels between the first processor and the second processor is closed.

[0047] Referring to FIG. 1 , the multiprocessors (100, 200) comprise a first processor (100), designated as the main processor (Main_uC), and a second processor (200), designated as the auxiliary processor (Co_uC).

[0048] The first processor (100) and the second processor (200), as depicted in FIG. 2, are interconnected via a high level communication channel and two auxiliary GPIO (General Purpose I / O) channels.

[0049] The first processor (100)(Main_uC) and the second processor (200)(Co_uC) are each connected to separate power supply apparatus. For example, the first processor (100) in FIG. 1 receives power by being connected to the power supply apparatus (300).

[0050] The first and second processors (100, 200) may control the power supplied from the power supply apparatus (300) to the first processor (100) by using their respective switch (Switchl , Switch2) control signals. At this time, the switches (Switchl , Switch2) are connected in parallel. For example, when the respective switch (Switchl , Switch2) control signals are both turned off, power to the first processor (100) is cut off. Conversely, if either one of the respective switch (Switchl , Switch2) control signals remains on, power continues to be supplied to the first processor (100). One of the first and second processors (100, 200) (for example: the second processor) performs the function of polling to wake up the system from low power (LP) mode (or sleep mode).

[0051] The first processor (100) may determine whether to switch to sleep mode, and the sleep request is transmitted via the communication (Comm) channel (for example: CAN communication, or the like).

[0052] To prevent the delivery of error signals (for example: sleep request error signals) through the communication (Comm) channel (for example: CAN communication, or the like), the processor checks whether the conditions for signal delivery are met using two GPIO channels (GPIO_M2C, GPIO_C2M). This may prevent the delivery of error signals (for example: sleep request error signals) when only one of the communication (Comm) channels (for example: CAN communication, or the like) is used independently.

[0053] For example, when a signal (for example: sleep request signal) is transmitted from the first processor (100) through the communication (Comm) channel, and the conditions are met through two GPIO channels (GPIO_M2C, GPIO_C2M), the second processor (200) recognizes this as a valid signal (for example: a normal sleep request signal).

[0054] Therefore, as depicted in FIG. 3, when any one of the three communication (Comm, GPIO*2) channels is closed, the system under the present embodiment senses which communication channel is closed, depending on the communication channel that is closed, in response, a method is provided to ensure stable operation of the multiprocessor system (in other words, to ensure consistent system operation).

[0055] FIGS. 4a and 4b are exemplary figures for describing the general purpose input / output (GPIO) operation of the automotive multiprocessor apparatus according to Embodiment 1 of the present invention. At this time, the description of the figure will focus solely on the sections directly related to the core technical aspects of the present invention.

[0056] As depicted in FIG. 4a, when all three communication (Comm, GPIO*2) channels between the first and second processors (100, 200) are in a normal state, the first GPIO terminal (GPIO_M2C), transmitted from the first processor (100) to the second processor (200) through the GPIO terminal, maintains a high (HIGH) level state in both the initialization (IN IT) state and the runtime (RUNTIME) state, as depicted in FIG. 4b (S101 , S102).

[0057] At this time, the system maintains high power (HP) mode.

[0058] As described above, when the first GPIO terminal (GPIO_M2C) maintains a high (HIGH) level state, if the sleep request (SleepReq = Sleep Request) signal is transmitted from the first processor (100)(Main_uC) to the second processor (200)(Co_uC) through the communication (Comm) channel (S103), the second processor (200) interprets this as an error state (MALFUNCTION) and disregards (Ignore) the sleep request (SleepReq) signal.

[0059] However, after the first GPIO terminal (GPIO_M2C), transmitted from the first processor (100) to the second processor (200) through the GPIO terminal, switches to a low (LOW) level state (S104), it enters a normal sleep state if the sleep request (SleepReq = Sleep Request) signal is transmitted from the first processor (100) to the second processor (200) through the communication (Comm) channel (S105).

[0060] At this time, the system switches to the low power (LP) mode.

[0061] As described above, in the present embodiment, there is an issue where the system may inadvertently switch to a low power (LP) mode due to the signal errors (for example: noise or logic errors) through the communication (Comm) channel. This problem arises when the first and second processors (100, 200) are switched to the low power (LP) mode (or sleep mode) based solely on the sleep request (SleepReq) signal transmitted from the first processor (100) through the communication (Comm) signal.

[0062] Therefore, in the present embodiment, stability and robustness are enhanced by ensuring that the first and second processors (100, 200) are switched to the low power (LP) mode, when both of the two conditions (in other words, when the sleep request (SleepReq) signal is transmitted through the communication (Comm) channel, after switching the first GPIO terminal (GPIO_M2C) to a low (LOW) level state) are met.

[0063] FIGS. 5a and 5b are exemplary figures for describing the GPIO operation of the automotive multiprocessor apparatus according to Embodiment 2 of the present invention. At this time, the description of the figure will focus solely on the sections directly related to the core technical aspects of the present invention. Referring to FIG. 5a, when the first processor (100) and the second processor (200) communicate through the communication (Comm) channel (for example: Can communication), the second processor (200) ensures that the first processor (100) processes signals only when it is sensed that the system is in a state where reception is possible, to prevent a retransmission error (if signals are transmitted during a reTransmission error or when the reception side is not yet prepared, and there is no response from the reception end, continued retransmission in an attempt to receive a response from the reception end can lead to a buffer overrun error).

[0064] If the first and second processors (100, 200) are woken up from the low power mode (in other words, sleep mode) in a normal state, the second processor (200) is always woken up first, followed by the first processor (100) being woken up. Consequently, when the second processor (200) is woken up, the second GPIO terminal (GPIO_C2M), transmitted from the second processor (200) to the first processor (100), is set to a low (LOW) level state.

[0065] In addition, when the first processor (100) is woken up, like the initialization (IN IT) state described in FIG. 4b, the first GPIO terminal (GPIO_M2C), transmitted from the first processor (100) to the second processor (200), is set to a high (HIGH) level state (S201 )

[0066] As described above, if the first GPIO terminal (GPIO_M2C) is set to a high (HIGH) level, the second processor (200) changes the second GPIO terminal (GPIO_C2M) to a high (HIGH) level state (S202). This indicates to the first processor (100) that the communication (comm) channel of the second processor (200) has changed to the reception ready state.

[0067] As described above, if the second GPIO terminal (GPIO_C2M) is set to a high (HIGH) level, the first processor (100) recognizes that the communication (Comm) channel of the second processor (200) has changed to the reception ready state, and the full function mode request (FullModeReq) signal is transmitted to the second processor (200) through the communication (Comm) channel (S203). This connects the communication (Comm) of the multiprocessor system of the first and second processors (100, 200), and once the communication (Comm) of the first and second processors (100, 200) is established, the second processor (200) sets and changes the second GPIO terminal (GPIO_C2M) to a low level (S204). When the sleep condition is met and the communication (Comm) of the first and second processors (100, 200) is established, the first processor (100) switches the first GPIO terminal (GPIO_M2C) to a low (LOW) level (S205), and then transmits the sleep request (SleepReq) signal to the second processor (200) through the communication (Comm) signal (S206).

[0068] As described above, to switch the first and second processors (100, 200) to the low power (LP) mode, when both of the two conditions (in other words, when the sleep request (SleepReq) signal is transmitted through the communication (Comm) channel, after switching the first GPIO terminal (GPIO_M2C) to a low (LOW) level state) are met, the second processor (200) switches the second GPIO terminal (GPIO_C2M) to the low power (LP) mode after switching to the high (HIGH) level state (S207).

[0069] Upon the second processor (200) entering to the low power (LP) mode, the second processor (200) turns off the first switch (Switchl ) described in FIG. 1 , and the second GPIO terminal (GPIO_C2M) is switched to the low (LOW) level state (S208). In response, the first processor (100) also turns off the second switch (Switch2) described in FIG. 1 , and enters the low power (LP) mode (a state in which the power is effectively turned off).

[0070] Although not specifically depicted in the figures, if the second GPIO terminal (GPIO_C2M) of the second processor (200) does not switch to a low (LOW) level state, it is determined that the second processor (200) has not normally entered a low-power (LP) mode. In response, the first processor (100) resets the second processor (200), and then the first processor (100) resets itself. Subsequently, when communication (Comm) of the first and second processors (100, 200) is established and the sleep conditions are met, step (S205) to step (S208) are executed again.

[0071] FIG. 6 is an exemplary figure for describing the operation of diagnosing a GPIO terminal of the automotive multiprocessor apparatus according to Embodiment 3 of the present invention. At this time, the description of the figure will focus solely on the sections directly related to the core technical aspects of the present invention. As depicted in FIG. 6, when the communication (Comm) channel is in a normal state, the first processor (100) transmits a diagnosis request (Diag req) signal through the communication (Comm) channel to the second processor (200), and transmits a specific waveform through the first GPIO terminal (GPIO_M2C). Consequently, when the second processor (200) generates the same waveform received through the first GPIO terminal (GPIO_M2C) (in other words, replicates the same waveform) and transmits it through the second GPIO terminal (GPIO_C2M) to the first processor (100), the GPIO terminals may diagnose normal states.

[0072] However, if the second processor (200) is unable to generate the same waveform received through the first GPIO terminal (GPIO_M2C) (in other words, cannot replicate the same waveform) and transmits only the level (in other words, high level or low level) corresponding to one end of the signal, this condition may be diagnosed as a short-circuited state (in other words, a battery short circuit, or a ground short circuit) in the GPIO terminal.

[0073] FIGS. 7a and 7b are exemplary figures for describing the operation for diagnosing the GPIO terminal when the communication (Comm) channel of the automotive multiprocessor apparatus is closed according to Embodiment 4 of the present invention. At this time, the description of the figure will focus solely on the sections directly related to the core technical aspects of the present invention.

[0074] First, referring to FIG. 5b, as described in wake-up initialization (INIT) operation processes (S201 to S204), when the first processor (100) wakes up and the first GPIO terminal (GPIO_M2C) that transmits a signal from the first processor (100) to the second processor (200) is set to a high (HIGH) level, the second processor (200) changes the second GPIO terminal (GPIO_C2M) to a high (HIGH) level state (S202). At this time, if the communication (Comm) channel is in a normal state, the first processor (100) transmits a full function mode request (FullModeReq) signal through the communication (Comm) channel to the second processor (200) (S203). In response, when the communication (Comm) of the first and second processors (100, 200) is established, the second processor (200) sets and changes the second GPIO terminal (GPIO_C2M) to a low (LOW) level (S204). However, when the communication (Comm) channel is in a closed state, as depicted in FIG. 7b, and the first processor (100) wakes up and sets the first GPIO terminal (GPIO_M2C) to a high (HIGH) level (S301 ), the second processor (200) changes the second GPIO terminal (GPIO_C2M) to a high (HIGH) level (S302). In response, the first processor (100) attempts a communication connection through the communication (Comm) channel to the second processor (200). However, the communication (Comm) channel is in a closed state, thus communication is not established (S303)(COMM FAULT). In addition, the second processor (200) maintains the second GPIO terminal (GPIO_C2M) in a high (HIGH) level state, therefore communication is not established (S304)(COMFAULT).

[0075] As described above, if a communication error (COMFAULT) state is maintained for a designated duration (for example: 3 seconds) or longer (in other words, if it is determined that the communication (Comm) channel is closed), the first and second processors (100, 200) immediately enter the GPIO diagnosis mode.

[0076] In other words, when the communication (Comm) channel is blocked and the system enters the GPIO diagnosis mode, the first processor (100) transmits a signal with a first PWM waveform (for example: 10 ms HIGH, 5 ms LOW) through the first GPIO terminal (GPIO_M2C), and the second processor (200) transmits the same PWM waveform through the second GPIO terminal (GPIO_C2M), occurring between both processors for a designated duration (for example: 10 seconds) between both processors (S305).

[0077] When the first and second processors (100, 200) receive a first PWM waveform (for example 10 ms HIGH, 5 ms LOW) designated between both processors, the first and second processors (100, 200) convert this signal into a second PWM waveform (for example: 5 ms HIGH, 10 ms LOW) and transmit it between the two processors (S306).

[0078] At this time, process S306 may be repeatedly executed the number of times specified.

[0079] When both processes S305 and S306 are normally completed (All OK), the first processor (100) changes the first GPIO terminal (GPIO_M2C) to a high (HIGH) level, and the second processor (200) changes the second GPIO terminal (GPIO_C2M) to a high (HIGH) level state (S307).

[0080] As described above, while the first GPIO terminal (GPIO_M2C) and the second GPIO terminal (GPIO_C2M) are held at a high (HIGH) level state, the first and second processors (100, 200) remain in a high-power (HP) mode state. In other words, through process S301 to process S307, only the communication (Comm) channel is in a closed state, while the first and second processors (100, 200) continue in a normal operating state. Accordingly, power management is performed using the first and second GPIO terminals.

[0081] FIGS. 8a and 8b are exemplary figures for describing the diagnosis operation when the communication (Comm) channel of the automotive multiprocessor apparatus according to Embodiment 5 of the present invention, is closed and the first GPIO terminal (GPI0_M2C) has experienced a short-circuited state (in other words, a battery short circuit or a ground short circuit). At this time, the description of the figure will focus solely on the sections directly related to the core technical aspects of the present invention.

[0082] Referring to FIG. 8b, when the communication (Comm) channel is closed (S401 ) and the first GPIO terminal (GPI0_M2C) is ground-shorted, the first GPIO terminal (GPI0_M2C) enters a low (LOW) level state (S402). Consequently, the second processor (200) is unable to change the second GPIO terminal (GPIO_C2M) to a high (HIGH) level state, and maintains it at a low (LOW) level state (S403) Consequently, the first processor (100) determines that the second processor (200) is absent and proceeds to execute its designated functions independently. When the communication (Comm) channel is closed and the first GPIO terminal (GPIO_M2C) is battery-shorted, the first GPIO terminal (GPIO_M2C) enters a high (HIGH) level state (S404). Consequently, the second processor (200) changes the second GPIO terminal (GPIO_C2M) to a high (HIGH) level state (S405).

[0083] In addition, as described with reference to S305 to S307 in FIG. 7b, the first processor (100) and the second processor (200) enter the GPIO diagnosis mode when the communication (Comm) channel is closed, by using the signal of the first PWM waveform (for example: 10 ms HIGH, 5 ms LOW) and the signal of the second PWM waveform (for example: 5 ms HIGH 10 ms LOW) between the two processors. However, the PWM waveform signals are not transmitted through the first GPIO terminal (GPIO_M2C) (S406, S408) (in other words, the PWM waveform signal is not changed and only the same PWM waveform signal is transmitted). Only the PWM waveform signal is transmitted through the second GPIO terminal (GPIO_C2M) (S407, S409). As a result, the first processor (100) sets the corresponding GPIO terminal to high (HIGH) and terminates communication with the second processor (200).

[0084] FIGS. 9a and 9b are exemplary figures for describing the diagnosis operation when the communication (Comm) channel of the automotive multiprocessor apparatus according to Embodiment 6 of the present invention, is closed and the second GPIO terminal (GPIO_C2M) has experienced a short-circuited state (in other words, a battery short circuit or a ground short circuit). At this time, the description of the figure will focus solely on the sections directly related to the core technical aspects of the present invention.

[0085] Referring to FIG. 9b, when the communication (Comm) channel is closed (S401 ) and the second GPIO terminal (GPIO_C2M) is ground-shorted, the first processor (100) sets the first GPIO terminal (GPIO_M2C) to a high (HIGH) level state (S501 ). In response, the second processor (200) is unable to change the second GPIO terminal (GPIO_C2M) to a high (HIGH) level state, and maintains it at a low (LOW) level state (S502).

[0086] Consequently, the first processor (100) determines that the second processor (200) is not operating.

[0087] When the communication (Comm) channel is closed and the second GPIO terminal (GPIO_C2M) is battery-shorted, the first processor (100) sets the first GPIO terminal (GPIO_M2C) to a high (HIGH) level state (S505). In response, upon the second processor (200) changing the second GPIO terminal (GPIO_C2M) to a high (HIGH) level state (S506), as described with reference to S305 to S307 in FIG. 7b, the first processor (100) and the second processor (200) enter the GPIO diagnosis mode when the communication (Comm) channel is closed, by using the signal of the first PWM waveform (for example: 10 ms HIGH, 5 ms LOW) and the signal of the second PWM waveform (for example: 5 ms HIGH 10 ms LOW) between the two processors.

[0088] However, in the GPIO diagnosis mode when the communication (Comm) channel is closed, only the PWM waveform signal is transmitted through the first GPIO terminal (GPIO_M2C) (S507), and the PWM waveform signal is not transmitted through the second GPIO terminal (GPIO_C2M) (S508). Therefore, the first processor (100) diagnosis that the corresponding GPIO terminal is battery- shorted, and the second processor (200) sets the corresponding GPIO terminal to high (HIGH) and closes so that dark current does not flow.

[0089] FIGS. 10a and 10b are exemplary figures for describing the operation for switching to the sleep mode when the communication (Comm) channel of the automotive multiprocessor apparatus, according to Embodiment 7 of the present invention, is in the normal state and the first GPIO terminal (GPIO_M2C) is diagnosed as being in a short-circuited state (in other words, a battery short circuit, a ground short circuit, or the like). At this time, the description of the figure will focus solely on the sections directly related to the core technical aspects of the present invention. As in FIGS. 6 to 9b, when the communication (Comm) channel is in the normal state and the first GPIO terminal (GPIO_M2C) is diagnosed as being in a short- circuited state (in other words, a battery short circuit, a ground short circuit, or the like), the first processor (100) shares the applicable information with the second processor (200).

[0090] Referring to FIG. 10b, if the communication (Comm) channel is in the normal state and the first GPIO terminal (GPIO_M2C) is ground-shorted, the applicable information has already been shared with the second processor (200); therefore, even if the first GPIO terminal (GPIO_M2C) is in a low (LOW) level state (S601 ), the first processor (100) can immediately enter sleep mode (Go sleep) by simply transmitting a sleep request signal to the second processor (200) through the communication (Comm) channel (S602).

[0091] In addition, if the communication (Comm) channel is in the normal state and the first GPIO terminal (GPIO_M2C) is battery-shorted, the applicable information has already been shared with the second processor (200); therefore, even if the first GPIO terminal (GPIO_M2C) is in a high (HIGH) level state (S603), the first processor (100) can immediately enter sleep mode (Go sleep) by simply transmitting a sleep request signal to the second processor (200) through the communication (Comm) channel (S604).

[0092] In addition, if the first and second processors (100, 200) are woken up, the first processor (100) transmits a normal state to the second processor (200) through the communication (Comm) channel (S605).

[0093] However, if an error (malfunction) occurs in the first GPIO terminal (GPIO_M2C), system safety is compromised. Accordingly, the first processor (100) or the second processor (200) may generate an alarm to the user.

[0094] FIGS. 11 a and 11 b are exemplary figures for describing the operation for switching to the sleep mode when the communication (Comm) channel of the automotive multiprocessor apparatus according to Embodiment 8 of the present invention, is in the normal state and the second GPIO terminal (GPIO_C2M) is diagnosed as being in a short-circuited state (in other words, a battery short circuit, a ground short circuit, or the like). At this time, the description of the figure will focus solely on the sections directly related to the core technical aspects of the present invention. As previously described in FIGS. 6 to 9b, when the communication (Comm) channel is in the normal state and the second GPIO terminal (GPIO_C2M) is diagnosed as being in a short-circuited state (in other words, a battery short, a ground short, or the like), the first processor (100) shares the applicable information with the second processor (200).

[0095] Referring to FIG. 11b, if the communication (Comm) channel is in the normal state and the second GPIO terminal (GPIO_C2M) is ground-shorted, the applicable information has already been shared with the first processor (100)(S701 ).

[0096] Therefore, even if the second GPIO terminal (GPIO_C2M) is in a low (LOW) level state, the first processor (100) can still enter sleep mode (Go sleep) by simply transmitting a sleep request signal to the second processor (200) through the communication (Comm) channel (S702).

[0097] In addition, if the communication (Comm) channel is in the normal state and the second GPIO terminal (GPIO_C2M) is battery-shorted, the applicable information has already been shared with the first processor (100)(S703). Therefore, even if the second GPIO terminal (GPIO_C2M) is in a high (HIGH) level state, the first processor (100) can still enter sleep mode (Go sleep) by simply transmitting a sleep request signal to the second processor (200) through the communication (Comm) channel (S704).

[0098] However, although not depicted in the figure, in cases where the second processor (200) does not enter a sleep mode, the first processor (100) may perform a self-reset via a watchdog (not shown), provided that the power supply is not interrupted after an idle period of a designated duration (N ms).

[0099] Subsequently, after the first processor (100) performs a self-reset or wake-up, it already recognizes that the second GPIO terminal (GPIO_C2M) is in a short- circuited state. Therefore, the first processor sets the first GPIO terminal (GPIO_M2C) to a low (LOW) level state (S705), and then immediately attempts to establish a communication link through the communication (Comm) channel (S706). If the second processor (200) fails to respond, the first processor (100) may automatically reset the second processor (200).

[0100] FIGS. 12a and 12b are exemplary figures for describing the mutual operations of the first and second processors (100, 200) when sensing communication (Comm) channel errors of the automotive multiprocessor apparatus according to Embodiment 9 of the present invention. At this time, the description of the figure will focus solely on the sections directly related to the core technical aspects of the present invention.

[0101] As described with reference to FIGS. 7a and 7b, when it is diagnosed that it is only the communication (Comm) channel that is closed (in other words, the two GPIO terminals are diagnosed as normal), and with reference to FIG. 12b: if the first processor (100) sets the first GPIO terminal (GPIO_M2C) to a high (HIGH) level (S801 ), the second processor (200) changes the second GPIO terminal (GPIO_C2M) to a high (HIGH) level state (S802), and the first GPIO terminal (GPIO_M2C) remains in a high power (HP) mode until it is set to a low (LOW) level.

[0102] In addition, when the first processor (100) sets the first GPIO terminal (GPIO_M2C) to a low (LOW) level (S803), the second processor (200) proceeds to sleep mode, and enters a pulldown state. Consequently, when the second GPIO terminal (GPIO_C2M) is changed to a low (LOW) level state (S804), only the first processor (100) proceeds to enter sleep mode.

[0103] FIGS. 13a and 13b are exemplary figures for describing the mutual operations of the first and second processors (100, 200) when sensing communication (Comm) channel errors, and errors of the first GPIO terminal (GPIO_M2C), of the automotive multiprocessor apparatus according to Embodiment 10 of the present invention. At this time, the description of the figure will focus solely on the sections directly related to the core technical aspects of the present invention.

[0104] If both the first and second processors (100, 200) are normal, the first processor (100), upon waking, sets the first GPIO terminal (GPIO_M2C) to a high (HIGH) level, and attempts to establish a communication (Comm) channel.

[0105] However, as depicted in FIG. 13a, when an error occurs in the communication (Comm) channel and in the first GPIO terminal (GPIO_M2C), the first GPIO terminal (GPIO_M2C) is not set to a high (HIGH) level (S901 ). In addition, the first and second processors (100, 200) do not establish a connection through the communication (Comm) channel between the two processors (S902, S903). Consequently, even if the second processor (200) wakes up, it switches back to sleep mode after a specific duration has elapsed (Case 2: anyway goes LP).

[0106] However, in cases where the second processor (200) is required to perform specific functions, even when the first processor (100) and the communication (Comm) channel, or two GPIO channels are not established, it may remain in a high power (HP) mode (Case 1 : keep Co-uC HP permanently).

[0107] At this time, in the two cases described above (e.g.: switching back to a sleep mode if a channel is not established, or remaining in high-power mode despite the failure to establish a channel), an alarm is output to the user. This ensures that the user can seek maintenance from a service center.

[0108] In addition, if the first processor (100) continuously senses communication (Comm) channel errors and errors at the first GPIO terminal (GPIO_M2C) (S904, S905), it may reset the first and second processors (100, 200) (S906).

[0109] This process may be repeatedly performed a designated number of times, and if the communication (Comm) channel errors and errors at the first GPIO terminal (GPIO_M2C) are still sensed, an alarm is output to the user. This ensures that the user can seek maintenance from a service center.

[0110] FIGS. 14a and 14b are exemplary figures for describing the operation of the first processor (100) monitoring the state of the second processor (200) of the automotive multiprocessor apparatus according to Embodiment 11 of the present invention. At this time, the description of the figure will focus solely on the sections directly related to the core technical aspects of the present invention.

[0111] Referring to FIG. 14b, upon initialization (INIT) or woke-up of the multiprocessor system, the second processor (200) transmits an Alive Counter (AliveCounter++) signal, formatted as a specific pulse pattern, to the first processor (100) through the communication (Comm) channel or the second GPIO terminal (GPIO_C2M) at predetermined time intervals. (S1001 ).

[0112] In response, when the first processor (100) transmits an Alive Counter (AliveCounter++) signal, formatted as a specific pulse pattern, through the communication (Comm) channel or the second GPIO terminal (GPIO_C2M) at predetermined time intervals, it initializes an internal timer (S1002). If an Alive Counter (AliveCounter++) signal, formatted as a specific pulse pattern, is not transmitted at predetermined time intervals, it resets the second processor (200) (S1003).

[0113] At this time, if a reset or error occurs, the internal reset counter and error counter continue to increment.

[0114] In addition, in a high power (HP) mode, the second processor (200) transmits an Alive Counter (AliveCounter++) signal, formatted as a specific pulse pattern, to the first processor (100) through the communication (Comm) channel or the second GPIO terminal (GPIO_C2M) at predetermined time intervals. (S1004).

[0115] In response, when the first processor (100) transmits an Alive Counter (AliveCounter++) signal, formatted as a specific pulse pattern, through the communication (Comm) channel or the second GPIO terminal (GPIO_C2M) at predetermined time intervals, it initializes an internal timer (S1005). If an Alive Counter (AliveCounter++) signal, formatted as a specific pulse pattern, is not transmitted at predetermined time intervals, it resets the second processor (200) (S1005, S1006).

[0116] At this time, if a reset or error occurs, the internal reset counter and error counter continue to increment.

[0117] As described above, in the present embodiment, there is an effect in that the communication connection state between automotive multiprocessors can be diagnosed, enabling stable execution of sleep and wake-up operations based on the status of the communication connection state between the processors. Although the present invention has been described with reference to the embodiments illustrated in the drawings, these are merely exemplary, and those having ordinary skill in the art will understand that various modifications and equivalent other embodiments are possible therefrom. Therefore, the scope of technical protection of the present invention should be determined by the following claims. Furthermore, the embodiment described in the present specification can be realized as, for example, a method or process, apparatus, software program, data stream or signal. Even if discussed only in the context of a single form of implementation (e.g., discussed only as a method), the implementation of the discussed feature may also be implemented in another form (e.g., an apparatus or program). The apparatus may be implemented as appropriate hardware, software, firmware, etc. The method may be implemented in an apparatus such as a processor, which generally refers to a processing device including, for example, a computer, a microprocessor, an integrated circuit, or a programmable logic device. The processor includes communication devices such as computers, cell phones, portable or personal information terminals (personal digital assistants: “PDAs”), other devices, and the like, which facilitate the communication of information between end-users easier. Description of the Symbols

[0118] 100: First processor (Main_uC)

[0119] 200: Second processor (Co_uC)

[0120] 300: Power supply apparatus

Claims

Patent claims1. An automotive multiprocessor apparatus comprising: a first processor, which is a main processor (Main_uC); a second processor, which is an auxiliary processor (Co_uC) connected to the first processor via a communication (Comm) channel and a GPIO channel using two GPIO (GPIO_M2C, GPIO_C2M) terminals; a power supply device for supplying power to the first processor; and a plurality of switches (Switchl , Switch2) connected in parallel to control the power supplied from the power supply device to the first processor, characterized in that the plurality of switches (Switchl , Switch2) are controlled respectively through switch control signals from the first and second processors, wherein if the switch control signals are all an off-state, the power applied to the first processor is cut off, and if any of the switch control signals maintains an on-state, the power continues to be supplied to the first processor, and the first and second processors check whether conditions of a signal transmitted using the GPIO channel are satisfied in order to prevent an error signal from being transmitted via the communication (Comm) channel.

2. The automotive multiprocessor apparatus of claim 1 , characterized in that the second processor recognizes, in a state in which the conditions of a signal transmitted via the GPIO channel are satisfied, a sleep request signal transmitted via the communication (Comm) channel from the first processor as a normal sleep request signal and proceeds to enter a sleep mode.

3. The automotive multiprocessor apparatus of claim 1 , characterized in that when the communication (Comm) channel and the two GPIO (GPIO_M2C, GPIO_C2M) channels are all in a normal state, if the first processor transmits, while a first GPIO terminal (GPIO_M2C) maintains a high (HIGH) level state, a sleep request (SleepReq) signal to the second processor via the communication (Comm) channel, the second processordetermines that it is in an error state and ignores the sleep request (SleepReq) signal, and if the first processor transmits, after the first GPIO terminal (GPI0_M2C) is switched to a low (LOW) level state, the sleep request (SleepReq) signal to the second processor via the communication (Comm) channel, the second processor recognizes that it is a normal signal and proceeds to enter a sleep mode.

4. The automotive multiprocessor apparatus of claim 3, characterized in that when proceeding to enter the sleep mode, the second processor turns off the first switch (Switch 1 ), and as the second GPIO terminal (GPI0_C2M) is switched to the low (LOW) level state, the first processor turns off the second switch (Switch2), thereby proceeding to enter a sleep mode, which is a low power (LP) mode.

5. The automotive multiprocessor apparatus of claim 1 , characterized in that in order to prevent a retransmission error during communication using the communication (Comm) channel between the first and second processors, if the first and second processors wake up, the second processor wakes up first to set the second GPIO terminal (GPIO_C2M) to a low (LOW) level, and the first processor (100) wakes up to set the first GPIO terminal (GPIO_M2C) to a high (HIGH) level, and when the first GPIO terminal (GPIO_M2C) is set to the high (HIGH) level, the second processor changes the second GPIO terminal (GPIO_C2M) to be in a high (HIGH) level state, thereby transmitting to the first processor that the communication (comm) channel of the second processor is in a reception ready state.

6. The automotive multiprocessor apparatus of claim 1 , characterized in that in order to diagnose the GPIO (GPIO_M2C, GPIO_C2M) terminals when the communication (Comm) channel is in a normal state, the first processor transmits a diagnosis request (Diag req) signal to the second processor via the communication (Comm) channel, and transmits a specific waveform via the first GPIO terminal (GPIO_M2C), andif the second processor generates the same waveform as that transmitted via the first GPIO terminal (GPIO_M2C), and transmits the same waveform to the first processor via the second GPIO terminal (GPIO_C2M), it is diagnosed that the GPIO (GPIO_M2C, GPIO_C2M) terminals are in a normal state.

7. The automotive multiprocessor apparatus of claim 6, characterized in that if the second processor fails to generate the same waveform as that transmitted via the first GPIO terminal (GPIO_M2C), and only transmits a high-level or low- level signal, it is diagnosed as a battery short circuit or ground short circuit.

8. The automotive multiprocessor apparatus of claim 1 , characterized in that in order to diagnose the GPIO (GPI0_M2C, GPI0_C2M) terminals when the communication (Comm) channel is blocked, when the first processor sets the first GPIO terminal (GPI0_M2C) to a high (HIGH) level, the second processor changes the second GPIO terminal (GPI0_C2M) to the high (HIGH) level, and then if communication is not established between the first and second processors for a specified period of time or longer, it is determined that the communication (Comm) channel is blocked, so that the first and second processors enter a GPIO diagnosis mode, and when entering the GPIO diagnosis mode, the first processor and the second processor repeatedly perform, for a specified number of times, a process of transmitting a signal of a specified first PWM waveform to each other for a specified period of time, wherein the first processor transmits the signal via the first GPIO terminal (GPI0_M2C), and the second processor transmits the signal via the second GPIO terminal (GPI0_C2M), and a process of converting the signal into a signal of a second PWM waveform and transmitting the converted signal to each other, and if the signals of the first and second PWM waveforms are all successfully received between the first and second processors, the first and second processors diagnose that the GPIO (GPI0_M2C, GPI0_C2M) terminals are in a normal state.

9. The automotive multiprocessor apparatus of claim 1 , characterized in thatif the first GPIO terminal (GPIO_M2C) is ground-shorted when the communication (Comm) channel is blocked, the first GPIO terminal (GPIO_M2C) comes to be in a low (LOW) level state, and thus the second processor is unable to change the second GPIO terminal (GPIO_C2M) to be in a high (HIGH) level state and maintains the same in the low (LOW) level state, so that the first processor determines that the second processor is not operating.

10. The automotive multiprocessor apparatus of claim 1 , characterized in that if the first GPIO terminal (GPIO_M2C) is battery-shorted when the communication (Comm) channel is blocked, the first GPIO terminal (GPIO_M2C) comes to be in a high (HIGH) level state, and thus the second processor changes the second GPIO terminal (GPIO_C2M) to be in the high (HIGH) level state, and the first and second processors use a signal of a first PWM waveform and a signal of a second PWM waveform which are specified between each other and enter a GPIO diagnosis mode when the communication (Comm) channel is blocked, and after entering the GPIO diagnosis mode when the communication (Comm) channel is blocked, if the PWM waveform signal through the first GPIO terminal (GPIO_M2C) is not transmitted, and only the PWM waveform signal through the second GPIO terminal (GPIO_C2M) is transmitted, the first processor diagnoses that the first GPIO terminal (GPIO_M2C) is battery-shorted.

11. The automotive multiprocessor apparatus of claim 1 , characterized in that if the second GPIO terminal (GPIO_C2M) is ground-shorted when the communication (Comm) channel is blocked, even if the first processor sets the first GPIO terminal (GPIO_M2C) to a high (HIGH) level, the second processor is unable to change the second GPIO terminal (GPIO_C2M) to the high (HIGH) level and maintains the same in a low (LOW) level state, so that the first processor determines that the second processor is not operating.

12. The automotive multiprocessor apparatus of claim 1 , characterized in that if the second GPIO terminal (GPIO_C2M) is battery-shorted when the communication (Comm) channel is blocked, the first processor sets the first GPIO terminal (GPIO_M2C) to be in a high (HIGH) level state, and accordingly, the second processor changes the second GPIO terminal (GPIO_C2M) to be in a high (HIGH) level state, so that the first and second processors use a signal of a first PWM waveform and a signal of a second PWM waveform which are specified between each other and enter a GPIO diagnosis mode when the communication (Comm) channel is blocked, and after entering the GPIO diagnosis mode when the communication (Comm) channel is blocked, if only the PWM waveform signal through the first GPIO terminal (GPIO_M2C) is transmitted, and the PWM waveform signal through the second GPIO terminal (GPIO_C2M) is not transmitted, the first processor diagnoses that the second GPIO terminal (GPIO_C2M) is battery-shorted.

13. The automotive multiprocessor apparatus of claim 1 , characterized in that in order to switch to a sleep mode when it is diagnosed that the communication (Comm) channel is in a normal state and the first GPIO terminal (GPIO_M2C) is ground-shorted, if the first processor transmits a sleep request signal to the second processor via the communication (Comm) channel when the first GPIO terminal (GPIO_M2C) is in a low (LOW) level state, the second processor immediately enters the sleep mode.

14. The automotive multiprocessor apparatus of claim 1 , characterized in that in order to switch to a sleep mode when it is diagnosed that the communication (Comm) channel is in a normal state and the first GPIO terminal (GPIO_M2C) is battery-shorted, if the first processor transmits a sleep request signal to the second processor via the communication (Comm) channel even when the first GPIO (GPIO_M2C) terminal is in a high (HIGH) level state, the second processor immediately enters the sleep mode.

15. The automotive multiprocessor apparatus of claim 1 , characterized in that in order to switch to a sleep mode when it is diagnosed that the communication (Comm) channel is in a normal state and the second GPIO (GPIO_C2M) terminal is ground-shorted, if the first processor (100) transmits a sleep request signal to the second processor via the communication (Comm) channel even when the second GPIO terminal (GPIO_C2M) is in a low (LOW) level state, the second processor immediately enters the sleep mode.

16. The automotive multiprocessor apparatus of claim 1 , characterized in that in order to switch to a sleep mode when it is diagnosed that the communication (Comm) channel is in a normal state and the second GPIO terminal (GPIO_C2M) is battery-shorted, if the first processor transmits a sleep request signal to the second processor via the communication (Comm) channel even when the second GPIO terminal (GPIO_C2M) is in a high (HIGH) level state, the second processor immediately enters the sleep mode.

17. The automotive multiprocessor apparatus of claim 1 , characterized in that in order to proceed to a high-power mode or sleep mode when the communication (Comm) channel is in an error state, if the first processor sets the first GPIO terminal (GPIO_M2C) to a high (HIGH) level, the second processor changes the second GPIO terminal (GPIO_C2M) to the high (HIGH) level, and maintains a high power (HP) mode until the first GPIO terminal (GPIO_M2C) is changed to a low (LOW) level, and and if the first processor sets the first GPIO terminal (GPIO_M2C) to the low (LOW) level, the second processor proceeds to enter the sleep mode to be in a pulldown state so that when the second GPIO terminal (GPIO_C2M) is changed to the low (LOW) level state, the first processor proceeds to enter the sleep mode.

18. The automotive multiprocessor apparatus of claim 1 , characterized in that if the first processor wakes up, the first processor sets the first GPIO terminal (GPIO_M2C) to a high (HIGH) level, and attempts to connect a communication (Comm) channel with the second processor, andif the first GPIO terminal (GPIO_M2C) is not set to the high (HIGH) level, and the communication (Comm) channel is not connected between the first and second processors, the first processor diagnoses that the communication (Comm) channel and the first GPIO terminal (GPIO_M2C) have errors, and even if the second processor wakes up, the second processor is switched back to the sleep mode after a certain period of time has elapsed, and when the errors of the communication (Comm) channel and the first GPIO terminal (GPIO_M2C) are continuously detected, the first processor resets the first and second processors.

19. The automotive multiprocessor apparatus of claim 1 , characterized in that the second processor transmits an Alive Counter signal in the form of a specific pulse to the first processor at regular time intervals via the communication (Comm) channel or the second GPIO terminal (GPIO_C2M), and the first processor initializes an internal timer when the Alive Counter signal in the form of a specific pulse is transmitted at regular time intervals via the communication (Comm) channel or the second GPIO terminal (GPIO_C2M), and resets the second processor when the Alive Counter signal in the form of a specific pulse is not transmitted at regular time intervals.

20. A method for controlling an automotive multiprocessor apparatus, wherein the automotive multiprocessor apparatus comprises: a first processor, which is a main processor (Main_uC); a second processor, which is an auxiliary processor (Co_uC) connected to the first processor via a communication (Comm) channel and a GPIO channel using two GPIO (GPIO_M2C, GPIO_C2M) terminals; a power supply device for supplying power to the first processor; and a plurality of switches (Switchl , Switch2) connected in parallel to control the power supplied from the power supply device to the first processor, characterized in that the first and second processors respectively control the plurality of switches (Switchl , Switch2) through respective switch control signals, wherein the power applied to the first processor is cut off by allowing the switch control signals to all be an off-state, and the power iscontinuously supplied to the first processor by allowing any one of the switch control signals to maintain an on-state; and the first and second processors check whether conditions of a signal transmitted using the GPIO channel are satisfied in order to prevent an error signal from being transmitted via the communication (Comm) channel.

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