Semiconductor device

Abstract

This semiconductor device comprises a first gate metal, a second gate metal, a third gate metal, a first contact metal, and a second contact metal. The first contact metal is connected to the second gate metal and to the source / drain of a third nanosheet transistor. The second contact metal is connected to the second gate metal, the source / drain of a first nanosheet transistor, and the source / drain of a second nanosheet transistor.

Description

Semiconductor Devices

[0001] The present invention relates to a semiconductor device.

[0002] Static random access memories (SRAMs) are widely used as semiconductor devices. Because SRAMs have high read and write speeds, they are used in applications requiring high-speed processing. Each SRAM cell is composed of six transistors (Tr): two pull-ups (PU), two pull-downs (PD), and two pass gates (PG). Because SRAMs have a complex element structure, it is difficult to improve integration density (miniaturization and high integration) by miniaturizing the elements and reducing the cell area. In response to the demand for high integration of SRAMs, a structure has been proposed in which each transistor is formed using a fin field effect transistor (FinFET) (see, for example, Patent Document 1). Furthermore, in order to improve integration density by miniaturizing elements and reducing cell area, a configuration has been proposed for SRAM in which pull-up and pull-down CMOS (Complementary Metal-Oxide-Semiconductor) inverters are formed using CFETs (Complementary Field-Effect Transistors) (see, for example, Non-Patent Document 1).

[0003] US Patent Publication No. 2014 / 0131813

[0004] H. Liu, et al., IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 70, NO. 3, MARCH 2023

[0005] SRAM requires the formation of pn junction contact metal to connect the source and drain of pull-up and pull-down CMOS. In the CFET SRAM described in Non-Patent Document 1, a middle contact is formed between the source and drain of a vertically stacked p-type semiconductor element and the source and drain of an n-type semiconductor element as the pn junction contact metal. However, forming the middle contact between stacked elements requires highly accurate processing to form contacts only between the source and drain of the stacked elements. This poses challenges such as complex manufacturing processes and poor contact reliability. Therefore, a semiconductor device structure that allows for the formation of pn junction contact metal using a simpler method is desired.

[0006] In order to solve the above-mentioned problems, the present invention provides a semiconductor device in which contact metal for a pn junction can be formed by a simple method.

[0007] The above and other objects of the present invention and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[0008] The semiconductor device of the present invention has a stacked configuration of a first transistor layer having a plurality of nanosheet transistors formed thereon and a second transistor layer having a plurality of nanosheet transistors formed thereon. The semiconductor device has a first gate metal, a second gate metal, and a third gate metal formed in common to the first transistor layer and the second transistor layer. The semiconductor device further includes a first nanosheet transistor having the first gate metal formed in the first transistor layer and a second nanosheet transistor having the third gate metal formed in the first transistor layer. The semiconductor device further includes a third nanosheet transistor having the third gate metal formed in the second transistor layer, a first contact metal connected to the second gate metal and the source / drain of the third nanosheet transistor, a second gate metal disposed between the first nanosheet transistor and the second nanosheet transistor, and a second contact metal connected to the source / drain of the first nanosheet transistor and the source / drain of the second nanosheet transistor. In addition, in the semiconductor device, the first contact metal is formed on the surface of the second transistor layer opposite to the first transistor layer, and the second contact metal is formed on the surface of the first transistor layer opposite to the second transistor layer.

[0009] In addition, the semiconductor device of the present invention has a plurality of bit cells arranged at the intersections of bit lines BL<0+3n>, bit lines BL<1+3n>, and bit lines BL<2+3n> [n=0, 1, 2, ... N] and word lines WL<0+3x>, word lines WL<1+3x>, and word lines WL<2+3x> [x=0, 1, 2, ... N]. The semiconductor device includes first bit cells connected to bit lines BL<0+3n>, BL<1+3n>, and word line WL<0+3x>, second bit cells connected to bit lines BL<2+3n>, BL<0+3n>, and word line WL<1+3x>, and third bit cells connected to bit lines BL<1+3n>, BL<2+3n>, and word line WL<2+3x>, and a first switch circuit connecting the bit lines BL<0+3n>, BL<1+3n>, and BL<2+3n> to either a first bit line BLT<n> or a second bit line BLB<n> of a first sense amplifier. When the word line WL<0+3x> is in the ON state, the first switch circuit connects the bit line BL<0+3n> to the first bit line BLT<n> and connects the bit line BL<1+3n> to the second bit line BLB<n>. When the word line WL<1+3x> is in the ON state, the first switch circuit connects the bit line BL<2+3n> to the first bit line BLT<n> and connects the bit line BL<0+3n> to the second bit line BLB<n-1>. When the word line WL<2+3x> is in the ON state, the first switch circuit connects the bit line BL<1+3n> to the first bit line BLT<n> and connects the bit line BL<2+3n> to the second bit line BLB<n>.

[0010] According to the present invention, it is possible to provide a semiconductor device in which contact metal for a pn junction can be formed by a simple method.

[0011] Problems, configurations, and effects other than those described above will become clear from the following description of the embodiments.

[0012] 1 is an equivalent circuit diagram of an SRAM bit cell; FIG. 2 is a plan layout diagram (top view) of the upper layer side of a semiconductor memory element formed with a CFET; FIG. 3 is a plan layout diagram (top view) of the lower layer side of a semiconductor memory element formed with a CFET; FIG. 4 is a cross-sectional view along the A-A' line of the semiconductor memory element shown in FIGS. 2 and 3; FIG. 4 is a cross-sectional view along the B-B' line of the semiconductor memory element shown in FIGS. 2 and 3; FIG. 5 is a plan layout diagram of the upper layer side of a semiconductor manufacturing apparatus according to a second embodiment formed with a CFET; FIG. 6 is a plan layout diagram of the lower layer side of a semiconductor manufacturing apparatus according to a second embodiment formed with a CFET; FIG. 7 is a wiring diagram of a semiconductor device according to a second embodiment; FIG. 8 is a table showing the relationship between switch circuits and word lines WL; FIG. 9 is a wiring diagram of a semiconductor device according to a third embodiment; FIG. 10 is a table showing the relationship between "read / write" and "read" of bit lines BL of a semiconductor device according to a third embodiment and ON / OFF of word lines WL.

[0013] Hereinafter, embodiments of a semiconductor device and a method for manufacturing a semiconductor device will be described with reference to the drawings, but the present invention is not limited to the following examples. In the following description, the drawings only show the configuration of the main parts of the semiconductor device, and other configurations such as insulating layers will be omitted. The description will be given in the following order: 1. Semiconductor device of first embodiment 2. Semiconductor device of second embodiment 3. Semiconductor device of third embodiment

[0014] 1. Semiconductor Device of First Embodiment A specific embodiment of the semiconductor device of the present invention will be described below. FIGS. 1 to 4 show schematic configuration diagrams of a semiconductor memory element as an example of a semiconductor device of the first embodiment. [Circuit Diagram of Semiconductor Device] FIG. 1 shows an equivalent circuit diagram of an SRAM (static random access memory) bit cell, as an example of a semiconductor memory element, which comprises six transistors (6Tr) in one bit cell. The SRAM 100 has six transistors (6Tr) in one bit cell. Of the six Transistors in the SRAM 100, four transistors constitute a first CMOS (Complementary Metal-Oxide-Semiconductor) inverter INV1 (hereinafter referred to as the first inverter INV1) and a second CMOS inverter INV2 (hereinafter referred to as the second inverter INV2). The SRAM 100 further includes two transistors that control input and output to the SRAM 100. In the SRAM 100, the first conductivity type is n-type and the second conductivity type is p-type.

[0015] 1, the first inverter INV1 and the second inverter INV2 are cross-coupled, i.e., the output of the first inverter INV1 is connected to the input of the second inverter INV2, and similarly, the output of the second inverter INV2 is connected to the input of the first inverter INV1.

[0016] The first inverter INV1 constituting the SRAM 100 includes a pull-up PMOS (p-type metal oxide semiconductor) transistor PU1 (hereinafter referred to as transistor PU1) and a pull-down NMOS (n-type metal oxide semiconductor) transistor PD1 (hereinafter referred to as transistor PD1). The second inverter INV2 includes a pull-up PMOS transistor PU2 (hereinafter referred to as transistor PU2) and a pull-down NMOS transistor PD2 (hereinafter referred to as transistor PD2).

[0017] The SRAM 100 includes a pass-gate PMOS transistor PG1 (hereinafter referred to as transistor PG1) connected between a first bit line BLT and the first and second inverters INV1 and INV2. One source / drain of the transistor PG1 is connected to the first bit line BLT. The other source / drain of the transistor PG1 is commonly connected to the output node of the first inverter INV1 and the input (gate) of the second inverter INV2. The SRAM 100 also includes a pass-gate PMOS transistor PG2 (hereinafter referred to as transistor PG2) connected between a second bit line BLB and the first and second inverters INV1 and INV2. One source / drain of the transistor PG2 is connected to the second bit line BLB. The other source / drain of the transistor PG2 is commonly connected to the output node of the second inverter INV2 and the input (gate) of the first inverter INV1. The gates of the transistors PG1 and PG2 are connected to a word line WL in a row of the SRAM array that connects the SRAMs 100. The transistors PG1 and PG2 may be NMOS transistors.

[0018] In the SRAM 100, both the first inverter INV1 and the second inverter INV2 are coupled between a power supply voltage Vdd and a reference potential Vss. That is, in the SRAM 100, one source / drain of the transistor PU1 is connected to the power supply voltage Vdd, and the other source / drain is connected to the source / drain of the transistor PD1. One source / drain of the transistor PD1 is connected to the reference potential Vss, and the other source / drain is connected to the source / drain of the transistor PU1. One source / drain of the transistor PU2 is connected to the power supply voltage Vdd, and the other source / drain is connected to the source / drain of the transistor PD2. One source / drain of the transistor PD2 is connected to the reference potential Vss, and the other source / drain is connected to the source / drain of the transistor PU2.

[0019] Transistors PU1 and PD1 share a gate. Transistors PU2 and PD2 share a gate. The common gate of transistors PU1 and PD1 is the input of the first inverter INV1. The common gate of transistors PU2 and PD2 is the input of the second inverter INV2. The connection (contact) between the source and drain of transistor PU1 and the source and drain of transistor PD1 is the output node of the first inverter INV1. The connection (contact) between the source and drain of transistor PU2 and the source and drain of transistor PD2 is the output node of the second inverter INV2.

[0020] [Configuration of Semiconductor Device] Next, the configuration of the semiconductor device (semiconductor memory element) of this embodiment will be described. FIG. 2 is a plan layout diagram (top view) of the upper layer side of a semiconductor memory element formed with a CFET. FIG. 3 is a plan layout diagram (top view) of the lower layer side of a semiconductor memory element formed with a CFET. FIG. 4 is a cross-sectional view of the semiconductor memory element shown in FIGS. 2 and 3 taken along line A-A'. FIG. 5 is a cross-sectional view of the semiconductor memory element shown in FIGS. 2 and 3 taken along line B-B'. Note that in the drawings shown in FIGS. 2-5, insulating layers and the like other than those constituting the main SRAM are omitted unless necessary for explanation.

[0021] As shown in Figures 2-5, the semiconductor device 200 has a CFET (Complementary Field Effect Transistor) structure in which nanosheet transistors (semiconductor elements) having a GAA (Gate All Around)-FET structure are stacked vertically. In the semiconductor device 200, the nanosheets also include nanowires. Figure 2 shows the planar layout of the upper layer of the CFET as viewed from the top of Figures 4 and 5. Figure 3 shows the planar layout of the lower layer of the CFET as viewed from the bottom of Figures 4 and 5.

[0022] 2 and 3 , the semiconductor device 200 includes four rows of transistor layers 111 (second transistor layer), 112 (fourth transistor layer), 113 (sixth transistor layer), and 114 (eighth transistor layer), which are separated in the column direction, as well as transistor layers 115 (first transistor layer), 116 (third transistor layer), 117 (fifth transistor layer), and 118 (seventh transistor layer). The bit cells of the SRAM 210 (first bit cell), the SRAM 211 (second bit cell), the SRAM 212 (third bit cell), and the SRAM 213 are formed in the transistor layers 111, 112, 113, 114, 115, 116, 117, and 118, respectively. The layers in which the transistor layers 111, 112, 113, and 114 are formed are referred to as the upper layers of the CFET. The layer on which the transistor layers 115, 116, 117, and 118 are formed is defined as the lower layer of the CFET.

[0023] Each of the SRAMs 210, 211, 212, and 213 is formed across a total of four semiconductor layers, including two rows of semiconductor layers and two upper and lower semiconductor layers. Specifically, the SRAM 210 is formed across the transistor layer 111 in the first row and the transistor layer 112 in the second row in the upper layers, and the transistor layer 115 in the first row and the transistor layer 116 in the second row in the lower layers. The SRAMs 212 and 213 are formed across the transistor layer 112 in the second row and the transistor layer 113 in the third row in the upper layers, and the transistor layer 116 in the second row and the transistor layer 117 in the third row in the lower layers. The SRAM 211 is formed across the transistor layer 113 in the third row and the transistor layer 114 in the fourth row in the upper layers, and the transistor layer 117 in the third row in the lower layers and the transistor layer 118 in the fourth row. The SRAM 210, SRAM 211, SRAM 212, and SRAM 213 each have the same structure, so the structure of the SRAM 210 will be described below as a representative.

[0024] 2, the SRAM 210 includes a gate metal 101 (first gate metal) that constitutes the gate electrode of a transistor PG1 (first nanosheet transistor) in a transistor layer 111. The SRAM 210 further includes a semiconductor layer 120 and a semiconductor layer 121 in the transistor layer 111, sandwiching the gate metal 101. The gate metal 101 is connected to a word line WL (not shown).

[0025] The SRAM 210 also includes a gate metal 102 (second gate metal) in contact with the semiconductor layer 121. The SRAM 210 also includes a gate metal 103 (third gate metal) that constitutes a transistor PD1 (third nanosheet transistor) in the transistor layer 111 on the opposite side of the semiconductor layer 121 with respect to the gate metal 102. The SRAM 210 also includes a semiconductor layer 122 and a semiconductor layer 123 that serve as the source and drain of the transistor PD1 in the transistor layer 111 across the gate metal 103. The semiconductor layer 122 is formed in a position that contacts the gate metal 102 and the gate metal 103.

[0026] The SRAM 210 has a contact metal 104 (first contact metal) that electrically connects the gate metal 102 and the semiconductor layer 122. The contact metal 104 is formed continuously from on the gate metal 102 to on the semiconductor layer 122. The SRAM 210 also has a contact metal 105. The contact metal 105 is formed on the semiconductor layer 123. The contact metal 105 electrically connects the semiconductor layer 123, which serves as the source and drain of the transistor PD1, to a reference potential Vss (not shown). The semiconductor layer 123 and the contact metal 105, together with the SRAM 210, are shared by adjacent SRAM bit cells (not shown).

[0027] In the SRAM 210, the gate metal 102 and the gate metal 103 are formed continuously from the transistor layer 111 in the first row to the transistor layer 112 in the second row. In the transistor layer 112, the gate metal 102 forms the gate electrode of the transistor PD2 (the sixth nanosheet transistor). The source and drain of the transistor PD2 are formed by the semiconductor layer 126 and the semiconductor layer 127 formed in the transistor layer 112 with the gate metal 102 sandwiched therebetween.

[0028] The SRAM 210 includes a contact metal 106 in the transistor layer 112. The contact metal 106 is formed on a semiconductor layer 127. The contact metal 106 electrically connects the semiconductor layer 127, which serves as the source and drain of the transistor PD2, to a reference potential Vss (not shown). The contact metal 106 is also shared by an SRAM 213 adjacent to the SRAM 210. Similarly, the semiconductor layer 127 is also shared by an SRAM 213 adjacent to the SRAM 210.

[0029] In the transistor layer 112, the gate metal 103 is formed in contact with the semiconductor layer 126. The SRAM 210 has a contact metal 107 (third contact metal) that electrically connects the gate metal 103 and the semiconductor layer 126. The contact metal 107 is formed continuously from above the gate metal 103 to above the semiconductor layer 126.

[0030] The SRAM 210 also includes a semiconductor layer 125 on the opposite side of the gate metal 103 from the semiconductor layer 126. The SRAM 210 also includes a gate metal 108 (fourth gate metal) in the transistor layer 112 that contacts the semiconductor layer 125 and forms the gate electrode of the transistor PG2 (fourth nanosheet transistor). The gate metal 108 is connected to a word line WL (not shown). The transistor layer 112 sandwiches the gate metal 108 and includes a semiconductor layer 124 and a semiconductor layer 125.

[0031] 3, in the semiconductor device 200, gate metals 101, 102, 103, and 108 are continuously formed from upper transistor layers 111, 112, 113, and 114 (FIG. 2) to lower transistor layers 115, 116, 117, and 118. The semiconductor device 200 also includes bit lines BL0, BL1, BL2, and BL3 that are parallel to the transistor layers 115, 116, 117, and 118. In FIG. 3, the bit lines BL0, BL1, BL2, and BL3 are indicated by dashed dotted lines. In the semiconductor device 200, the bit lines BL0, BL1, BL2, and BL3 function as the first bit line BLT and the second bit line BLB of the SRAM 100 shown in FIG. 1.

[0032] The SRAM 210 includes a gate metal 101 that constitutes the gate electrode of the transistor PG1 in the transistor layer 115. The SRAM 210 further includes a semiconductor layer 130 and a semiconductor layer 131 that serve as the source and drain of the transistor PG1 in the transistor layer 115, sandwiching the gate metal 101. The SRAM 210 also includes a contact metal 140 on the semiconductor layer 130. The contact metal 140 electrically connects the semiconductor layer 130, which serves as the source and drain of the transistor PG1, to the bit line BL0. The semiconductor layer 130 and the contact metal 140 are shared with the SRAM 210 by an adjacent SRAM bit cell (not shown).

[0033] The SRAM 210 includes a semiconductor layer 131 between gate metal 101 and gate metal 102 in the transistor layer 115. The SRAM 210 also includes a semiconductor layer 132 between gate metal 102 and gate metal 103 in the transistor layer 115. The SRAM 210 also includes a gate metal 103 that forms the gate electrode of transistor PU1 (second nanosheet transistor) on the opposite side of the semiconductor layer 132 from the gate metal 102 in the transistor layer 115. The SRAM 210 also includes a semiconductor layer 133 that, together with the semiconductor layer 132, serves as the source / drain of transistor PU1 on the opposite side of the semiconductor layer 132 from the gate metal 103 in the transistor layer 115.

[0034] The SRAM 210 includes a contact metal 141 (second contact metal). The contact metal 141 is formed on the gate metal 102, the semiconductor layer 131, and the semiconductor layer 132. The contact metal 141 electrically connects the gate metal 102, the semiconductor layer 131, which is the source and drain of the transistor PG1, and the semiconductor layer 132, which is the source and drain of the transistor PU1. The SRAM 210 also includes a contact metal 142. The contact metal 142 is formed on the semiconductor layer 133. The contact metal 142 electrically connects the semiconductor layer 133, which is the source and drain of the transistor PU1, to a power supply voltage Vdd (not shown). The semiconductor layer 133 and the contact metal 142 are shared with the SRAM 210 and an adjacent SRAM bit cell (not shown).

[0035] In the SRAM 210, the gate metal 102 and the gate metal 103 are formed continuously from the transistor layer 115 in the first row to the transistor layer 116 in the second row. In the transistor layer 116, the gate metal 102 forms the gate electrode of the transistor PU2 (the fifth nanosheet transistor). The source and drain of the transistor PU2 are formed by the semiconductor layers 136 and 137 formed in the transistor layer 116 with the gate metal 102 sandwiched therebetween.

[0036] The SRAM 210 includes a contact metal 143 in the transistor layer 116. The contact metal 143 is formed on the semiconductor layer 137. The contact metal 143 electrically connects the semiconductor layer 137, which serves as the source and drain of the transistor PU2, to a power supply voltage Vdd (not shown). The contact metal 143 is also shared by the SRAM 213 adjacent to the SRAM 210. Similarly, the semiconductor layer 137 is also shared by the SRAM 213 adjacent to the SRAM 210.

[0037] In the transistor layer 116, the gate metal 103 is formed in contact with the semiconductor layer 136. The SRAM 210 further includes a semiconductor layer 135 on the opposite side of the gate metal 103 from the semiconductor layer 136. The SRAM 210 further includes a gate metal 108 in contact with the semiconductor layer 135 in the transistor layer 116 to form the gate electrode of the transistor PG2. The gate metal 108 is connected to a word line WL (not shown). The transistor layer 116 further includes a semiconductor layer 134 on the opposite side of the gate metal 108 from the semiconductor layer 135, which serves as the source / drain of the transistor PG2 together with the semiconductor layer 135. The gate metal 108 that forms the gate electrode of the transistor PG2 is arranged in a different column from the gate metal 101 that forms the gate electrode of the transistor PG1.

[0038] The SRAM 210 includes a contact metal 144 (fourth contact metal). The contact metal 144 is formed on the gate metal 103, the semiconductor layer 135, and the semiconductor layer 136. The contact metal 144 electrically connects the gate metal 103, the semiconductor layer 135, which is the source and drain of the transistor PG2, and the semiconductor layer 136, which is the source and drain of the transistor PU2. The SRAM 210 also includes a contact metal 145 (fifth contact metal) on the semiconductor layer 134. The contact metal 145 electrically connects the semiconductor layer 134, which is the source and drain of the transistor PG2, to the bit line BL1. The semiconductor layer 134 and the contact metal 145 are shared by the SRAM 210 and the adjacent SRAM 212.

[0039] 2 are regions formed in the transistor layer 111 into which n-type or p-type dopant ions have been introduced. Semiconductor layers 124, 125, 126, and 127 are regions formed in the transistor layer 112 into which n-type or p-type dopant ions have been introduced. Semiconductor layers 130, 131, 132, and 133 are regions formed in the transistor layer 115 into which n-type or p-type dopant ions have been introduced. Semiconductor layers 134, 135, 136, and 137 are regions formed in the transistor layer 116 into which n-type or p-type dopant ions have been introduced.

[0040] [Cross-sectional structure (1) of semiconductor device] In the semiconductor device 200, as shown in Fig. 4, in the cross-sectional view of the semiconductor memory element taken along line A-A' shown in Fig. 2 and Fig. 3, the transistor layer 111 of the first upper row and the transistor layer 115 of the first lower row of the SRAM 210 are stacked. Fig. 4 shows only the configuration of the transistor layer 111 of the first upper row and the transistor layer 115 of the first lower row that form the SRAM 210. In addition, the SRAMs 211, 212, and 213 shown in Fig. 2 and Fig. 3 also have the same configuration as the SRAM 210 shown in Fig. 4.

[0041] 4, the SRAM 210 has a stacked structure of an upper transistor layer 111 and a lower transistor layer 115. The transistor layer 111 and the transistor layer 115 are separated by an insulating layer 110. The transistor layer 111 and the transistor layer 115 are connected by gate metals 101, 102, and 103.

[0042] The gate metal 101, the gate metal 102, and the gate metal 103 are formed continuously on the upper transistor layer 111 and the lower transistor layer 115. Therefore, the gate metal 101, the gate metal 102, and the gate metal 103, together with the insulating layer 110, are interposed between the upper transistor layer 111 and the lower transistor layer 115. In addition, an insulating layer (not shown), such as a gate insulating film, is formed between the gate metals 101, 102, and 103 and the transistor layers 111 and 115.

[0043] The transistor layer 111 includes a semiconductor layer 120, a semiconductor layer 151, a semiconductor layer 121, a semiconductor layer 152, a semiconductor layer 122, a semiconductor layer 153, and a semiconductor layer 123. In the transistor layer 111, for example, the semiconductor layer 120, the semiconductor layer 121, the semiconductor layer 122, and the semiconductor layer 123 are n-type semiconductor regions, and the semiconductor layer 151, the semiconductor layer 152, and the semiconductor layer 153 are p-type semiconductor regions.

[0044] The gate metal 101 is disposed in a region sandwiched between the semiconductor layer 120 and the semiconductor layer 121. In addition, a semiconductor layer 151 is provided in the region between the semiconductor layer 120 and the semiconductor layer 121 together with the gate metal 101. In Fig. 4, four layers of gate metal 101 and three layers of semiconductor layer 151 are stacked in the same direction as the direction in which the transistor layer 111 and the transistor layer 115 are stacked. In addition, the periphery of the semiconductor layer 151 in the direction perpendicular to the line A-A' is covered with the gate metal 101.

[0045] The gate metal 102 is disposed in a region sandwiched between the semiconductor layer 121 and the semiconductor layer 122. In addition, a semiconductor layer 152 is provided in the region between the semiconductor layer 121 and the semiconductor layer 122 together with the gate metal 102. In Fig. 4, four layers of the gate metal 102 and three layers of the semiconductor layer 152 are stacked. In addition, the periphery of the semiconductor layer 152 in a direction perpendicular to the line A-A' is covered with the gate metal 102.

[0046] Gate metal 103 is disposed in a region sandwiched between semiconductor layer 122 and semiconductor layer 123. In addition, semiconductor layer 153 is provided in the region between semiconductor layer 122 and semiconductor layer 123 together with gate metal 103. In Fig. 4, four layers of gate metal 103 and three layers of semiconductor layer 153 are stacked. In addition, the periphery of semiconductor layer 153 in a direction perpendicular to line A-A' is covered with gate metal 103.

[0047] The transistor layer 115 includes a semiconductor layer 130, a semiconductor layer 161, a semiconductor layer 131, a semiconductor layer 162, a semiconductor layer 132, a semiconductor layer 163, and a semiconductor layer 133. In the transistor layer 115, for example, the semiconductor layer 130, the semiconductor layer 131, the semiconductor layer 132, and the semiconductor layer 133 are p-type semiconductor regions, and the semiconductor layer 161, the semiconductor layer 162, and the semiconductor layer 163 are n-type semiconductor regions.

[0048] In the transistor layer 115, the gate metal 101 is disposed in a region sandwiched between the semiconductor layer 130 and the semiconductor layer 131. In addition, a semiconductor layer 161 is provided in the region between the semiconductor layer 130 and the semiconductor layer 131 together with the gate metal 101. In FIG. 4, four layers of the gate metal 101 and three layers of the semiconductor layer 161 are stacked. In addition, the periphery of the semiconductor layer 161 in a direction perpendicular to the line A-A' is covered with the gate metal 101.

[0049] In the transistor layer 115, the gate metal 102 is disposed in a region sandwiched between the semiconductor layer 131 and the semiconductor layer 132. In addition, a semiconductor layer 162 is provided in the region between the semiconductor layer 131 and the semiconductor layer 132 together with the gate metal 102. In Fig. 4, four layers of the gate metal 102 and three layers of the semiconductor layer 162 are stacked. In addition, the periphery of the semiconductor layer 162 in a direction perpendicular to the line A-A' is covered with the gate metal 102.

[0050] In the transistor layer 115, the gate metal 103 is disposed in a region sandwiched between the semiconductor layer 132 and the semiconductor layer 133. In addition, the region between the semiconductor layer 132 and the semiconductor layer 133 includes a semiconductor layer 163 together with the gate metal 103. In Fig. 4, four layers of the gate metal 103 and three layers of the semiconductor layer 163 are stacked. In addition, the periphery of the semiconductor layer 163 in a direction perpendicular to the line A-A' is covered with the gate metal 103.

[0051] In the SRAM 210, the surfaces of the lowest gate metals 101, 102, and 103 formed in the transistor layer 115 are exposed from the lower part of the transistor layer 115. The lower part of the transistor layer 115 has a recessed shape in the region where the gate metals 101, 102, and 103 are formed, down to a position where the surfaces of the gate metals 101, 102, and 103 are exposed. As a result, the transistor layer 115 has a region where the semiconductor layers 130, 131, 132, and 133 extend toward the bit line BL0 side beyond the surfaces of the lowest gate metals 101, 102, and 103.

[0052] In the SRAM 210, in the transistor layer 111, a transistor PD1 is configured by a semiconductor layer 122, a semiconductor layer 123, a semiconductor layer 153, and a gate metal 103. The semiconductor layer 122 and the semiconductor layer 123 are the source and drain of the transistor PD1. The semiconductor layer 153 is the channel region of the transistor PD1. The gate metal 103 is the gate electrode of the transistor PD1.

[0053] In the transistor layer 115, the semiconductor layer 130, the semiconductor layer 131, the semiconductor layer 161, and the gate metal 101 form the transistor PG1. The semiconductor layer 130 and the semiconductor layer 131 form the source and drain of the transistor PG1. The semiconductor layer 161 forms the channel region of the transistor PG1. The gate metal 101 forms the gate electrode of the transistor PG1.

[0054] In the transistor layer 115, the semiconductor layer 132, the semiconductor layer 133, the semiconductor layer 163, and the gate metal 103 form the transistor PU1. The semiconductor layer 132 and the semiconductor layer 133 are the source and drain of the transistor PU1. The semiconductor layer 163 is the channel region of the transistor PU1. The gate metal 103 is the gate electrode of the transistor PU1.

[0055] The SRAM 210 has a contact metal 104 on the transistor layer 111. The contact metal 104 is formed from the surface of the uppermost gate metal 102 exposed from the transistor layer 111 to the surface of the semiconductor layer 122. The insulating layer of the gate metal 102 is removed from the surface exposed from the transistor layer 111, exposing the surface. Therefore, the contact metal 104 forms an electrical connection from the gate metal 102 to the semiconductor layer 122.

[0056] The SRAM 210 also has a contact metal 105 on the transistor layer 111. The contact metal 105 is formed between the semiconductor layer 123 that forms the source and drain of the transistor PD1 and a reference potential Vss (not shown) on the transistor layer 111. The contact metal 105 electrically connects the source and drain of the transistor PD1 to the reference potential Vss.

[0057] The SRAM 210 has a contact metal 140 below the transistor layer 115. The contact metal 140 is formed from the tip of the region where the semiconductor layer 130 extends downward to the bit line BL0 arranged below the transistor layer 115 via the insulating layer 110. This contact metal 140 connects the semiconductor layer 130 that forms the source and drain of the transistor PG1 to the bit line BL0.

[0058] The SRAM 210 has a contact metal 141 below the transistor layer 115. The contact metal 141 covers from the tip of the region where the semiconductor layer 131 extends downward to the surface of the lowest layer of the gate metal 102 exposed from the bottom of the transistor layer 115 and to the tip of the region where the semiconductor layer 132 extends downward. The contact metal 141 forms electrical connections among the semiconductor layer 131 that constitutes the source and drain of the transistor PG1, the gate metal 102, and the semiconductor layer 132 that constitutes the source and drain of the transistor PU1.

[0059] The SRAM 210 has a contact metal 142 below the transistor layer 115. The contact metal 142 is formed from the tip of a region extending below the semiconductor layer 133 that constitutes the source and drain of the transistor PU1 to a power supply voltage Vdd (not shown) that is arranged below the transistor layer 115. This contact metal 142 connects the semiconductor layer 133 that constitutes the source and drain of the transistor PU1 to the power supply voltage Vdd.

[0060] As described above, the SRAM 210 has contact metal 104 and contact metal 141. Therefore, the semiconductor layer 131 constituting the source and drain of transistor PG1 is electrically connected to the semiconductor layer 122 constituting the source and drain of transistor PD1 via the contact metal 141, gate metal 102, and contact metal 104. The semiconductor layer 131 constituting the source and drain of transistor PG1 is electrically connected to the semiconductor layer 132 constituting the source and drain of transistor PU1 via the contact metal 141.

[0061] Furthermore, the gate metal 102 constitutes the gate electrode of the transistor PD2 formed in the transistor layer 112 and the gate electrode of the transistor PU2 formed in the transistor layer 116. Therefore, the semiconductor layer 131 constituting the source and drain of the transistor PG1 is electrically connected to the gate metal 102 by the contact metal 141, thereby forming electrical connections between the source and drain of the transistor PG1 and the gate electrodes of the transistor PD2 and the transistor PU2.

[0062] As a result, the SRAM 210 has connections between the source and drain of the transistor PG1 and the output node of the first inverter INV1 and the input of the second inverter INV2 via the contact metal 104 and the contact metal 141.

[0063] Furthermore, in the SRAM 210, the semiconductor layer 122 constituting the source and drain of the transistor PD1 and the semiconductor layer 132 constituting the source and drain of the transistor PU1 are electrically connected via contact metal 141, gate metal 102, and contact metal 104. Therefore, in the first inverter INV1, the contact metal for the pn junction between the source and drain of the transistor PD1 and the source and drain of the transistor PU1 is formed by the contact metal 141, gate metal 102, and contact metal 104. [Cross-Sectional Structure (2) of the Semiconductor Device] In the semiconductor device 200, as shown in FIG. 5, in the cross-sectional view of the semiconductor memory element taken along line B-B' shown in FIGS. 2 and 3, the transistor layer 112 of the second upper row and the transistor layer 116 of the second lower row of the SRAM 210 are stacked. FIG. 5 shows only the configuration of the transistor layer 112 of the second upper row and the transistor layer 116 of the first lower row that form the SRAM 210.

[0064] In the SRAM 210, the configuration of the transistor layer 112 in the second upper row and the transistor layer 116 in the second lower row shown in Fig. 5 has the same configuration as the transistor layer 111 in the first upper row and the transistor layer 115 in the first lower row shown in Fig. 4, but with the left and right reversed. Therefore, the following description will not be repeated for the configuration shown in Fig. 4. In addition, the SRAMs 211, 212, and 213 shown in Figs. 2 and 3 also have the same configuration as the SRAM 210 shown in Fig. 5.

[0065] 5 shows the configuration of the transistor PG2, the transistor PD2, and the transistor PU2 formed in the transistor layer 112 and the transistor layer 116. As shown in FIG. 5, the SRAM 210 has a stacked structure of an upper transistor layer 112 and a lower transistor layer 116. The transistor layer 112 and the transistor layer 116 are separated by an insulating layer 110. The transistor layer 112 and the transistor layer 116 are connected by gate metal 102, gate metal 103, and gate metal 108.

[0066] The gate metal 102, the gate metal 103, and the gate metal 108 are formed continuously on the upper transistor layer 112 and the lower transistor layer 116. Therefore, the gate metal 102, the gate metal 103, and the gate metal 108, together with the insulating layer 110, are interposed between the upper transistor layer 112 and the lower transistor layer 116. In addition, an insulating layer (not shown), such as a gate insulating film, is formed between the gate metals 102, 103, and 108 and the transistor layers 112 and 116.

[0067] The transistor layer 112 includes a semiconductor layer 124, a semiconductor layer 154, a semiconductor layer 125, a semiconductor layer 155, a semiconductor layer 126, a semiconductor layer 156, and a semiconductor layer 127. In the transistor layer 112, for example, the semiconductor layer 124, the semiconductor layer 125, the semiconductor layer 126, and the semiconductor layer 127 are n-type semiconductor regions, and the semiconductor layer 154, the semiconductor layer 155, and the semiconductor layer 156 are p-type semiconductor regions.

[0068] In the transistor layer 112, the gate metal 108 is disposed in a region sandwiched between the semiconductor layers 124 and 125. A semiconductor layer 154 is provided in the region between the semiconductor layers 124 and 125 together with the gate metal 108. In the transistor layer 112, the gate metal 102 is disposed in a region sandwiched between the semiconductor layers 126 and 127. A semiconductor layer 156 is provided in the region between the semiconductor layers 126 and 127 together with the gate metal 102. In the transistor layer 112, the gate metal 103 is disposed in a region sandwiched between the semiconductor layers 125 and 126. A semiconductor layer 155 is provided in the region between the semiconductor layers 125 and 126 together with the gate metal 103.

[0069] The transistor layer 116 includes a semiconductor layer 134, a semiconductor layer 164, a semiconductor layer 135, a semiconductor layer 165, a semiconductor layer 136, a semiconductor layer 166, and a semiconductor layer 137. In the transistor layer 116, for example, the semiconductor layer 134, the semiconductor layer 135, the semiconductor layer 136, and the semiconductor layer 137 are p-type semiconductor regions, and the semiconductor layer 164, the semiconductor layer 165, and the semiconductor layer 166 are n-type semiconductor regions.

[0070] In the transistor layer 116, the gate metal 108 is disposed in a region sandwiched between the semiconductor layer 134 and the semiconductor layer 135. A semiconductor layer 164 is provided in the region between the semiconductor layer 134 and the semiconductor layer 135 together with the gate metal 108. In the transistor layer 116, the gate metal 102 is disposed in a region sandwiched between the semiconductor layer 136 and the semiconductor layer 137. A semiconductor layer 166 is provided in the region between the semiconductor layer 136 and the semiconductor layer 137 together with the gate metal 102. In the transistor layer 116, the gate metal 103 is disposed in a region sandwiched between the semiconductor layer 135 and the semiconductor layer 136. A semiconductor layer 165 is provided in the region between the semiconductor layer 135 and the semiconductor layer 136 together with the gate metal 103.

[0071] In the SRAM 210, the surfaces of the lowest gate metals 102, 103, and 108 formed in the transistor layer 116 are exposed from the lower part of the transistor layer 116. The lower part of the transistor layer 116 has a recessed shape in the region where the gate metals 102, 103, and 108 are formed, down to a position where the surfaces of the gate metals 102, 103, and 108 are exposed. As a result, the transistor layer 116 has a region where the semiconductor layers 134, 135, 136, and 137 extend toward the bit line BL1 beyond the surfaces of the lowest layers of the gate metals 102, 103, and 108.

[0072] In the SRAM 210, in the transistor layer 112, the transistor PD2 is configured by the semiconductor layer 126, the semiconductor layer 127, the semiconductor layer 156, and the gate metal 102. The semiconductor layer 126 and the semiconductor layer 127 are the source and drain of the transistor PD2. The semiconductor layer 156 is the channel region of the transistor PD2. The gate metal 102 is the gate electrode of the transistor PD2.

[0073] In the transistor layer 116, the semiconductor layer 134, the semiconductor layer 135, the semiconductor layer 164, and the gate metal 108 form the transistor PG2. The semiconductor layer 135 and the semiconductor layer 136 form the source and drain of the transistor PG2. The semiconductor layer 164 forms the channel region of the transistor PG2. The gate metal 108 forms the gate electrode of the transistor PG2.

[0074] In the transistor layer 116, the semiconductor layer 136, the semiconductor layer 137, the semiconductor layer 166, and the gate metal 102 form a transistor PU2. The semiconductor layer 136 and the semiconductor layer 137 are the source and drain of the transistor PU2. The semiconductor layer 166 is the channel region of the transistor PU2. The gate metal 102 is the gate electrode of the transistor PU2.

[0075] The SRAM 210 has a contact metal 107 on the transistor layer 112. The contact metal 107 is formed from the surface of the uppermost gate metal 103 exposed from the transistor layer 112 to the surface of the semiconductor layer 126. The insulating layer of the gate metal 103 is removed from the surface exposed from the transistor layer 112, exposing the surface. Therefore, the contact metal 107 forms an electrical connection from the gate metal 103 to the semiconductor layer 126.

[0076] The SRAM 210 also has a contact metal 106 on the transistor layer 112. The contact metal 106 is formed between the semiconductor layer 127 that forms the source and drain of the transistor PD2 and a reference potential Vss (not shown) on the transistor layer 112. The contact metal 106 electrically connects the source and drain of the transistor PD2 to the reference potential Vss.

[0077] The SRAM 210 has a contact metal 145 below the transistor layer 116. The contact metal 145 is formed from the tip of the region where the semiconductor layer 134 extends downward to the bit line BL1 disposed below the transistor layer 116 via the insulating layer 110. This contact metal 145 connects the semiconductor layer 134 that forms the source and drain of the transistor PG2 to the bit line BL1.

[0078] The SRAM 210 has a contact metal 144 below the transistor layer 116. The contact metal 144 covers from the tip of the region where the semiconductor layer 135 extends downward to the surface of the lowest layer of the gate metal 103 exposed from the bottom of the transistor layer 116 and to the tip of the region where the semiconductor layer 136 extends downward. The contact metal 144 forms electrical connections among the semiconductor layer 135 that forms the source and drain of the transistor PG2, the gate metal 103, and the semiconductor layer 136 that forms the source and drain of the transistor PU2.

[0079] The SRAM 210 has a contact metal 143 below the transistor layer 116. The contact metal 143 is formed from the tip of a region extending below the semiconductor layer 137 that constitutes the source and drain of the transistor PU2 to a power supply voltage Vdd (not shown) that is arranged below the transistor layer 116. This contact metal 143 connects the semiconductor layer 137 that constitutes the source and drain of the transistor PU2 to the power supply voltage Vdd.

[0080] As described above, the SRAM 210 has contact metal 107 and contact metal 144. Therefore, the semiconductor layer 135 constituting the source and drain of transistor PG2 is electrically connected to the semiconductor layer 126 constituting the source and drain of transistor PD2 via contact metal 144, gate metal 103, and contact metal 107. The semiconductor layer 135 constituting the source and drain of transistor PG2 is electrically connected to the semiconductor layer 136 constituting the source and drain of transistor PU2 via contact metal 144.

[0081] Furthermore, the gate metal 103 constitutes the gate electrode of the transistor PD1 formed in the transistor layer 111 and the gate electrode of the transistor PU1 formed in the transistor layer 115. Therefore, the semiconductor layer 135 constituting the source and drain of the transistor PG2 is electrically connected to the gate metal 103 by the contact metal 144, thereby forming electrical connections between the source and drain of the transistor PG2 and the gate electrodes of the transistor PD1 and the transistor PU1.

[0082] As a result, the SRAM 210 has connections between the source and drain of the transistor PG2 and the output node of the second inverter INV2 and the input of the first inverter INV1 via the contact metal 107 and the contact metal 144.

[0083] Furthermore, in the SRAM 210, the semiconductor layer 126 that forms the source and drain of the transistor PD2 and the semiconductor layer 136 that forms the source and drain of the transistor PU2 are electrically connected via contact metal 144, gate metal 103, and contact metal 107. Therefore, in the second inverter INV2, the contact metal for the pn junction between the source and drain of the transistor PD2 and the source and drain of the transistor PU2 is formed by the contact metal 144, gate metal 103, and contact metal 107.

[0084] In the semiconductor device 200 having the above-described configuration, the semiconductor layer 120 and the gate metal 101, the semiconductor layer 121 and the gate metal 102, and the semiconductor layer 122 and the gate metal 103 have the same structure in the transistor layer 111. Furthermore, in the semiconductor device 200, the semiconductor layer 130 and the gate metal 101, the semiconductor layer 131 and the gate metal 102, and the semiconductor layer 132 and the gate metal 103 have the same structure in the transistor layer 115. That is, the semiconductor device 200 has a structure in which the semiconductor layers 120, 121, 122, 123, 130, 131, 132, and 133 and the gate metals 101, 102, and 103 having the same structure are repeatedly formed in the SRAM 210.

[0085] Similarly, in the semiconductor device 200, the transistor layers 112, 116, 113, 117, 114, and 118 have the same configuration as the transistor layer 111. Therefore, in the semiconductor device 200, the SRAMs 210, 211, 212, and 213 have a structure in which the same semiconductor layers and gate metals are repeatedly formed. As a result, in the semiconductor device 200, it is not necessary to remove gate metals that do not function as gate electrodes of the transistors PG1, PG2, PD1, PD2, PU1, and PU2 in the transistor layers 111, 112, 113, 114, 115, 116, 117, and 118. Furthermore, in the semiconductor device 200, contact metals 104, 107, 141, and 144 formed on the upper and lower semiconductor layers form contact metals for the pn junctions of the source and drain of the transistors PD1 and PD2 and the transistors PU1 and PU2. Therefore, it is not necessary to form contact metal for pn junction between the upper transistor layers 111, 112, 113, and 114 and the lower transistor layers 115, 116, 117, and 118. Therefore, the semiconductor device 200 can be manufactured by a simpler method than the conventional CFET SRAM.

[0086] 2. Semiconductor Device of Second Embodiment Next, a semiconductor device of a second embodiment will be described. The semiconductor device of the second embodiment is a configuration in which a read circuit for an SRAM bit cell, a switch circuit, and the configuration of each connection wiring are added to the semiconductor device of the first embodiment described above. Therefore, detailed description of the same configuration as the semiconductor device of the first embodiment described above will be omitted.

[0087] 6-8 show the configuration of the semiconductor device of the second embodiment. Fig. 6 is a plan layout diagram of the upper layer of the semiconductor manufacturing device formed with CFET. Fig. 7 is a plan layout diagram of the lower layer of the semiconductor manufacturing device formed with CFET. Fig. 8 is a wiring diagram of the semiconductor device of the second embodiment.

[0088] 6 and 7, the semiconductor device 300 has four SRAM bit cells, namely, SRAM 210, SRAM 211, SRAM 212, and SRAM 214. The semiconductor device 300 has a structure in which three types of SRAM bit cells, namely, SRAM 210, SRAM 211, and SRAM 212, are repeatedly arranged. Therefore, for example, the SRAM 214 has the same configuration as the SRAM 210 that is repeatedly arranged.

[0089] The SRAM 210 has the same configuration as that of the first embodiment described above. The SRAM 211, SRAM 212, and SRAM 214 also have the same configuration as the SRAM 210. In the following description, the configurations relating to the SRAM 210, SRAM 211, and SRAM 212 of the semiconductor device 300 will be mainly described. The other configurations are similar to the configurations relating to the SRAM 210, SRAM 211, and SRAM 212, so descriptions will be omitted.

[0090] 6 , in the semiconductor device 300, word lines WL are arranged along the transistor layers 111, 112, 113, 114, and 119. Furthermore, the reference potential Vss is arranged above and overlapping the transistor layers 111, 112, 113, 114, and 119. For this reason, the wiring for the reference potential Vss is not shown.

[0091] In the SRAM 210, contact metal 105 formed on the source and drain of transistor PD1 is connected to the reference potential Vss at contact 172. In the SRAM 210, contact metal 106 formed on the source and drain of transistor PD2 is connected to the reference potential Vss at contact 174. In the SRAMs 212, 213, and 214, similar to the SRAM 210, the contact metal formed on the source and drain of transistor PD1 is connected to the reference potential Vss, and the contact metal formed on the source and drain of transistor PD2 is connected to the reference potential Vss.

[0092] In the SRAM 210, gate metal 101, which serves as the gate electrode of transistor PG1, is connected to word line WL181 at contact 171. In the SRAM 210, gate metal 108, which serves as the gate electrode of transistor PG2, is connected to word line WL182 at contact 173. WL<0> is provided as a word line address to connect the gate metals 101 and 108, which serve as the gate electrodes of transistors PG1 and PG2 of the SRAM 210, to word lines WL181 and WL182.

[0093] Similarly, in the SRAM 211, gate metal 103, which serves as the gate electrode of transistor PG1, is connected to word line WL183 at contact 202. In the SRAM 211, gate metal 201, which serves as the gate electrode of transistor PG2, is connected to word line WL186 at contact 222. WL<1> is provided as a word line address to connect gate metals 103 and 220, which serve as the gate electrodes of transistors PG1 and PG2 of the SRAM 211, to word lines WL183 and WL186. In the SRAM 211, contact metal 203 (seventh contact metal) formed on the source and drain of transistor PD1 is connected to reference potential Vss at contact 204. In the SRAM 211, contact metal 205, which serves as the source and drain of transistor PD2, is connected to reference potential Vss at contact 206. The contact metal 203 and contact 204 are shared by the adjacent SRAMs 211 and 212. Furthermore, the contact metal 205 and the contact 206 are shared by the adjacent SRAM 211 and SRAM 214 .

[0094] In the SRAM 212, a gate metal 223 serving as the gate electrode of the transistor PG1 is connected to the word line WL182 at a contact 224. In the SRAM 212, a gate metal 225 serving as the gate electrode of the transistor PG2 is connected to the word line WL184 at a contact 226. A word line address WL<2> is provided to connect the gate metals 223 and 225 serving as the gate electrodes of the transistors PG1 and PG2 of the SRAM 212 to the word lines WL182 and WL184.

[0095] In the SRAM 214, gate metal 101, which serves as the gate electrode of transistor PG1, is connected to word line WL185 at contact 227. In the SRAM 214, gate metal 108, which serves as the gate electrode of transistor PG2, is connected to word line WL187 at contact 228. A word line address WL<0> is provided to connect the gate metals 101 and 108, which serve as the gate electrodes of transistors PG1 and PG2 of the SRAM 214, to word lines WL185 and WL187. Furthermore, for each SRAM bit cell formed in the semiconductor device 300, word line addresses WL<4>, WL<5>, WL<6>, WL<7>, ... are provided to connect the gate metals, which serve as the gate electrodes of transistors PG1 and PG2, to word lines WL.

[0096] 7 , in the semiconductor device 300, wiring for the power supply voltage Vdd is arranged along the transistor layers 115, 116, 117, 118, and 129. Furthermore, the bit line BL is arranged above and overlapping the transistor layers 115, 116, 117, 118, and 129. For this reason, the wiring of the bit line BL is not shown.

[0097] In the SRAM 210, contact metal 142 formed on the source and drain of transistor PU1 is connected to wiring 191 of power supply voltage Vdd at contact 176. In the SRAM 210, contact metal 143 formed on the source and drain of transistor PU2 is connected to wiring 192 of power supply voltage Vdd at contact 177. In the SRAMs 212, 213, and 214, similar to the SRAM 210, the contact metal formed on the source and drain of transistor PU1 is connected to power supply voltage Vdd, and the contact metal formed on the source and drain of transistor PU2 is connected to power supply voltage Vdd.

[0098] In the SRAM 210, contact metal 140 provided on the semiconductor layer 130 that serves as the source and drain of the transistor PG1 is connected to the bit line BL<0> at a contact 175. In the SRAM 210, contact metal 145 provided on the semiconductor layer 134 that serves as the source and drain of the transistor PG2 is connected to the bit line BL<1> at a contact 178.

[0099] Similarly, in the SRAM 211, a contact metal 233 provided on the semiconductor layer that will become the source and drain of transistor PG1 is connected to bit line BL<2> at contact 234. Also, in the SRAM 211, a contact metal 235 provided on the semiconductor layer that will become the source and drain of transistor PG2 is connected to bit line BL<3> at contact 236. In the SRAM 211, a contact metal 207 (sixth contact metal) formed on the source and drain of transistor PU1 is connected to wiring 193 of power supply voltage Vdd at contact 208. Also, in the SRAM 211, a contact metal 209 formed on the source and drain of transistor PU2 is connected to wiring 194 of power supply voltage Vdd at contact 195. The contact metal 207 and contact 208 are shared by the adjacent SRAMs 211 and 212. Furthermore, the contact metal 209 and the contact 195 are shared by the adjacent SRAM 211 and SRAM 214 .

[0100] In the SRAM 212, contact metal 145 provided in the semiconductor layer 134 that serves as the source and drain of transistor PG1 is connected to bit line BL<1> at contact 178. That is, in the SRAM 212, the semiconductor layer 134 that serves as the source and drain of transistor PG1 is shared with the semiconductor layer 134 that serves as the source and drain of transistor PG2 of the SRAM 210. The SRAM 210 and the SRAM 212 share the contact metal 145 connected to bit line BL<1> and the contact 178. In addition, in the SRAM 212, contact metal 231 provided in the semiconductor layer that serves as the source and drain of transistor PG2 is connected to bit line BL<2> at contact 232.

[0101] In the SRAM 214, a contact metal 237 provided in a semiconductor layer that serves as the source and drain of transistor PG1 is connected to bit line BL<3> at contact 238. In the SRAM 214, a contact metal 239 provided in a semiconductor layer that serves as the source and drain of transistor PG2 is connected to bit line BL<4> at contact 230. Furthermore, in each SRAM bit cell formed in the semiconductor device 300, contact metals provided in the semiconductor layer that serves as the source and drain of transistors PG1 and PG2 are connected to bit line BL<0>, bit line BL<1>, bit line BL<2>, bit line BL<3>, bit line BL<4>, ... bit line BL<n> at contacts.

[0102] [Wiring Diagram of Semiconductor Device] FIG. 8 shows a wiring diagram of the SRAM bit cells of the semiconductor device 300, the bit lines BL connected to the SRAM bit cells, the word lines WL, the sense amplifiers SA (first sense amplifiers), and the switch circuits 301 (first switch circuits) arranged between the sense amplifiers SA and the SRAM bit cells.

[0103] 8 , in the semiconductor device 300, bit lines BL are arranged in the row direction, including bit line BL<0>, bit line BL<1>, bit line BL<2>, bit line BL<3>, bit line BL<4>, ..., and bit line BL<11>. The bit lines BL are connected to one of sense amplifiers SA240, 250, 260, and 270. Furthermore, word lines WL are arranged in the column direction, including word line WL<0>, word line WL<1>, word line WL<2>, word line WL<3>, word line WL<4>, word line WL<5>, .... The word lines WL are connected to, for example, a word line driver (not shown).

[0104] In the semiconductor device 300, SRAM bit cells are arranged at positions where bit lines BL and word lines WL intersect. For example, an SRAM 210 is arranged at a position where word line WL<0> intersects with bit line BL<0> and bit line BL<1>. An SRAM 211 is arranged at a position where word line WL<1> intersects with bit line BL<2> and bit line BL<3>. An SRAM 212 is arranged at a position where word line WL<2> intersects with bit line BL<1> and bit line BL<2>.

[0105] In the semiconductor device 300, the SRAM bit cells are divided into three groups, WL<0+3x>, WL<1+3x>, and WL<2+3x>, based on the addresses of the word lines WL to which they are connected. Here, x=0, 1, 2, ..., N. In FIG. 8 , the word line WL<0> and the word line WL<3> are exemplified as WL<0+3x>. Furthermore, the word line WL<1> and the word line WL<4> are exemplified as WL<1+3x>, and the word line WL<2> and the word line WL<5> are exemplified as WL<2+3x>.

[0106] Here, the SRAM bit cells connected to WL<0+3x> are group A, the SRAM bit cells connected to WL<1+3x> are group B, and the SRAM bit cells connected to WL<2+3x> are group C. In the example shown in Figure 8, SRAMs 210, 214, 217, and 220 are group A, SRAMs 211, 215, and 218 are group B, and SRAMs 212, 216, 219, and 221 are group C. Also, the SRAM bit cells connected to word line WL<3> are group A, the SRAM bit cells connected to word line WL<4> are group B, and the SRAM bit cells connected to word line WL<5> are group C.

[0107] In the semiconductor device 300, the addresses of the bit lines BL can be expressed as BL<0+3n>, BL<1+3n>, and BL<2+3n>, where n = 0, 1, 2, ..., N. In FIG. 8, BL<0+3n> is exemplified by the bit line BL<0>, the bit line BL<3>, the bit line BL<6>, and the bit line BL<9>. BL<1+3n> is exemplified by the bit line BL<1>, the bit line BL<4>, the bit line BL<7>, and the bit line BL<10>, and BL<2+3n> is exemplified by the bit line BL<2>, the bit line BL<5>, the bit line BL<8>, and the bit line BL<11>.

[0108] In the semiconductor device 300, the SRAM bit cells of group A connected to WL<0+3x> are connected to BL<0+3n> and BL<1+3n>. For example, SRAM 210 is connected to bit line BL<0> and bit line BL<1>, SRAM 214 is connected to bit line BL<3> and bit line BL<4>, SRAM 217 is connected to bit line BL<6> and bit line BL<7>, and SRAM 220 is connected to bit line BL<9> and bit line BL<10>. Furthermore, the SRAM bit cells of group B connected to WL<1+3x> are connected to BL<0+3n> and BL<2+3n>. For example, SRAM 211 is connected to bit lines BL<2> and BL<3>, SRAM 215 is connected to bit lines BL<5> and BL<6>, and SRAM 218 is connected to bit lines BL<8> and BL<9>. Furthermore, the SRAM bit cells of group C connected to WL<2+3x> are connected to BL<1+3n> and BL<2+3n>. For example, SRAM 212 is connected to bit lines BL<1> and BL<2>, SRAM 216 is connected to bit lines BL<4> and BL<5>, SRAM 219 is connected to bit lines BL<7> and BL<8>, and SRAM 221 is connected to bit lines BL<10> and BL<11>.

[0109] 8 also illustrates sense amplifiers SA240, SA250, SA260, and SA270 as examples of sense amplifiers SA connected to bit lines BL. One sense amplifier SA is provided for each row of SRAM bit cells in groups A, B, and C. In the example shown in FIG. 8, one sense amplifier SA240 is provided for SRAM210, SRAM211, and SRAM212, as well as for SRAM bit cells that share bit lines BL with these SRAM bit cells. In the example shown in FIG. 8, one sense amplifier SA240 is provided for bit lines BL<0>, BL<1>, BL<2>, and BL<3>. One sense amplifier SA250 is provided for bit lines BL<3>, BL<4>, BL<5>, and BL<6>. In this way, bit line BL<3> is shared by sense amplifier SA240 and sense amplifier SA250. That is, one sense amplifier SA is provided for BL<0+3n>, BL<1+3n>, BL<2+3n>, and BL<0+3(n+1)>.

[0110] Furthermore, the semiconductor device 300 includes a switch circuit 301 between the SRAM bit cell connected by the bit line BL and the sense amplifier SA. The bit line BL is connected to the first bit line BLT or the second bit line BLB of the sense amplifier SA via the switch circuit 301. The first bit line BLT and the second bit line BLB connected to the sense amplifier SA can be expressed as BLT<n> and BLB<n>, where n=0, 1, 2, ..., N. In FIG. 8, the sense amplifier SA240 has n=0, and the bit line BL connected to the sense amplifier SA240 is expressed as the first bit line BLT<0> and the second bit line BLB<0>. Similarly, the sense amplifier SA250 has n=1, and the bit line BL connected to the sense amplifier SA250 is expressed as the first bit line BLT<1> and the second bit line BLB<1>. The sense amplifier SA260 has n=2, and the bit lines BL connected to the sense amplifier SA260 are denoted as the first bit line BLT<2> and the second bit line BLB<2>. The sense amplifier SA270 has n=3, and the bit lines BL connected to the sense amplifier SA270 are denoted as the first bit line BLT<3> and the second bit line BLB<3>.

[0111] 8, the switch circuit 301 has a switch MOS transistor having the bit line BL and the first bit line BLT or the second bit line BLB as its source and drain, and a switch wiring A_WLA, A_WLB, or A_WLC connected to its gate electrode. The wiring A_WLA, A_WLB, and A_WLC are connected to, for example, a driver of the switch circuit 301 (not shown). A voltage is applied to one of the wiring A_WLA, A_WLB, and A_WLC selected by the driver of the switch circuit 301.

[0112] For example, the bit line BL<0> is connected to the first bit line BLT<0> of the sense amplifier SA240 via a transistor 241 connected to the wiring A_WLA. Similarly, the bit line BL<1> is connected to the second bit line BLB<0> of the sense amplifier SA240 via a transistor 242 connected to the wiring A_WLA. The bit line BL<1> is also connected to the first bit line BLT<0> of the sense amplifier SA240 via a transistor 245 connected to the wiring A_WLC. The bit line BL<2> is also connected to the first bit line BLT<0> of the sense amplifier SA240 via a transistor 243 connected to the wiring A_WLB. The bit line BL<2> is also connected to the second bit line BLB<0> of the sense amplifier SA240 via a transistor 246 connected to the wiring A_WLC. The bit line BL<3> is connected to the second bit line BLB<0> of the sense amplifier SA240 via a transistor 244 connected to the wiring A_WLB. The bit line BL<3> is also connected to the first bit line BLT<1> of the sense amplifier SA250 via a transistor 251 connected to the wiring A_WLA. The bit line BL<4> is connected to the second bit line BLB<1> of the sense amplifier SA250 via a transistor 252 connected to the wiring A_WLA. The bit line BL<4> is also connected to the first bit line BLT<1> of the sense amplifier SA250 via a transistor 255 connected to the wiring A_WLC. The bit line BL<5> is connected to the first bit line BLT<1> of the sense amplifier SA250 via a transistor 253 connected to the wiring A_WLB. The bit line BL<5> is connected to the second bit line BLB<1> of the sense amplifier SA250 via a transistor 256 connected to the wiring A_WLC. The bit line BL<6> is connected to the second bit line BLB<1> of the sense amplifier SA250 via a transistor 254 connected to the wiring A_WLB. The bit line BL<6> is connected to the first bit line BLT<2> of the sense amplifier SA260 via a transistor 261 connected to the wiring A_WLA.Similarly, bit lines BL<7> to BL<11> are connected to the first bit line BLT<2>, first bit line BLT<3>, second bit line BLB<2>, or second bit line BLB<3> of sense amplifiers SA260, 270 via each transistor connected to wiring A_WLA, wiring A_WLB, or wiring A_WLC.

[0113] The relationship between the bit line BL, the sense amplifier SA, and the first bit line BLT and second bit line BLB connected to the sense amplifier SA can be summarized as follows: The bit line BL<0+3n> is connected to the first bit line BLT<n> of the sense amplifier SA via a MOS transistor connected to the wiring A_WLA. The bit line BL<0+3n> is connected to the second bit line BLB<(n-1)> of the sense amplifier SA via a MOS transistor connected to the wiring A_WLB. The bit line BL<1+3n> is connected to the first bit line BLT<n> of the sense amplifier SA via a MOS transistor connected to the wiring A_WLC. The bit line BL<1+3n> is connected to the second bit line BLB<n> of the sense amplifier SA via a MOS transistor connected to the wiring A_WLA. The bit line BL<2+3n> is connected to the first bit line BLT<n> of the sense amplifier SA via a transistor connected to the wiring A_WLB. The bit line BL<2+3n> is connected to a second bit line BLB<n> of the sense amplifier SA via a MOS transistor connected to a wiring A_WLC.

[0114] For example, the SRAM 210 connected to the word line WL<0> is connected to the bit line BL<0> and the bit line BL<1>. Therefore, the SRAM 210 is connected to the first bit line BLT<0> of the sense amplifier SA240 by the bit line BL<0> via a transistor 241 connected to the wiring A_WLA. Furthermore, the SRAM 210 is connected to the second bit line BLB<0> of the sense amplifier SA240 by the bit line BL<1> via a transistor 242 connected to the wiring A_WLA. In this way, the bit line BL<0> and the bit line BL<1> of the SRAM 210 are connected to the first bit line BLT<0> and the second bit line BLB<0> of the sense amplifier SA240 by switching via the wiring A_WLA.

[0115] Similarly, the SRAM 211 connected to the word line WL<1> is connected to the bit line BL<2> and the bit line BL<3>. The SRAM 211 is connected to the first bit line BLT<0> of the sense amplifier SA240 via the bit line BL<2> and the transistor 243 connected to the wiring A_WLB. Furthermore, the SRAM 211 is connected to the second bit line BLB<0> of the sense amplifier SA240 via the bit line BL<3> and the transistor 244 connected to the wiring A_WLB. In this way, the bit line BL<2> and the bit line BL<3> of the SRAM 211 are connected to the first bit line BLT<0> and the second bit line BLB<0> of the sense amplifier SA240 by switching via the wiring A_WLB.

[0116] Furthermore, the SRAM 212 connected to the word line WL<2> is connected to the bit line BL<1> and the bit line BL<2>. The SRAM 212 is connected to the first bit line BLT<0> of the sense amplifier SA240 by the bit line BL<1> via a transistor 245 connected to the wiring A_WLC. Furthermore, the SRAM 212 is connected to the second bit line BLB<0> of the sense amplifier SA240 by the bit line BL<2> via a transistor 246 connected to the wiring A_WLC. In this way, the bit line BL<1> and the bit line BL<2> of the SRAM 212 are connected to the first bit line BLT<0> and the second bit line BLB<0> of the sense amplifier SA240 by switching via the wiring A_WLC.

[0117] As described above, the SRAM bit cell connected to WL<0+3x> is connected to the first bit line BLT or the second bit line BLB<0> of the sense amplifier SA under the control of the wiring A_WLA of the switch circuit 301. Similarly, the SRAM bit cell connected to WL<1+3x> is connected to the first bit line BLT or the second bit line BLB<0> of the sense amplifier SA under the control of the wiring A_WLB of the switch circuit 301. The SRAM bit cell connected to WL<2+3x> is connected to the first bit line BLT or the second bit line BLB<0> of the sense amplifier SA under the control of the wiring A_WLC of the switch circuit 301.

[0118] Therefore, in a configuration in which adjacent SRAM bit cells share a bit line BL in the semiconductor device 300, the SRAM bit cell connected to the sense amplifier SA can be arbitrarily selected by controlling the wiring A_WLA, wiring A_WLB, and wiring A_WLC. For example, consider SRAM 210 and SRAM 212, which share bit line BL<1>. In this case, wiring A_WLA is turned ON, and wiring A_WLB and wiring A_WLC are turned OFF. At this time, the bit line BL<0> connected to SRAM 210 is connected to the first bit line BLT<0> of the sense amplifier SA240, and the bit line BL<1> is connected to the second bit line BLB<0> of the sense amplifier SA240. Here, SRAM 212 is also connected to the second bit line BLB<0> of the sense amplifier SA240 by the bit line BL<1>. However, because the wiring A_WLB and the wiring A_WLC are OFF, the bit line BL<2> connected to the SRAM 212 is not connected to either the first bit line BLT<0> or the second bit line BLB<0> of the sense amplifier SA240. Therefore, by driving the wiring A_WLA, only the SRAM 210 can be connected to the sense amplifier SA240.

[0119] Next, the SRAM 210 and SRAM 212, which share the bit line BL<1>, will be described. In this case, when the line A_WLC is turned ON and the lines A_WLA and A_WLB are turned OFF, the bit line BL<1> connected to the SRAM 212 is connected to the first bit line BLT<0> of the sense amplifier SA240, and the bit line BL<2> is connected to the second bit line BLB<0> of the sense amplifier SA240. Here, the SRAM 210 is also connected to the first bit line BLT<0> of the sense amplifier SA240 by the bit line BL<1>. However, because the line A_WLA and the line A_WLB are OFF, the bit line BL<0> connected to the SRAM 210 is not connected to either the first bit line BLT<0> or the second bit line BLB<0> of the sense amplifier SA240. Therefore, by driving the wiring A_WLC, only the SRAM 212 can be connected independently to the sense amplifier SA240. Similarly, in the SRAM 212 and SRAM 211 that share the bit line BL<2>, the wiring A_WLB is turned ON and the wiring A_WLA and wiring A_WLC are turned OFF. This allows only the SRAM 211 to be connected to the sense amplifier SA240.

[0120] 9 shows the relationship between the wirings A_WLA, A_WLB, and A_WLC of the switch circuit 301 and the word lines WL<0+3x>, WL<1+3x>, and WL<2+3x>. As shown in the table in FIG. 9, the semiconductor device 300 can arbitrarily control the driving of the SRAM bit cells of group A connected to WL<0+3x>, the SRAM bit cells of group B connected to WL<1+3x>, or the SRAM bit cells of group C connected to WL<2+3x> by controlling the wirings A_WLA, A_WLB, and A_WLC. In the table in FIG. 9, "1" indicates an ON state and "0" indicates an OFF state.

[0121] 3. Semiconductor Device of Third Embodiment Next, a semiconductor device of a third embodiment will be described. The semiconductor device of the third embodiment has a configuration in which a single-ended readout circuit is added to the semiconductor device of the second embodiment described above. Therefore, detailed description of the same configuration as the semiconductor device of the second embodiment described above will be omitted.

[0122] FIG. 10 shows the configuration of a semiconductor device according to the third embodiment. FIG. 10 is a wiring diagram of the semiconductor device. The semiconductor device 400 shown in FIG. 10 has a configuration in which a single-ended read circuit 401 is added to the semiconductor device 300 shown in FIG. 8 described above. Furthermore, the semiconductor device 400 shown in FIG. 10 has two types of word lines WL, namely, word line WL_L and word line WL_R, to which each SRAM bit cell is connected. Furthermore, the semiconductor device 400 shown in FIG. 10 omits the word lines WL<3>, WL<4>, and WL<5>, and the SRAM bit cells connected to these word lines WL, which are present in the semiconductor device 300 shown in FIG. 8 described above. Except for these, the semiconductor device 400 shown in FIG. 10 has the same configuration as the semiconductor device 300 shown in FIG. 8 described above.

[0123] The single-ended read circuit 401 has, as sense amplifiers SA (second sense amplifiers), sense amplifiers SA410, SA420, SA430, and SA440. The single-ended read circuit 401 further has a switch circuit SW450 (second switch circuit) to which the sense amplifiers SA410, 420, 430, and 440 and the bit lines BL<0>-<11> are connected.

[0124] The sense amplifiers SA410, 420, 430, and 440 are connected to the switch circuit SW450 by a single bit line BLS. The address of the single bit line BLS can be expressed as BLS<n>, where n=0, 1, 2, . . . N. In the example shown in FIG. 10, the single bit line BLS<0> connected to the sense amplifier SA410, the single bit line BLS<1> connected to the sense amplifier SA420, the single bit line BLS<2> connected to the sense amplifier SA430, and the single bit line BLS<3> connected to the sense amplifier SA440 are connected to the switch circuit SW450.

[0125] In addition, in the semiconductor device 400, SRAM bit cells are arranged at positions where two bit lines BL intersect with two word lines WL_L and WL_R. For example, the SRAM 210 is connected to the bit lines BL<0> and BL<1> and the word lines WL_L<0> and WL_R<0>. Similarly, the SRAM 211 is connected to the bit lines BL<2> and BL<3> and the word lines WL_L<1> and WL_R<1>. The SRAM 212 is connected to the bit lines BL<1> and BL<2> and the word lines WL_L<2> and WL_R<2>.

[0126] In the semiconductor device 400, the word lines WL are divided into six types for each address: word line WL_L<0+3x>, word line WL_R<0+3x>, word line WL_L<1+3x>, word line WL_R<1+3x>, word line WL_L<2+3x>, and word line WL_R<2+3x>. Note that x = 0, 1, 2, ..., N. In the semiconductor device 400, the word line WL_L and the word line WL_R are paired in the same SRAM bit cell. Therefore, in the semiconductor device 400, the SRAM bit cells are divided into three groups: group A connected to word lines WL_L<0+3x> and word lines WL_R<0+3x>, group B connected to word lines WL_L<1+3x> and word lines WL_R<1+3x>, and group C connected to word lines WL_L<2+3x> and word lines WL_R<2+3x>.

[0127] 10 , the word line WL_L<0> is exemplified as the word line WL_L<0+3x>, and the word line WL_R<0> is exemplified as the word line WL_R<0+3x>. The word line WL_L<1> is exemplified as the word line WL_L<1+3x>, and the word line WL_R<1> is exemplified as the word line WL_R<1+3x>. The word line WL_L<2> is exemplified as the word line WL_L<2+3x>, and the word line WL_R<3> is exemplified as the word line WL_R<2+3x>. Furthermore, SRAMs 210, 214, 217, and 220 connected to word line WL_L<0> and word line WL_R<0> are group A, SRAMs 211, 215, and 218 connected to word line WL_L<1> and word line WL_R<1> are group B, and SRAMs 212, 216, 219, and 221 connected to word line WL_L<2> and word line WL_R<2> are group C.

[0128] Similar to the semiconductor device of the second embodiment described above, the semiconductor device 400 performs either reading or writing (hereinafter referred to as "read / write") of SRAM bit cells by sense amplifiers SA240, 250, 260, and 270 (hereinafter also referred to as first sense amplifiers SA) using a switch circuit 301. Furthermore, by adding a single-ended read circuit 401 to the semiconductor device 400, it becomes possible for sense amplifiers SA410, 420, 430, and 440 (hereinafter also referred to as second sense amplifiers SA) to read SRAM bit cells different from the SRAM bit cells that are "read / written" by the first sense amplifier SA.

[0129] The circuit logic of the switch circuit SW450 in the single-ended read circuit 401 is shown in FIG. 11. FIG. 11 is a table showing the relationship between the "read / write" and "read" of the bit line BL of the semiconductor device 400 and the ON / OFF of the corresponding word line WL. When performing both "read / write" of one SRAM bit cell and "read" of another SRAM bit cell, the semiconductor device 400 can take any of the states (1) to (6) shown in FIG. 11.

[0130] 11, WL_L<0+3x>, WL_R<0+3x>, WL_L<1+3x>, WL_R<1+3x>, WL_L<2+3x>, and WL_R<2+3x> indicate the state of the word line WL, with "1" indicating the ON state and "0" indicating the OFF state. Also, in FIG. 11, BL<0+3n>, BL<1+3n>, and BL<2+3n> indicate that the SRAM bit cell connected to the bit line BL is in either a "read / write" or "read" state.

[0131] 11, for example, WL_L<0+3x>, WL_R<0+3x>, and WL_L<1+3x> are ON, and WL_R<1+3x>, WL_L<2+3x>, and WL_R<2+3x> are OFF. In this case, the bit lines BL paired with BL<0+3n> and BL<1+3n> are the targets of "read / write" by the first sense amplifier SA. BL<2+3n> is the target of "read" by the single-ended read circuit 401.

[0132] For example, the SRAM 210, SRAM 211, and SRAM 212 shown in FIG. 10 will be described as an example. In the state (1) shown in FIG. 11, WL_L<0+3x>, WL_R<0+3x>, and WL_L<1+3x> are ON, and WL_R<1+3x>, WL_L<2+3x>, and WL_R<2+3x> are OFF. This means that in FIG. 10, word line WL_L<0>, word line WL_R<0>, and word line WL_L<1> are ON. Then, word line WL_R<1>, word line WL_L<2>, and word line WL_R<2> are OFF. That is, this indicates that both the word line WL_L<0> and the word line WL_R<0> to which the SRAM 210 is connected are in the ON state, and that only the word line WL_L<1> to which the SRAM 211 is connected is in the ON state. Also, this indicates that only the word line WL_R<1> to which the SRAM 211 is connected is in the OFF state, and that both the word line WL_L<2> and the word line WL_R<2> to which the SRAM 212 is connected are in the OFF state.

[0133] At this time, the semiconductor device 400 connects the bit line pair of bit line BL<0> and bit line BL<1> of the SRAM 210 to the sense amplifier SA240 by switching the wiring A_WLA using the switch circuit 301, and ``read / write'' of the SRAM 210 is performed.

[0134] Also, in the SRAM 211 at this time, the bit line BL<2> that intersects with the word line WL_L<1> is not connected to the sense amplifier SA240 due to the switching of the switch circuit 301. Therefore, the switch circuit SW450 can connect the bit line BL<2> of the SRAM 211 to the single-ended read circuit 401. Then, the switch circuit SW450 connects the bit line BL<2> of the SRAM 211 to the sense amplifier SA410 via the single bit line BLS<0>. As a result, the sense amplifier SA410 becomes able to "read" the SRAM 211.

[0135] Similarly, in the state (2) shown in Figure 11, WL_L<0+3x>, WL_R<0+3x>, and WL_R<2+3x> are ON, and WL_L<1+3x>, WL_R<1+3x>, and WL_L<2+3x> are OFF. This state indicates that in Figure 10, both the word line WL_L<0> and the word line WL_R<0> to which SRAM 210 is connected are ON, and only one word line WL_R<2> to which SRAM 212 is connected is ON. It also indicates that only one word line WL_L<2> to which SRAM 212 is connected is OFF, and both the word line WL_L<1> and the word line WL_R<1> to which SRAM 213 is connected are OFF.

[0136] 11 , in order to perform "read / write" of the SRAM 210, the pair of word lines WL_L<0> and WL_R<0> of the SRAM 210 are turned ON. Then, by switching the wiring A_WLA by the switch circuit 301, the bit line pair of the bit line BL<0> and the bit line BL<1> of the SRAM 210 is connected to the sense amplifier SA240, and "read / write" of the SRAM 210 is performed.

[0137] 11, in order to "read" the SRAM 212, only one word line WL_R<2> of the SRAM 212 is turned ON. Then, the bit line BL<2> of the SRAM 212 is connected to the sense amplifier SA410 by switching the switch circuit SW450. This makes it possible to "read" the SRAM 212 by the single-ended read circuit 401.

[0138] As described above, in the states (1) and (2) shown in FIG. 11, the word lines WL_L<0+3x> and WL_R<0+3x> are turned ON. Therefore, the word line pair connected to the SRAM bit cells of group A shown in FIG. 10 is turned ON. Then, by switching the wiring A_WLA by the switch circuit 301, the bit line pair of bit lines BL<0+3n> and BL<1+3n> from the SRAM bit cells of group A is connected to the first sense amplifier SA. This enables "reading / writing" of the SRAM bit cells of group A.

[0139] 11, the word line WL_L<1+3x> is turned on. Therefore, only one of the word lines connected to the SRAM bit cells of group B shown in FIG. 10 is turned on. Then, the switch circuit SW450 connects the bit line BL<2+3n> from the SRAM bit cells of group B to the single-ended read circuit 401. This allows the single-ended read circuit 401 to "read" the SRAM bit cells of group B using the bit line BL<2+3n>.

[0140] 11, the word line WL_R<2+3x> is turned on. Therefore, only one of the word lines connected to the SRAM bit cells of group C shown in FIG. 10 is turned on. Then, the switch circuit SW450 connects the bit line BL<2+3n> from the SRAM bit cells of group C to the single-ended read circuit 401. This allows the single-ended read circuit 401 to "read" the SRAM bit cells of group C using the bit line BL<2+3n>.

[0141] Similarly, in states (3) to (6), it is possible to perform "read / write" of one SRAM bit cell and "read" of another SRAM bit cell. In states (3) and (4) shown in FIG. 11, word line WL_L<1+3x> and word line WL_R<1+3x> are turned ON. Therefore, the word line pair connected to the SRAM bit cells of group B shown in FIG. 10 is turned ON. Then, by switching the wiring A_WLB by the switch circuit 301, the bit line pair of bit line BL<0+3n> and bit line BL<2+3n> from the SRAM bit cells of group B is connected to the first sense amplifier SA. This enables "read / write" of the SRAM bit cells of group B. 11, for example, the pair of word lines WL_L<1> and WL_R<1> of the SRAM 211 of group B are turned ON. Then, by switching the wiring A_WLB by the switch circuit 301, the bit line pair of bit lines BL<2> and BL<3> from the SRAM 211 of group B is connected to the sense amplifier SA240. This makes it possible to "read / write" to the SRAM 211 of group B.

[0142] Also, in the state (3) shown in FIG. 11 , the word line WL_L<2+3x> is turned ON. Therefore, only one of the word lines connected to the SRAM bit cells of group C shown in FIG. 10 is turned ON. Then, the switch circuit SW450 connects the bit line BL<1+3n> from the SRAM bit cells of group C to the single-ended read circuit 401. This allows the single-ended read circuit 401 to "read" the SRAM bit cells of group C using the bit line BL<1+3n>. For example, in the state (3) shown in FIG. 11 , the word line WL_L<2> of the SRAM 212 of group C is turned ON. Then, the switch circuit SW450 connects the bit line BL<1> from the SRAM 212 of group C to the single-ended read circuit 401. This allows the single-ended read circuit 401 to "read" the SRAM 212 of group C using the bit line BL<1>.

[0143] 11 , the word line WL_R<0+3x> is turned ON. Therefore, only one of the word lines connected to the SRAM bit cells of group A shown in FIG. 10 is turned ON. Then, the switch circuit SW450 connects the bit line BL<1+3n> from the SRAM bit cells of group A to the single-ended read circuit 401. This allows the single-ended read circuit 401 to "read" the SRAM bit cells of group A using the bit line BL<1+3n>. For example, in the state (4) shown in FIG. 11 , the word line WL_R<0> of the SRAM 210 of group A is turned ON. Then, the switch circuit SW450 connects the bit line BL<1> from the SRAM 210 of group A to the single-ended read circuit 401. This allows the single-ended read circuit 401 to "read" the SRAM 210 of group A using the bit line BL<1>.

[0144] 11, the word line WL_L<2+3x> and the word line WL_R<2+3x> are turned on. Therefore, the word line pair connected to the SRAM bit cells of group C shown in FIG. 10 is turned on. Then, by switching the wiring A_WLC by the switch circuit 301, the bit line pair of bit line BL<1+3n> and bit line BL<2+3n> from the SRAM bit cells of group C is connected to the first sense amplifier SA. This enables "reading / writing" of the SRAM bit cells of group C. For example, in the states (5) and (6) shown in FIG. 11, the pair of word line WL_L<2> and word line WL_R<2> of the SRAM 212 of group C is turned on. Then, by switching the wiring A_WLC by the switch circuit 301, the bit line pair of the bit line BL<1> and the bit line BL<2> from the SRAM 212 of group C is connected to the sense amplifier SA240. This makes it possible to "read / write" to the SRAM 212 of group C.

[0145] 11 , the word line WL_L<0+3x> is turned ON. Therefore, only one of the word lines connected to the SRAM bit cells of group A shown in FIG. 10 is turned ON. Then, the switch circuit SW450 connects the bit line BL<0+3n> from the SRAM bit cells of group A to the single-ended read circuit 401. This allows the single-ended read circuit 401 to "read" the SRAM bit cells of group A using the bit line BL<0+3n>. For example, in the state (5) shown in FIG. 11 , the word line WL_L<0> of the SRAM 210 of group A is turned ON. Then, the switch circuit SW450 connects the bit line BL<0> from the SRAM 210 of group A to the single-ended read circuit 401. This allows the single-ended read circuit 401 to "read" the SRAM 210 of group A using the bit line BL<0>.

[0146] Also, in the state (6) shown in FIG. 11 , the word line WL_R<1+3x> is turned ON. Therefore, only one of the word lines connected to the SRAM bit cells of group B shown in FIG. 10 is turned ON. Then, the switch circuit SW450 connects the bit line BL<0+3n> from the SRAM bit cells of group B to the single-ended read circuit 401. This allows the single-ended read circuit 401 to "read" the SRAM bit cells of group B using the bit line BL<0+3n>. For example, in the state (6) shown in FIG. 11 , the word line WL_R<1> of the SRAM 211 of group B is turned ON. Then, the switch circuit SW450 connects the bit line BL<3> from the SRAM 211 of group B to the single-ended read circuit 401. This allows the single-ended read circuit 401 to "read" the SRAM 211 of group B using the bit line BL<3>.

[0147] In this manner, the semiconductor device 400 turns on the word line WL_L and word line WL_R that form a pair with the SRAM bit cell to be read / written. Then, using the switch circuit 301 and the sense amplifier SA, it performs "reading / writing" on the SRAM bit cell to be read / written. Furthermore, the semiconductor device 400 turns on the word line WL_L or word line WL_R of another SRAM bit cell to be read. Then, the single-ended read circuit 401 connects the bit line BL of the SRAM bit cell to be read to the sense amplifier SA via the single bit line BLS, and performs "reading" on the SRAM bit cell to be read. As a result, the semiconductor device 400 not only performs "reading / writing" on the specified SRAM bit cell like the semiconductor device in the second embodiment, but also simultaneously performs "reading" on other SRAM bit cells using the single-ended read circuit.

[0148] The present invention is not limited to the configurations described in the above-described embodiments, and various modifications and changes are possible without departing from the scope of the present invention.

[0149] 100, 210, 211, 212, 213, 214, 215, 216, 217, 218, 219, 220, 221 SRAM, 101, 102, 103, 108, 201, 223, 225 Gate metal, 104, 105, 106, 107, 140, 141, 142, 143, 144, 145, 203, 205, 207, 209, 231, 233, 235, 237, 239 Contact metal, 110 Insulating layer, 111, 112, 113, 114, 115, 116, 117, 118, 119, 129 Transistor layers, 120, 121, 122, 123, 124, 125, 126, 127, 130, 131, 132, 133, 134, 135, 136, 137, 151, 152, 153, 161, 162, 163 Semiconductor layers, 171, 172, 173, 174, 175, 176, 177, 178, 195, 202, 204, 206, 208, 222, 224, 226, 227, 228, 230, 232, 234, 236, 238 Contacts, 191, 192, 193, 194 Wiring, 200, 300, 400 Semiconductor device, 240, 250, 260, 270, 410, 420, 430, 440 Sense amplifier SA, 241, 242, 243, 244, 245, 246, 251, 252, 253, 254, 255, 256, 261 Transistor, 301, SW450 Switch circuit, 401 Single-ended read circuit, BL0, BL1, BL2, BL3 Bit lines, WL181, WL182, WL183, WL184, WL185, WL186, WL187 Word lines

Claims

1. A semiconductor device in which a first transistor layer on which a plurality of nanosheet transistors are formed and a second transistor layer on which a plurality of nanosheet transistors are formed are stacked, comprising: a first gate metal, a second gate metal, and a third gate metal formed in common to the first transistor layer and the second transistor layer; a first nanosheet transistor having the first gate metal and formed in the first transistor layer; a second nanosheet transistor having the third gate metal and formed in the first transistor layer; a third nanosheet transistor having the third gate metal and formed in the second transistor layer; a first contact metal connected to the second gate metal and the source and drain of the third nanosheet transistor; and a second contact metal arranged between the first nanosheet transistor and the second nanosheet transistor, and connected to the source and drain of the first nanosheet transistor and the source and drain of the second nanosheet transistor. a first contact metal formed on a surface of the second transistor layer opposite to the first transistor layer, and a second contact metal formed on a surface of the first transistor layer opposite to the second transistor layer.

2. The semiconductor device according to claim 1, comprising: a third transistor layer formed parallel to the row direction of the first transistor layer and having a plurality of nanosheet transistors formed thereon; and a fourth transistor layer formed parallel to the row direction of the first transistor layer and having a plurality of nanosheet transistors formed thereon; the third transistor layer and the fourth transistor layer are stacked; and the second gate metal and the third gate metal are formed continuously on the first transistor layer, the second transistor layer, the third transistor layer, and the fourth transistor layer.

3. The semiconductor device described in claim 2, comprising: a fourth gate metal adjacent to the third gate metal and formed commonly to the third transistor layer and the fourth transistor layer; a fourth nanosheet transistor formed in the third transistor layer having the fourth gate metal; a fifth nanosheet transistor formed in the third transistor layer having the second gate metal; a sixth nanosheet transistor formed in the fourth transistor layer having the second gate metal; a third contact metal connected to the third gate metal and the source and drain of the sixth nanosheet transistor; and a fourth contact metal connected to the third gate metal arranged between the fourth nanosheet transistor and the fifth nanosheet transistor, the source and drain of the fourth nanosheet transistor, and the source and drain of the fifth nanosheet transistor, wherein the third contact metal is formed on the surface of the fourth transistor layer opposite the third transistor layer, and the fourth contact metal is formed on the surface of the third transistor layer opposite the fourth transistor layer.

4. The semiconductor device described in claim 3, wherein in the first transistor layer, the second transistor layer, the third transistor layer, and the fourth transistor layer, a bit cell of a semiconductor element is formed, consisting of: the first gate metal of the first nanosheet transistor and the fourth gate metal of the fourth nanosheet transistor connected to a word line; the source and drain of the first nanosheet transistor connected to a first bit line; the source and drain of the fourth nanosheet transistor connected to a second bit line; the source and drain of the second nanosheet transistor and the fifth nanosheet transistor connected to a power supply voltage; and the source and drain of the third nanosheet transistor and the sixth nanosheet transistor connected to a reference potential.

5. The semiconductor device according to claim 4, comprising: a fifth transistor layer formed parallel to the row direction with the third transistor layer and having a plurality of nanosheet transistors formed thereon; a sixth transistor layer formed parallel to the row direction with the fourth transistor layer and having a plurality of nanosheet transistors formed thereon; a seventh transistor layer formed parallel to the row direction with the fifth transistor layer and having a plurality of nanosheet transistors formed thereon; and an eighth transistor layer formed parallel to the row direction with the sixth transistor layer and having a plurality of nanosheet transistors formed thereon, wherein the fifth transistor layer and the sixth transistor layer are stacked, and the seventh transistor layer and the eighth transistor layer are stacked.

6. The semiconductor device according to claim 5, comprising: a first bit cell formed in the first transistor layer, the second transistor layer, the third transistor layer, and the fourth transistor layer; a second bit cell formed in the fifth transistor layer, the sixth transistor layer, the seventh transistor layer, and the eighth transistor layer; and a third bit cell formed in the third transistor layer, the fourth transistor layer, the fifth transistor layer, and the sixth transistor layer.

7. The semiconductor device described in claim 6, wherein in the third transistor layer, the first bit cell and the third bit cell share the source and drain of the nanosheet transistor and a fifth contact metal where the source and drain connect to a bit line; in the fifth transistor layer, the second bit cell and the third bit cell share the source and drain of the nanosheet transistor and a sixth contact metal where the source and drain connect to a power supply voltage; and in the sixth transistor layer, the second bit cell and the third bit cell share the source and drain of the nanosheet transistor and a seventh contact metal where the source and drain connect to a reference potential.

8. A semiconductor device having a plurality of bit cells arranged at intersections of bit lines BL<0+3n>, bit lines BL<1+3n>, and bit lines BL<2+3n> [n=0, 1, 2, ..., N] and word lines WL<0+3x>, word lines WL<1+3x>, and word lines WL<2+3x> [x=0, 1, 2, ..., N], comprising: first bit cells connected to the bit lines BL<0+3n>, bit lines BL<1+3n>, and word lines WL<0+3x>; second bit cells connected to the bit lines BL<2+3n>, bit lines BL<0+3n>, and word lines WL<1+3x>; a third bit cell connected to the bit line BL<1+3n>, the bit line BL<2+3n>, and the word line WL<2+3x>; and a first switch circuit connecting the bit line BL<0+3n>, the bit line BL<1+3n>, and the bit line BL<2+3n> to either a first bit line BLT<n> or a second bit line BLB<n> of a first sense amplifier, wherein the first switch circuit connects the bit line BL<0+3n> to the first bit line BLT<n> and connects the bit line BL<1+3n> to the second bit line BLB<n> when the word line WL<0+3x> is in an ON state; A semiconductor device in which, when the word line WL<1+3x> is in an ON state, the bit line BL<2+3n> is connected to the first bit line BLT<n> and the bit line BL<0+3n> is connected to the second bit line BLB<n-1>, and when the word line WL<2+3x> is in an ON state, the bit line BL<1+3n> is connected to the first bit line BLT<n> and the bit line BL<2+3n> is connected to the second bit line BLB<n>.

9. A single-ended read circuit connected to the bit lines BL<0+3n>, the bit lines BL<1+3n>, and the bit lines BL<2+3n> on the opposite side to the first sense amplifier, comprising: a word line WL_L<0+3x> and a word line WL_R<0+3x> as the word lines WL<0+3x>; a word line WL_L<1+3x> and a word line WL_R<1+3x> as the word lines WL<1+3x>; and a word line WL_L<2+3x> and a word line WL_R<2+3x> as the word lines WL<2+3x>, wherein the single-ended read circuit comprises: a second sense amplifier; a second switch circuit that connects any one of the bit line BL<0+3n>, the bit line BL<1+3n>, and the bit line BL<2+3n> to the bit line BLS<n> of the second sense amplifier, wherein the second switch circuit connects the bit line BL<2+3n> to the bit line BLS<n> when the word line WL_L<0+3x>, the word line WL_R<0+3x>, and the word line WL_L<1+3x> are in an ON state, and connects the bit line BL<2+3n> to the bit line BLS<n> when the word line WL_L<0+3x>, the word line WL_R<0+3x>, and the word line WL_R<2+3x> are in an ON state, When the word line WL_L<1+3x>, the word line WL_R<1+3x>, and the word line WL_R<0+3x> are in an ON state, the bit line BL<1+3n> is connected to the bit line BLS<n>; when the word line WL_L<1+3x>, the word line WL_R<1+3x>, and the word line WL_L<2+3x> are in an ON state, the bit line BL<1+3n> is connected to the bit line BLS<n>; when the word line WL_L<2+3x>, the word line WL_R<2+3x>, and the word line WL_L<0+3x> are in an ON state, the bit line BL<2+3n> is connected to the bit line BLS<n>; 9. The semiconductor device according to claim 8, wherein when the word line WL_L<2+3x>, the word line WL_R<2+3x>, and the word line WL_R<1+3x> are in an ON state, the bit line BL<2+3n> is connected to the bit line BLS<n>.

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