MOS switch having extended range of operation

Abstract

Methods and apparatus for an analog switch system that includes nodes for positive and negative supply voltage and input and output signals for the switched signal. A MOS switch has a gate, a source, and a drain, a channel, and a gate-to-channel capacitance. A switch control circuit is coupled to the MOS switch, wherein the switch control circuit includes a gate driver circuit configured to control a gate-to-source voltage on the MOS switch to maintain a constant on-resistance while a peak of the input signal generates a gate voltage on the MOS switch above or below an operating level.

Description

[0001]Attorney Docket No. THAT-063AWO MOS SWITCH HAVING EXTENDED RANGE OF OPERATION CROSS REFERENCE TO RELATED APPLICATIONS The present application claims the benefit of U.S. Provisional Application No.63 / 675,334, filed on July 25, 2024, which is incorporated herein by reference. BACKGROUND FIG.1 shows a prior art gate drive circuit to turn a NMOS switch 100 by applying a voltage higher than the NMOS threshold voltage between the NMOS gate and source by the gate drive 104 while gate drive to the nega^ve power supply 105 is disconnected. To turn the switch off, zero volts or a nega^ve voltage is applied between the NMOS gate and source terminals by the gate drive 105 while gate drive 104 to the posi^ve power supply is disconnected. Likewise, an analog switch 100 can be implemented with a PMOS transistor and the switch can be similarly explained only by reversing the polari^es. The switch can drive an external load 101. An external switch control 102 can be coupled to the gate drive circuit 104, 105. A common implementa^on of a gate drive circuit 104 or 105 connects the analog switch 100 gate terminal to one or the other power supplies. This method is limited by a few factors: power supply voltage, voltage swing at the switch terminals (source and drain), and the oxide breakdown voltage between gate and all other terminals. For integrated high voltage MOS transistors, the breakdown voltage between the gate and source or bulk terminals is o^en much less than the breakdown voltage between the drain and source or between the drain and the bulk terminals. Thus, using this gate drive approach, MOS analog switches constructed in this type of semiconductor processes cannot take advantage of the full signal swing capability suggested by the maximum drain-source voltage. To overcome the limitation of low MOS gate to source breakdown voltage, another prior art gate drive solution is voltage sensing gate drive disclosed in U.S. Patent No.8,610,469, Attorney Docket No. THAT-063AWO which is incorporated herein by reference, entitled “Dynamic switch driver for low- distortion programmable-gain amplifier,” a portion of which is shown in FIG.2. This technique ensures that the analog switch gate source voltage is kept either constant or to not exceed the maximum breakdown voltages. When the switch is on, a floating voltage source 203 is applied between gate and source terminals of the analog switch 200 through the gate drive block 204. The external signal voltage 210 at the source terminal X is sensed. A replica of the terminal voltage is buffered 202 and it is added to the floating gate source voltage 203 such that the gate source voltage is never exceeded beyond its maximum specification. To keep the MOS switch off, a similar circuit 205 enables another voltage source which applies a reversed gate source polarity through the gate drive block 204 to maintain the MOS switches in off state. The off-state voltage source is also floating. The MOS terminal sensing circuits 201202205 drive the off-state voltage source to maintain the off state regardless of the input voltages. The maximum gate voltage swing is limited by the power supply. For an NMOS switch in on state, the gate has to be at a more posi^ve poten^al than the source. When the input voltage at X terminal swings posi^ve, the analog switch gate voltage is the sum of the input voltage plus the addi^onalfloa^ng offset voltage source 203. The maximum gate voltage, at the switch gate drive 204 output, cannot be higher than the posi^ve power supply. Therefore, in the best case, the maximum input amplitude is the power supply minus the gate source threshold voltage. In reality, other circuits between the analog switch gate terminal and the posi^ve power supply can even further limit the maximum input voltage. For high voltage MOS switch transistors, the maximum input peak amplitude is o^en several volts below the power supply voltage. A similar logic thread can be made for the PMOS switching transistors and the minimum input voltage swing compared to the most nega^ve power supply rail. Therefore, for a PMOS switch, the minimum signal amplitude is typically several volts above the minimum power supply voltage. Attorney Docket No. THAT-063AWO On known solution to overcoming the limitations on the conventional operating range is to use an analog switch made of an NMOS and PMOS transistor in parallel. This circuit is also known as a transmission gate. While this solution extends the conventional operating range closer to the power supply rails, the silicon area and dissipated power required to implement it almost double. In high voltage applications, the low on-resistance transistors are large and doubling the area could be price and packaging prohibitive. The doubling of the power dissipation has a negative effect in battery powered applications. SUMMARY Example embodiments of the disclosure provide methods and apparatus for providing a gate-drive circuit which allows the analog switch gate to source voltage to stay rela^vely constant while keeping the MOS transistor(s) on for input ac signal voltage peaks closer to the power supply rails. When describing example embodiments of the disclosure, we shall refer to the range of ac signal voltages applied to an analog switch, a range where the maximum and minimum are within the available power supply voltages, as the “conven^onal opera^ng range.” It will be readily appreciated that an advantage of voltage sensing gate drive is the constant gate to source switch voltage, which makes the switch on-resistance substan^ally independent of the input voltage swings. Example embodiments of the disclosure allow the voltage sensing gate drive to go above the maximum power supply or below the minimum power supply increasing up to the maximum and minimum input signal peaks for which the switch gate to source voltage to remain constant. A constant on-resistance reduces the nonlineari^es and distor^on at the switch output terminal. In one aspect, an analog switch system comprises: a first node for a positive voltage supply signal; a second node for a negative voltage supply signal; an input terminal to receive an input signal and an output terminal to output an output signal; a MOS switch having a gate, a source, Attorney Docket No. THAT-063AWO and a drain, a channel, and a gate-to-channel capacitance, wherein the MOS switch is configured to turn the input signal on and off; a switch control circuit coupled to the MOS switch, wherein the switch control circuit includes a gate driver circuit configured to control a gate-to-source voltage on the MOS switch to maintain a constant on-resistance while a peak of the input signal generates a gate voltage on the MOS switch above or below the respective positive or negative voltage supply signal. A system can further include one or more of the following features: the switch control circuit includes an averaging circuit to average the input and output signals, the MOS switch comprises first and second transistors coupled end to end and the averaging circuit comprises a node between the first and second transistors, the switch control circuit includes a comparator circuit having an input coupled to an output of the averaging circuit and an output coupled to the gate drive circuit, the MOS switch and the gate control circuit are configured such that a charge on the gate-to-channel capacitance holds a voltage on the gate-to-source of the MOS transistor during the signal peaks above the operating level, the MOS switch remains on during the signal peaks due to the charge on the gate-to-channel capacitance applying a voltage on the gate of the MOS switch that is above the positive voltage supply signal, and / or the switch gate drive circuit is configured to maintain a high impedance state during the signal peaks for the input signal above the operating level. In another aspect, a method comprises: providing a first node for a positive voltage supply signal and a second node for a negative voltage supply signal; employing an input terminal to receive an input signal and an output terminal to output an output signal for an analog switch; employing a MOS switch having a gate, a source, and a drain, a channel, and a gate-to-channel capacitance, wherein the MOS switch is configured to turn the input signal on and off; employing a switch control circuit coupled to the MOS switch, wherein the switch control circuit includes a gate driver circuit configured to control a gate-to-source voltage on the MOS switch to maintain a constant on-resistance while a peak of the input signal generates a gate voltage on the MOS switch above or below the respective positive or negative voltage supply signal. Attorney Docket No. THAT-063AWO A method can further include one or more of the following features: the switch control circuit includes an averaging circuit to average the input and output signals, the MOS switch comprises first and second transistors coupled end to end and the averaging circuit comprises a node between the first and second transistors, the switch control circuit includes a comparator circuit having an input coupled to an output of the averaging circuit and an output coupled to the gate drive circuit, the MOS switch and the gate control circuit are configured such that a charge on the gate-to-channel capacitance holds a voltage on the gate-to-source of the MOS transistor during the signal peaks above the operating level, the MOS switch remains on during the signal peaks due to the charge on the gate-to-channel capacitance applying a voltage on the gate of the MOS switch that is above the positive voltage supply signal, and / or the switch gate drive circuit is configured to maintain a high impedance state during the signal peaks for the input signal above the operating level. In another aspect, an analog switch system comprises: a first node for a first voltage supply signal; a second node for a second voltage supply signal; an input terminal to receive an input signal and an output terminal to output an output signal; a bipolar MOS switch comprising first and second transistors each having a respective gate, source, and drain, channel, and a gate-to- channel capacitance, wherein the gates of the first and second transistors are connected together, wherein the MOS transistor is configured to turn the input signal on and off; and a switch control circuit coupled to the MOS switch, wherein the switch control circuit comprises: third, fourth and fifth transistors coupled end-to-end; a voltage controlled current source coupled to the first node; a first diode coupled between the voltage controlled current source and the third transistor; and a second diode coupled between the fifth transistor and the second node, wherein the node between the first and second transistors comprises an averaging circuit for the input and output signals, wherein a gate of the fifth transistor is coupled to a node between the first and second transistors, wherein the gates of the first and second transistor are coupled to a terminal of the third transistor, and wherein a charge on a gate to channel capacitance of the first and second transistors maintains the first and second transistors in the on state while the first diode is off during peaks of the input signal that allow a voltage on the gates of the first and second transistors to exceed the first voltage supply signal. Attorney Docket No. THAT-063AWO In another aspect, a method for processing a signal with an analog switch comprises: employing a first node for a first voltage supply signal and a second node for a second voltage supply signal; employing an input terminal to receive an input signal and an output terminal to output an output signal; employing a bipolar MOS switch comprising first and second transistors each having a respective gate, source, and drain, channel, and a gate-to-channel capacitance, wherein the gates of the first and second transistors are connected together, wherein the MOS transistor is configured to turn the input signal on and off; and employing a switch control circuit coupled to the MOS switch, wherein the switch control circuit comprises: third, fourth and fifth transistors coupled end-to-end; a voltage controlled current source coupled to the first node; a first diode coupled between the voltage controlled current source and the third transistor; and a second diode coupled between the fifth transistor and the second node, wherein the node between the first and second transistors comprises an averaging circuit for the input and output signals, wherein a gate of the fifth transistor is coupled to a node between the first and second transistors, wherein the gates of the first and second transistor are coupled to a terminal of the third transistor, and wherein a charge on a gate to channel capacitance of the first and second transistors maintains the first and second transistors in the on state while the first diode is off during peaks of the input signal that allow a voltage on the gates of the first and second transistors to exceed the first voltage supply signal. BRIEF DESCRIPTION OF THE DRAWINGS The foregoing features of this disclosure, as well as the disclosure itself, may be more fully understood from the following descrip^on of the drawings in which: FIG.1 is a general block of a commonly used prior art gate drive for an analog switch. FIG.2 is a general block of a prior art voltage sensing gate drive for an analog switch. FIG.3 is a high level block diagram of a MOS analog switch control in accordance with example embodiments of the disclosure; Attorney Docket No. THAT-063AWO FIG.4 is representa^on of a NMOS transistor in a cross sec^on and from the top in accordance with example embodiments of the disclosure; FIG.5 is a representa^on of various MOS analog switches in accordance with example embodiments of the disclosure; FIG.6 is a more detailed block diagram implementa^on of a gate-drive circuit in accordance with example embodiments of the disclosure; FIG.7 is detailed circuit of the block diagram in FIG.6 for NMOS bipolar switch in accordance with example embodiments of the disclosure; FIG.8 is detailed circuit of the block diagram in FIG.6 for PMOS bipolar switch in accordance with example embodiments of the disclosure; FIG.9 shows simulated behavior of the gate drive above the minimum design frequency in accordance with example embodiments of the disclosure; and FIG.10 shows simulated behavior of the gate drive below the minimum design frequency in accordance with example embodiments of the disclosure. DETAILED DESCRIPTION FIG.3 shows an example embodiment of an analog switch circuit having enhanced linear opera^on in accordance with example embodiments of the disclosure. The circuit includes at least one Metal Oxide Semiconductor (MOS) device 310 to turn on and off the signal path between an input X and an output Y. The analog switch 310 can control on or off dc (^me-invariant) and ac (^me-variant) input signals 312 at input node X. The switch output Y is connected to an external load 313. A gate driver circuit 311 translates a control input signal, which can be a digitalfixed logic level or an arbitrary voltage or Attorney Docket No. THAT-063AWO current, to a desired gate to source voltage Vgs that will maintain the MOS device 310 in the on or off state over the en^re opera^ng voltage range of the signal being switched. The gate driver circuit 311 output is capable of high impedance state. An averaging circuit 315 monitors the average of the switch input and output terminals X and Y. The switch terminals average voltage Vavg is output from the averaging circuit 315 to the analog switch gate drive circuit 311 which outputs a constant gate to source voltage Vgs for the analog switch 310. A constant gate to source voltage Vgs inside the analog switch 310 significantly reduces on-resistance non-lineari^es while maintaining the analog switch 310 on-resistance substan^ally steady. In example embodiment, a comparator circuit 318, 319 compares the average voltage Vavg to a replica of the posi^ve and nega^ve power supplies. Each of the comparators 318, 319 has a respec^ve input that is one of the power supplies with a dc offset 320, 321. For signals below the posi^ve power supply voltage replica and above the nega^ve power supply voltage replica, both comparator 318, 319 outputs are in ON state. In the illustrated embodiment, the comparator 318, 319 outputs are input to an AND logic gate 316. The output of AND logic gate 316 and an external switch control 314 are fed to AND logic gate 317 the output of which is an input to the switch gate drive circuit 311. For low on-resistance applica^ons, the analog switch 310 comprises at least one large MOS device to minimize the on-resistance between X and Y switch terminals. All large MOS transistors have substan^al gate to channel capacitance Cgs. This capacitance, if appropriately charged, can maintain the MOS switch 310 in the on state. As described more fully below, example embodiments of the disclosure exploit this large switch gate to channel capacitance and the source ^me-variant nature of the source to allow the analog switch 310 to maintain low on-resistance during signal peaks which are close to or at the power supply levels. Referring now to FIG.4, it is useful to observe that the equivalent circuit of a MOS Attorney Docket No. THAT-063AWO transistor between gate and all other terminals, especially the source terminal, is a capacitor or a combination of capacitors. When voltage is applied across the capacitor terminals, charge is stored on both capacitor plates. One plate is the gate conductive material, typically conductive polysilicon, and the other plate is the top of the transistor channel under the gate silicon oxide. The gate to channel capacitance is a function of MOS transistor operating region. In an analog switch application, the voltage between the drain and the source is very low such that it is much smaller than the effective voltage. The effective voltage is defined as the difference between the actual gate to source voltage and the MOS transistor threshold voltage. VDS<< VGS- VtUnder these condi^ons, the MOS transistor operates in the triode, also known as linear, region. In the triode mode the channel is not pinched. The capacitance between the gate and channel can be expressed as two capacitors from gate to source and drain, respec^vely, as follows (see, e.g., P. Gray, P. Hurst, S. Lewis, R. Meyer, Analysis and Design of Analog Integrated Circuits, 5thedi^on, page 51): ^ ^^^^^ ^^ = ^^^ =where Cgs is the capacitance Cgd is the capacitance form gate to drain, Cox is the gate to channel capacitance per unit area, W is the gate width and L is the gate length. In triode region, the channel under the gate is uniform and the two capacitances are equal. An addi^onal capacitance is formed by the overlap of the gate to source and gate to drain regions. This is called the overlap capacitance Cov. The value of the overlap capacitance Cov is calculated as follows [P. Gray, P. Hurst, S. Lewis, R. Meyer, Analysis and Design of Analog Integrated Circuits, 5thedi^on, page 142]: Cov = Cox WLd where Ld is the length of the overlap region between the gate and the source and / or drain diffusion. The total value of the gate to channel capacitance can be expressed as follows: CT= Cgs + Cgd + 2Cov Attorney Docket No. THAT-063AWO A charged capacitor acts like a small ba^ery. The capacitor maintains its charge, and therefore the voltage across, as long as there is no path to remove the stored charges. The MOS switches are rela^vely large-area transistors in low on-resistance applica^ons. Since the parasi^c capacitance between the gate terminal and channel is propor^onal to the transistor area, the gate to channel capacitance of low on-resistance MOS transistors is o^en on the order of several picofarads. For ^me-varying input signals, such as audio signals, a signal-dependent varia^on of the gate to source voltage, results in changes of the MOS switch on-resistance, and thus, nonlinear varia^on of the load volt. The voltage sensing gate to source circuit maintains a constant gate to source voltage which makes the switch on resistance constant except for input signal peaks which are beyond the conven^onal opera^ng range. In example embodiments of the disclosure, a circuit provides gate to source voltage circuitry which maintains substantially constant switch on-resistance for input signal peaks which are beyond the switch’s conventional operating range. The duration of such peaks is typically very short, fractions of the ac signal period, and the charged gate to channel capacitance can hold the gate to source voltage steady for this short period of ^me. During input signal voltage peaks beyond the conven^onal opera^ng range, circuity can maintain a high impedance state to minimize leakage of the charged gate to channel capacitance. Although the gate to source voltage circuitry is in high impedance state, the impedance isfinite and there is a small leakage current discharging the gate to channel capacitor. However, this technique can be made to work down to very low frequencies. The charge Q stored in the MOS transistor gate to channel capacitor is dependent on two factors: Q = C ^ V C is the gate to channel capacitance and V is the voltage across it. Attorney Docket No. THAT-063AWO The charge accumulated in the MOS gate parasi^c capacitors can leak through the gate oxide or external circuitry. The preferred gate drive is the voltage sensing circuit. In this case, the MOS transistor parasi^c capacitance can discharge through the voltage source between the gate and source or through the circuits connected to the power supplies. The gate to channel capacitance is propor^onal to channel area. The gate to source bias voltage is the other factor determining the parasi^c capacitor charge. The channel area is calculated, to afirst approxima^on, by mul^plying the MOS transistor width, W, by the length, L, dimensions as defined in FIG.4. For low on-resistance applica^ons, the channel length is o^en chosen to be the minimum allowed by the semiconductor process. The transistor width is varied to obtain the desired on-resistance. The amount of gate charge can be varied by the transistor width, thus the gate to channel capacitance, and the gate to source voltage. The transistor width is limited by factors such as prac^cal die area and switch speed. The gate to source voltage is limited by the maximum allowed in the process over the required opera^ng temperature range. At very low frequencies, if the signal exceeds the conven^onal opera^ng range for a long enough ^me, leakage currents will reduce the charge stored in the transistor gate to channel capacitance. This will result in the on-resistance varying over ^me and thus, on- resistance nonlinearity will result. Switch nonlinearity translates into signal distor^on as measured on the output load. Depending on the applica^on, the transistor size and bias can be chosen based on the required minimum low frequency performance, distor^on and / or nonlinearity. The MOS analog switch can be unipolar or bipolar. Unipolar is appropriate for an external dc input voltage of known polarity. For ac signals, the input voltage polarity changes and a bipolar switch is required. Attorney Docket No. THAT-063AWO FIG.5 shows an analog MOS device 500 having an input X and an output Y, which is coupled to an external load. A gate drive circuit 504 is coupled to the MOS switch 500. A switch control 503 having on and off states is coupled to the gate drive circuit 504. In the illustrated embodiment, the MOS switch 500 is shown as a bipolar NMOS device. As shown, the switch can be provided a PMOS bipolar device 510, a unipolar NMOS device 520, or a unipolar PMOS device 530. It is understood that the single NMOS transistor 520 requires that the external voltage source 502 is always more posi^ve at terminal X compared to terminal Y. Also, the gate drive circuit 504 has to be posi^ve and higher than the voltage at terminal Y plus the NMOS threshold voltage, (VY + Vtn). The requirements for the PMOS switch 530 are the opposite polarity of the NMOS analog switch 520. The bipolar NMOS switch 500 comprises two NMOS transistors in series. The two transistors are in on state as long as the gate drive 504 output is more positive than either voltage at terminal X or terminal Y. A more positive gate voltage maintains the channel inversion in the NMOS transistors. The requirements for the bipolar PMOS switch 510 are the opposite polarity of the bipolar NMOS analog switch 520. It is understood that the term “MOS switch” can refer to unipolar and bipolar configurations. That is, “MOS switch” can include more than one transistor. FIG.6 shows an example implementation of the block diagram of the gate-drive circuit 300 of FIG.3, which allows the analog switch gate to source voltage to stay relatively constant while keeping the MOS transistor(s) on for input ac signal voltage peaks closer to the power supply rails. First and second unidirectional blocks 602, 604 are added in series with circuits to the positive 601 and / or negative 605 power supplies. The first unidirectional block 602 connected to the positive power supply allows connection of the circuit connected to the positive power supply 601 only when the MOS transistor gate voltage Vg is below or close to the positive power supply voltage. Similarly, the second unidirectional block 604 to the negative 605 power supply allows connection of the circuit connected to the negative power supply, only when the MOS transistor gate voltage is above or close to the power Attorney Docket No. THAT-063AWO supply voltage. When the gate voltage is pushed beyond the conven^onal opera^ng range, the unidirec^onal block(s) 602, 604 disconnect an amplifier 603 power source from the circuits 601, 605 to the power supplies. The amplifier 603 output switches to a high impedance state allowing the charged gate to channel capacitor in the analog MOS switch (not shown) tofloat. The gate to source poten^al keeps the MOS switch on. FIG.7 shows an example implementa^on of the circuit of FIG.6 with NMOS transistors M3 and M4 forming the bipolar MOS analog switch 700 for input X and output Y. Diode- connected transistors M0 and M1 form the voltage source between the switch 700 gate and source. When currentflows from drain to source in transistors M0 and M1, voltage is developed across the gate to source terminals of the two transistors connected as diodes. In the illustrated embodiment, transistor M2 comprises a switch terminal sensing circuit. The average voltage between the switch terminals X and Y, is applied at the gate of M2. The output of the sensing circuit, formed by transistor M2, is the source of M2. The output, the source of M2, has a posi^ve one Vgs dc offset compared to the average voltage at the switch terminals, X and Y. Therefore, the total gate to source voltage Vgs present at the MOS switches, M3 and M4, is the sum of the gate to source voltages Vgs of M0, M1 and M2. The Vgs voltages are controlled by the current supplied from a voltage controlled current source (VCCC) G0 and M0-M1 geometry features, such as channel width and length. The unidirec^onal block to the posi^ve power supply is implemented by the diode D0and to the nega^ve power supply by the diode D1. When the M3-M4 gate voltage is higher than the posi^ve power supply voltage minus the minimum voltage across VCCC G0, diode D0turns off and isolates M3-M4 gates from VCCC G0. Similarly, when the M3-M4 gate voltage is lower than the nega^ve power supply, D1turns off and isolates transistors M0, M1 and M2 from reversed current through their body diodes. Attorney Docket No. THAT-063AWO When diodes D1 or D0 turn off, there is no currentflowing in transistors M0, M1 and M2. Therefore, transistors M0, M1 and M2 are in a high impedance state. The charge accumulated in the gate to channel capacitances of transistors M3-M4, theore^cally has nowhere to discharge other than through the low andfinite reverse leakage currents of D1 and / or D0. FIG.8 shows an example PMOS implementa^on of FIG.7 in which the NMOS transistors are replaced with PMOS transistors and the PMOS transistors by NMOS transistors. As will be readily apparent to those skilled in the art, the two switches in FIG.s 7 and 8 can be combined in a complementary switch u^lizing both N and P MOS devices. The increase in allowable input voltage swing above the conven^onal opera^ng range at the switch input terminal, X or Y, as shown in the embodiments FIG.7 and FIG.8, is about 1V. The increase is not dependent on the power supply voltage. Therefore, the percentage gain benefit is higher for lower power supply voltages. FIGs.9 and 10 shows example performance characteris^cs for the circuit of FIG.7. The power supply voltages Vpos and Vneg are +15V and -15V, respec^vely. On the nega^ve input voltage swing, the average voltage between the switch terminals X and Y, can reach the nega^ve power supply, Vneg. The limi^ng factor on the nega^ve swing is the drain to source voltage Vds of M2, which cannot be less than the voltage (Vgs2–Vt2), where Vt2is the PMOS transistor M2 threshold voltage. For a low drain current in transistor M2 (tens of uA), the voltage difference (Vgs2–Vt2) approaches zero volts. If we assume that the turn on voltage of diode D1 and the threshold voltage of transistor M2 are of similar magnitudes, the average voltage between switch terminals X and Y can reach the same magnitude as the nega^ve power supply, Vneg. The positive swing is limited by the gate to source voltage of NMOS transistors M3-M4. Attorney Docket No. THAT-063AWO The voltage at the node Gate is the average voltage between the switch terminals X and Y plus the gate to source voltage of transistors M3-M4. Typically, the gate to source voltage of transistors M3-M4 is several volts. If diode D0 in FIG.7 is ignored for now, the maximum average voltage at the switch terminals X and Y cannot be higher than (Vpos – VG0 – Vgs3-4), where VG0 is the minimum allowed voltage across current source G0. The typical minimum voltage for VG0 is about 0.5V and for Vgs3-4 about 3V. It makes the maximum positive input voltage swing, before the switch M3-M4 on-resistance starts to vary in value because of gate to source changing voltage, about 3.5V below the positive supply voltage, Vpos. This limitation is especially important when the power supplies are low, such as +5V and -5V, respectively. Diode D0 in series with the VCCC G0, is on when the input voltage is within the conventional operating range. The turn on voltage of diode D0 is about 0.5V. Typically, the current source G0 is made of two PMOS transistor in series, also known as cascade. The minimum voltage across a PMOS cascode circuit is about 0.5V. Therefore, when the average voltage at switch terminals X and Y is such that the voltage at node Gate is higher than the positive power supply minus ~1V, diode D0turns off and there is no more current flowing in transistors M0, M1 and M2. These transistors turn off and they present high impedance. However, the gate to source voltage of M3-M4 is stored in the gate to channel capacitance of M3-M4. This capacitance can hold the charge and bias the M3-M4 gate to source to remain on during the peaks when the average voltage at switch terminals X and Y is high enough such that diode D0 turns off. In FIG.9, the input voltage waveform frequency is 20Hz, which is generally considered the lowest frequency for an audio system. In this case, the charge on the MOS switch gate to channel capacitance does not have enough time to dissipate and the switch can stay on allowing the signal to reach 14.3V, or just 0.7V below the power supply voltage. During the peak transitions when D0 turns off, the gate voltage of transistors M3-M4 can surpass the power supply voltage because the node is now floating and driven by the M3-M4 source voltage plus their gate to voltage stored in the gate to channel Attorney Docket No. THAT-063AWO capacitance. When the charge stored in the gate to channel capacitance starts to dissipate due external leakage mechanisms inD0, M3-M4 gate to channel oxide and M0- M2 transistors, the M3-M4 gate to source voltage starts to diminish. However, for frequencies above the minimum input frequency, in this particular case 20Hz, the M3- M4 gate to source voltage remains high enough to keep the M3-M4 in the triode or linear region and maintaining proper operation of the switch and the input and output waveforms are indistinguishable. FIG.10 shows the behavior of the circuit in FIG.7 when a very low frequency, lower than 20Hz is applied. In this par^cular case a 0.02 Hz, with a period of 50s, sinusoidal input voltage is applied. When diode D0 turns off, the charge stored in the MOS gate to channel capacitance dissipates faster, through leakage, than the ^me input signal is outside the maximum opera^ng range and the switch resistance is increased such that the output clips at 13.3V or 1.7V below the posi^ve supply voltage of +15V. The charge stored in the gate to channel capacitance being quickly dissipated in a few milliseconds, the gate voltage is clipped below the posi^ve power supply voltage and the output voltage is clipped as well due to increased switch on-resistance. Having described preferred embodiments, it will now become apparent to one of ordinary skill in the art that other embodiments incorporate their concepts may be used. Elements of different embodiments described herein may be combined to form other embodiments not specifically set forth above. Various elements, which are described in the context of a single embodiment, may also be provided separately or in any suitable sub combina^on. Other embodiments not specifically described herein are also within the scope of the following claims. All references cited herein are hereby incorporated herein by reference in their en^rety. Attorney Docket No. THAT-063AWO It is felt therefore that these embodiments should not be limited to disclosed embodiments, but rather should be limited only by the spirit and scope of the appended claims. What is claimed is:

Claims

Attorney Docket No. THAT-063AWO 1. An analog switch system, comprising: a first node for a positive voltage supply signal; a second node for a negative voltage supply signal; an input terminal to receive an input signal and an output terminal to output an output signal; a MOS switch having a gate, a source, and a drain, a channel, and a gate-to-channel capacitance, wherein the MOS switch is configured to turn the input signal on and off; a switch control circuit coupled to the MOS switch, wherein the switch control circuit includes a gate driver circuit configured to control a gate-to-source voltage on the MOS switch to maintain a constant on-resistance while a peak of the input signal generates a gate voltage on the MOS switch above or below the respective positive or negative voltage supply signal.

2. The system according to claim 1, wherein the switch control circuit includes an averaging circuit to average the input and output signals.

3. The system according to claim 2, wherein the MOS switch comprises first and second transistors coupled end to end and the averaging circuit comprises a node between the first and second transistors.

4. The system according to claim 2, wherein the switch control circuit includes a comparator circuit having an input coupled to an output of the averaging circuit and an output coupled to the gate drive circuit.

5. The system according to claim 3, wherein the MOS switch and the gate control circuit are configured such that a charge on the gate-to-channel capacitance holds a voltage on the gate-to- source of the MOS transistor during the signal peaks above the operating level.

6. The system according to claim 3, wherein the MOS switch remains on during the signal peaks due to the charge on the gate-to-channel capacitance applying a voltage on the gate of the MOS switch that is above the positive voltage supply signal.Attorney Docket No. THAT-063AWO 7. The system according to claim 1, wherein the switch gate drive circuit is configured to maintain a high impedance state during the signal peaks for the input signal above the operating level.

8. A method, comprising: providing a first node for a positive voltage supply signal and a second node for a negative voltage supply signal; employing an input terminal to receive an input signal and an output terminal to output an output signal for an analog switch; employing a MOS switch having a gate, a source, and a drain, a channel, and a gate-to- channel capacitance, wherein the MOS switch is configured to turn the input signal on and off; employing a switch control circuit coupled to the MOS switch, wherein the switch control circuit includes a gate driver circuit configured to control a gate-to-source voltage on the MOS switch to maintain a constant on-resistance while a peak of the input signal generates a gate voltage on the MOS switch above or below the respective positive or negative voltage supply signal.

9. The method according to claim 8, wherein the switch control circuit includes an averaging circuit to average the input and output signals.

10. The method according to claim 9, wherein the MOS switch comprises first and second transistors coupled end to end and the averaging circuit comprises a node between the first and second transistors.

11. The method according to claim 9, wherein the switch control circuit includes a comparator circuit having an input coupled to an output of the averaging circuit and an output coupled to the gate drive circuit.Attorney Docket No. THAT-063AWO 12. The method according to claim 10, wherein the MOS switch and the gate control circuit are configured such that a charge on the gate-to-channel capacitance holds a voltage on the gate-to- source of the MOS transistor during the signal peaks above the operating level.

13. The method according to claim 10, wherein the MOS switch remains on during the signal peaks due to the charge on the gate-to-channel capacitance applying a voltage on the gate of the MOS switch that is above the positive voltage supply signal.

14. The method according to claim 8, wherein the switch gate drive circuit is configured to maintain a high impedance state during the signal peaks for the input signal above the operating level.

15. An analog switch system, comprising: a first node for a first voltage supply signal; a second node for a second voltage supply signal; an input terminal to receive an input signal and an output terminal to output an output signal; a bipolar MOS switch comprising first and second transistors each having a respective gate, source, and drain, channel, and a gate-to-channel capacitance, wherein the gates of the first and second transistors are connected together, wherein the MOS transistor is configured to turn the input signal on and off; and a switch control circuit coupled to the MOS switch, wherein the switch control circuit comprises: third, fourth and fifth transistors coupled end-to-end; a voltage controlled current source coupled to the first node; a first diode coupled between the voltage controlled current source and the third transistor; and a second diode coupled between the fifth transistor and the second node, wherein the node between the first and second transistors comprises an averaging circuit for the input and output signals, wherein a gate of the fifth transistor is coupled to a nodeAttorney Docket No. THAT-063AWO between the first and second transistors, wherein the gates of the first and second transistor are coupled to a terminal of the third transistor, and wherein a charge on a gate to channel capacitance of the first and second transistors maintains the first and second transistors in the on state while the first diode is off during peaks of the input signal that allow a voltage on the gates of the first and second transistors to exceed the first voltage supply signal.

16. A method for processing a signal with an analog switch, comprising: employing a first node for a first voltage supply signal and a second node for a second voltage supply signal; employing an input terminal to receive an input signal and an output terminal to output an output signal; employing a bipolar MOS switch comprising first and second transistors each having a respective gate, source, and drain, channel, and a gate-to-channel capacitance, wherein the gates of the first and second transistors are connected together, wherein the MOS transistor is configured to turn the input signal on and off; and employing a switch control circuit coupled to the MOS switch, wherein the switch control circuit comprises: third, fourth and fifth transistors coupled end-to-end; a voltage controlled current source coupled to the first node; a first diode coupled between the voltage controlled current source and the third transistor; and a second diode coupled between the fifth transistor and the second node, wherein the node between the first and second transistors comprises an averaging circuit for the input and output signals, wherein a gate of the fifth transistor is coupled to a node between the first and second transistors, wherein the gates of the first and second transistor are coupled to a terminal of the third transistor, and wherein a charge on a gate to channel capacitance of the first and second transistors maintains the first and second transistors in the on state while the first diode is off during peaks of the input signal that allow a voltage on the gates of the first and second transistors to exceedAttorney Docket No. THAT-063AWO the first voltage supply signal.

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