Method and apparatus for generating code, and electronic device and program product

Abstract

Provided in the embodiments of the present disclosure are a method and apparatus for generating code, and an electronic device and a program product. The method comprises: on the basis of a source code in a target language, generating a multi-level intermediate representation of the source code. The method further comprises: on the basis of the multi-level intermediate representation, generating a low-level virtual machine intermediate representation of the source code. The method further comprises: in response to the low-level virtual machine intermediate representation meeting a predetermined condition, generating an executable file package in the target language. In addition, the method further comprises: in response to the low-level virtual machine intermediate representation not meeting the predetermined condition, regenerating a multi-level intermediate representation of the source code. In the embodiments of the present disclosure, by means of a traceable iterative compilation process, a process that does not meet the predetermined condition during compilation can be adjusted in a timely manner, thereby reducing the cost of compilation and improving the development efficiency of developers.

Description

Methods, apparatus, electronic devices, and program products for generating code. Technical Field

[0001] This disclosure generally relates to the field of computers, and more specifically to methods, apparatus, electronic devices, and program products for generating code. Background Technology

[0002] Multi-Level Intermediate Representation (MLIR) and Low-Level Virtual Machine Intermediate Representation (LLVM-IR) both enhance compiler efficiency and flexibility, promote code optimization and cross-platform compatibility, and are important technologies in modern software development and high-performance computing. MLIR in the compilation process is a high-level abstraction concept designed to simplify and unify program representation and optimization across multiple levels of abstraction. It allows developers to operate at different levels of abstraction, from high-level function call graphs to low-level instruction sequences, thereby achieving finer-grained code optimization.

[0003] The low-level virtual machine intermediate representation is a core component of the LLVM compiler infrastructure. It is a statically typed, control-flow-oriented intermediate language used to represent intermediate states during the compilation process. It can be optimized at compile time, link time, load time, and even runtime, and is then translated into native code for the target machine. The design of the low-level virtual machine intermediate representation complements that of multi-level intermediate representations, together providing strong support for the compiler's efficient code generation and optimization.

[0004] Summary of the Invention

[0005] Embodiments of this disclosure provide a method, apparatus, electronic device, and program product for generating code.

[0006] According to a first aspect of this disclosure, a method for generating code is provided. The method includes generating a multi-level intermediate representation of the source code based on source code in a target language. The method also includes generating a low-level virtual machine intermediate representation of the source code based on the multi-level intermediate representation. The method further includes generating an executable file package in the target language in response to the low-level virtual machine intermediate representation meeting predetermined conditions. Furthermore, the method includes regenerating the multi-level intermediate representation of the source code in response to the low-level virtual machine intermediate representation not meeting predetermined conditions.

[0007] In a second aspect of this disclosure, an apparatus for generating code is provided. The apparatus includes a multi-layer intermediate representation generation device configured to generate a multi-layer intermediate representation of source code based on source code in a target language. The apparatus also includes a low-level virtual machine intermediate representation generation module configured to generate a low-level virtual machine intermediate representation of the source code based on the multi-layer intermediate representation. The apparatus further includes an executable file package generation module configured to generate an executable file package in the target language in response to the low-level virtual machine intermediate representation meeting predetermined conditions. Furthermore, the apparatus includes a multi-layer intermediate representation regeneration module configured to regenerate the multi-layer intermediate representation of the source code in response to the low-level virtual machine intermediate representation not meeting predetermined conditions.

[0008] In a third aspect of this disclosure, an electronic device is provided. The electronic device includes a processor and a memory coupled to the processor, the memory having instructions stored therein, which, when executed by the processor, cause the electronic device to perform the method according to the first aspect.

[0009] In a fourth aspect of this disclosure, a computer program product is provided that stores computer-executable instructions thereon, wherein the computer-executable instructions are executed by a processor to implement the method of the first aspect.

[0010] The summary section is intended to present the chosen concepts in a simplified form, which will be further described in the detailed description below. The summary section is not intended to identify key or principal features of the claimed subject matter, nor is it intended to limit the scope of the claimed subject matter. Attached Figure Description

[0011] The above and other features, advantages, and aspects of the embodiments of this disclosure will become more apparent from the accompanying drawings and the following detailed description. In the drawings, the same or similar reference numerals denote the same or similar elements, wherein:

[0012] Figure 1 shows a schematic diagram of an example environment in which some embodiments of this disclosure may be implemented;

[0013] Figure 2 shows a flowchart of a method for generating code according to some embodiments of the present disclosure;

[0014] Figure 3 illustrates a schematic diagram of a process for generating an executable file package according to some embodiments of this disclosure;

[0015] Figure 4 illustrates a schematic diagram of a compilation process for bidirectional derivation during the generation of target code, according to some embodiments of the present disclosure.

[0016] Figure 5 shows a block diagram of an apparatus for generating code according to some embodiments of the present disclosure; and

[0017] Figure 6 shows a block diagram of an electronic device according to some embodiments of the present disclosure.

[0018] In all the accompanying figures, the same or similar reference numerals denote the same or similar elements. Detailed Implementation

[0019] It is understood that the data involved in this technical solution (including but not limited to the data itself, the acquisition or use of the data) shall comply with the requirements of relevant laws, regulations and related provisions.

[0020] Embodiments of this disclosure will now be described in more detail with reference to the accompanying drawings. While some embodiments of this disclosure are shown in the drawings, it should be understood that this disclosure can be implemented in various forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided to provide a more thorough and complete understanding of this disclosure. It should be understood that the accompanying drawings and embodiments of this disclosure are for illustrative purposes only and are not intended to limit the scope of protection of this disclosure.

[0021] In the description of embodiments of this disclosure, the term "comprising" and similar terms should be understood as open-ended inclusion, i.e., "including but not limited to". The term "based on" should be understood as "at least partially based on". The term "one embodiment" or "the embodiment" should be understood as "at least one embodiment". The terms "first", "second", etc., may refer to different or the same objects unless explicitly stated. Other explicit and implicit definitions may also be included below.

[0022] As mentioned above, multi-level intermediate representations and low-level virtual machine intermediate representations play extremely important roles in the compilation process. In related technologies, the compilation process typically follows a linear, unidirectional execution model, meaning that the compilation process can only proceed sequentially, from source code analysis, syntax parsing, semantic analysis, to generating object code. This process is particularly evident in the conversion from multi-level intermediate representations to low-level virtual machine intermediate representations. During this conversion, the compiler performs a series of checks and verifications on the generated low-level virtual machine intermediate representation to ensure the correctness and efficiency of the code.

[0023] However, if an error is discovered at this stage, the traditional approach is to halt the entire compilation process without attempting to "backtrack" or "reverse engineer" the error—that is, without trying to return to multiple intermediate representation levels to correct the problem and then re-convert. Instead, the entire compilation process needs to be restarted from scratch, starting with source code analysis, until the entire compilation process is completed. While this approach ensures the quality and reliability of the executable file, it undoubtedly increases the compilation cost and makes it inconvenient for developers to debug flexibly, thus reducing development efficiency.

[0024] According to embodiments of this disclosure, a multi-level intermediate representation is generated by analyzing the source code of the target language. Then, based on the generated multi-level intermediate representation, a low-level virtual machine intermediate representation of the source code is further generated, laying the foundation for subsequent compilation and execution processes. After generating the low-level virtual machine intermediate representation, it is verified to ensure that it meets predetermined conditions (e.g., optimization conditions). If the generated low-level virtual machine intermediate representation meets the predetermined conditions, the executable file package can continue to be generated. If the generated low-level virtual machine intermediate representation fails to meet the predetermined conditions, the process returns to the multi-level intermediate representation generation stage and iterates again to further optimize the compilation process.

[0025] Through this backtracking process of continuous iteration and optimization, a low-level virtual machine intermediate representation that meets predetermined conditions can eventually be generated, and then an executable file package of the target language can be generated. This not only ensures the efficient operation and reliability of the program, but also reduces the cost of compilation and improves the development efficiency of developers.

[0026] Figure 1 illustrates a schematic diagram of an example environment 100 in which some embodiments of this disclosure can be implemented. As shown in Figure 1, the compilation process is the process of converting high-level language source code 110 (e.g., Python) into a low-level language (typically machine language or assembly language) so that computer hardware can directly execute it. During the compilation process, the compiler front end mainly focuses on the analysis and conversion of the source code 110. It is responsible for reading the source code, performing lexical analysis, syntax analysis, semantic analysis, etc., until an intermediate representation is generated (e.g., it may be a multi-level intermediate representation 130 and / or a low-level virtual machine intermediate representation 140). The compiler back end mainly focuses on how to convert the intermediate representation into target code 150, also called target machine code.

[0027] As shown in Figure 1, source code 110 is human-readable program text written by a programmer using a high-level programming language. The process of converting source code 110 into an abstract syntax tree (AST) 120 typically occurs during the front-end analysis phase of a compiler or interpreter. An abstract syntax tree is a tree-like structure where nodes represent various syntactic elements in the source code, such as variable declarations, function calls, and loop structures.

[0028] Referring to Figure 1, the compilation process involves transforming the abstract syntax tree 120 into an intermediate representation. The intermediate representation is an internal representation used for optimization and analysis during compilation. The compiler can generate one or more intermediate representations for deeper analysis and optimization. For example, a common intermediate representation is three-address code, which simplifies complex expressions into sequences of simple instructions, each with at most three operands. Other types of intermediate representations exist, such as SSA (Static Single Assignment) forms, which help eliminate redundant computations and optimize control flow.

[0029] As shown in Figure 1, the abstract syntax tree 120 can first be converted into a multi-level intermediate representation 130, and then further converted into a lower-level virtual machine intermediate representation 140 that is closer to the target code. The existence of the multi-level intermediate representation 130 allows the compiler to progressively refine the source code 110, representing a process that gradually moves from high-level abstraction down to a representation closer to the target machine. The multi-level intermediate representation 130 can encapsulate multiple domain dialects, which are designed to optimize the compilation process. For example, it can encapsulate the Linalg domain dialect, which is specifically designed for representing and optimizing linear algebra and array operations. Within the multi-level intermediate representation 130, multiple domain dialects can be converted to each other, i.e., from one domain dialect to another, thus helping the compiler implement a pipelined process from high-level abstraction to low-level hardware optimization. The specific domain dialects encapsulated in the multi-level intermediate representation 130 can be determined based on the specific compilation and optimization tasks.

[0030] Referring back to Figure 1, unlike the multi-level intermediate representation 130, the low-level virtual machine intermediate representation 140 is closer to machine language while still maintaining a certain degree of independence, enabling cross-platform execution. For example, the Java compiler generates bytecode, a low-level intermediate representation that can be interpreted and executed by the Java Virtual Machine (JVM) or further compiled into native machine code. It's important to understand that the multi-level intermediate representation and low-level virtual machine intermediate representation mentioned in this article are both intermediate representations, representing a narrow definition. For example, an abstract syntax tree is also a type of multi-level intermediate representation in a broader sense.

[0031] Referring back to Figure 1, after the process of converting source code 110 into an abstract syntax tree 120, and then into a multi-level intermediate representation 130 and finally a low-level virtual machine intermediate representation 140, the low-level virtual machine intermediate representation 140 can be checked and verified to determine whether the entire compilation process has met the predetermined goals or conditions. For example, if developers want to generate a low-level virtual machine intermediate representation of target code for a certain hardware platform, they need certain hardware information. However, if this hardware information is lost during compilation, then the compilation process has not met the predetermined conditions. In this case, the low-level virtual machine intermediate representation 140 can be traced back to the multi-level intermediate representation 130 via step 162 for verification and checking. If it is found that the predetermined optimization conditions still cannot be met, the process can be traced back to the abstract syntax tree 120 via step 164 for further verification and analysis to regenerate the multi-level intermediate representation 130 for source code 110, and then the compilation process can be repeated. If, after verification and checking, the generated low-level virtual machine intermediate representation 140 meets the predetermined conditions, then the target code 150 can be generated using this low-level virtual machine intermediate representation 140.

[0032] Through this continuous iterative and optimized compilation process that includes a backtracking mechanism, a low-level virtual machine intermediate representation that meets predetermined conditions can be generated, and an executable file package can be generated based on this representation. This process not only ensures the efficient operation and reliability of the program, but also effectively reduces compilation costs, thereby improving the development efficiency of developers.

[0033] The process according to embodiments of the present disclosure will be described in detail below with reference to Figures 2 to 6. For ease of understanding, the specific data mentioned in the following description are exemplary and are not intended to limit the scope of protection of this disclosure. It is understood that the embodiments described below may also include additional actions not shown and / or actions shown may be omitted, and the scope of this disclosure is not limited in this respect.

[0034] Figure 2 illustrates a flowchart of a method 200 for generating code according to some embodiments of the present disclosure. Referring to Figure 2, method 200 includes blocks 202, 204, 206, and 208. The execution subject of method 200 can be an apparatus for generating code, which can be a server, such as a computing system, a single server, a distributed server, a system of servers configured in the cloud, or a standalone device or system. This apparatus can be implemented in software and / or hardware. Method 200 will now be described with the execution subject being an apparatus for generating code.

[0035] In box 202, a multi-level intermediate representation of the source code is generated based on the source code in the target language. For example, referring to Figure 1, source code 110 is human-readable program text written by a programmer using a high-level programming language. For example, it could be source code in Python as the target language. In some embodiments, source code 110 can be process orchestration code that describes the orchestration process and the process node code of the tasks in the orchestration process, which describes the user-defined orchestration process. In order to compile source code 110 into target code 150 suitable for machine recognition and execution, source code 110 can first be converted into an intermediate representation for deeper analysis and optimization. For example, it can first be converted into a multi-level intermediate representation 130, which is usually closer to machine language than the source code, but still maintains a certain level of abstraction, thus making the conversion optimization rules more general.

[0036] In box 204, a low-level virtual machine intermediate representation of the source code is generated based on the multi-level intermediate representation. For example, referring to Figure 1, after reducing the level of abstraction through the multi-level intermediate representation 130, the multi-level intermediate representation 130 can be further transformed into a low-level virtual machine intermediate representation 140 because it is closer to the code structure of the target machine and also contains more information related to the target architecture. This allows the compiler to optimize for different target architectures, thereby improving the program's running efficiency.

[0037] In box 206, in response to the low-level virtual machine intermediate representation meeting predetermined conditions, an executable file package in the target language is generated. For example, referring to Figure 1, when the generated low-level virtual machine intermediate representation 140 meets predetermined optimization conditions, the low-level virtual machine intermediate representation 140 can then be successfully converted into target code 150, thereby generating an executable file package. In some embodiments, this can be a platform-specific executable file package (e.g., x86, etc.).

[0038] In box 208, in response to the low-level virtual machine intermediate representation not meeting predetermined conditions, the multi-level intermediate representation of the source code is regenerated. For example, referring to Figure 1, if the generated low-level virtual machine intermediate representation 140 does not meet the predetermined optimization conditions, then the process will backtrack to deriving the multi-level intermediate representation 130 from the low-level virtual machine intermediate representation 140, and regenerate the multi-level intermediate representation 130. This allows the compilation process to continue iteratively until the generated low-level virtual machine intermediate representation 140 meets the predetermined optimization conditions.

[0039] In this embodiment, a multi-level intermediate representation is generated by analyzing the source code of the target language. Then, based on the generated multi-level intermediate representation, a low-level virtual machine intermediate representation of the source code is further generated, laying the foundation for subsequent compilation and execution. After generating the low-level virtual machine intermediate representation, it is verified to ensure that it meets predetermined conditions. If the generated low-level virtual machine intermediate representation meets the predetermined conditions, the executable file package can continue to be generated. If the generated low-level virtual machine intermediate representation does not meet the predetermined conditions, the process returns to the multi-level intermediate representation generation stage and repeats this process to further adjust the compilation process.

[0040] Through this backtracking process of continuous iteration and optimization, a low-level virtual machine intermediate representation that meets predetermined conditions can eventually be generated, and then an executable file package of the target language can be generated. This not only ensures the efficient operation and reliability of the program, but also reduces the cost of compilation and improves the development efficiency of developers.

[0041] Figure 3 illustrates a schematic diagram of a process 300 for generating an executable file package according to some embodiments of this disclosure. Referring to Figure 3, in data structure 310, a serialized file 312 is obtained from the intermediate layer between the front-end and back-end. In some embodiments, the orchestration process expressed by the user through the canvas of the front-end can be stored in a digital, serialized form in the data structure of the intermediate layer. For example, the data can be stored in a BFF (Backend for Frontends) data structure in JSON format. BFF is a backend service designed specifically for the front-end. As an intermediate layer, it can process and transform data to adapt to different system components.

[0042] Referring again to Figure 3, the serialized file 312 obtained from the middleware layer between the front-end and back-end is converted into orchestration code 322 and process node code 324 in the target language (e.g., Python). For example, a JSON-formatted serialized file can be converted into orchestration code 322 and process node code 324 presented in Python. The generated orchestration code 322 and process node code 324 can then form an orchestration paradigm 320, ensuring the reliability of the generated code. In some embodiments, the generated code can be optimized during the generation of the orchestration paradigm 320 to ensure its executability.

[0043] As shown in Figure 3, to effectively utilize the generated code, it needs to be compiled into machine language that is machine-readable and executable. During the compilation process, to optimize the process and improve efficiency, the generated target language code can first be converted into a multi-layered intermediate representation 332. In some embodiments, the multi-layered intermediate representation 332 can encapsulate various domain dialects, which can be mutually converted according to developer-defined rules to optimize the compilation process. By converting the source code into a multi-layered intermediate representation, the compiler can separate the stages of source code parsing, optimization, and target code generation, with each layer of the intermediate representation representing a different level of abstraction. Furthermore, it allows the compiler to independently develop and optimize each part of the multi-layered intermediate representation, improving modularity and maintainability.

[0044] Referring again to Figure 3, although the multi-level intermediate representation 332 can represent various levels of abstraction, from high-level language features to low-level machine instructions, it typically does not directly generate machine code. Instead, it relies on the low-level virtual machine intermediate representation 334 or other backends to complete this process. In some embodiments, tools such as the Clang compiler frontend, LLVM Linker, and LLVM Assembler can be used to convert the multi-level intermediate representation 332 into the low-level virtual machine intermediate representation 334. This facilitates the integration of code into existing build and deployment processes, thereby enabling cross-platform execution with the help of LLVM.

[0045] To more clearly describe the bidirectional derivation compilation process of generating intermediate representations of low-level virtual machines with excellent reduced compilation costs, the following description will be made in conjunction with Figure 4.

[0046] Figure 4 illustrates a schematic diagram of a compilation process 400 for bidirectional derivation during the regeneration of target code, according to some embodiments of this disclosure. As shown in Figure 4, source code 410, written in Python, describes a process for printing all numbers in the Fibonacci sequence less than a given value n (n = 1000). During compilation, an abstract syntax tree 420 can then be constructed step-by-step. Before constructing the abstract syntax tree 420, lexical analysis and syntax analysis can be performed on the source code 410. Lexical analysis (also known as scanning) converts the source code character stream into a series of meaningful tokens, resulting in Table 1:

[0047] Referring again to Figure 4, following lexical analysis, syntax analysis (also known as parsing) can be performed. Its purpose is to check whether the token sequence conforms to the language's grammatical rules and to construct a syntax tree, typically an abstract syntax tree. An abstract syntax tree (AST) is a tree-like data structure that ignores irrelevant details in the source code, retaining only its grammatical structure. Based on the code above, the approximate structure of the abstract syntax tree is as follows:

[0048] Each node type, such as FunctionDef, Assign, While, Expr, Call, and BinOp, corresponds to a specific syntactic structure identified during syntax analysis. Here, Module is the root node of the entire abstract syntax tree 420, containing all top-level statements. FunctionDef nodes represent function definitions, Assign nodes represent assignment statements, While nodes represent loop structures, and Expr nodes are typically used to represent expression statements, such as function calls. Call nodes represent function calls, BinOp nodes represent binary operations (such as addition), and Compare nodes represent comparison operations. In Python, the abstract syntax tree of the source code can be obtained directly.

[0049] Referring again to Figure 4, in some embodiments, after the abstract syntax tree 420 of the source code 410 is generated, further important analyses, namely type checking 430, are required. Type checking 430 ensures type safety and consistency of the program, thereby preventing errors that may occur during program code execution, such as preventing illegal operations like attempting to add strings and integers. In some embodiments, the abstract syntax tree 420 can be traversed to check variable declarations, function definitions, type consistency, etc., and annotations can be added to the abstract syntax tree 420 to include type information and other metadata. For example, for "a, b = 0, 1", variables a and b are declared and initialized as integers. The type checker will record that the types of a and b are int. For "a, b = b, a + b", it will check whether the type of b is consistent with the type of a, and whether the operation a + b is legal. Since a and b are both integers, the addition is not a problem. In some embodiments, after type checking 430 is correct, the abstract syntax tree 420 can be converted into a multi-level intermediate representation at 440. This approach of separating type checking from code conversion allows different parts of the compiler to focus on their own tasks, thereby increasing the compiler's flexibility.

[0050] Referring again to Figure 4, in some embodiments, the multi-layered intermediate representation can be optimized from dialect A to dialect B, and then to dialect C. Dialect A can be the representation closest to the source code, preserving the original structure and semantics, and therefore can be used for preliminary syntax analysis and semantic checking. Dialect B can be a domain dialect that focuses more on improving code execution efficiency and resource consumption, while dialect C can be a domain dialect closer to the target machine code, ensuring that the final generated code is compatible with the target platform. Developers can select and optimize the domain dialect according to their development needs. This enables professional programmers to write high-performance code in an intuitive, advanced, and familiar way.

[0051] Referring again to Figure 4, as described above, to make the multi-level intermediate representation closer to machine language, it can be converted into a low-level virtual machine intermediate representation at 450. After the converted low-level virtual machine intermediate representation is checked and verified to be acceptable, it can be converted into the target code required by the developer at 460. If, after verification and checking, the converted low-level virtual machine intermediate representation is found to not meet the expected requirements or predetermined conditions, the process can be reversed from 470 to 440 to re-derive the multi-level intermediate representation of the low-level virtual machine intermediate representation. Then, at 480 and 430, a type check is performed again on the syntax tree 420 to generate a new abstract syntax tree and multi-level intermediate representation for the source code 410. This is then converted into a new low-level virtual machine intermediate representation at 450 for verification. If the verification result still does not meet the predetermined conditions, the process of generating the multi-level intermediate representation can be iterated again until the generated low-level virtual machine intermediate representation meets the predetermined conditions.

[0052] This multi-layered static bidirectional compilation method can convert dynamic languages ​​(such as Python) into static languages ​​(C / Rust-like), and achieve static inference without using any runtime type information. This eliminates the overhead of interpreted execution, reduces the time of Ahead-of-Time (AOT) compilation, and improves the overall compilation performance.

[0053] Returning to Figure 3, once the generated low-level virtual machine intermediate representation meets predetermined conditions, it can be converted into an executable file. For example, a native file can be directly generated for cross-platform execution on 340. In some embodiments, the low-level virtual machine intermediate representation that meets predetermined conditions can also generate an orchestration process file package 336 related to the orchestration process. For example, if the orchestration process is presented in Python, a Python package can be generated, and then on 340, it can be combined with third-party Python packages to achieve cross-platform execution. In some embodiments, if the generated low-level virtual machine intermediate representation does not meet predetermined optimization conditions, iterative compilation can be performed by backtracking to the multi-level intermediate representation 332 via 338.

[0054] Through this backtracking process of continuous iteration and optimization, a low-level virtual machine intermediate representation that meets predetermined conditions can eventually be generated, and then an executable file package of the target language can be generated. This not only ensures the efficient operation and reliability of the program, but also reduces the cost of compilation and improves the development efficiency of developers.

[0055] Figure 5 shows a block diagram of an apparatus 500 for generating code according to some embodiments of the present disclosure. As shown in Figure 5, the apparatus 500 includes a multi-level intermediate representation generation module 502, configured to generate a multi-level intermediate representation of source code based on source code in a target language. The apparatus 500 also includes a low-level virtual machine intermediate representation generation module 504, configured to generate a low-level virtual machine intermediate representation of source code based on the multi-level intermediate representation. The apparatus 500 also includes an executable file package generation module 506, configured to generate an executable file package in the target language in response to the low-level virtual machine intermediate representation meeting predetermined conditions. Furthermore, the apparatus 500 includes a multi-level intermediate representation regeneration module 508, configured to regenerate the multi-level intermediate representation of source code in response to the low-level virtual machine intermediate representation not meeting predetermined conditions.

[0056] In some embodiments, the multi-layer intermediate representation generation module 502 includes: a first generation module configured to generate an abstract syntax tree corresponding to the source code based on the source code, wherein the abstract syntax tree is a tree-like representation of the source code; and a second generation module configured to generate a multi-layer intermediate representation of the source code based on the abstract syntax tree.

[0057] In some embodiments, the second generation module includes: a first determining module that traverses and checks the types of nodes in the abstract syntax tree to determine the check result for the abstract syntax tree; and a first derivation module configured to, in response to the determined check result for the abstract syntax tree being correct, derive a multi-layer intermediate representation corresponding to the source code layer by layer.

[0058] In some embodiments, the first derivation module includes: a second derivation module configured to derive a first-level intermediate representation of the multi-level intermediate representation from the abstract syntax tree; and a third derivation module configured to derive a second-level intermediate representation of the multi-level intermediate representation from the first-level intermediate representation of the multi-level intermediate representation.

[0059] In some embodiments, the low-level virtual machine intermediate representation generation module 504 includes: a third generation module generating a low-level virtual machine intermediate representation based on a second-level intermediate representation of a multi-level intermediate representation.

[0060] In some embodiments, the executable file package generation module 506 includes: a fourth generation module configured to generate machine code corresponding to the source code based on a low-level virtual machine intermediate representation; and a fifth generation module configured to generate an executable file package based on the machine code.

[0061] In some embodiments, the multi-level intermediate representation regeneration module 508 includes: a backtracking module configured to backtrack to the abstract syntax tree in response to a lower-level virtual machine intermediate representation not meeting predetermined conditions; and a sixth generation module configured to regenerate the multi-level intermediate representation of the source code based on the abstract syntax tree.

[0062] In some embodiments, the apparatus 500 further includes: an acquisition module configured to acquire an orchestration flow drawn by a user on a canvas of a graphical user interface; and a seventh generation module configured to generate source code in a target language based on the orchestration flow, wherein the source code includes orchestration code representing the semantics of the flow and flow node code representing tasks in the orchestration flow.

[0063] In some embodiments, the seventh generation module further includes a second determining module configured to determine a serialization file corresponding to the orchestration process based on the orchestration process; and an eighth generation module configured to generate source code for the target language based on the serialization file.

[0064] Figure 6 shows a block diagram of an electronic device 600 according to some embodiments of the present disclosure. Device 600 may be the device or apparatus described in the embodiments of the present disclosure. As shown in Figure 6, device 600 includes a central processing unit (CPU) and / or a graphics processing unit (GPU) 601, which can perform various appropriate actions and processes according to computer program instructions stored in read-only memory (ROM) 602 or loaded from storage unit 608 into random access memory (RAM) 603. Various programs and data required for the operation of device 600 may also be stored in RAM 603. CPU / GPU 601, ROM 602, and RAM 603 are interconnected via bus 604. Input / output (I / O) interface 605 is also connected to bus 604. Although not shown in Figure 6, device 600 may also include a coprocessor.

[0065] Multiple components in device 600 are connected to I / O interface 605, including: input unit 606, such as keyboard, mouse, etc.; output unit 607, such as various types of monitors, speakers, etc.; storage unit 608, such as disk, optical disk, etc.; and communication unit 609, such as network card, modem, wireless transceiver, etc. Communication unit 609 allows device 600 to exchange information / data with other devices through computer networks such as the Internet and / or various telecommunications networks.

[0066] The various methods or processes described above can be executed by CPU / GPU 601. For example, in some embodiments, the methods may be implemented as computer software programs tangibly contained in a machine-readable medium, such as storage unit 608. In some embodiments, part or all of the computer program may be loaded and / or installed on device 600 via ROM 602 and / or communication unit 609. When the computer program is loaded into RAM 603 and executed by CPU / GPU 601, one or more steps or actions in the methods or processes described above may be performed.

[0067] In some embodiments, the methods and processes described above can be implemented as a computer program product. The computer program product may include a computer-readable storage medium having computer-readable program instructions loaded thereon for performing various aspects of this disclosure.

[0068] Computer-readable storage media can be tangible devices capable of holding and storing instructions for use by an instruction execution device. Computer-readable storage media can be, for example, but not limited to, electrical storage devices, magnetic storage devices, optical storage devices, electromagnetic storage devices, semiconductor storage devices, or any suitable combination thereof. More specific examples (a non-exhaustive list) of computer-readable storage media include: portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), static random access memory (SRAM), portable compact disc read-only memory (CD-ROM), digital multifunction disc (DVD), memory sticks, floppy disks, mechanical encoding devices, such as punch cards or recessed protrusions storing instructions thereon, and any suitable combination thereof. The computer-readable storage media used herein are not to be construed as transient signals themselves, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through waveguides or other transmission media (e.g., light pulses through fiber optic cables), or electrical signals transmitted through wires.

[0069] The computer-readable program instructions described herein can be downloaded from computer-readable storage media to various computing / processing devices, or downloaded via a network, such as the Internet, a local area network (LAN), a wide area network (WAN), and / or a wireless network, to an external computer or external storage device. The network may include copper cables, fiber optic cables, wireless transmission, routers, firewalls, switches, gateway computers, and / or edge servers. A network adapter card or network interface in each computing / processing device receives the computer-readable program instructions from the network and forwards them to the computer-readable storage media in the respective computing / processing device.

[0070] Computer program instructions used to perform the operations of this disclosure may be assembly instructions, instruction set architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, status setting data, or source code or object code written in any combination of one or more programming languages, including object-oriented programming languages ​​and conventional procedural programming languages. The computer-readable program instructions may execute entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving a remote computer, the remote computer may be connected to the user's computer via any type of network—including a local area network (LAN) or a wide area network (WAN)—or may be connected to an external computer (e.g., via the Internet using an Internet service provider). In some embodiments, electronic circuitry, such as programmable logic circuitry, field-programmable gate arrays (FPGAs), or programmable logic arrays (PLAs), is personalized by utilizing the status information of the computer-readable program instructions to implement various aspects of this disclosure.

[0071] These computer-readable program instructions can be provided to a processing unit of a general-purpose computer, a special-purpose computer, or other programmable data processing apparatus to produce a machine such that, when executed by the processing unit of the computer or other programmable data processing apparatus, they create means for implementing the functions / actions specified in one or more blocks of the flowchart and / or block diagram. These computer-readable program instructions can also be stored in a computer-readable storage medium that causes a computer, programmable data processing apparatus, and / or other device to operate in a particular manner. Thus, the computer-readable medium storing the instructions comprises an article of manufacture that includes instructions for implementing aspects of the functions / actions specified in one or more blocks of the flowchart and / or block diagram.

[0072] Computer-readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other device to cause a series of operational steps to be performed on the computer, other programmable data processing apparatus, or other device to produce a computer-implemented process, thereby causing the instructions executed on the computer, other programmable data processing apparatus, or other device to perform the functions / actions specified in one or more boxes of a flowchart and / or block diagram.

[0073] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of devices, methods, and computer program products according to various embodiments of the present disclosure. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of an instruction containing one or more executable instructions for implementing a specified logical function. In some alternative implementations, the functions marked in the blocks may occur in a different order than those marked in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, may be implemented using a dedicated hardware-based system that performs the specified function or action, or using a combination of dedicated hardware and computer instructions.

[0074] The various embodiments of this disclosure have been described above. These descriptions are exemplary and not exhaustive, nor are they limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen to best explain the principles, practical applications, or technical improvements to the technology in the market, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. A method for generating code, comprising: generating a multi-layer intermediate representation of source code in a target language based on the source code; generating a low-level virtual machine intermediate representation of the source code based on the multi-layer intermediate representation; in response to the low-level virtual machine intermediate representation satisfying a predetermined condition, generating an executable package in the target language based on the low-level virtual machine intermediate representation; and in response to the low-level virtual machine intermediate representation not satisfying the predetermined condition, regenerating the multi-layer intermediate representation of the source code. 2.The method of claim 1, wherein generating a multi-layer intermediate representation of source code in a target language based on the source code comprises: generating an abstract syntax tree corresponding to the source code based on the source code, the abstract syntax tree being a tree-like representation of the source code; and generating the multi-layer intermediate representation of the source code based on the abstract syntax tree. 3.The method of claim 2, wherein generating the multi-layer intermediate representation of the source code based on the abstract syntax tree comprises: traversing and checking types of nodes in the abstract syntax tree to determine a checking result for the abstract syntax tree; and in response to the determined checking result for the abstract syntax tree being correct, layer by layer deducing the multi-layer intermediate representation corresponding to the source code. 4.The method of claim 3, wherein in response to the determined checking result for the abstract syntax tree being correct, layer by layer deducing the multi-layer intermediate representation corresponding to the source code comprises: deducing a first layer intermediate representation of the multi-layer intermediate representation from the abstract syntax tree; and deducing a second layer intermediate representation of the multi-layer intermediate representation from the first layer intermediate representation of the multi-layer intermediate representation. 5.The method of claim 4, wherein generating a low-level virtual machine intermediate representation of the source code based on the multi-layer intermediate representation comprises: generating the low-level virtual machine intermediate representation based on the second layer intermediate representation of the multi-layer intermediate representation. 6.The method of claim 5, wherein in response to the low-level virtual machine intermediate representation satisfying the predetermined condition, generating an executable package in the target language based on the low-level virtual machine intermediate representation comprises: generating machine code corresponding to the source code based on the low-level virtual machine intermediate representation; and generating the executable package based on the machine code. 7.The method of claim 6, wherein in response to the low-level virtual machine intermediate representation not satisfying the predetermined condition, regenerating the multi-layer intermediate representation of the source code comprises: in response to the low-level virtual machine intermediate representation not satisfying the predetermined condition, backtracking to the abstract syntax tree; and regenerating the multi-layer intermediate representation of the source code based on the abstract syntax tree. 8.The method of claim 1, further comprising: acquiring an orchestration flow drawn by a user on a canvas of a graphical user interface; and generating the source code in the target language based on the orchestration flow, the source code comprising flow orchestration code representing flow semantics and flow node code representing tasks in the orchestration flow. ​ ​ ​ ​ ​ ​ 9. The method of claim 8, wherein generating the source code in the target language based on the orchestration flow comprises: determining a serialized file corresponding to the orchestration flow based on the orchestration flow; and generating the source code in the target language based on the serialized file.

10. An apparatus for generating code, comprising: a multi-layer intermediate representation generation apparatus configured to generate a multi-layer intermediate representation of a source code in a target language based on the source code; a low-level virtual machine intermediate representation generation module configured to generate a low-level virtual machine intermediate representation of the source code based on the multi-layer intermediate representation; an executable package generation module configured to generate an executable package of the target language in response to the low-level virtual machine intermediate representation satisfying a predetermined condition; and a multi-layer intermediate representation regeneration module configured to regenerate the multi-layer intermediate representation of the source code in response to the low-level virtual machine intermediate representation not satisfying the predetermined condition.

11. An electronic device, comprising: a processor; and a memory coupled with the processor, the memory having stored therein instructions which, when executed by the processor, cause the electronic device to perform the method according to any one of claims 1 to 9.

12. A computer program product comprising computer-executable instructions, wherein the computer-executable instructions are executed by a processor to implement the method according to any one of claims 1 to 9. ​ ​

Images