Pixel circuit and driving method therefor, display substrate, and display apparatus

Abstract

A pixel circuit, comprising: a drive sub-circuit (11), a data writing sub-circuit (13), a compensation sub-circuit (12), a coupling sub-circuit (14) and a first control sub-circuit (15). The coupling sub-circuit (14) is coupled to a first node (N1) and a third node (N3). The first control sub-circuit (15) is configured to write a first reference voltage signal, which is provided by a first reference voltage line (REF1), into the third node (N3) under the control of a first control line (S1) after the data writing sub-circuit (13) writes a data signal to the third node (N3), such that the data signal is coupled to the first node (N1) by means of the coupling sub-circuit (14).

Description

Pixel circuits and their driving methods, display substrates and display devices Technical Field

[0001] This article relates to, but is not limited to, the field of display technology, and in particular to a pixel circuit and its driving method, a display substrate and a display device. Background Technology

[0002] Organic light-emitting diodes (OLEDs) possess advantages such as ultra-thinness, wide viewing angle, active emission, high brightness, continuously adjustable emission color, low cost, fast response speed, low power consumption, wide operating temperature range, and flexible display capabilities. They have gradually become a promising next-generation display technology and are receiving increasing attention. Based on different driving methods, OLEDs can be divided into two types: passive matrix (PM) and active matrix (AM). AMOLEDs are current-driven devices that use independent thin-film transistors (TFTs) to control each sub-pixel, allowing each sub-pixel to emit light continuously and independently.

[0003] Summary of the Invention

[0004] The following is an overview of the subject matter described in detail herein. This overview is not intended to limit the scope of the claims.

[0005] This embodiment provides a pixel circuit and its driving method, a display substrate, and a display device.

[0006] On one hand, this embodiment provides a pixel circuit, including: a driving sub-circuit, a data writing sub-circuit, a compensation sub-circuit, a coupling sub-circuit, and a first control sub-circuit. The driving sub-circuit is coupled to a first node, a fourth node, and a fifth node, and configured to provide a driving signal to the fourth node under the control of the first node. The compensation sub-circuit is coupled to a second scan line, the first node, and the fourth node, and configured to turn on the first node and the fourth node under the control of the second scan line, so that a threshold voltage of the driving sub-circuit is written to the first node. The coupling sub-circuit is coupled to the first node and a third node. The data writing sub-circuit is coupled to the first scan line, a data line, and the third node, and configured to send a data signal provided by the data line to the third node under the control of the first scan line. The first control sub-circuit is coupled to a first control line, the third node, and a first reference voltage line, and configured to, after the data writing sub-circuit writes the data signal to the third node, write a first reference voltage signal provided by the first reference voltage line to the third node under the control of the first control line, so that the data signal is coupled to the first node through the coupling sub-circuit.

[0007] In some exemplary embodiments, the duration for which the data writing subcircuit writes the data signal to the third node is less than the duration for which the compensation subcircuit writes the threshold voltage of the driving subcircuit to the first node; and the start time for the data writing subcircuit to write the data signal to the third node is later than the start time for the compensation subcircuit to write the threshold voltage of the driving subcircuit to the first node.

[0008] In some exemplary embodiments, the effective level signal provided by the second scan line is configured to control the compensation sub-circuit to write the threshold voltage of the driving sub-circuit into the first node. The time between the end time of the data writing sub-circuit writing the data signal into the third node and the start time of the effective level signal provided by the second scan line is a first duration, and the time between the end time of the data writing sub-circuit writing the data signal into the third node and the end time of the effective level signal provided by the second scan line is a second duration; the second duration is less than the first duration.

[0009] In some exemplary embodiments, the effective level signal provided by the second scan line is configured to control the compensation sub-circuit to write the threshold voltage of the driving sub-circuit into the first node. The effective level signal provided by the second scan line includes three equally divided phases: a first signal phase, a second signal phase, and a third signal phase, with the start time of the effective level signal provided by the first scan line following the first signal phase.

[0010] In some exemplary embodiments, the coupling sub-circuit includes: a first coupling sub-circuit and a second coupling sub-circuit; the first coupling sub-circuit is coupled to the first node and the second node, and the second coupling sub-circuit is coupled to the second node and the third node. The pixel circuit further includes: a second control sub-circuit, coupled to a second control line, the second node, and a first voltage terminal, configured to, under the control of the second control line, turn on the second node and the first voltage terminal, such that the second coupling sub-circuit stores the data signal written to the third node.

[0011] In some exemplary embodiments, the first coupling sub-circuit includes: a first capacitor; a first electrode of the first capacitor is coupled to the first node, and a second electrode of the first capacitor is coupled to the second node; the second coupling sub-circuit includes: a second capacitor; a first electrode of the second capacitor is coupled to the second node, and a second electrode of the second capacitor is coupled to the third node. The compensation sub-circuit includes: a compensation transistor; the gate of the compensation transistor is coupled to the second scan line, the first electrode of the compensation transistor is coupled to the fourth node, and the second electrode of the compensation transistor is coupled to the first node. The second control sub-circuit includes: a second control transistor; the gate of the second control transistor is coupled to the second control line, the first electrode of the second control transistor is coupled to the first voltage terminal, the first voltage terminal is coupled to the first power supply line, and the second electrode of the second control transistor is coupled to the second node.

[0012] In some exemplary embodiments, the compensation transistor and the second control transistor are oxide thin-film transistors, and the second control line and the second scan line are configured to provide the same signal.

[0013] In some exemplary embodiments, the data writing sub-circuit includes: a data writing transistor, the gate of which is coupled to the first scan line, a first electrode of which is coupled to the data line, and a second electrode of which is coupled to the third node. The first control sub-circuit includes: a first control transistor, the gate of which is coupled to the first control line, a first electrode of which is coupled to the first reference voltage line, and a second electrode of which is coupled to the third node. The compensation sub-circuit includes: a compensation transistor, the gate of which is coupled to the second scan line, a first electrode of which is coupled to the fourth node, and a second electrode of which is coupled to the first node.

[0014] In some exemplary embodiments, the data write transistor and the first control transistor are of the same transistor type, but different from the transistor type of the compensation transistor. The first control line and the second scan line are configured to provide the same signal.

[0015] In some exemplary embodiments, the pixel circuit further includes a first light-emitting control sub-circuit, coupled to a first light-emitting control line, a first power supply line, and the fifth node, configured to write a first power signal provided by the first power supply line to the fifth node under the control of the first light-emitting control line. The first control line and the first light-emitting control line are configured to provide the same signal.

[0016] In some exemplary embodiments, the data writing transistor and the first control transistor are of different transistor types, while the data writing transistor and the compensation transistor are of the same transistor type.

[0017] In some exemplary embodiments, the first control line and the first scan line are configured to transmit the same signal.

[0018] In some exemplary embodiments, the pixel circuit further includes a second light-emitting control sub-circuit and a fourth reset sub-circuit. The second light-emitting control sub-circuit is coupled to a second light-emitting control line, the fourth node, and the sixth node, and is configured to turn on the fourth node and the sixth node under the control of the second light-emitting control line. The sixth node is coupled to a first electrode of the light-emitting element. The fourth reset sub-circuit is coupled to the third node, the first reference voltage line, and the third reset control line, and is configured to write a first reference voltage signal provided by the first reference voltage line to the third node under the control of the third reset control line.

[0019] In some exemplary embodiments, the first control line and the second light emission control line are configured to provide the same signal.

[0020] In some exemplary embodiments, the pixel circuit further includes: a first reset sub-circuit and a second reset sub-circuit. The first reset sub-circuit is coupled to a first reset control line, a first reset voltage line, and the fourth node, and is configured to write a first reset voltage signal provided by the first reset voltage line to the fourth node under the control of the first reset control line; or, the first reset sub-circuit is coupled to the first reset control line, the first reset voltage line, and the first node, and is configured to write a first reset voltage signal provided by the first reset voltage line to the first node under the control of the first reset control line. The second reset sub-circuit is coupled to a second reset control line, a second reset voltage line, and a sixth node, and is configured to write a second reset voltage signal provided by the second reset voltage line to the sixth node under the control of the second reset control line, wherein the sixth node is coupled to a first electrode of the light-emitting element.

[0021] In some exemplary embodiments, the pixel circuit further includes a third reset sub-circuit coupled to the second reset control line, the second reference voltage line and the fifth node, configured to write a second reference voltage signal provided by the second reference voltage line to the fifth node under the control of the second reset control line.

[0022] In some exemplary embodiments, the pixel circuit further includes a third capacitor, wherein a first electrode of the third capacitor is coupled to a first bias signal line, and a second electrode of the third capacitor is coupled to the first node or the second node.

[0023] In some exemplary embodiments, the pixel circuit further includes a fourth capacitor, the first electrode of which is coupled to a second bias signal line, and the second electrode of which is coupled to the fourth node or the fifth node.

[0024] On the other hand, this embodiment provides a driving method for a pixel circuit, applied to the pixel circuit as described above. The driving method includes: a compensation sub-circuit, under the control of a second scan line, turns on a first node and a fourth node, such that a threshold voltage of the driving sub-circuit is written to the first node; a data writing sub-circuit, under the control of the first scan line, writes a data signal provided by a data line to a third node; a first control sub-circuit, under the control of a first control line, writes a first reference voltage signal provided by a first reference voltage line to the third node, such that the data signal is coupled to the first node through a coupling sub-circuit; and the driving sub-circuit, under the control of the first node, provides a driving signal to the fourth node.

[0025] On the other hand, this embodiment provides a display substrate, including: a plurality of sub-pixels and at least one first scan driving circuit. At least one of the plurality of sub-pixels includes a light-emitting element and a pixel circuit for driving the light-emitting element to emit light. The first scan driving circuit includes: a plurality of first scan driving units. The pixel circuit is as described above. The nth-level first scan driving unit is configured to provide a first scan signal to the pixel circuit of the nth row of sub-pixels; n is an integer greater than 0. The (2i-1)th-level first scan driving unit is cascaded with the (2i+1)th-level first scan driving unit, and the (2i)th-level first scan driving unit is cascaded with the (2i+2)th-level first scan driving unit, where i is an integer greater than 0.

[0026] In some exemplary embodiments, the display substrate further includes a first light-emitting driving circuit, which includes a plurality of cascaded first light-emitting driving units. The nth-level first light-emitting driving unit is configured to provide a first light-emitting control signal to the pixel circuit of the nth row of sub-pixels; or, configured to provide a first light-emitting control signal to the pixel circuits of the (2n-1)th and 2nth rows of sub-pixels.

[0027] In some exemplary embodiments, the display substrate further includes: a second scan driving circuit and a second light-emitting driving circuit; the second scan driving circuit includes a plurality of cascaded second scan driving units; the second light-emitting driving circuit includes a plurality of cascaded second light-emitting driving units. The nth-level second scan driving circuit is configured to provide a second scan signal to the pixel circuits of the (2n-1)th and (2n-th)th row sub-pixels. The nth-level second light-emitting driving circuit is configured to provide a second light-emitting control signal to the pixel circuits of the (2n-1)th and (2n-th)th row sub-pixels. The second scan driving circuit and the second light-emitting driving circuit are located on the same side of the plurality of sub-pixels along the row direction of the sub-pixels.

[0028] In some exemplary embodiments, the display substrate further includes: a first reset driving circuit and a second reset driving circuit; the first reset driving circuit includes a plurality of cascaded first reset driving units; the second reset driving circuit includes a plurality of cascaded second reset driving units. The nth-level first reset driving circuit is configured to provide a first reset control signal to the pixel circuits of the (2n-1)th and (2n-th)th row sub-pixels. The nth-level second reset driving circuit is configured to provide a second reset control signal to the pixel circuits of the (2n-1)th and (2n-th)th row sub-pixels. The first reset driving circuit and the second reset driving circuit are located on different sides of the plurality of sub-pixels along the row direction of the sub-pixels.

[0029] On the other hand, this embodiment provides a display device including the display substrate as described above.

[0030] After reading and understanding the accompanying diagrams and detailed descriptions, the other aspects can be understood.

[0031] Overview of the attached figures

[0032] The accompanying drawings are provided to further understand the technical solutions of this disclosure and constitute a part of the specification. They are used together with the embodiments of this disclosure to explain the technical solutions of this disclosure and do not constitute a limitation on the technical solutions of this disclosure.

[0033] Figure 1 is an equivalent circuit diagram of a pixel circuit;

[0034] Figure 2 is a schematic diagram of the structure of a pixel circuit according to at least one embodiment of the present disclosure;

[0035] Figure 3 is another structural schematic diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0036] Figure 4 is another structural schematic diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0037] Figure 5 is an equivalent circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0038] Figure 6 is a timing diagram of the pixel circuit shown in Figure 5;

[0039] Figure 7 is a schematic diagram of the driving architecture of the pixel circuit of at least one embodiment of the present disclosure;

[0040] Figure 8 is another equivalent circuit diagram of the pixel circuit of at least one embodiment of the present disclosure;

[0041] Figure 9 is a timing diagram of the pixel circuit shown in Figure 8;

[0042] Figure 10 is a schematic diagram of another driving architecture of the pixel circuit according to at least one embodiment of the present disclosure;

[0043] Figure 11 is another equivalent circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0044] Figure 12 is a timing diagram of the pixel circuit shown in Figure 11;

[0045] Figure 13 is a schematic diagram of another driving architecture of the pixel circuit according to at least one embodiment of the present disclosure;

[0046] Figure 14 is another equivalent circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0047] Figure 15 is the timing diagram of the pixel circuit shown in Figure 14;

[0048] Figure 16 is another structural schematic diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0049] Figure 17 is another equivalent circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0050] Figure 18 is a timing diagram of the pixel circuit shown in Figure 17;

[0051] Figure 19 is another equivalent circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0052] Figure 20 is a timing diagram of the pixel circuit shown in Figure 19;

[0053] Figure 21 is another schematic diagram of the pixel circuit according to at least one embodiment of the present disclosure;

[0054] Figure 22 is another equivalent circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0055] Figure 23 is another equivalent circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0056] Figure 24 is a timing diagram of the pixel circuit shown in Figure 23;

[0057] Figure 25 is a schematic diagram of another driving architecture of the pixel circuit according to at least one embodiment of the present disclosure;

[0058] Figure 26 is another equivalent circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0059] Figure 27 is another equivalent circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0060] Figure 28 is a timing diagram of the pixel circuit shown in Figure 27;

[0061] Figure 29 is another equivalent circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0062] Figure 30 is a flowchart of a pixel circuit driving method according to at least one embodiment of the present disclosure;

[0063] Figure 31 is a schematic diagram of a display device according to at least one embodiment of the present disclosure.

[0064] Detailed Explanation

[0065] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings. The implementation can be carried out in many different forms. Those skilled in the art will readily understand that the methods and content can be transformed into other forms without departing from the spirit and scope of this disclosure. Therefore, this disclosure should not be construed as limited to the content described in the following embodiments. Unless otherwise specified, the embodiments and features in the embodiments of this disclosure can be arbitrarily combined with each other.

[0066] In the accompanying drawings, the size of one or more constituent elements, the thickness of layers, or areas are sometimes exaggerated for clarity. Therefore, this disclosure is not necessarily limited to these dimensions, and the shape and size of one or more parts in the drawings do not reflect true proportions. Furthermore, the drawings schematically illustrate ideal examples, and this disclosure is not limited to the shapes or values ​​shown in the drawings.

[0067] The ordinal numbers such as "first," "second," and "third" used in this specification are used to avoid confusion among the constituent elements, not to limit the quantity. The term "multiple" in this disclosure refers to two or more quantities.

[0068] In this specification, for convenience, terms such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer" are used to indicate orientation or positional relationships in conjunction with the accompanying drawings. This is solely for the purpose of facilitating the description and simplification, and does not imply that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this disclosure. The positional relationships of the constituent elements may be appropriately varied depending on the orientation of the constituent elements being described. Therefore, the use of terms not limited to those described in the specification may be appropriately replaced as needed.

[0069] In this specification, unless otherwise expressly specified and limited, the terms "installation," "connection," "linking," and "coupling" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; a mechanical connection or link; a direct connection, an indirect connection via an intermediate component, or a connection within two components. Those skilled in the art will understand the meaning of these terms in this disclosure as appropriate. "Coupling" can include "electrical connection," which can include situations where constituent elements are connected together by a component having some electrical function. There are no particular limitations on the term "component having some electrical function," as long as it allows for the transmission of electrical signals between the connected constituent elements. Examples of "component having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other multifunctional components.

[0070] In this specification, a transistor is a device that includes at least three terminals: a gate (gate electrode), a drain, and a source. A transistor has a channel region between its drain (drain electrode terminal, drain region, or drain electrode) and its source (source electrode terminal, source region, or source electrode), and current can flow through the drain, the channel region, and the source. In this specification, the channel region refers to the region through which current primarily flows.

[0071] In this specification, the first terminal can be the drain and the second terminal can be the source, or vice versa. Additionally, the gate can also be called the control terminal. In cases where transistors with opposite polarities are used or where the current direction changes during circuit operation, the functions of the "source" and "drain" are sometimes interchanged. Therefore, in this specification, the "source" and "drain" can be interchanged.

[0072] In this specification, "approximately" and "about" mean without strictly defined limits, allowing for errors in the process and measurement. In this disclosure, "same" includes values ​​differing by less than 10%, such as values ​​differing by less than 5%.

[0073] In this disclosure, the effective level signal includes the level signal for turning on the transistor. For example, the effective level signal for turning on a P-type transistor is a low level signal, and the effective level signal for turning on an N-type transistor is a high level signal.

[0074] Figure 1 shows an equivalent circuit diagram of a pixel circuit. As shown in Figure 1, the pixel circuit includes seven transistors (i.e., transistors T01 to T07) and a storage capacitor Cst. All seven transistors are of the same type; for example, all seven are P-type transistors. The gates of transistors T02 and T04 are connected to the first gate line GATE1, the gate of transistor T01 is connected to the second gate line GATE2, the gate of transistor T07 is connected to the third gate line GATE3, and the gates of transistors T05 and T06 are connected to the light emission control line EML. In this pixel circuit, the data voltage provided by the data signal line DATA drives transistor T03 to write the data voltage and compensate for the threshold voltage Vth. During the data writing stage, transistors T02 and T04 use the same scan signal provided by the first gate line GATE1 to achieve data writing and threshold voltage compensation.

[0075] However, as the resolution and frequency of display devices increase, the above-mentioned scheme of using data voltage for threshold voltage compensation will encounter driving bottlenecks. For example, as the display refresh rate increases, the data writing time (1H) of a single row of pixel circuits within a frame will gradually decrease. As the data writing time decreases, difficulties in data writing and insufficient threshold voltage compensation will occur.

[0076] This embodiment provides a pixel circuit and its driving method, a display substrate and a display device, which can improve the compensation effect of threshold voltage, thereby improving display performance.

[0077] Figure 2 is a schematic diagram of the structure of a pixel circuit according to at least one embodiment of the present disclosure. In some examples, as shown in Figure 2, the pixel circuit of this embodiment may include at least: a driving sub-circuit 11, a data writing sub-circuit 13, a compensation sub-circuit 12, a coupling sub-circuit 14, and a first control sub-circuit 15. The driving sub-circuit 11 is coupled to a first node N1, a fourth node N4, and a fifth node N5, and is configured to provide a driving signal to the fourth node N4 under the control of the first node N1. The compensation sub-circuit 12 is coupled to a second scan line GL2, the first node N1, and the fourth node N4, and is configured to turn on the first node N1 and the fourth node N4 under the control of the second scan line GL2, so that the threshold voltage of the driving sub-circuit 11 is written to the first node N1. The coupling sub-circuit 14 is coupled to the first node N1 and the third node N3. The data writing sub-circuit 13 is coupled to the first scan line GL1, the data line DL, and the third node N3, and is configured to transmit the data signal provided by the data line DL to the third node N3 under the control of the first scan line GL1. The first control sub-circuit 15 is coupled to the first control line S1, the third node N3 and the first reference voltage line REF1, and is configured to write the first reference voltage signal provided by the first reference voltage line REF1 to the third node N3 under the control of the first control line S1 after the data writing sub-circuit 13 writes the data signal to the third node N3, so that the data signal is coupled to the first node N1 through the coupling sub-circuit 14.

[0078] The pixel circuit provided in this embodiment can separate the data writing process and the threshold voltage compensation process by setting a coupling sub-circuit, which is beneficial to improving the threshold voltage compensation effect and thus improving display performance.

[0079] In some examples, the duration for the data writing sub-circuit 13 to write the data signal to the third node N3 can be less than the duration for the compensation sub-circuit 12 to write the threshold voltage of the driving sub-circuit 11 to the first node N1. The start time for the data writing sub-circuit 13 to write the data signal to the third node N3 can be later than the start time for the compensation sub-circuit 12 to write the threshold voltage of the driving sub-circuit 11 to the first node N1. This example allows for separate control of the data writing process and the threshold voltage compensation process. By increasing the compensation duration of the threshold voltage, the compensation effect of the threshold voltage can be improved, thereby improving the uniformity of the screen display. Moreover, having the data signal written later than the threshold voltage written helps ensure the validity of the data signal.

[0080] In some examples, the first scan line GL1 can be configured to provide a first scan signal, and the second scan line GL2 can be configured to provide a second scan signal. The first scan signal can be configured to control the data writing sub-circuit 13 to write a data signal to the third node N3, and the second scan signal can be configured to control the compensation sub-circuit 12 to write the threshold voltage of the driving sub-circuit 11 to the first node N1. The first scan signal can be different from the second scan signal. For example, the duration of the effective level signal of the first scan signal can be shorter than the duration of the effective level signal of the second scan signal. The first scan signal and the second scan signal can be provided by different scan driving circuits; for example, the first scan signal can be provided by the first scan driving circuit, and the second scan signal can be provided by the second scan driving circuit. This example, by separating the data signal writing and the threshold voltage compensation stage, can increase the compensation time for the threshold voltage, making the threshold voltage compensation time sufficient and improving the compensation effect of the threshold voltage.

[0081] In some examples, the effective level signal provided by the second scan line GL2 can be configured to control the compensation sub-circuit 12 to write the threshold voltage of the driving sub-circuit 11 to the first node N1. The time between the end of the data writing sub-circuit 13 writing the data signal to the third node N3 and the start time of the effective level signal provided by the second scan line GL1 is a first duration, and the time between the end of the data writing sub-circuit 13 writing the data signal to the third node N3 and the end time of the effective level signal provided by the second scan line GL2 is a second duration; the second duration is less than the first duration. In this example, the data writing process is performed in the latter half of the threshold voltage compensation stage, which can increase the compensation time for the threshold voltage, making the threshold voltage compensation time sufficient and improving the compensation effect of the threshold voltage.

[0082] In some examples, the valid level signal provided by the second scan line GL2 can be configured to control the compensation sub-circuit 12 to write the threshold voltage of the driving sub-circuit 11 into the first node N1. The valid level signal provided by the second scan line GL2 can include three equally divided stages: a first signal stage, a second signal stage, and a third signal stage. The start time of the valid level signal provided by the first scan line GL1 can be after the first signal stage. In this example, the data writing process is performed in the latter half of the threshold voltage compensation stage, which can increase the compensation time for the threshold voltage, making the threshold voltage compensation time sufficient and improving the compensation effect.

[0083] Figure 3 is another structural schematic diagram of a pixel circuit according to at least one embodiment of the present disclosure. In some examples, as shown in Figure 3, the pixel circuit of this embodiment may include at least: a driving sub-circuit 11, a data writing sub-circuit 13, a compensation sub-circuit 12, a coupling sub-circuit 14, a first control sub-circuit 15, and a second control sub-circuit 16.

[0084] In some examples, the coupling sub-circuit 14 may include a first coupling sub-circuit 141 and a second coupling sub-circuit 142. The first coupling sub-circuit 141 is coupled to a first node N1 and a second node N2, and the second coupling sub-circuit 142 is coupled to the second node N2 and a third node N3. The second control sub-circuit 16 is coupled to a second control line S2, the second node N2 and the first voltage terminal VL, and is configured to conduct under the control of the second control line S2, such that the second coupling sub-circuit 142 stores the data signal written to the third node N3. The remaining structure of the pixel circuit in this example can be referred to the description of the foregoing embodiments, and will not be repeated here.

[0085] In some examples, the first control line S1 can be configured to provide a first control signal, and the second control line S2 can be configured to provide a second control signal. The first control signal can be configured to control the writing of a first reference voltage signal to the third node N3, and the second control signal can be configured to control the writing of a voltage signal provided by the first voltage terminal VL to the second node N2. The second control signal can be the same as the second scan signal. The first control signal can be the same as the second control signal, or it can be different from the second control signal. For example, the duration of the effective level signal of the first control signal can be greater than or equal to the duration of the effective level signal of the second control signal. In some examples, the first control signal, the second control signal, and the second scan signal can be the same. This example uses the first control signal provided by the first control line S1 to control the potential of the third node N3, which can improve the leakage current of the third node.

[0086] Figure 4 is another structural schematic diagram of a pixel circuit according to at least one embodiment of the present disclosure. In some examples, as shown in Figure 4, the pixel circuit of this embodiment may include: a driving sub-circuit 11, a compensation sub-circuit 12, a data writing sub-circuit 13, a first coupling sub-circuit 141, a second coupling sub-circuit 142, a first control sub-circuit 15, a second control sub-circuit 16, a first light emission control sub-circuit 21, a second light emission control sub-circuit 22, a first reset sub-circuit 23, a second reset sub-circuit 24, and a third reset sub-circuit 25.

[0087] In some examples, the first light-emitting control sub-circuit 21 is coupled to the first light-emitting control line EM1, the first power line VDD, and the fifth node N5, and is configured to write the first power signal provided by the first power line VDD to the fifth node N5 under the control of the first light-emitting control line EM1. The second light-emitting control sub-circuit 22 is coupled to the second light-emitting control line EM2, the fourth node N4, and the sixth node N6, and is configured to turn on the fourth node N4 and the sixth node N6 under the control of the second light-emitting control line EM2. The first reset sub-circuit 23 is coupled to the first reset control line RST1, the first reset voltage line INIT1, and the fourth node N4, and is configured to write the first reset voltage signal provided by the first reset voltage line INIT1 to the fourth node N4 under the control of the first reset control line RST1. The second reset sub-circuit 24 is coupled to the second reset control line RST2, the second reset voltage line INIT2, and the sixth node N6, and is configured to write the second reset voltage signal provided by the second reset voltage line INIT2 to the sixth node N6 under the control of the second reset control line RST2. The third reset sub-circuit 25 is coupled to the second reset control line RST2, the second reference voltage line REF2, and the fifth node N5, and is configured to write the second reference voltage signal provided by the second reference voltage line REF2 to the fifth node N5 under the control of the second reset control line RST2. The first electrode of the light-emitting element is coupled to the sixth node N6, and the second electrode of the light-emitting element is coupled to the second power supply line VSS. The remaining structure of the pixel circuit in this example can be referred to the description of the foregoing embodiments, and will not be repeated here.

[0088] In some examples, the light-emitting element can be an organic light-emitting diode (OLED). The first electrode of the light-emitting element can be an anode, and the second electrode can be a cathode. However, this embodiment is not limited to this.

[0089] In some examples, the second reset sub-circuit 24 resets the sixth node N6, eliminating leakage current in the second light-emitting control sub-circuit 22. This prevents the light-emitting element from emitting light in the dark due to the leakage current, improving display quality. Furthermore, it eliminates residual positive charge on the surface of the first electrode of the light-emitting element, extending its lifespan. The third reset sub-circuit 25 can write a second reference voltage to the fifth node N5, resetting it. The first reset sub-circuit 23 can reset the fourth node N4.

[0090] In some examples, the first light-emitting control line EM1 can be configured to provide a first light-emitting control signal, and the second light-emitting control line EM2 can be configured to provide a second light-emitting control signal. The first light-emitting control signal can be configured to control the first light-emitting control sub-circuit 21 to write a first power signal to the fifth node N5, and the second light-emitting control signal can be configured to control the second light-emitting control sub-circuit 22 to conduct the fourth node N4 and the sixth node N6, thereby providing a driving signal to the light-emitting element, causing the light-emitting element to emit light. The first light-emitting control signal can be different from the second light-emitting control signal. For example, the first control signal can be the same as the first light-emitting control signal, or the first control signal can be the same as the second light-emitting control signal. The first light-emitting control signal and the second light-emitting control signal can be provided by different light-emitting driving circuits; for example, the first light-emitting control signal can be provided by the first light-emitting driving circuit, and the second light-emitting control signal can be provided by the second light-emitting driving circuit.

[0091] In some examples, the first reset control line RST1 can be configured to provide a first reset control signal, and the second reset control line RST2 can be configured to provide a second reset control signal. The first reset control signal can be configured to control the first reset sub-circuit 23 to reset the fourth node N4, the second reset control signal can be configured to control the second reset sub-circuit 24 to reset the sixth node N6, and the third reset sub-circuit 25 to reset the fifth node N5. The first reset control signal may be different from the second reset control signal. The first reset control signal and the second reset control signal may be provided by different reset drive circuits; for example, the first reset control signal may be provided by the first reset drive circuit, and the second reset control signal may be provided by the second reset drive circuit.

[0092] In some examples, the first power line VDD can continuously provide a constant high-level signal; for example, the first power line VDD can provide a first power signal. The second power line VSS can continuously provide a constant low-level signal; for example, the second power line VSS can provide a second power signal. The first power signal can be greater than the second power signal.

[0093] In some examples, the first voltage terminal VL can be coupled to a trace providing a regulated signal to stabilize the potential of the second node N2. For instance, the first voltage terminal VL can be coupled to the first power supply line VDD.

[0094] In some examples, the first reference voltage line REF1 can be configured to provide a first reference voltage signal, and the second reference voltage line REF2 can be configured to provide a second reference voltage signal. The first reference voltage signal and the second reference voltage signal can be different. For example, both the first reference voltage signal and the second reference voltage signal can be less than the first power supply signal.

[0095] In some examples, the first reset voltage line INIT1 can be configured to provide a first reset voltage signal, and the second reset voltage line INIT2 can be configured to provide a second reset voltage signal. The first reset voltage signal and the second reset voltage signal can be the same or different. This embodiment is not limited in this respect.

[0096] Figure 5 is an equivalent circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure. In some examples, as shown in Figure 5, the driving sub-circuit 11 may include a driving transistor T3; the compensation sub-circuit 12 may include a compensation transistor T2; the data writing sub-circuit 13 may include a data writing transistor T4; the first coupling sub-circuit 141 may include a first capacitor C1; the second coupling sub-circuit 142 may include a second capacitor C2; the first control sub-circuit 15 may include a first control transistor T10; the second control sub-circuit 16 may include a second control transistor T9; the first light emission control sub-circuit 21 may include a first light emission control transistor T5; the second light emission control sub-circuit 22 may include a second light emission control transistor T6; the first reset sub-circuit 23 may include a first reset transistor T1; the second reset sub-circuit 24 may include a second reset transistor T7; and the third reset circuit 25 may include a third reset transistor T8.

[0097] In some examples, as shown in Figure 5, the gate of driving transistor T3 is coupled to the first node N1, the first electrode of driving transistor T3 is coupled to the fifth node N5, and the second electrode of driving transistor T3 is coupled to the fourth node T4. The gate of compensation transistor T2 is coupled to the second scan line GL2, the first electrode of compensation transistor T2 is coupled to the fourth node N4, and the second electrode of compensation transistor T2 is coupled to the first node N1. The gate of data writing transistor T4 is coupled to the first scan line GL1, the first electrode of data writing transistor T4 is coupled to the data line DL, and the second electrode of data writing transistor T4 is coupled to the third node N3. The first electrode of the first capacitor C1 is coupled to the first node N1, and the second electrode of the first capacitor C1 is coupled to the second node N2. The first electrode of the second capacitor C2 is coupled to the second node N2, and the second electrode of the second capacitor C2 is coupled to the third node N3. The gate of the second control transistor T9 is coupled to the second control line S2, the first terminal of the second control transistor T9 is coupled to the first power supply line VDD (i.e., the first voltage terminal is coupled to the first power supply line VDD), and the second terminal of the second control transistor T9 is coupled to the second node N2. The gate of the first control transistor T10 is coupled to the first control line S1, the first terminal of the first control transistor T10 is coupled to the first reference voltage line REF1, and the second terminal of the first control transistor T10 is coupled to the third node N3. The gate of the first light-emitting control transistor T5 is coupled to the first light-emitting control line EM1, the first terminal of the first light-emitting control transistor T5 is coupled to the first power supply line VDD, and the second terminal of the first light-emitting control transistor T5 is coupled to the fifth node N5. The gate of the second light-emitting control transistor T6 is coupled to the second light-emitting control line EM2, the first terminal of the second light-emitting control transistor T6 is coupled to the fourth node N4, and the second terminal of the second light-emitting control transistor T6 is coupled to the sixth node N6. The gate of the first reset transistor T1 is coupled to the first reset control line RST1, the first electrode of the first reset transistor T1 is coupled to the first reset voltage line INIT1, and the second electrode of the first reset transistor T1 is coupled to the fourth node N4. The gate of the second reset transistor T7 is coupled to the second reset control line RST2, the first electrode of the second reset transistor T7 is coupled to the second reset voltage line INIT2, and the second electrode of the second reset transistor T7 is coupled to the sixth node N6. The gate of the third reset transistor T8 is coupled to the second reset control line RST2, the first electrode of the third reset transistor T8 is coupled to the second reference voltage line REF2, and the second electrode of the third reset transistor T8 is coupled to the fifth node N5. The first electrode of the light-emitting element EL is coupled to the sixth node N6, and the second electrode of the light-emitting element EL is coupled to the second power supply line VSS.

[0098] In some examples, the first node N1 is the connection point of the first capacitor C1, the compensation transistor T2, and the driving transistor T3. The second node N2 is the connection point of the first capacitor C1, the second capacitor C2, and the second control transistor T9. The third node N3 is the connection point of the second capacitor C2, the data writing transistor T4, and the first control transistor T10. The fourth node N4 is the connection point of the first reset transistor T1, the compensation transistor T2, the driving transistor T3, and the second light-emitting control transistor T6. The fifth node N5 is the connection point of the first light-emitting control transistor T5, the third reset transistor T8, and the driving transistor T3. The sixth node N6 is the connection point of the second light-emitting control transistor T6, the second reset transistor T7, and the light-emitting element EL.

[0099] Figure 5 shows an exemplary structure of the driving sub-circuit 11, compensation sub-circuit 12, data writing sub-circuit 13, first coupling sub-circuit 141, second coupling sub-circuit 142, first control sub-circuit 15, second control sub-circuit 16, first light-emitting control sub-circuit 21, second light-emitting control sub-circuit 22, first reset sub-circuit 23, second reset sub-circuit 24, and third reset sub-circuit 25. It is readily understood by those skilled in the art that the implementation of the above sub-circuits is not limited to this, as long as their functions can be achieved.

[0100] In some examples, as shown in Figure 5, the compensation transistor T2 and the second control transistor T9 can be N-type thin-film transistors, such as oxide thin-film transistors; the first reset transistor T1, the driving transistor T3, the data writing transistor T4, the first light-emitting control transistor T5, the second light-emitting control transistor T6, the second reset transistor T7, the third reset transistor T8, and the first control transistor T10 can be P-type thin-film transistors, such as low-temperature polycrystalline silicon (LTPS) thin-film transistors. The active layer of the LTPS thin-film transistor can be made of low-temperature polycrystalline silicon (LTPS), while the active layer of the oxide thin-film transistor can be made of oxide semiconductor (Oxide). LTPS thin-film transistors have advantages such as high mobility and fast charging, while oxide thin-film transistors have advantages such as low leakage current. Integrating LTPS and oxide thin-film transistors onto a single display substrate to form a low-temperature polycrystalline oxide (LTPO) display substrate can leverage the advantages of both, reducing power consumption and improving display quality.

[0101] Figure 6 is a timing diagram of the pixel circuit shown in Figure 5. As shown in Figure 5, the pixel circuit of this example may include: 10 transistors (i.e., transistors T1 to T10), 2 capacitor units (i.e., first capacitor C1 and second capacitor C2), 13 input terminals (i.e., data line DL, first scan line GL1, second scan line GL2, first control line S1, second control line S2, first light emission control line EM1, second light emission control line EM2, first reset control line RST1, second reset control line RST2, first reference voltage line REF1, second reference voltage line REF2, first reset voltage line INIT1 and second reset voltage line INIT2), and 2 power supply terminals (i.e., first power supply line VDD and second power supply line VSS).

[0102] In some examples, as shown in Figure 6, the operation of the pixel circuit within a frame time period may include the following stages. In this example, the second control line S2 and the second scan line GL2 can be configured to provide the same signal; that is, the second control signal provided by the second control line S2 and the second scan signal provided by the second scan line GL2 can be the same. The gate of the second control transistor T9 can be coupled to the second scan line GL2, and the first terminal of the second control transistor T9 can be coupled to the first power supply line VDD.

[0103] The first stage t11 can also be called the first reset stage. The first reset signal provided by the first reset control line RST1 is low, and the first reset transistor T1 is turned on. The second scan signal provided by the second scan line GL2 is high, and both the compensation transistor T2 and the second control transistor T9 are turned on. The first reset voltage signal provided by the first reset voltage line INIT1 can be provided to the first node N1 through the turned-on first reset transistor T1 and compensation transistor T2, causing the first node N1 to reset to the first reset voltage Vinit1. The first power supply signal provided by the first power supply line VDD can be provided to the second node N2 through the turned-on second control transistor T9, and the voltage of the second node N2 is the first power supply voltage Vdd. The first control signal provided by the first control line S1 is low, the first control transistor T10 is turned on, and the first reference voltage signal provided by the first reference voltage line REF1 is provided to the third node N3, and the voltage of the third node N3 is the first reference voltage Vref1.

[0104] In the first stage t11, the first light emission control signal provided by the first light emission control line EM1 is at a high level, and the first light emission control transistor T5 is turned off; the second light emission control signal provided by the second light emission control line EM2 is at a high level, and the second light emission control transistor T6 is turned off; the second reset control signal provided by the second reset control line RST2 is at a high level, and both the second reset transistor T7 and the third reset transistor T8 are turned off; the first scan signal provided by the first scan line GL1 is at a high level, and the data writing transistor T4 is turned off.

[0105] During the transition phase between the first stage t11 and the second stage t12, the second scan signal provided by the second scan line GL2 jumps to a low level, the first reset control signal provided by the first reset control line RST1 jumps to a high level, the second reset control signal provided by the second reset control line RST2 jumps to a low level, and the remaining signals remain in the state of the first stage t11.

[0106] The second stage, t12, can also be called the second reset stage or the first bias stage. The second reset control signal provided by the second reset control line RST2 is low, and both the second reset transistor T7 and the third reset transistor T8 are turned on. The second reset voltage signal provided by the second reset voltage line INIT2 is written to the sixth node N6 through the turned-on second reset transistor T7. The voltage at the sixth node N6 is the second reset voltage Vinit2, thus resetting the first electrode of the light-emitting element EL. The second reference voltage signal provided by the second reference voltage line REF2 is written to the fifth node N5 through the turned-on third reset transistor T8. The voltage at the fifth node N5 is the second reference voltage Vref2. The second scan signal provided by the second scan line GL2 is low, and both the compensation transistor T2 and the second control transistor T9 are turned off. The first reset control signal provided by the first reset control line RST1 is high, and the first reset transistor T1 is turned off. In this stage, the driving transistor T3 is in a biased state.

[0107] During the transition between the second stage t12 and the third stage t13, the first light emission control signal provided by the first light emission control line EM1 jumps to a low level, the second scan signal provided by the second scan line GL2 jumps to a high level, the second reset control signal provided by the second reset control line RST2 jumps to a high level, and the remaining signals remain in the state of the second stage t12.

[0108] The third stage, t13, can also be called the threshold compensation stage. The second scan signal provided by the second scan line GL2 is high, and both the compensation transistor T2 and the second control transistor T9 are turned on. The first node N1 and the fourth node N4 are connected through the conducting compensation transistor T2. The first power signal provided by the first power line VDD can be provided to the second node N2 through the conducting second control transistor T9, and the voltage of the second node N2 is the first power supply voltage Vdd. The first light emission control signal provided by the first light emission control line EM1 is low, and the first light emission control transistor T5 is turned on. The first power signal provided by the first power line VDD is provided to the fifth node N5 through the conducting first light emission control transistor T5. In this stage, the driving transistor T3 is turned on, and the first power signal provided by the first power line VDD is used to perform threshold compensation on the driving transistor T3, writing the threshold voltage Vth of the driving transistor T3 into the first node N1. The voltage of the first node N1 is Vdd + Vth, where Vdd is the first power supply voltage of the first power signal provided by the first power line VDD. The second reset control signal provided by the second reset control line RST2 is high, and the second reset transistor T7 and the third reset transistor T8 are turned off. The remaining transistors remain in the state of the second stage t12.

[0109] The fourth stage, t14, can also be called the data writing stage. The first scan signal provided by the first scan line GL1 goes low, turning on the data writing transistor T4. The data signal provided by the data line DL is written to the third node N3 through the activated data writing transistor T4. The first control signal provided by the first control line S1 goes high, turning off the first control transistor T10. The remaining transistors maintain the state of the third stage, t13.

[0110] During the transition between stage t14 (fourth stage) and stage t15 (fifth stage), the first scan signal provided by the first scan line GL1 goes high, the second scan signal provided by the second scan line GL2 goes low, the first control signal provided by the first control line S1 goes low, the first light emission control signal provided by the first light emission control line EM1 goes high, and the second reset control signal provided by the second reset control line RST2 goes low. The remaining signals remain in the state of stage t14.

[0111] The fifth stage, t15, can also be called the second bias stage. The second reset control signal provided by the second reset control line RST2 is low, and both the second reset transistor T7 and the third reset transistor T8 are turned on. The second scan signal provided by the second scan line GL2 is low, and both the compensation transistor T2 and the second control transistor T9 are turned off. The first scan signal provided by the first scan line GL1 is high, and the data writing transistor T4 is turned off. The first light emission control signal provided by the first light emission control line EM1 is high, and the first light emission control transistor T5 is turned off. The first control signal provided by the first control line S1 is low, and the first control transistor T10 is turned on. The second reference voltage signal provided by the second reference voltage line REF2 can be provided to the third node N3 through the turned-on first control transistor T10. The second control transistor T9 is turned off, and the second node N2 is floating. The data signal written to the third node N3 during the data writing stage can be coupled to the first node N1 through the second capacitor C2 and the first capacitor C1. In this stage, the driving transistor T3 is in a biased state. The second light emission control transistor T6 is in a turned-off state, and the first reset transistor T1 is in a turned-off state.

[0112] The sixth stage, t16, can also be called the light-emitting stage. The first control signal provided by the first control line S1 is low, the first control transistor T10 is turned on, and the voltage of the third node N3 remains at the first reference voltage Vref1. The first light-emitting control signal provided by the first light-emitting control line EM1 is low, and the first light-emitting control transistor T5 is turned on; the second light-emitting control signal provided by the second light-emitting control line EM2 is low, and the second light-emitting control transistor T6 is turned on. The compensation transistor T2, the second control transistor T9, the data writing transistor T4, the first reset transistor T1, the second reset transistor T7, and the third reset transistor T8 are all turned off. In this stage, the driving transistor T3 is turned on. The first node N1 can simultaneously record the compensation information for both the data voltage and the threshold voltage. The voltage of the first node N1 is Vdd + Vth + Vref1 - Vdata, where Vdata is the data voltage. The gate-source voltage difference of the driving transistor T3 is Vgs = Vdd + Vth + Vref1 - Vdata - Vdd = Vth + Vref1 - Vdata. During the pixel circuit's driving process, the driving current flowing through the driving transistor T3 is determined by its gate-source voltage difference. Therefore, the driving current of the driving transistor T3 is: Id = 0.5 × K × (Vgs - Vth) 2 =0.5×K×(Vth+Vref1-Vdata-Vth) 2 = 0.5 × K × (Vref1 - Vdata) 2 .

[0113] Where K is a constant.

[0114] In this example, the driving signal output by the driving transistor T3 is independent of the threshold voltage Vth of the driving transistor T3, which can eliminate the influence of the threshold voltage of the driving transistor on the driving signal, thereby ensuring uniform display brightness and improving the display effect.

[0115] In the pixel circuit timing example, during the first bias stage (i.e., the second stage t12) and the second bias stage (i.e., the fifth stage t15), the driving transistor T3 can be in a biased state, which can serve to calibrate the voltage and improve image retention. In other examples, only the first bias stage or the second bias stage can be set in the pixel circuit timing.

[0116] In the pixel circuit operation timing of this example, the threshold voltage and data signal of the driving transistor T3 can be written to the first node N1 and the third node N3, respectively. By controlling the second node N2 with the second control transistor T9 and the third node N3 with the first control transistor T10, the data signal can be written from the third node N3 to the first node N1, thus realizing the data signal writing. This example separates the charging process of writing the data signal to the first node from the threshold voltage compensation process, allowing for flexible control of the threshold compensation duration and improving the threshold voltage compensation effect.

[0117] In some examples, the valid level signal provided by the first scan line GL1 (a low level signal in this example) can be configured to control the data writing transistor T4 to write the data signal to the third node N3. The valid level signal provided by the second scan line GL2 (a high level signal in this example) can be configured to control the compensation transistor T2 to write the threshold voltage of the driving transistor T3 to the first node N1. The time between the end of the data writing transistor T4 writing the data signal to the third node N3 and the start of the valid level signal provided by the second scan line GL2 can be a first duration L1, and the time between the end of the data writing transistor T4 writing the data signal to the third node N3 and the end of the valid level signal provided by the second scan line GL2 can be a second duration L2. The second duration L2 is less than the first duration L1. For example, the second duration L2 can be 0.

[0118] In some examples, the effective level signal provided by the second scan line GL2 may include three equally divided phases: a first signal phase X1, a second signal phase X2, and a third signal phase X3, with the start time of the effective level signal provided by the first scan line GL1 following the first signal phase X1. For example, the start time of the effective level signal provided by the first scan line GL1 may follow the second signal phase X2.

[0119] This example performs the data writing process in the latter half of the threshold voltage compensation stage, which can increase the compensation time for the threshold voltage, ensuring sufficient compensation time and improving the compensation effect.

[0120] This example demonstrates how setting a first capacitor C1 and a second capacitor C2 can effectively maintain the written data signal and ensure the writing effect of the data signal.

[0121] In the pixel circuit provided in this example, the compensation transistor T2 and the second control transistor T9 are oxide thin film transistors, which can prevent leakage current from the first node N1 and the second node N2, thus helping to ensure circuit performance.

[0122] Figure 7 is a schematic diagram of a driving architecture for a pixel circuit according to at least one embodiment of the present disclosure. In some examples, as shown in Figure 7, the display substrate may include multiple sub-pixels and multiple gate driving circuits. The multiple sub-pixels may be arranged in an array along a first direction X and a second direction Y. The first direction X may intersect with the second direction Y; for example, the first direction X may be perpendicular to the second direction Y. The multiple sub-pixels arranged along the first direction X constitute a row of sub-pixels, and the multiple sub-pixels arranged along the second direction Y constitute a column of sub-pixels. The first direction X may also be referred to as the row direction, and the second direction Y may also be referred to as the column direction. A sub-pixel may include a pixel circuit and a light-emitting element electrically connected to the pixel circuit. The pixel circuit may be configured to drive the light-emitting element to emit light.

[0123] In some examples, the light-emitting element can be any of the following: a light-emitting diode (LED), an organic light-emitting diode (OLED), a quantum dot light-emitting diode (QLED), or a micro-LED (including mini-LED or micro-LED). For example, the light-emitting element can be an OLED, which can emit red, green, blue, or white light under the drive of its corresponding pixel circuit. The color of the light emitted by the light-emitting element can be determined as needed. In some examples, the light-emitting element may include an anode, a cathode, and an organic light-emitting layer located between the anode and cathode. The anode of the light-emitting element can be electrically connected to the corresponding pixel circuit. However, this embodiment is not limited in this respect.

[0124] In some examples, the display substrate may include a display area and a bezel area located on at least one side of the display area. Multiple sub-pixels may be located in the display area, and multiple gate driving circuits may be located in the bezel areas on both sides of the display area along a first direction X. However, this embodiment is not limited to this. In other examples, both the multiple sub-pixels and the multiple gate driving circuits may be located in the display area to achieve a narrow bezel design.

[0125] In some examples, the pixel circuitry included in a sub-pixel is shown in Figure 5. As shown in Figure 7, multiple gate driving circuits may include: a first scan driving circuit (e.g., including first scan driving circuits 31a and 31b), a second scan driving circuit 32, a first light-emitting driving circuit 33, a second light-emitting driving circuit 34, a first reset driving circuit 35, a second reset driving circuit 36, and a first control driving circuit 37.

[0126] In some examples, the first scan driving circuits 31a and 31b can be configured to provide a first scan signal to the pixel circuits of multiple sub-pixels via a first scan line; the second scan driving circuit 32 can be configured to provide a second scan signal to the pixel circuits of multiple sub-pixels via a second scan line; the first light emission driving circuit 33 can be configured to provide a first light emission control signal to the pixel circuits of multiple sub-pixels via a first light emission control line; the second light emission driving circuit 34 can be configured to provide a second light emission control signal to the pixel circuits of multiple sub-pixels via a second light emission control line; the first reset driving circuit 35 can be configured to provide a first reset control signal to the pixel circuits of multiple sub-pixels via a first reset control line; the second reset driving circuit 36 ​​can be configured to provide a second reset control signal to the pixel circuits of multiple sub-pixels via a second reset control line; and the first control driving circuit 37 can be configured to provide a first control signal to the pixel circuits of multiple sub-pixels via a first control line. In this example, the second control signal can be the same as the second scan signal.

[0127] In some examples, as shown in Figure 7, the first scanning driving circuits 31a and 31b can be located on both sides of multiple sub-pixels along the first direction X, for example, within the border areas of the display area along the first direction X. For instance, the first scanning driving circuit 31a can be located in the left border area, and the first scanning driving circuit 31b can be located in the right border area. The first light-emitting driving circuit 33 and the second light-emitting driving circuit 34 can be located on different sides of the multiple sub-pixels along the first direction X; the first reset driving circuit 35 and the second reset driving circuit 36 ​​can be located on different sides of the multiple sub-pixels along the first direction X.

[0128] In some examples, the first scan driving circuit 31a, the first light-emitting driving circuit 33, the first control driving circuit 37, and the second reset driving circuit 36 ​​can be located on the same side of multiple sub-pixels along the first direction X, for example, all located in the left border region. Within the left border region, the first scan driving circuit 31a, the first light-emitting driving circuit 33, the first control driving circuit 37, and the second reset driving circuit 36 ​​can be sequentially arranged along a direction away from the sub-pixels. The first scan driving circuit 31b, the second light-emitting driving circuit 34, the first reset driving circuit 35, and the second scan driving circuit 32 can be located on the same side of multiple sub-pixels along the first direction X, for example, all located in the right border region. Within the right border region, the first scan driving circuit 31b, the second light-emitting driving circuit 34, the first reset driving circuit 35, and the second scan driving circuit 32 can be sequentially arranged along a direction away from the sub-pixels. In this example, the first scan signal can be driven from both sides, and the remaining signals can be driven from one side. In other examples, the first scan signal can be driven from one side. The arrangement of the multiple gate driving circuits in this example facilitates wiring layout.

[0129] In some examples, the first scan driving circuits 31a and 31b may each include multiple first scan driving units. These multiple first scan driving units can be arranged at intervals along the second direction Y. The nth level first scan driving unit can be configured to provide a first scan signal to the pixel circuit of the nth row of sub-pixels, where n is an integer greater than 0. Specifically, the (2i-1)th level first scan driving unit is cascaded with the (2i+1)th level first scan driving unit, and the 2ith level first scan driving unit is cascaded with the (2i+2)th level first scan driving unit, where i is an integer greater than 0. For example, the first scan driving units of odd-numbered rows (first, third, fifth, seventh, etc.) can be cascaded sequentially; the first scan driving units of even-numbered rows (second, fourth, sixth, eighth, etc.) can be cascaded sequentially. In this example, the first scan area units are cascaded separately for odd and even rows, which allows for overlap of the effective level signals output by adjacent rows of first scan driving units, providing sufficient time for data signal writing and resulting in a smaller rise time (Tr) / fall time (Tf) ratio for the output signal.

[0130] In some examples, the second scan driving circuit 32 may include a plurality of cascaded second scan driving units. The nth-level second scan driving circuit may be configured to provide second scan signals to the pixel circuits of two rows (e.g., the 2n-1th row and the 2nth row, or the nth row and the n+1th row); the n+1th-level second scan driving circuit may be configured to provide second scan signals to the pixel circuits of two rows (e.g., the n+2th row and the n+3th row).

[0131] In some examples, the first light-emitting driving circuit 33 may include a plurality of cascaded first light-emitting driving units. The nth-level first light-emitting driving unit may be configured to provide a first light-emitting control signal to the pixel circuits of two rows (e.g., the 2n-1th row and the 2nth row, or the nth row and the n+1th row) of sub-pixels; the n+1th-level first light-emitting driving unit may be configured to provide a first light-emitting control signal to the pixel circuits of two rows (e.g., the n+2th row and the n+3th row) of sub-pixels.

[0132] In some examples, the second light-emitting driving circuit 34 may include a plurality of cascaded second light-emitting driving units. The nth-level second light-emitting driving unit may be configured to provide a second light-emitting control signal to the pixel circuits of two rows (e.g., the 2n-1th row and the 2nth row, or the nth row and the n+1th row) of sub-pixels; the n+1th-level second light-emitting driving unit may be configured to provide a second light-emitting control signal to the pixel circuits of two rows (e.g., the n+2th row and the n+3th row) of sub-pixels.

[0133] In some examples, the first reset drive circuit 35 may include a plurality of cascaded first reset drive units. The nth-level first reset drive unit may be configured to provide a first reset control signal to the pixel circuits of two rows (e.g., row 2n-1 and row 2n, or row n and row n+1) of sub-pixels; the n+1th-level first reset drive unit may be configured to provide a first reset control signal to the pixel circuits of two rows (e.g., row n+2 and row n+3) of sub-pixels.

[0134] In some examples, the second reset driving circuit 36 ​​may include a plurality of cascaded second reset driving units. The nth-level second reset driving unit may be configured to provide a second reset control signal to the pixel circuits of two rows (e.g., row 2n-1 and row 2n, or row n and row n+1) of sub-pixels; the n+1th-level second reset driving unit may be configured to provide a second reset control signal to the pixel circuits of two rows (e.g., row n+2 and row n+3) of sub-pixels.

[0135] In some examples, the first control drive circuit 37 may include a plurality of cascaded first control drive units. The nth-level first control drive unit may be configured to provide a first control signal to the pixel circuit of two rows (e.g., row 2n-1 and row 2n, or row n and row n+1) of sub-pixels; the n+1th-level first control drive unit may be configured to provide a first control signal to the pixel circuit of two rows (e.g., row n+2 and row n+3) of sub-pixels.

[0136] In this example, the first scan driving circuits 31a and 31b can drive the pixel circuits of odd-numbered and even-numbered rows separately. The second scan driving circuit 32, the first light-emitting driving circuit 33, the second light-emitting driving circuit 34, the first reset driving circuit 35, the second reset driving circuit 36, and the first control driving circuit 37 all use one driving unit to drive the pixel circuits of two rows of sub-pixels. When using one driving unit to drive the pixel circuits of two rows of sub-pixels, the signal generated by the driving unit can be shifted according to 2H, which can achieve a driving cycle of 2H, thus facilitating high-frequency display. In other examples, when using one driving unit to drive the pixel circuits of one row of sub-pixels, the signal generated by the driving unit can be shifted according to 1H.

[0137] Figure 8 is another equivalent circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure. In some examples, as shown in Figure 8, the pixel circuit of this example may include: a driving transistor T3, a compensation transistor T2, a data writing transistor T4, a first light-emitting control transistor T5, a second light-emitting control transistor T6, a first reset transistor T1, a second reset transistor T7, a third reset transistor T8, a second control transistor T9, a first control transistor T10, a first capacitor C1, and a second capacitor C2. The gates of the first control transistor T10, the second control transistor T9, and the compensation transistor T2 are all coupled to the second scan line GL2. In this example, the second control line S2, the first control line S1, and the second scan line GL2 may be configured to provide the same signal. In other words, the second scan signal, the first control signal, and the second control signal in this example may be the same. Further description of the pixel circuit of this example can be found in the description of the foregoing embodiments, and will not be repeated here.

[0138] Figure 9 is a timing diagram of the pixel circuit shown in Figure 8. As shown in Figure 8, the pixel circuit in this example may include: 10 transistors (i.e., transistors T1 to T10), 2 capacitor units (i.e., first capacitor C1 and second capacitor C2), 11 input terminals (i.e., data line DL, first scan line GL1, second scan line GL2, first light emission control line EM1, second light emission control line EM2, first reset control line RST1, second reset control line RST2, first reference voltage line REF1, second reference voltage line REF2, first reset voltage line INIT1 and second reset voltage line INIT2), and 2 power supply terminals (i.e., first power supply line VDD and second power supply line VSS). In this example, the compensation transistor T2 and the second control transistor T9 are N-type transistors, and the remaining transistors are P-type transistors.

[0139] In some examples, as shown in Figure 9, the operation of a pixel circuit can include the following stages within a frame time period. This example illustrates the operation of the pixel circuit for the nth row sub-pixel.

[0140] The first stage t21 can also be called the first reset stage. The first reset control signal provided by the first reset control line RST1 is low, and the first reset transistor T1 is turned on. The second scan signal provided by the second scan line GL2 is high, turning on the compensation transistor T2 and the second control transistor T9, while turning off the first control transistor T10. The first light emission control signal provided by the first light emission control line EM1 is high, and the first light emission control transistor T5 is turned off. The second light emission control signal provided by the second light emission control line EM2 is high, and the second light emission control transistor T6 is turned off. The second reset control signal provided by the second reset control line RST2 is high, and both the second reset transistor T7 and the third reset transistor T8 are turned off. The first scan signal provided by the first scan line GL1(n) is high, and the data writing transistor T4 is turned off. In this stage, the first node N1 is reset to the first reset voltage Vinit1.

[0141] The second stage, t22, can also be called the second reset stage or the first bias stage. The second reset control signal provided by the second reset control line RST2 is low, and both the second reset transistor T7 and the third reset transistor T8 are turned on. The sixth node N6 is reset to the second reset voltage Vinit2, and the voltage of the fifth node N5 is the second reference voltage Vref2. The second scan signal provided by the second scan line GL2 is low, the compensation transistor T2 and the second control transistor T9 are turned off, the first control transistor T10 is turned on, and the voltage of the third node N3 is the first reference voltage Vref1. The data write transistor T4, the first reset transistor T1, the first light-emitting control transistor T5, and the second light-emitting control transistor T6 are all turned off. During this stage, the driving transistor T3 is in a biased state.

[0142] The third stage, t23, can also be called the threshold compensation stage. The second scan signal provided by the second scan line GL2 is high, and both compensation transistor T2 and the second control transistor T9 are turned on, while the first control transistor T10 is turned off. The first light-emitting control signal provided by the first light-emitting control line EM1 is low, and the first light-emitting control transistor T5 is turned on, writing the first power signal provided by the first power line VDD to the fifth node N5. Data writing transistor T4, the second light-emitting control transistor T6, the first reset transistor T1, the second reset transistor T7, and the third reset transistor T8 are all turned off. In this stage, the driving transistor T3 is turned on, and the threshold voltage Vth of the driving transistor T3 is written to the first node N1.

[0143] The fourth stage, t24, can also be called the data writing stage. The first scan signal provided by the first scan line GL1(n) goes low, the data writing transistor T4 turns on, and the data signal provided by the data line DL is written to the third node N3 through the turned-on data writing transistor T4. The remaining transistors remain in the state of the third stage, t23.

[0144] The fifth stage, t25, can also be called the second bias stage. The second reset control signal provided by the second reset control line RST2 is low, and both the second reset transistor T7 and the third reset transistor T8 are turned on. The second scan signal provided by the second scan line GL2 is low, and both the compensation transistor T2 and the second control transistor T9 are turned off. The first control transistor T10 is turned on, writing the first reference voltage Vref1 to the third node N3, causing the data signal to couple to the first node N1. The first light-emitting control transistor T5, the second light-emitting control transistor T6, the first reset transistor T1, and the data writing transistor T4 are all turned off. In this stage, the driving transistor T3 is in a biased state.

[0145] The sixth stage, t26, can also be called the light-emitting stage. The second scan signal provided by the second scan line GL2 is at a low level. Compensation transistor T2 and the second control transistor T9 are both off, while the first control transistor T10 is on. The voltage at the third node N3 remains at the first reference voltage Vref1, which helps improve the leakage current at the third node N3. The first light-emitting control transistor T5 and the second light-emitting control transistor T6 are both on; compensation transistor T2, the second control transistor T9, the data writing transistor T4, the first reset transistor T1, the second reset transistor T7, and the third reset transistor T8 are all off. In this stage, the driving transistor T3 is on. The gate-source voltage difference of the driving transistor T3 is Vgs = Vdd + Vth + Vref1 - Vdata - Vdd = Vth + Vref1 - Vdata. The driving current of the driving transistor T3 is: Id = 0.5 × K × (Vgs - Vth). 2 =0.5×K×(Vth+Vref1-Vdata-Vth) 2 = 0.5 × K × (Vref1 - Vdata) 2 .

[0146] Where K is a constant, Vdata is the data voltage, Vref1 is the first reference voltage, and Vth is the threshold voltage.

[0147] In this example, the driving signal output by the driving transistor T3 is independent of the threshold voltage Vth of the driving transistor T3, which can eliminate the influence of the threshold voltage of the driving transistor on the driving signal, thereby ensuring uniform display brightness and improving the display effect.

[0148] This example separates the data signal writing process of the first node's charging process from the threshold voltage compensation process, allowing for flexible control of the threshold compensation duration and improving the threshold voltage compensation effect. In the pixel circuit of this example, the second scan signal is used to simultaneously control the compensation transistor, the first control transistor, and the second control transistor, which helps save signal sources and wiring, and improves the leakage current of the third node N3.

[0149] Figure 10 is a schematic diagram of another driving architecture of a pixel circuit according to at least one embodiment of the present disclosure. In some examples, as shown in Figure 10, taking the pixel circuit including a sub-pixel as shown in Figure 8 as an example, the multiple gate driving circuits in this example may include: a first scan driving circuit 31, a second scan driving circuit 32, a first light-emitting driving circuit 33, a second light-emitting driving circuit 34, a first reset driving circuit 35, and a second reset driving circuit 36.

[0150] In some examples, the first scan driving circuit 31 and the second scan driving circuit 32 may be located on different sides of multiple sub-pixels along the first direction X, the first light emission driving circuit 33 and the second light emission driving circuit 34 may be located on different sides of multiple sub-pixels along the first direction X, and the first reset driving circuit 35 and the second reset driving circuit 36 ​​may be located on different sides of multiple sub-pixels along the first direction X.

[0151] In some examples, the first scan driving circuit 31, the first light-emitting driving circuit 33, and the second reset driving circuit 36 ​​can be located on the same side of multiple sub-pixels along the first direction X, for example, all located in the left border region. Within the left border region, the first scan driving circuit 31, the first light-emitting driving circuit 33, and the second reset driving circuit 36 ​​can be sequentially arranged along a direction away from the sub-pixels. The second scan driving circuit 32, the second light-emitting driving circuit 34, and the first reset driving circuit 35 can be located on the same side of multiple sub-pixels along the first direction X, for example, all located in the right border region. Within the right border region, the second scan driving circuit 32, the second light-emitting driving circuit 34, and the first reset driving circuit 35 can be sequentially arranged along a direction away from the sub-pixels. In this example, all gate driving circuits can adopt a single-sided driving method.

[0152] In some examples, as shown in Figures 9 and 10, the first scan driving circuit 31 includes multiple first scan driving units. These multiple first scan driving units can be sequentially arranged along the second direction Y. Specifically, the (2i-1)th level first scan driving unit and the (2i+1)th level first scan driving unit can be cascaded, and the (2i)th level first scan driving unit and the (2i+2)th level first scan driving unit can be cascaded, where i is an integer greater than 0. For example, the first scan driving units of odd-numbered rows such as the first row, third row, fifth row, and seventh row can be cascaded sequentially; the first scan driving units of even-numbered rows such as the second row, fourth row, sixth row, and eighth row can be cascaded sequentially. For example, the first scan signal provided by the (n-1)th to (n+2)th level first scan driving units through the first scan lines GL1(n-1) to GL1(n+2) can be as shown in Figure 9. In this example, the first scan area unit uses a cascaded configuration with odd and even rows separated. This allows for an overlap in the effective level signals (low level signals in this example) output by the first scan drive units of adjacent rows, providing sufficient time for data signal writing and resulting in a smaller rise time (Tr) / fall time (Tf) ratio for the output signal. In other examples, the first scan drive units of the first scan drive circuit can use a conventional row-by-row sequential cascading method, which also produces the output waveform shown in Figure 9. This embodiment is not limited to this approach.

[0153] In some examples, as shown in Figure 9, because the effective level signals output by adjacent first scan drive units overlap during certain periods (for example, the overlap period between the output signals of the (n-1)th and nth first scan drive units is the second period ②), when the (n-1)th row pixel circuit receives the data signal transmitted by the data line, the nth row pixel circuit will also receive the same data signal. In this case, the (n-1)th stage first scan drive unit needs to be turned off before providing the data signal to the nth row pixel circuit. This ensures that the writing of the previous row's data signal is not affected, and that the current row's data signal is completely written. In other words, the data signal transmitted by the data line provides the data signals of the (n-1), nth, (n+1), and (n+2)th rows to the corresponding row's pixel circuits during the second period ②, third period ③, fourth period ④, and fifth period ⑤ shown in Figure 9, respectively. In this way, since a first scan drive unit outputs a 2H pulse signal, sufficient time is allowed for writing the data signal. This is not the actual 2H duration for writing the data signal, but rather a sufficient pulse width for data signal writing.

[0154] The first scan driving circuit in this example can drive the pixel circuits of odd-numbered and even-numbered rows individually. The second scan driving circuit, the first light-emitting driving circuit, the second light-emitting driving circuit, the first reset driving circuit, and the second reset driving circuit all use a single driving unit to drive the pixel circuits of two rows of sub-pixels, achieving a 2H driving cycle, which is beneficial for supporting high-frequency displays. Moreover, the arrangement of multiple gate driving circuits in this example facilitates wiring layout. Further descriptions of the driving architecture of this example can be found in the description of the embodiment shown in Figure 7, and will not be repeated here.

[0155] Figure 11 is another equivalent circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure. In some examples, as shown in Figure 11, the pixel circuit of this example may include: a driving transistor T3, a compensation transistor T2, a data writing transistor T4, a first light-emitting control transistor T5, a second light-emitting control transistor T6, a first reset transistor T1, a second reset transistor T7, a third reset transistor T8, a second control transistor T9, a first control transistor T10, a first capacitor C1, and a second capacitor C2. The gate of the first control transistor T10 is coupled to the first light-emitting control line EM1, and the gates of the second control transistor T9 and the compensation transistor T2 are both coupled to the second scan line GL2. In this example, the second control line S2 and the second scan line GL2 may be configured to transmit the same signal; the first control line S1 and the first light-emitting control line EM1 may be configured to transmit the same signal. In other words, in this example, the second control signal and the second scan signal may be the same, and the first control signal and the first light-emitting control signal may be the same. Further description of the pixel circuit of this example can be found in the description of the foregoing embodiments, and will not be repeated here.

[0156] Figure 12 is a timing diagram of the pixel circuit shown in Figure 11. As shown in Figure 12, the pixel circuit of this example may include: 10 transistors (i.e., transistors T1 to T10), 2 capacitor units (i.e., first capacitor C1 and second capacitor C2), 11 input terminals (i.e., data line DL, first scan line GL1, second scan line GL2, first light emission control line EM1, second light emission control line EM2, first reset control line RST1, second reset control line RST2, first reference voltage line REF1, second reference voltage line REF2, first reset voltage line INIT1 and second reset voltage line INIT2), and 2 power supply terminals (i.e., first power supply line VDD and second power supply line VSS). In some examples, the compensation transistor T2 and the second control transistor T9 are N-type transistors, and the remaining transistors are P-type transistors.

[0157] In some examples, as shown in Figure 12, the operation of a pixel circuit can include the following stages within a frame time period.

[0158] The first stage, t31, can also be called the first reset stage or the first bias stage. The second reset control signal provided by the second reset control line RST2 is low, the second reset transistor T7 and the third reset transistor T8 are turned on, the sixth node N6 is reset to the second reset voltage Vinit2, and the voltage of the fifth node N5 is the second reference voltage Vref2. The second scan signal provided by the second scan line GL2 is high, and both the compensation transistor T2 and the second control transistor T9 are turned on. The first light emission control signal provided by the first light emission control line EM1 is high, and both the first light emission control transistors T5 and T10 are turned off. The first reset control signal provided by the first reset control line RST1 is high, and the first reset transistor T1 is turned off. The second light emission control signal provided by the second light emission control line EM2 is high, and the second light emission control transistor T6 is turned off. The first scan signal provided by the first scan line GL1 is high, and the data write transistor T4 is turned off.

[0159] The second stage, t32, can also be called the second reset stage. The first reset control signal provided by the first reset control line RST1 is low, and the first reset transistor T1 is turned on. In this stage, the first node N1 is reset to the first reset voltage Vinit1. The second reset control signal provided by the second reset control line RST2 is high, and both the second reset transistor T7 and the third reset transistor T8 are turned off.

[0160] The third stage, t33, can also be called the threshold compensation stage. The second scan signal provided by the second scan line GL2 is high, and both the compensation transistor T2 and the second control transistor T9 are turned on, writing the threshold voltage of the driving transistor T3 to the first node N1. The first reset control signal provided by the first reset control line RST1 is low, and the first reset transistor T1 is turned off. The first light emission control signal provided by the first light emission control line EM1 is low, and both the first light emission control transistor T5 and the first control transistor T10 are turned on. The voltage at the third node N3 is the first reference voltage Vref1.

[0161] The fourth stage, t34, can also be called the data writing stage. The first scan signal provided by the first scan line GL1 jumps to a low level, the data writing transistor T4 turns on, and the data signal provided by the data line DL is written to the third node N3 through the turned-on data writing transistor T4. The first light emission control signal provided by the first light emission control line EM1 is at a high level, and both the first light emission control transistor T5 and the first control transistor T10 are turned off.

[0162] In the fifth stage (t35), the first scan signal provided by the first scan line GL1 is high, and the data writing transistor T4 is off. The second scan signal provided by the second scan line GL2 is low, and both the compensation transistor T2 and the second control transistor T9 are off. The first light emission control signal provided by the first light emission control line EM1 is low, and both the first light emission control transistor T5 and the first control transistor T10 are on. The second control transistor T9 is off, and the second node N2 is floating. The data signal written to the third node N3 during the data writing stage can be coupled to the first node N1 through the second capacitor C2 and the first capacitor C1.

[0163] In stage t36, also known as the second bias stage, the second reset control signal provided by the second reset control line RST2 is low, and both the second reset transistor T7 and the third reset transistor T8 are turned on. The sixth node N6 is reset to the second reset voltage Vinit2, and the voltage of the fifth node N5 is the second reference voltage Vref2. The second scan signal provided by the second scan line GL2 is low, and both the compensation transistor T2 and the second control transistor T9 are turned off. The first scan signal provided by the first scan line GL1 is high, and the data writing transistor T4 is turned off. The first light emission control signal provided by the first light emission control line EM1 is high, and both the first light emission control transistor T5 and the first control transistor T10 are turned off. In this stage, the driving transistor T3 is in a biased state.

[0164] In stage 7 (t37), also known as the light-emitting stage, the first light-emitting control signal provided by the first light-emitting control line EM1 is low, and both the first light-emitting control transistor T5 and the first control transistor T10 are turned on. The voltage of the third node N3 remains at the first reference voltage Vref1, which helps to improve the leakage current of the third node N3. The second light-emitting control signal provided by the second light-emitting control line EM2 is low, and the second light-emitting control transistor T6 is turned on. The compensation transistor T2, the second control transistor T9, the data writing transistor T4, the first reset transistor T1, the second reset transistor T7, and the third reset transistor T8 are all turned off. In this stage, the driving transistor T3 is turned on. The voltage of the first node N1 is Vdd + Vth + Vref1 - Vdata, where Vdata is the data voltage. The gate-source voltage difference of the driving transistor T3 is Vgs = Vdd + Vth + Vref1 - Vdata - Vdd = Vth + Vref1 - Vdata. The driving current of the driving transistor T3 is: Id = 0.5 × K × (Vgs - Vth) 2 =0.5×K×(Vth+Vref1-Vdata-Vth) 2 = 0.5 × K × (Vref1 - Vdata) 2 .

[0165] Where K is a constant, Vdata is the data voltage, Vref1 is the first reference voltage, and Vth is the threshold voltage.

[0166] In this example, the driving signal output by the driving transistor T3 is independent of the threshold voltage Vth of the driving transistor T3, which can eliminate the influence of the threshold voltage of the driving transistor on the driving signal, thereby ensuring uniform display brightness and improving the display effect.

[0167] This example separates the data signal writing process of the first node's charging process from the threshold voltage compensation process, allowing for flexible control of the threshold compensation duration and improving the threshold voltage compensation effect. In the pixel circuit of this example, the second scan signal is used to simultaneously control the compensation transistor and the first control transistor, and the first light emission control signal is used to simultaneously control the first light emission control transistor and the second control transistor. This helps save signal sources and wiring, and also helps improve the leakage current of the third node N3.

[0168] Figure 13 is a schematic diagram of another driving architecture for a pixel circuit according to at least one embodiment of the present disclosure. In some examples, as shown in Figure 13, taking the pixel circuit included in a sub-pixel as shown in Figure 11 as an example, the plurality of gate driving circuits in this example may include: a first scan driving circuit 31, a second scan driving circuit 32, a first light-emitting driving circuit 33, a second light-emitting driving circuit 34, a first reset driving circuit 35, and a second reset driving circuit 36.

[0169] In some examples, the first light-emitting driving circuit 33 may include multiple cascaded first light-emitting driving units. The nth-level first light-emitting driving unit may be configured to provide a first light-emitting control signal to the pixel circuit of the nth row of sub-pixels; the (n+1)th-level first light-emitting driving unit may be configured to provide a first light-emitting control signal to the pixel circuit of the (n+1)th row of sub-pixels, where n is an integer greater than 0.

[0170] The first light-emitting driving circuit in this example can drive the pixel circuit of each row of sub-pixels individually, and the first scanning driving circuit can drive the pixel circuits of odd-numbered rows and even-numbered rows individually. The second scanning driving circuit, the second light-emitting driving circuit, the first reset driving circuit, and the second reset driving circuit all use a single driving unit to drive the pixel circuits of two rows of sub-pixels, achieving a driving cycle of 2H, which is beneficial for supporting high-frequency displays. Moreover, the first light-emitting control signal provided by the first light-emitting driving circuit in this example simultaneously controls the second control transistor and the first light-emitting control transistor, which can help improve the leakage current of the third node N3. Further descriptions of the driving architecture of this example can be found in the descriptions of the embodiments shown in Figures 7 and 10 above, and will not be repeated here.

[0171] Figure 14 is another equivalent circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure. In some examples, as shown in Figure 14, the pixel circuit of this example may include: a driving transistor T3, a compensation transistor T2, a data writing transistor T4, a first light-emitting control transistor T5, a second light-emitting control transistor T6, a first reset transistor T1, a second reset transistor T7, a third reset transistor T8, a second control transistor T9, a first control transistor T10, a first capacitor C1, and a second capacitor C2. The gate of the first control transistor T10 is coupled to the first light-emitting control line EM1, and the gates of the second control transistor T9 and the compensation transistor T2 are both coupled to the second scan line GL2. In this example, the driving transistor T3, the compensation transistor T2, the data writing transistor T4, the first light-emitting control transistor T5, the second light-emitting control transistor T6, the first reset transistor T1, the second reset transistor T7, the third reset transistor T8, the second control transistor T9, and the first control transistor T10 may all be P-type transistors. Further description of the pixel circuit of this example can be found in the description of the foregoing embodiments, and will not be repeated here.

[0172] Figure 15 is a timing diagram of the pixel circuit shown in Figure 14. As shown in Figure 14, the pixel circuit of this example may include: 10 transistors (i.e., transistors T1 to T10), 2 capacitor units (i.e., first capacitor C1 and second capacitor C2), 11 input terminals (i.e., data line DL, first scan line GL1, second scan line GL2, first light emission control line EM1, second light emission control line EM2, first reset control line RST1, second reset control line RST2, first reference voltage line REF1, second reference voltage line REF2, first reset voltage line INIT1 and second reset voltage line INIT2), and 2 power supply terminals (i.e., first power supply line VDD and second power supply line VSS). All 10 transistors in this example are P-type transistors.

[0173] In some examples, as shown in Figure 15, the operation of a pixel circuit can include the following stages within a frame time period.

[0174] In the first stage t51, the second reset control signal provided by the second reset control line RST2 is low, the second reset transistor T7 and the third reset transistor T8 are turned on, the sixth node N6 is reset to the second reset voltage Vinit2, and the voltage of the fifth node N5 is the second reference voltage Vref2. The second scan signal provided by the second scan line GL2 is high, and both the compensation transistor T2 and the second control transistor T9 are turned on. The first light emission control signal provided by the first light emission control line EM1 is high, and both the first light emission control transistor T5 and the first control transistor T10 are turned off. The first reset control signal provided by the first reset control line RST1 is high, and the first reset transistor T1 is turned off. The second light emission control signal provided by the second light emission control line EM2 is high, and the second light emission control transistor T6 is turned off. The first scan signal provided by the first scan line GL1 is high, and the data write transistor T4 is turned off.

[0175] In the second stage t52, the first reset control signal provided by the first reset control line RST1 is at a low level, and the first reset transistor T1 is turned on. In this stage, the first node N1 is reset to the first reset voltage Vinit1.

[0176] In the third stage t53, the second reset control signal provided by the second reset control line RST2 is low, the second reset transistor T7 and the third reset transistor T8 are turned on, the sixth node N6 is reset to the second reset voltage Vinit2, and the voltage of the fifth node N5 is the second reference voltage Vref2. The second scan signal provided by the second scan line GL2 is high, and both the compensation transistor T2 and the second control transistor T9 are turned off.

[0177] In the fourth stage t54, the first light emission control signal provided by the first light emission control line EM1 is at a low level, and both the first light emission control transistor T5 and the first control transistor T10 are turned on, writing the first reference voltage Vref1 to the third node N3. The second scan signal provided by the second scan line GL2 is at a low level, and both the compensation transistor T2 and the second control transistor T9 are turned on, writing the threshold voltage of the driving transistor T3 to the first node N1.

[0178] In the fifth stage t55, the first scan signal provided by the first scan line GL1 jumps to a low level, the data writing transistor T4 turns on, and the data signal provided by the data line DL is written to the third node N3 through the turned-on data writing transistor T4. The first light emission control signal provided by the first light emission control line EM1 is at a high level, and both the first light emission control transistor T5 and the first control transistor T10 are turned off.

[0179] In stage t56, the first light-emitting control signal provided by the first light-emitting control line EM1 is at a low level, and both the first light-emitting control transistor T5 and the first control transistor T10 are turned on, writing the first reference voltage Vref1 to the third node N3. The second scan signal provided by the second scan line GL2 is at a high level, and both the compensation transistor T2 and the second control transistor T9 are turned off. With the second control transistor T9 off, the second node N2 is floating, and the data signal written to the third node N3 during the data writing stage can be coupled to the first node N1 through the second capacitor C2 and the first capacitor C1.

[0180] In stage t57, the second reset control signal provided by the second reset control line RST2 is low, the second reset transistor T7 and the third reset transistor T8 are turned on, the sixth node N6 is reset to the second reset voltage Vinit2, and the voltage of the fifth node N5 is the second reference voltage Vref2. During this stage, the drive transistor T3 is in a biased state.

[0181] In stage 8 (t58), the first light-emitting control signal provided by the first light-emitting control line EM1 is low, and both the first light-emitting control transistor T5 and the first control transistor T10 are turned on. The voltage of the third node N3 remains at the first reference voltage Vref1, which helps to improve the leakage current of the third node N3. The second light-emitting control signal provided by the second light-emitting control line EM2 is low, and the second light-emitting control transistor T6 is turned on. In this stage, the driving transistor T3 is turned on. The voltage of the first node N1 is Vdd + Vth + Vref1 - Vdata, where Vdata is the data voltage. The gate-source voltage difference of the driving transistor T3 is Vgs = Vdd + Vth + Vref1 - Vdata - Vdd = Vth + Vref1 - Vdata. The driving current of the driving transistor T3 is: Id = 0.5 × K × (Vgs - Vth) 2 =0.5×K×(Vth+Vref1-Vdata-Vth) 2 = 0.5 × K × (Vref1 - Vdata) 2 .

[0182] Where K is a constant, Vdata is the data voltage, Vref1 is the first reference voltage, and Vth is the threshold voltage.

[0183] In this example, the driving signal output by the driving transistor T3 is independent of the threshold voltage Vth of the driving transistor T3, which can eliminate the influence of the threshold voltage of the driving transistor on the driving signal, thereby ensuring uniform display brightness and improving the display effect.

[0184] In some examples, the effective level signal provided by the first scan line GL1 (a low level signal in this example) can be configured to control the data writing transistor T4 to write the data signal to the third node N3. The effective level signal provided by the second scan line GL2 (a low level signal in this example) can be configured to control the compensation transistor T2 to write the threshold voltage of the driving transistor T3 to the first node N1. The time between the end of the data writing transistor T4 writing the data signal to the third node N3 and the start of the effective level signal provided by the second scan line GL2 can be a first duration L1, and the time between the end of the data writing transistor T4 writing the data signal to the third node N3 and the end of the effective level signal provided by the second scan line GL2 can be a second duration L2. The second duration L2 is less than the first duration L1. In this example, the data writing process is performed in the latter half of the threshold voltage compensation stage, which increases the compensation time for the threshold voltage, ensuring sufficient compensation time and improving the compensation effect.

[0185] This example separates the data signal writing process to the charging process of the first node from the threshold voltage compensation process, allowing for flexible control of the threshold compensation duration and improving the threshold voltage compensation effect. Furthermore, the pixel circuits in this example use the same type of transistors, which simplifies the process flow and reduces the manufacturing complexity of the display substrate. The driving architecture of the pixel circuit in this example can be described with reference to the embodiments shown in Figures 10 and 13, and therefore will not be repeated here.

[0186] Figure 16 is another structural schematic diagram of a pixel circuit according to at least one embodiment of the present disclosure. In some examples, as shown in Figure 16, the pixel circuit of this example may include: a driving sub-circuit 11, a compensation sub-circuit 12, a data writing sub-circuit 13, a first coupling sub-circuit 141, a second coupling sub-circuit 142, a first control sub-circuit 15, a second control sub-circuit 16, a first light emission control sub-circuit 21, a second light emission control sub-circuit 22, a first reset sub-circuit 23, a second reset sub-circuit 24, and a third reset sub-circuit 25. The first reset sub-circuit 23 is coupled to a first reset control line RST1, a first reset voltage line INIT1, and a first node N1, and is configured to write a first reset voltage signal provided by the first reset voltage line INIT1 to the first node N1 under the control of the first reset control line RST1. The remaining structure of the pixel circuit of this example can be referred to the description of the foregoing embodiments, and will not be repeated here.

[0187] Figure 17 is another equivalent circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure. In some examples, as shown in Figure 17, the pixel circuit of this example may include: a driving transistor T3, a compensation transistor T2, a data writing transistor T4, a first light-emitting control transistor T5, a second light-emitting control transistor T6, a first reset transistor T1, a second reset transistor T7, a third reset transistor T8, a second control transistor T9, a first control transistor T10, a first capacitor C1, and a second capacitor C2. The gate of the first reset transistor T1 is coupled to the first reset control line RST1, the first terminal of the first reset transistor T1 is coupled to the first reset voltage line INIT1, and the second terminal of the first reset transistor T1 is coupled to the first node N1. The gates of the second control transistor T9 and the compensation transistor T2 are both coupled to the second scan line GL2, the first terminal of the second control transistor T9 is coupled to the first power supply line VDD, and the gate of the first control transistor T10 is coupled to the first light-emitting control line EM1. Further description of the pixel circuit of this example can be found in the description of the foregoing embodiments, and will not be repeated here.

[0188] Figure 18 is a timing diagram of the pixel circuit shown in Figure 17. As shown in Figure 17, the pixel circuit of this example may include: 10 transistors (i.e., transistors T1 to T10), 2 capacitor units (i.e., first capacitor C1 and second capacitor C2), 11 input terminals (i.e., data line DL, first scan line GL1, second scan line GL2, first light emission control line EM1, second light emission control line EM2, first reset control line RST1, second reset control line RST2, first reference voltage line REF1, second reference voltage line REF2, first reset voltage line INIT1 and second reset voltage line INIT2), and 2 power supply terminals (i.e., first power supply line VDD and second power supply line VSS). In this example, transistors T1 to T10 are all P-type transistors.

[0189] In some examples, as shown in Figure 18, the operation of a pixel circuit can include the following stages within a frame time period. This example illustrates the operation of the pixel circuit in the (n-1)th row.

[0190] In the first stage t41, the second reset control line RST2 provides a low-level second reset control signal, and both the second reset transistor T7 and the third reset transistor T8 are turned on; the second scan line GL2 provides a low-level second scan signal, and both the compensation transistor T2 and the second control transistor T9 are turned on. The first light-emitting control transistor T5, the second light-emitting control transistor T6, the first control transistor T10, the first reset transistor T1, and the data writing transistor T4 are all turned off.

[0191] In the second stage t42, the first reset control line RST1 provides a low-level first reset control signal, and the first reset transistor T1 is turned on. The second scan line GL2 provides a low-level second scan signal, and both the compensation transistor T2 and the second control transistor T9 are turned on. In this stage, the first node N1 is reset to the first reset voltage Vinit1.

[0192] In the third stage t43, both compensation transistor T2 and the second control transistor T9 are turned on; the first light-emitting control line EM1(n-1) provides a low-level signal, and both the first light-emitting control transistor T5 and the first control transistor T10 are turned on. The voltage of the third node N3 is the first reference voltage Vref1. In this stage, the driving transistor T3 is turned on, and the threshold voltage Vth of the driving transistor T3 is written to the first node N1.

[0193] In the fourth stage t44, the first scan line GL1(n-1) provides a low-level first scan signal, the data writing transistor T4 is turned on, and the data signal provided by the data line DL is written to the third node N3 through the turned-on data writing transistor T4. The first light emission control signal provided by the first light emission control line EM1 is high-level, and both the first light emission control transistor T5 and the first control transistor T10 are turned off.

[0194] In the fifth stage t45, the first light-emitting control line EM1(n-1) provides a low-level first light-emitting control signal, and both the first light-emitting control transistor T5 and the first control transistor T10 are turned on, writing the first reference voltage Vref1 to the third node N3.

[0195] In the sixth stage t46, the second reset control line RST2 provides a low-level second reset control signal, and both the second reset transistor T7 and the eighth reset transistor T8 are turned on. The sixth node N6 is reset to the second reset voltage Vinit2, and the voltage of the fifth node N5 is the second reference voltage Vref2.

[0196] In stage 7 (t47), the first light-emitting control line EM1(n-1) provides a low-level signal, and both the first light-emitting control transistor T5 and the first control transistor T10 are turned on. The voltage of the third node N3 remains at the first reference voltage Vref1, which helps to improve the leakage current of the third node N3. The second light-emitting control transistor T6 is turned on. In this stage, the driving transistor T3 is turned on. The gate-source voltage difference of the driving transistor T3 is Vgs = Vdd + Vth + Vref1 - Vdata - Vdd = Vth + Vref1 - Vdata. The driving current of the driving transistor T3 is: Id = 0.5 × K × (Vgs - Vth) 2 =0.5×K×(Vth+Vref1-Vdata-Vth) 2 = 0.5 × K × (Vref1 - Vdata)2 .

[0197] Where K is a constant, Vdata is the data voltage, Vref1 is the first reference voltage, and Vth is the threshold voltage.

[0198] In this example, the driving signal output by the driving transistor T3 is independent of the threshold voltage Vth of the driving transistor T3, which can eliminate the influence of the threshold voltage of the driving transistor on the driving signal, thereby ensuring uniform display brightness and improving the display effect.

[0199] This example separates the data signal writing process to the charging process of the first node from the threshold voltage compensation process, allowing for flexible control of the threshold compensation duration and improving the threshold voltage compensation effect. Furthermore, the pixel circuits in this example use the same type of transistors, which simplifies the process flow and reduces the manufacturing complexity of the display substrate. The driving architecture of the pixel circuit in this example can be described with reference to the embodiments shown in Figures 10 and 13, and therefore will not be repeated here.

[0200] Figure 19 is another equivalent circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure. In some examples, as shown in Figure 19, the pixel circuit of this example may include: a driving transistor T3, a compensation transistor T2, a data writing transistor T4, a first light-emitting control transistor T5, a second light-emitting control transistor T6, a first reset transistor T1, a second reset transistor T7, a third reset transistor T8, a second control transistor T9, a first control transistor T10, a first capacitor C1, and a second capacitor C2. The gates of the first control transistor T10 and the data writing transistor T4 are both coupled to the first scan line GL1. The gates of the second control transistor T9 and the compensation transistor T2 are both coupled to the second scan line GL2. In this example, the first control line S1 and the first scan line GL1 may be configured to provide the same signal, and the second control line S2 and the second scan line GL2 may be configured to provide the same signal. In other words, the second scan signal and the second control signal of this example may be the same, and the first scan signal and the first control signal may be the same. In this example, the data writing transistor T4, the compensation transistor T2, and the second control transistor T9 are N-type transistors, while the remaining transistors are P-type transistors. Further descriptions of the pixel circuit in this example can be found in the descriptions of the foregoing embodiments, and will not be repeated here.

[0201] Figure 20 is a timing diagram of the pixel circuit shown in Figure 19. As shown in Figure 19, the pixel circuit of this example may include: 10 transistors (i.e., transistors T1 to T10), 2 capacitor units (i.e., first capacitor C1 and second capacitor C2), 11 input terminals (i.e., data line DL, first scan line GL1, second scan line GL2, first light emission control line EM1, second light emission control line EM2, first reset control line RST1, second reset control line RST2, first reference voltage line REF1, second reference voltage line REF2, first reset voltage line INIT1 and second reset voltage line INIT2), and 2 power supply terminals (i.e., first power supply line VDD and second power supply line VSS).

[0202] In some examples, as shown in Figure 20, the operation of a pixel circuit can include the following stages within a frame time period.

[0203] The first stage, t61, can also be called the first reset stage. The first reset control signal provided by the first reset control line RST1 is low, and the first reset transistor T1 is turned on. The second scan signal provided by the second scan line GL2 is high, and both the compensation transistor T2 and the second control transistor T9 are turned on. The first node N1 is reset to the first reset voltage Vinit1. The first scan signal provided by the first scan line GL1 is low, the data write transistor T4 is turned off, and the first control transistor T10 is turned on.

[0204] The second stage, t62, can also be called the first bias stage or the second reset stage. The second reset control signal provided by the second reset control line RST2 is low, and both the second reset transistor T7 and the third reset transistor T8 are turned on. The sixth node N6 is reset to the second reset voltage Vinit2, and the voltage at the fifth node N5 is the second reference voltage Vref2. During this stage, the driving transistor T3 is in a biased state.

[0205] The third stage, t63, can also be called the threshold compensation stage. The second scan signal provided by the second scan line GL2 is high, and both the compensation transistor T2 and the second control transistor T9 are turned on. The first scan signal provided by the first scan line GL1 is low, the first control transistor T10 is turned on, and the data writing transistor T4 is turned off. The first light emission control signal provided by the first light emission control line EM1 is low, and the first light emission control transistor T5 is turned on. In this stage, the driving transistor T3 is turned on, and the threshold voltage Vth of the driving transistor T3 is written to the first node N1. The voltage of the second node N2 is the first power supply voltage Vdd, and the voltage of the third node N3 is the first reference voltage Vref1.

[0206] The fourth stage, t64, can also be called the data writing stage. The first scan signal provided by the first scan line GL1 jumps to a high level, the first control transistor T10 is turned off, the data writing transistor T4 is turned on, and the data signal provided by the data line DL is written to the third node N3 through the turned-on data writing transistor T4.

[0207] The fifth stage, t65, can also be called the second bias stage. The second reset control signal provided by the second reset control line RST2 is low, and both the second reset transistor T7 and the third reset transistor T8 are turned on. During this stage, the drive transistor T3 is in a biased state.

[0208] The sixth stage, t66, can also be called the light-emitting stage. The first scan signal provided by the first scan line GL1 is low, the data writing transistor T4 is off, the first control transistor T10 is on, and the voltage of the third node N3 remains at the first reference voltage Vref1, which helps improve the leakage current of the third node N3. The first light-emitting control transistor T5, the second light-emitting control transistor T6, and the driving transistor T3 are all on. The gate-source voltage difference of the driving transistor T3 is Vgs = Vdd + Vth + Vref1 - Vdata - Vdd = Vth + Vref1 - Vdata. The driving current of the driving transistor T3 is: Id = 0.5 × K × (Vgs - Vth) 2 =0.5×K×(Vth+Vref1-Vdata-Vth) 2 = 0.5 × K × (Vref1 - Vdata) 2 .

[0209] Where K is a constant, Vdata is the data voltage, Vref1 is the first reference voltage, and Vth is the threshold voltage.

[0210] In this example, the driving signal output by the driving transistor T3 is independent of the threshold voltage Vth of the driving transistor T3, which can eliminate the influence of the threshold voltage of the driving transistor on the driving signal, thereby ensuring uniform display brightness and improving the display effect.

[0211] This example separates the charging process of writing data signals to the first node from the threshold voltage compensation process, allowing for flexible control of the threshold compensation duration and improving the threshold voltage compensation effect. In the pixel circuit of this example, the first scan signal simultaneously controls the data writing transistor and the second control transistor, which helps save signal sources and wiring, and improves the leakage current of the third node N3. The driving architecture of the pixel circuit in this example can be referred to the description of the embodiments shown in Figure 10 or Figure 13, and therefore will not be repeated here.

[0212] Figure 21 is another structural schematic diagram of a pixel circuit according to at least one embodiment of the present disclosure. In some examples, as shown in Figure 21, the pixel circuit of this example may include: a driving sub-circuit 11, a compensation sub-circuit 12, a data writing sub-circuit 13, a first coupling sub-circuit 141, a second coupling sub-circuit 142, a first control sub-circuit 15, a second control sub-circuit 16, a first light emission control sub-circuit 21, a second light emission control sub-circuit 22, a first reset sub-circuit 23, a second reset sub-circuit 24, a third reset sub-circuit 25, and a fourth reset sub-circuit 26. The fourth reset sub-circuit 26 is coupled to the third reset control line RST3, the first reference voltage line REF1, and the third node N3, and is configured to write the first reference voltage signal provided by the first reference voltage line REF1 to the third node N3 under the control of the third reset control line RST3. The remaining structure of the pixel circuit of this example can be referred to the description of the foregoing embodiments, and will not be repeated here.

[0213] Figure 22 is another equivalent circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure. In some examples, as shown in Figure 22, the fourth reset sub-circuit may include a fourth reset transistor T11, the gate of which is coupled to the second reset control line RST2, the first terminal of which is coupled to the first reference voltage line REF1, and the second terminal of which is coupled to the third node N3. In this example, the second reset control line RST2 and the third reset control line may be configured to provide the same signal; in other words, the second reset control signal and the third reset control signal may be the same. The gate of the first control transistor T10 is coupled to the second light emission control line EM2. In other words, the second light emission control line EM2 and the first control line may be configured to provide the same signal; that is, the second light emission control signal and the first control signal may be the same. In this example, the data writing transistor T4, the compensation transistor T2, and the second control transistor T9 may all be N-type transistors, and the remaining transistors may all be P-type transistors. Further description of the pixel circuit of this example can be found in the description of the foregoing embodiments, and therefore will not be repeated here.

[0214] The timing diagram of the pixel circuit in this example can be referred to the timing diagram shown in Figure 20. The first control transistor T10 is turned on in the sixth stage t66 (i.e., the light-emitting stage), which not only couples the data signal to the first node N1 but also improves the leakage current of the third node N3. The remaining timing diagram of the pixel circuit can be found in the description of the foregoing embodiment, and therefore will not be repeated here.

[0215] This example separates the data signal writing process of the first node's charging process from the threshold voltage compensation process, allowing for flexible control of the threshold compensation duration and improving the threshold voltage compensation effect. Furthermore, using the second light-emitting control signal to simultaneously control both the second control transistor and the second light-emitting control transistor can save on signal sources and wiring, and also improve the leakage current of the third node N3. The pixel circuit driving architecture of this example can be referred to the description of the embodiments shown in Figures 10 or 13, and therefore will not be repeated here.

[0216] Figure 23 is another equivalent circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure. In some examples, as shown in Figure 23, the pixel circuit of this example may include: a driving transistor T3, a compensation transistor T2, a data writing transistor T4, a second light-emitting control transistor T6, a first reset transistor T1, a second reset transistor T7, a second control transistor T9, a first control transistor T10, a first capacitor C1, a second capacitor C2, and a third capacitor C3. The first electrode of the driving transistor T3 is coupled to the first power supply line VDD. The fifth node of this example is directly coupled to the first power supply line VDD. The first electrode of the third capacitor C3 is coupled to the first bias signal line V1, and the second electrode is coupled to the first node N1. The gates of the compensation transistor T2, the second control transistor T9, and the first control transistor T10 are all coupled to the second scan line GL2. In this example, the second scan line GL2, the first control line, and the second control line can be configured to provide the same signal; in other words, the second scan signal, the first control signal, and the second control signal of this example can be the same. In this example, the compensation transistor T2 and the second control transistor T9 can both be N-type transistors, while the remaining transistors are P-type transistors. Further description of the pixel circuit in this example can be found in the description of the foregoing embodiments, and therefore will not be repeated here.

[0217] Figure 24 is a timing diagram of the pixel circuit shown in Figure 23. As shown in Figure 23, the pixel circuit of this example may include: 8 transistors (i.e., transistors T1, T2, T3, T4, T6, T7, T9 and T10), 3 capacitor units (i.e., first capacitor C1, second capacitor C2 and third capacitor C3), 10 input terminals (i.e., data line DL, first scan line GL1, second scan line GL2, second light emission control line EM2, first reset control line RST1, second reset control line RST2, first reference voltage line REF1, first coupling signal line V1, first reset voltage line INIT1 and second reset voltage line INIT2), and 2 power supply terminals (i.e., first power supply line VDD and second power supply line VSS).

[0218] In some examples, as shown in Figure 24, the operation of the pixel circuit may include the following stages within a frame time period. In this example, the first coupling signal line V1 and the second reset control line RST2 are described as providing the same signal. In other words, the first electrode of the third capacitor C3 can be coupled to the second reset control line RST2.

[0219] The first stage, t71, can also be called the first reset stage. The first reset control signal provided by the first reset control line RST1 is low, and the first reset transistor T1 is turned on. The second scan signal provided by the second scan line GL2 is high, and both the compensation transistor T2 and the second control transistor T9 are turned on, while the first control transistor T10 is turned off. The first node N1 is reset to the first reset voltage Vinit1.

[0220] The second stage, t72, can also be called the first bias stage or the second reset stage. The second reset control signal provided by the second reset control line RST2 is low, the second reset transistor T7 is turned on, and the sixth node N6 is reset to the second reset voltage Vinit2. The voltage of the first node N1 is pulled down by the second reset control signal, and the driving transistor T3 is biased. The second scan signal provided by the second scan line GL2 is low, the compensation transistor T2 and the second control transistor T9 are both turned off, the first control transistor T10 is turned on, and the voltage of the third node N3 is the first reference voltage Vref1.

[0221] The third stage, t73, can also be called the threshold compensation stage. The second scan signal provided by the second scan line GL2 is high, and both compensation transistor T2 and the second control transistor T9 are turned on, while the first control transistor T10 is turned off. In this stage, the driving transistor T3 is turned on, and its threshold voltage Vth is written to the first node N1. The voltage of the first node N1 is Vdd + Vth, where Vdd is the first power supply voltage provided by the first power line VDD. The voltage of the second node N2 is the first power supply voltage Vdd.

[0222] The fourth stage, t74, can also be called the data writing stage. The first scan signal provided by the first scan line GL1 jumps to a low level, the data writing transistor T4 turns on, and the data signal provided by the data line DL is written to the third node N3 through the turned-on data writing transistor T4.

[0223] The fifth stage t75 can also be called the second bias stage. The second reset control signal provided by the second reset control line RST2 is at a low level, the second reset transistor T7 is turned on, the potential of the first node N1 is pulled down by the second reset control signal, and the driving transistor T3 is in a bias state.

[0224] The sixth stage, t76, can also be called the light-emitting stage. The first control transistor T10 is turned on, and the voltage at the third node N3 is the first reference voltage Vref1. The second light-emitting control transistor T6 and the driving transistor T3 are also turned on. The voltage at the first node N1 is Vdd + Vth + Vref1 - Vdata. The gate-source voltage difference of the driving transistor T3 is Vgs = Vdd + Vth + Vref1 - Vdata - Vdd = Vth + Vref1 - Vdata. The driving current of the driving transistor T3 is: Id = 0.5 × K × (Vgs - Vth) 2 =0.5×K×(Vth+Vref1-Vdata-Vth) 2 = 0.5 × K × (Vref1 - Vdata) 2 .

[0225] Where K is a constant, Vdata is the data voltage, Vref1 is the first reference voltage, and Vth is the threshold voltage.

[0226] In this example, the driving signal output by the driving transistor T3 is independent of the threshold voltage Vth of the driving transistor T3, which can eliminate the influence of the threshold voltage of the driving transistor on the driving signal, thereby ensuring uniform display brightness and improving the display effect.

[0227] This example separates the data signal writing process of the first node during charging from the threshold voltage compensation process, allowing for flexible control of the threshold compensation duration and improving the threshold voltage compensation effect. Furthermore, the third capacitor C3 and the first bias signal line can be used to control the bias of the driving transistor at the first node N1.

[0228] Figure 25 is a schematic diagram of another driving architecture for a pixel circuit according to at least one embodiment of the present disclosure. In some examples, as shown in Figure 25, taking the pixel circuit included in a sub-pixel as shown in Figure 23 as an example, the multiple gate driving circuits in this example may include: a first scan driving circuit (e.g., including first scan driving circuits 31a and 31b), a second scan driving circuit 32, a second light-emitting driving circuit 34, a first reset driving circuit 35, and a second reset driving circuit 36.

[0229] In some examples, the first scan driving circuits 31a and 31b can be located on both sides of the plurality of sub-pixels along the first direction X. The first reset driving circuit 35 and the second reset driving circuit 36 ​​can be located on both sides of the plurality of sub-pixels along the first direction X. The second scan driving circuit 32 and the second light-emitting driving circuit 34 can be located on both sides of the plurality of sub-pixels along the first direction X.

[0230] In some examples, the first scan driving circuit 31a, the second light-emitting driving circuit 34, and the second reset driving circuit 36 ​​can be located on the same side of multiple sub-pixels along the first direction X, for example, all located in the left border region. Within the left border region, the first scan driving circuit 31a, the second light-emitting driving circuit 34, and the second reset driving circuit 36 ​​can be sequentially arranged along a direction away from the sub-pixels. The first scan driving circuit 31b, the second scan driving circuit 32, and the first reset driving circuit 35 can be located on the same side of multiple sub-pixels along the first direction X, for example, all located in the right border region. Within the right border region, the first scan driving circuit 31b, the second scan driving circuit 32, and the first reset driving circuit 35 can be sequentially arranged along a direction away from the sub-pixels. In this example, the first scan signal can be driven from both sides, and the remaining signals can be driven from one side. In other examples, the first scan signal can be driven from one side. The arrangement of the multiple gate driving circuits in this example facilitates wiring layout.

[0231] Further descriptions of the driving architecture of the pixel circuit in this example can be found in the description of the foregoing embodiments, and will not be repeated here.

[0232] Figure 26 is another equivalent circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure. In some examples, as shown in Figure 26, the pixel circuit of this example may include: a driving transistor T3, a compensation transistor T2, a data writing transistor T4, a second light-emitting control transistor T6, a first reset transistor T1, a second reset transistor T7, a second control transistor T9, a first control transistor T10, a first capacitor C1, a second capacitor C2, and a third capacitor C3. The first electrode of the driving transistor T3 is coupled to the first power supply line VDD. The fifth node in this example is directly coupled to the first power supply line VDD. The first electrode of the third capacitor C3 is coupled to the first bias signal line V1, and the second electrode is coupled to the second node N2. The gates of the compensation transistor T2, the second control transistor T9, and the first control transistor T10 are all coupled to the second scan line GL2. In this example, the compensation transistor T2 and the second control transistor T9 may both be N-type transistors, and the remaining transistors may be P-type transistors. Further descriptions of the pixel circuit of this example can be found in the descriptions of the foregoing embodiments, and will not be repeated here.

[0233] The timing diagram of the pixel circuit in this example can be referred to the timing diagram shown in Figure 24. This example utilizes the third capacitor and the first bias signal line to control the second node N2 to bias the driving transistor T3, which helps to improve image retention. The timing diagram and driving architecture of the pixel circuit in this example can be found in the description of the foregoing embodiments, and therefore will not be repeated here.

[0234] Figure 27 is another equivalent circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure. In some examples, as shown in Figure 27, the pixel circuit of this example may include: a driving transistor T3, a compensation transistor T2, a data writing transistor T4, a first light-emitting control transistor T5, a second light-emitting control transistor T6, a first reset transistor T1, a second reset transistor T7, a second control transistor T9, a first control transistor T10, a first capacitor C1, a second capacitor C2, and a fourth capacitor C4. The first electrode of the fourth capacitor C4 is coupled to the second bias signal line V2, and the second electrode is coupled to the fifth node N5. The gates of the compensation transistor T2, the second control transistor T9, and the first control transistor T10 are all coupled to the second scan line GL2. In this example, the second reset transistor T7, the compensation transistor T2, and the second control transistor T9 may all be N-type transistors, and the remaining transistors may all be P-type transistors. Further descriptions of the pixel circuit of this example can be found in the descriptions of the foregoing embodiments, and will not be repeated here.

[0235] Figure 28 is a timing diagram of the pixel circuit shown in Figure 27. As shown in Figure 27, the pixel circuit of this example may include: 10 transistors (i.e., transistors T1 to T10), 3 capacitor units (i.e., first capacitor C1, second capacitor C2 and fourth capacitor C4), 11 input terminals (i.e., data line DL, first scan line GL1, second scan line GL2, first light emission control line EM1, second light emission control line EM2, first reset control line RST1, second reset control line RST2, first reference voltage line REF1, second coupling signal line V2, first reset voltage line INIT1 and second reset voltage line INIT2), and 2 power supply terminals (i.e., first power supply line VDD and second power supply line VSS).

[0236] In some examples, as shown in Figure 28, the operation of the pixel circuit may include the following stages within a frame time period. In this example, the second coupling signal line V2 and the second reset control line RST2 are described as providing the same signal. In other words, the first electrode of the fourth capacitor C4 can be coupled to the second reset control line RST2.

[0237] The first stage, t81, can also be called the first reset stage. The first reset control signal provided by the first reset control line RST1 is low, and the first reset transistor T1 is turned on. The second scan signal provided by the second scan line GL2 is high, and both the compensation transistor T2 and the second control transistor T9 are turned on, while the first control transistor T10 is turned off. The first node N1 is reset to the first reset voltage Vinit1.

[0238] The second stage, t82, can also be called the first bias stage or the second reset stage. The second reset control signal provided by the second reset control line RST2 is high, the second reset transistor T7 is turned on, and the sixth node N6 is reset to the second reset voltage Vinit2. The potential of the fifth node N5 is pulled high by the second reset control signal, and the driving transistor T3 is biased. The second scan signal provided by the second scan line GL2 is low, the compensation transistor T2 and the second control transistor T9 are both turned off, the first control transistor T10 is turned on, and the voltage of the third node N3 is the first reference voltage Vref1.

[0239] The third stage, t83, can also be called the threshold compensation stage. The second scan signal provided by the second scan line GL2 is at a high level, and both compensation transistor T2 and the second control transistor T9 are turned on, while the first control transistor T10 is turned off. In this stage, the driving transistor T3 is turned on, and its threshold voltage Vth is written to the first node N1. The voltage of the first node N1 is Vdd + Vth, where Vdd is the first power supply voltage provided by the first power line VDD. The voltage of the second node N2 is the first power supply voltage Vdd.

[0240] The fourth stage, t84, can also be called the data writing stage. The first scan signal provided by the first scan line GL1 jumps to a low level, the data writing transistor T4 turns on, and the data signal provided by the data line DL is written to the third node N3 through the turned-on data writing transistor T4.

[0241] The fifth stage t85 can also be called the second bias stage. The second reset control signal provided by the second reset control line RST2 is at a high level, the second reset transistor T7 is turned on, the potential of the fifth node N5 is pulled high by the second reset control signal, and the driving transistor T3 is in a bias state.

[0242] The sixth stage, t86, can also be called the light-emitting stage. The first control transistor T10 is turned on, and the voltage at the third node N3 is the first reference voltage Vref1. The first light-emitting control transistor T5, the second light-emitting control transistor T6, and the driving transistor T3 are all turned on. The voltage at the first node N1 is Vdd + Vth + Vref1 - Vdata. The gate-source voltage difference of the driving transistor T3 is Vgs = Vdd + Vth + Vref1 - Vdata - Vdd = Vth + Vref1 - Vdata. The driving current of the driving transistor T3 is: Id = 0.5 × K × (Vgs - Vth) 2 =0.5×K×(Vth+Vref1-Vdata-Vth) 2 = 0.5 × K × (Vref1 - Vdata) 2 .

[0243] Where K is a constant, Vdata is the data voltage, Vref1 is the first reference voltage, and Vth is the threshold voltage.

[0244] In this example, the driving signal output by the driving transistor T3 is independent of the threshold voltage Vth of the driving transistor T3, which can eliminate the influence of the threshold voltage of the driving transistor on the driving signal, thereby ensuring uniform display brightness and improving the display effect.

[0245] This example separates the data signal writing process of the first node's charging process from the threshold voltage compensation process, allowing for flexible control of the threshold compensation duration and improving the threshold voltage compensation effect. Furthermore, the fourth capacitor and the second bias signal line can be used to control the fifth node N5 to bias the driving transistor T3, which helps to mitigate image retention. The pixel circuit driving architecture of this example can be described with reference to the embodiments shown in Figures 10 or 13, and therefore will not be repeated here.

[0246] Figure 29 is another equivalent circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure. In some examples, as shown in Figure 29, the pixel circuit of this example may include: a driving transistor T3, a compensation transistor T2, a data writing transistor T4, a first light-emitting control transistor T5, a second light-emitting control transistor T6, a first reset transistor T1, a second reset transistor T7, a second control transistor T9, a first control transistor T10, a first capacitor C1, a second capacitor C2, and a fourth capacitor C4. The first electrode of the fourth capacitor C4 is coupled to the second bias signal line V2, and the second electrode is coupled to the fourth node N4. The gates of the compensation transistor T2, the second control transistor T9, and the first control transistor T10 are all coupled to the second scan line GL2. In this example, the second reset transistor T7, the compensation transistor T2, and the second control transistor T9 may all be N-type transistors, and the remaining transistors may all be P-type transistors. Further descriptions of the pixel circuit of this example can be found in the descriptions of the foregoing embodiments, and will not be repeated here.

[0247] The timing diagram of the pixel circuit in this example can be referred to the timing diagram shown in Figure 28. In this example, the fourth capacitor and the second bias signal line can be used to control the fourth node N4 to bias the driving transistor T3. The timing diagram and driving architecture of the pixel circuit in this example can be found in the description of the foregoing embodiments, and therefore will not be repeated here.

[0248] Figure 30 is a flowchart of a pixel circuit driving method according to at least one embodiment of the present disclosure. In some examples, as shown in Figure 30, the pixel circuit driving method of this example may include the following steps:

[0249] Step 701: Under the control of the second scan line, the compensation sub-circuit turns on the first node and the fourth node, so that the threshold voltage of the driving sub-circuit is written into the first node.

[0250] Step 702: Under the control of the first scan line, the data writing sub-circuit writes the data signal provided by the data line to the third node;

[0251] Step 703: Under the control of the first control line, the first control sub-circuit writes the first reference voltage signal provided by the first reference voltage line to the third node, so that the data signal is coupled to the first node through the coupling sub-circuit;

[0252] Step 704: Under the control of the first node, the driving sub-circuit provides a driving signal to the fourth node.

[0253] In some examples, the duration for which the data writing subcircuit writes the data signal to the third node is less than the duration for which the compensation subcircuit writes the threshold voltage of the driving subcircuit to the first node. The start time for the data writing subcircuit to write the data signal to the third node is later than the start time for the compensation subcircuit to write the threshold voltage of the driving subcircuit to the first node. This example can improve the compensation effect of the threshold voltage, thereby improving the uniformity of the image display; moreover, the later writing time of the data signal compared to the threshold voltage writing time can help ensure the validity of the data signal.

[0254] In some examples, the pixel circuit may further include: a second reset sub-circuit and a third reset sub-circuit; the second reset sub-circuit is coupled to a second reset control line, a second reset voltage line, and a sixth node, the sixth node being coupled to a first electrode of the light-emitting element; the third reset sub-circuit is coupled to the second reset control line, a second reference voltage line, and a fifth node. The driving method of this example further includes at least one of the following: before the compensation sub-circuit writes the threshold voltage of the driving sub-circuit to the first node, the second reset sub-circuit, under the control of the second reset control line, writes a second reset voltage signal provided by the second reset voltage line to the sixth node; the third reset sub-circuit, under the control of the second reset control line, writes a second reference voltage signal provided by the second reference voltage line to the fifth node; after the data writing sub-circuit writes the data signal provided by the data line to the third node, the second reset sub-circuit, under the control of the second reset control line, writes the second reset voltage signal provided by the second reset voltage line to the sixth node; the third reset sub-circuit, under the control of the second reset control line, writes a second reference voltage signal provided by the second reference voltage line to the fifth node. In this example, setting the driving transistor to a bias state before the compensation sub-circuit writes the threshold voltage of the driving sub-circuit to the first node, or after the data writing sub-circuit writes the data signal provided by the data line to the third node, can serve to calibrate the voltage and improve image retention.

[0255] In some examples, while the driving sub-circuit, under the control of the first node, provides a driving signal to the fourth node, the first control line continuously provides a valid level signal. In this example, during the light-emitting phase, the first control sub-circuit, under the control of the first control line, continuously writes a first reference voltage to the third node, which can help improve the leakage current of the third node.

[0256] The driving method for the pixel circuit in this embodiment can be referred to the description of the foregoing embodiment, and therefore will not be repeated here.

[0257] This embodiment also provides a display substrate, including: a plurality of sub-pixels and at least one first scan driving circuit. At least one of the plurality of sub-pixels includes a light-emitting element and a pixel circuit for driving the light-emitting element to emit light; the pixel circuit is the pixel circuit described in the foregoing embodiments. The first scan driving circuit includes: a plurality of first scan driving units. The nth-level first scan driving unit is configured to provide a first scan signal to the pixel circuit of the nth row of sub-pixels; n is an integer greater than 0. The (2i-1)th-level first scan driving unit is cascaded with the (2i+1)th-level first scan driving unit, and the (2i)th-level first scan driving unit is cascaded with the (2i+2)th-level first scan driving unit; i is an integer greater than 0.

[0258] In this embodiment, the first scan driving circuit of the display substrate uses a cascaded configuration of odd-numbered rows and even-numbered rows, which allows the effective level signals output by adjacent rows of first scan driving units to overlap, providing sufficient time for data signal writing and resulting in a smaller Tr / Tf of the output signal.

[0259] In some exemplary embodiments, the display substrate may further include: a first light-emitting driving circuit, the first light-emitting driving circuit including a plurality of cascaded first light-emitting driving units; the nth level first light-emitting driving unit is configured to provide a first light-emitting control signal to the pixel circuit of the nth row of sub-pixels; or, configured to provide a first light-emitting control signal to the pixel circuit of the (2n-1)th and 2nth row of sub-pixels.

[0260] In some exemplary embodiments, the display substrate may further include: a second scan driving circuit and a second light-emitting driving circuit; the second scan driving circuit includes a plurality of cascaded second scan driving units; the second light-emitting driving circuit includes a plurality of cascaded second light-emitting driving units. The nth-level second scan driving circuit is configured to provide a second scan signal to the pixel circuits of the (2n-1)th and (2n-th)th row sub-pixels; the nth-level second light-emitting driving circuit is configured to provide a second light-emitting control signal to the pixel circuits of the (2n-1)th and (2n-th)th row sub-pixels. The second scan driving circuit and the second light-emitting driving circuit are located on the same side of the plurality of sub-pixels along the row direction of the sub-pixels.

[0261] In some exemplary embodiments, the display substrate may further include: a first reset driving circuit and a second reset driving circuit; the first reset driving circuit includes a plurality of cascaded first reset driving units; the second reset driving circuit includes a plurality of cascaded second reset driving units. The nth-level first reset driving circuit is configured to provide a first reset control signal to the pixel circuits of the (2n-1)th and (2n-th)th row sub-pixels; the nth-level second reset driving circuit is configured to provide a second reset control signal to the pixel circuits of the (2n-1)th and (2n-th)th row sub-pixels. The first reset driving circuit and the second reset driving circuit are located on both sides of the plurality of sub-pixels along the row direction of the sub-pixels.

[0262] The description of the display substrate in this embodiment can be found in the description of the foregoing embodiments, and therefore will not be repeated here.

[0263] Figure 30 is a schematic diagram of a display device according to at least one embodiment of the present disclosure. In some examples, as shown in Figure 30, this embodiment provides a display device 91, including the display substrate 910 of the foregoing embodiments. In some examples, the display substrate 910 may include an OLED display substrate, a QLED display substrate, a Micro-LED display substrate, or a Mini-LED display substrate. The display device 91 can be any product or component with display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator. However, this embodiment is not limited thereto.

[0264] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0265] Although embodiments of this application have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting this application. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of this application.

Claims

1. A pixel circuit comprising: The driving sub-circuit, the data writing sub-circuit, the compensation sub-circuit, the coupling sub-circuit and the first control sub-circuit; The driving sub-circuit is coupled with the first node, the fourth node and the fifth node, and is configured to provide a driving signal to the fourth node under the control of the first node; The data writing sub-circuit is coupled with the first scan line, the data line and the third node, and is configured to write a data signal provided by the data line to the third node under the control of the first scan line; The compensation sub-circuit is coupled with the second scan line, the first node and the fourth node, and is configured to turn on the first node and the fourth node under the control of the second scan line, so that the threshold voltage of the driving sub-circuit is written to the first node; The coupling sub-circuit is coupled with the first node and the third node; The first control sub-circuit is coupled with the first control line, the third node and the first reference voltage line, and is configured to write a first reference voltage signal provided by the first reference voltage line to the third node under the control of the first control line after the data writing sub-circuit writes the data signal to the third node, so that the data signal is coupled to the first node through the coupling sub-circuit.

2. The pixel circuit of claim 1, wherein, The duration for the data writing sub-circuit to write the data signal to the third node is less than the duration for the compensation sub-circuit to write the threshold voltage of the driving sub-circuit to the first node; and the starting time for the data writing sub-circuit to write the data signal to the third node is later than the starting time for the compensation sub-circuit to write the threshold voltage of the driving sub-circuit to the first node.

3. The pixel circuit of claim 1, wherein, The effective level signal provided by the second scan line is configured to control the compensation sub-circuit to write the threshold voltage of the driving sub-circuit to the first node; The ending time for the data writing sub-circuit to write the data signal to the third node is a first duration away from the starting time of the effective level signal provided by the second scan line, and the ending time for the data writing sub-circuit to write the data signal to the third node is a second duration away from the ending time of the effective level signal provided by the second scan line; the second duration is less than the first duration.

4. The pixel circuit of claim 1, wherein, The effective level signal provided by the second scan line is configured to control the compensation sub-circuit to write the threshold voltage of the driving sub-circuit to the first node; The effective level signal provided by the second scan line includes three equal stages: a first signal stage, a second signal stage and a third signal stage, and the starting time of the effective level signal provided by the first scan line is located after the first signal stage.

5. The pixel circuit according to any one of claims 1 to 4, wherein, The coupling sub-circuit includes a first coupling sub-circuit and a second coupling sub-circuit; the first coupling sub-circuit is coupled with the first node and a second node, and the second coupling sub-circuit is coupled with the second node and the third node; The pixel circuit further comprises a second control sub-circuit coupled with the second control line, the second node and a first voltage terminal, and configured to turn on the second node and the first voltage terminal under the control of the second control line, so that the second coupling sub-circuit stores a data signal written into the third node.

6. The pixel circuit of claim 5, wherein, The first coupling sub-circuit comprises a first capacitor, a first electrode of the first capacitor being coupled with the first node, and a second electrode of the first capacitor being coupled with the second node. The second coupling sub-circuit comprises a second capacitor, a first electrode of the second capacitor being coupled with the second node, a second electrode of the second capacitor being coupled with the third node. The compensation sub-circuit comprises a compensation transistor, a gate of the compensation transistor being coupled with the second scan line, a first electrode of the compensation transistor being coupled with the fourth node, and a second electrode of the compensation transistor being coupled with the first node. The second control sub-circuit comprises a second control transistor, a gate of the second control transistor being coupled with the second control line, a first electrode of the second control transistor being coupled with the first voltage terminal, and a second electrode of the second control transistor being coupled with the second node; and the first voltage terminal is coupled with a first power supply line.

7. The pixel circuit of claim 6, wherein, The compensation transistor and the second control transistor are oxide thin film transistors, and the second control line and the second scan line are configured to provide the same signal.

8. The pixel circuit according to any one of claims 1 to 4, wherein The data writing sub-circuit comprises a data writing transistor, a gate of the data writing transistor being coupled with the first scan line, a first electrode of the data writing transistor being coupled with the data line, and a second electrode of the data writing transistor being coupled with the third node. The first control sub-circuit comprises a first control transistor, a gate of the first control transistor being coupled with the first control line, a first electrode of the first control transistor being coupled with the first reference voltage line, and a second electrode of the first control transistor being coupled with the third node. The compensation sub-circuit comprises a compensation transistor, a gate of the compensation transistor being coupled with the second scan line, a first electrode of the compensation transistor being coupled with the fourth node, and a second electrode of the compensation transistor being coupled with the first node.

9. The pixel circuit of claim 8, wherein, The data writing transistor and the first control transistor are of the same transistor type, and different from the transistor type of the compensation transistor; and the first control line and the second scan line are configured to provide the same signal.

10. The pixel circuit of claim 8, further comprising: a first light emitting control sub-circuit coupled with a first light emitting control line, a first power supply line and the fifth node, and configured to write a first power supply signal provided by the first power supply line into the fifth node under the control of the first light emitting control line; the first control line and the first light emitting control line are configured to provide the same signal.

11. The pixel circuit of claim 8, wherein, The data writing transistor and the first control transistor are of different transistor types, and the data writing transistor and the compensation transistor are of the same transistor type.

12. The pixel circuit of claim 11, wherein, The first control line and the first scan line are configured to transmit the same signal.

13. The pixel circuit of claim 11, further comprising: a second light emitting control sub-circuit coupled to the second light emitting control line, the fourth node and a sixth node, and configured to turn on the fourth node and the sixth node under the control of the second light emitting control line, the sixth node being coupled to a first electrode of the light emitting element; a fourth reset sub-circuit coupled to the third node, the first reference voltage line and a third reset control line, and configured to write a first reference voltage signal provided by the first reference voltage line to the third node under the control of the third reset control line.

14. The pixel circuit of claim 13, wherein, The first control line and the second light emitting control line are configured to provide the same signal.

15. The pixel circuit of any one of claims 1 to 4, further comprising: a first reset sub-circuit coupled to a first reset control line, a first reset voltage line and the fourth node, and configured to write a first reset voltage signal provided by the first reset voltage line to the fourth node under the control of the first reset control line; or the first reset sub-circuit being coupled to the first reset control line, a first reset voltage line and the first node, and configured to write a first reset voltage signal provided by the first reset voltage line to the first node under the control of the first reset control line; a second reset sub-circuit coupled to a second reset control line, a second reset voltage line and a sixth node, and configured to write a second reset voltage signal provided by the second reset voltage line to the sixth node under the control of the second reset control line, the sixth node being coupled to a first electrode of the light emitting element; 16. The pixel circuit of claim 15, further comprising: a third reset sub-circuit coupled to the second reset control line, a second reference voltage line and the fifth node, and configured to write a second reference voltage signal provided by the second reference voltage line to the fifth node under the control of the second reset control line.

17. The pixel circuit of claim 15, further comprising: a third capacitor, a first electrode of the third capacitor being coupled to a first bias signal line, a second electrode of the third capacitor being coupled to the first node or the second node.

18. The pixel circuit of claim 15, further comprising: a fourth capacitor, a first electrode of the fourth capacitor being coupled to a second bias signal line, a second electrode of the fourth capacitor being coupled to the fourth node or the fifth node.

19. A driving method of a pixel circuit, applied to the pixel circuit of any one of claims 1 to 18, the driving method comprising: a compensation sub-circuit turning on the first node and the fourth node under the control of a second scan line, so that a threshold voltage of a driving sub-circuit is written to the first node; a data writing sub-circuit writing a data signal provided by a data line to a third node under the control of a first scan line; a first control sub-circuit writing a first reference voltage signal provided by a first reference voltage line to the third node under the control of a first control line, so that the data signal is coupled to the first node through a coupling sub-circuit; the driving sub-circuit providing a driving signal to the fourth node under the control of the first node.

20. A display substrate, comprising: The plurality of sub-pixels and at least one first scan driving circuit, at least one of the plurality of sub-pixels comprising a light emitting element and a pixel circuit for driving the light emitting element to emit light; The pixel circuit is the pixel circuit according to any one of claims 1 to 18; The first scan driving circuit comprises a plurality of first scan driving units; The nth-stage first scan driving unit is configured to provide a first scan signal to the pixel circuits of the nth row of sub-pixels; n is an integer greater than 0; The 2i-1-stage first scan driving unit is cascaded with the 2i+1-stage first scan driving unit, and the 2i-stage first scan driving unit is cascaded with the 2i+2-stage first scan driving unit, i being an integer greater than 0.

21. The display substrate of claim 20, further comprising: The first light emitting driving circuit comprises a plurality of cascaded first light emitting driving units; The nth-stage first light emitting driving unit is configured to provide a first light emitting control signal to the pixel circuits of the nth row of sub-pixels; Alternatively, the nth-stage first light emitting driving unit is configured to provide a first light emitting control signal to the pixel circuits of the 2n-1th row and the 2nth row of sub-pixels.

22. The display substrate of claim 20, further comprising: The second scan driving circuit and the second light emitting driving circuit; the second scan driving circuit comprises a plurality of cascaded second scan driving units; The second light emitting driving circuit comprises a plurality of cascaded second light emitting driving units; The nth-stage second scan driving circuit is configured to provide a second scan signal to the pixel circuits of the 2n-1th row and the 2nth row of sub-pixels; The nth-stage second light emitting driving circuit is configured to provide a second light emitting control signal to the pixel circuits of the 2n-1th row and the 2nth row of sub-pixels; The second scan driving circuit and the second light emitting driving circuit are located on the same side of the plurality of sub-pixels along the row direction of the sub-pixels.

23. The display substrate of claim 20, further comprising: The first reset driving circuit and the second reset driving circuit; The first reset driving circuit comprises a plurality of cascaded first reset driving units; The second reset driving circuit comprises a plurality of cascaded second reset driving units; The nth-stage first reset driving circuit is configured to provide a first reset control signal to the pixel circuits of the 2n-1th row and the 2nth row of sub-pixels; The nth-stage second reset driving circuit is configured to provide a second reset control signal to the pixel circuits of the 2n-1th row and the 2nth row of sub-pixels; The first reset driving circuit and the second reset driving circuit are located on different sides of the plurality of sub-pixels along the row direction of the sub-pixels.

24. A display device comprising the display substrate according to any one of claims 20 to 23.

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