Electroencephalogram signal processing circuit

Abstract

An electroencephalogram signal processing circuit, comprising a differential amplification circuit (10), a comparison circuit (20), and a logic circuit. The logic circuit comprises a signal shaping unit (30), an SR trigger (40), and a signal flipping unit (50). An electroencephalogram signal is amplified by means of the differential amplification circuit (10). By means of the comparison circuit (20), the amplified electroencephalogram signal is compared with a reference signal, and high and low levels are output; that is, the comparison circuit acts as a digital-to-analog converter. The signal shaping unit (30) can shape and strengthen the signal output by the comparison circuit (20) to obtain a high-quality signal. The signal is then processed by the SR trigger (40) and finally output by means of the signal flipping unit (50). The electroencephalogram signal processing circuit can provide highly precise electroencephalogram signals to improve the driving efficiency of signals on a subsequent digital circuit and ensure the precision and stability of signal transmission, thereby improving the flexibility and configurability of the system.

Description

EEG signal processing circuit Technical Field

[0001] This invention relates to the field of integrated circuit technology, and in particular to an electroencephalogram (EEG) signal processing circuit. Background Technology

[0002] Neurophysiological signals include local field potentials and electrical signals that directly reflect neural activity, such as EEG (electroencephalogram), LFP (local field potential), ECG (electrocardiogram), EMG (electromyography), and certain spike signals. These signals have different amplitudes and frequency bands, typically ranging from 1µV to 10mV, with frequencies distributed between 0.1Hz and 10kHz. The signal amplitudes are weak, requiring high-precision comparators to ensure resolution. Furthermore, further signal processing is necessary to enhance the signal's driving capability for subsequent circuits.

[0003] Summary of the Invention

[0004] The purpose of this invention is to provide an electroencephalogram (EEG) signal processing circuit to solve the problem of how to design a circuit to improve the accuracy and driving capability of EEG signals.

[0005] To solve the above-mentioned technical problems, the present invention provides an electroencephalogram (EEG) signal processing circuit, comprising:

[0006] A differential amplifier circuit, wherein an EEG signal is input to the positive input terminal of the differential amplifier circuit, and a reference signal is input to the negative input terminal of the differential amplifier circuit;

[0007] A comparator circuit is connected to the positive and negative output terminals of the differential amplifier circuit. When the amplified EEG signal is greater than the reference signal, the positive output terminal of the comparator circuit outputs a high level, and the negative output terminal outputs a low level. When the amplified EEG signal is less than or equal to the reference signal, the positive output terminal of the comparator circuit outputs a low level, and the negative output terminal outputs a high level.

[0008] The logic circuit includes a signal shaping unit, an SR flip-flop, and a signal toggling unit. The set terminal of the SR flip-flop is connected to the positive output terminal of the comparator circuit through the signal shaping unit, and the reset terminal of the SR flip-flop is connected to the negative output terminal of the comparator circuit through the signal shaping unit. The signal toggling unit flips the signals output from both output terminals of the SR flip-flop before outputting them.

[0009] Optionally, the comparison circuit is connected to a clock signal to control its own working state. When the clock signal is high, the comparison circuit compares the amplified EEG signal with the reference signal, thereby outputting corresponding high and low levels at the two output terminals of the comparison circuit. When the clock signal is low, both output terminals of the comparison circuit output high levels, and the output state of the SR flip-flop remains the same as the output state of the SR flip-flop when the previous high-level clock signal was received.

[0010] Optionally, the differential amplifier circuit is a differential amplifier circuit with cross-coupled MOS transistors.

[0011] Optionally, the differential amplifier circuit includes a first to a seventh MOS transistor, wherein the first to third MOS transistors are all PMOS transistors, and the fourth to seventh MOS transistors are all NMOS transistors;

[0012] The source of the first MOSFET is connected to the power supply voltage, and the gate of the first MOSFET is connected to the control signal. The drain of the first MOSFET is connected to the source of the second MOSFET and the source of the third MOSFET. The gate of the second MOSFET serves as the positive input terminal of the differential amplifier circuit, and the gate of the third MOSFET serves as the negative input terminal of the differential amplifier circuit. The drain of the second MOSFET is connected to the drain of the fifth MOSFET, and the drain of the third MOSFET is connected to the drain of the sixth MOSFET. The drain and gate of the fourth MOSFET are both connected to the gate of the sixth MOSFET, and the drain and gate of the seventh MOSFET are both connected to the gate of the fifth MOSFET. The sources of the fourth, fifth, sixth, and seventh MOSFETs are all grounded. The drain of the fourth MOSFET leads to the negative output terminal of the differential amplifier, and the drain of the seventh MOSFET leads to the positive output terminal of the differential amplifier.

[0013] Optionally, the gain of the differential amplifier circuit is greater than or equal to 6 times.

[0014] Optionally, the comparison circuit includes a StrongARM Latch comparator.

[0015] Optionally, the comparator circuit includes eight to eighteenth MOS transistors, wherein the eighteenth to thirteenth MOS transistors are PMOS transistors and the fourteenth to eighteenth MOS transistors are NMOS transistors;

[0016] The sources of the eighth to thirteenth MOSFETs are all connected to the power supply voltage. The drains of the tenth MOSFET, the ninth MOSFET, the fourteenth MOSFET, the gate of the eleventh MOSFET, and the gate of the fifteenth MOSFET are connected together. The drains of the eleventh MOSFET, the twelfth MOSFET, the fifteenth MOSFET, the gate of the tenth MOSFET, and the gate of the fourteenth MOSFET are connected together. The sources of the fourteenth MOSFET, the eighth MOSFET, and the sixteenth MOSFET are connected together. The sources of the fifteenth MOSFET, the seventeenth MOSFET, and the thirteenth MOSFET are connected together. The sources of the sixteenth MOSFET and the seventeenth MOSFET are both connected to the drain of the eighteenth MOSFET. The source of the eighteenth MOSFET is grounded.

[0017] The gates of the eighth MOS transistor, the ninth MOS transistor, the twelfth MOS transistor, the thirteenth MOS transistor, and the eighteenth MOS transistor are all connected to a clock signal;

[0018] The gate of the sixteenth MOS transistor serves as the positive input terminal of the comparator circuit, the seventeenth MOS transistor serves as the negative input terminal of the comparator circuit, the drain of the tenth MOS transistor leads to the negative output terminal of the comparator circuit, and the drain of the eleventh MOS transistor leads to the positive output terminal of the comparator circuit.

[0019] Optionally, the signal shaping unit includes multiple first inverters and multiple second inverters. The set terminal of the SR flip-flop is connected to the positive output terminal of the comparator circuit through an even number of cascaded first inverters, and the reset terminal of the SR flip-flop is connected to the negative output terminal of the comparator circuit through an even number of cascaded second inverters.

[0020] Optionally, the SR trigger is a NAND gate SR trigger.

[0021] Optionally, the signal flipping unit includes multiple third inverters, and the two outputs of the SR flip-flop are respectively connected to an odd number of cascaded third inverters.

[0022] The above-described EEG signal processing circuit includes a differential amplifier circuit, a comparator circuit, and a logic circuit. The differential amplifier circuit amplifies the EEG signal, and the comparator circuit compares the amplified EEG signal with a reference signal and outputs high and low levels, thus acting as a digital-to-analog converter. The signal shaping unit shapes and strengthens the signal output from the comparator circuit to obtain a high-quality signal. After processing by an SR flip-flop, the signal is finally output through a signal flipping unit. In this way, the EEG signal processing circuit of the present invention can obtain a high-precision EEG signal, improve the driving efficiency of the signal for subsequent digital circuits, ensure the accuracy and stability of signal transmission, and enhance the flexibility and configurability of the system. Attached Figure Description

[0023] Those skilled in the art will understand that the accompanying drawings are provided to better understand the invention and do not constitute any limitation on the scope of the invention. Wherein:

[0024] Figure 1 is a schematic diagram of an electroencephalogram (EEG) signal processing circuit according to an embodiment of the present invention;

[0025] Figure 2 is a schematic diagram of a differential amplifier circuit according to an embodiment of the present invention;

[0026] Figure 3 is a schematic diagram of a comparison circuit according to an embodiment of the present invention;

[0027] Figure 4 is a schematic diagram of a logic circuit according to an embodiment of the present invention.

[0028] In the attached image:

[0029] 10 - Differential amplifier circuit; 20 - Comparator circuit; 30 - Signal shaping unit; 40 - SR flip-flop; 50 - Signal toggle unit;

[0030] M1 - First MOSFET; M2 - Second MOSFET; M3 - Third MOSFET; M4 - Fourth MOSFET; M5 - Fifth MOSFET; M6 - Sixth MOSFET; M7 - Seventh MOSFET; M8 - Eighth MOSFET; M9 - Ninth MOSFET; M10 - Tenth MOSFET; M11 - Eleventh MOSFET; M12 - Twelfth MOSFET; M13 - Thirteenth MOSFET; M14 - Fourteenth MOSFET; M15 - Fifteenth MOSFET; M16 - Sixteenth MOSFET; M17 - Seventeenth MOSFET; M8 - Eighteenth MOSFET;

[0031] U1 - First inverter; U2 - Second inverter; U3 - Third inverter. Detailed Implementation

[0032] To make the objectives, advantages, and features of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and are not drawn to scale, and are only used to facilitate and clarify the explanation of the embodiments of this invention. Furthermore, the structures shown in the drawings are often part of the actual structures. In particular, different figures may emphasize different aspects and may sometimes use different scales.

[0033] As used in this invention, the singular forms “a,” “an,” and “the” include plural objects; the term “or” is generally used to mean “and / or”; the term “a number” is generally used to mean “at least one”; and the term “at least two” is generally used to mean “two or more”. Furthermore, the terms “first,” “second,” and “third” are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as “first,” “second,” or “third” may explicitly or implicitly include one or at least two of that feature. “One end” and “the other end,” as well as “proximal end” and “distal end,” generally refer to two corresponding parts, including not only endpoints. The terms “installed,” “connected,” and “joined” should be interpreted broadly, for example, as a fixed connection, a detachable connection, or an integral part; a mechanical connection or an electrical connection; a direct connection or an indirect connection through an intermediate medium; or a connection within two elements or an interaction between two elements. Furthermore, as used in this invention, the phrase "one element is disposed on another element" generally only indicates that there is a connection, coupling, cooperation, or transmission relationship between the two elements, and the connection, coupling, cooperation, or transmission between the two elements can be direct or indirect through an intermediate element. It should not be construed as indicating or implying a spatial positional relationship between the two elements, i.e., one element can be located arbitrarily inside, outside, above, below, or to one side of the other element, unless otherwise explicitly stated. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0034] Figure 1 is a schematic diagram of an electroencephalogram (EEG) signal processing circuit according to an embodiment of the present invention. Referring to Figure 1, an embodiment of the present invention schematically provides an EEG signal processing circuit, which includes a differential amplifier circuit 10, a comparison single-channel, and a logic circuit. The EEG signal is input to the positive input terminal of the differential amplifier circuit 10, and a reference signal is input to the negative input terminal of the differential amplifier circuit 10. The gain of the differential amplifier circuit 10 is fixed, amplifying the EEG signal. The gain of the differential amplifier circuit 10 is greater than or equal to 6 times. The comparator circuit 20 is connected to the positive and negative output terminals of the differential amplifier circuit 10. Specifically, the positive input terminal of the comparator is connected to the positive output terminal of the differential amplifier circuit 10, and the negative input terminal of the comparator is connected to the negative output terminal of the differential amplifier circuit 10, thereby comparing the amplified EEG signal with the reference signal. When the amplified EEG signal is greater than the reference signal, the positive output terminal of the comparator circuit 20 outputs a high level, and the negative output terminal of the comparator circuit 20 outputs a low level. When the amplified EEG signal is less than or equal to the reference signal, the positive output terminal of the comparator circuit 20 outputs a low level, and the negative output terminal of the comparator circuit 20 outputs a high level. The logic circuit includes a signal shaping unit 30, an SR flip-flop 40, and a signal toggling unit 50. The set terminal of the SR flip-flop 40 is connected to the positive output terminal of the comparator circuit 20 through the signal shaping unit 30, and the reset terminal of the SR flip-flop 40 is connected to the negative output terminal of the comparator circuit 20 through the signal shaping unit 30. The signal toggling unit 50 flips the signals output from both terminals of the SR flip-flop 40 before outputting them. As those skilled in the art will understand, the signal shaping unit 30 shapes the signal output from the comparator circuit 20, the signal toggling unit 50 flips the phase of the signal, and the function of the SR flip-flop 40 is to convert its input signal into a stable output.

[0035] The above-described EEG signal processing circuit amplifies the EEG signal through a differential amplifier circuit 10. A comparator circuit 20 compares the amplified EEG signal with a reference signal and outputs high and low levels, thus acting as a digital-to-analog converter. A signal shaping unit 30 shapes and strengthens the signal output from the comparator circuit 20 to obtain a high-quality signal. The signal is then processed by an SR flip-flop 40 and finally output through a signal flipping unit 50. In this way, the EEG signal processing circuit of the present invention can obtain a high-precision EEG signal, improve the driving efficiency of the signal for subsequent digital circuits, ensure the accuracy and stability of signal transmission, and enhance the flexibility and configurability of the system.

[0036] Furthermore, the comparator circuit 20 is connected to a clock signal to control its own working state. When the clock signal is high, the comparator circuit 20 works in the comparison state, thereby comparing the amplified EEG signal with the reference signal, and then outputting the corresponding high and low levels at the two output terminals of the comparator circuit 20. When the clock signal is low, the comparator circuit 20 does not compare the EEG signal with the reference signal, and both output terminals of the comparator circuit 20 output high levels. At this time, the output state of the SR flip-flop 40 remains the same as the output state of the SR flip-flop 40 when the previous high-level clock signal was received.

[0037] Preferably, the differential amplifier circuit 10 is a differential amplifier circuit 10 with cross-coupled MOSFETs. A differential amplifier with cross-coupled MOSFETs refers to the interconnection between the source / gate circuits of two or more MOSFETs, which can effectively form a negative impedance, increase the load impedance, realize signal amplification or other circuit functions, improve the amplifier gain, and improve the circuit.

[0038] Figure 2 is a schematic diagram of a differential amplifier circuit according to an embodiment of the present invention. As an example, the differential amplifier circuit 10 includes first to seventh MOS transistors, where the first to third MOS transistors are all PMOS transistors, and the fourth to seventh MOS transistors are all NMOS transistors. The source of the first MOS transistor M1 is connected to the power supply voltage (VDD), and the gate of the first MOS transistor M1 is connected to the control signal (Vb). The drain of the first MOS transistor M1 is connected to the source of the second MOS transistor M2 and the source of the third MOS transistor M3. The gate of the second MOS transistor M2 serves as the positive input terminal (Vin1+) of the differential amplifier circuit 10, and the gate of the third MOS transistor M3 serves as the negative input terminal (Vin1-) of the differential amplifier circuit 10. The drain of the second MOS transistor M2 is connected to the drain of the fifth MOS transistor M5, the drain of the third MOS transistor M3 is connected to the drain of the sixth MOS transistor M6, and both the drain and gate of the fourth MOS transistor M4 are connected to the gate of the sixth MOS transistor M6. The seventh MOS transistor M7... The drain and gate of the first MOSFET M1 are both connected to the gate of the fifth MOSFET M5. The sources of the fourth MOSFET M4, fifth MOSFET M5, sixth MOSFET M6, and seventh MOSFET M7 are all grounded. The drain of the fourth MOSFET M4 leads to the negative output terminal (Vout1-) of the differential amplifier, and the drain of the seventh MOSFET M7 leads to the positive output terminal (Vout1+) of the differential amplifier. The signal Vb controls the on / off state of the first MOSFET M1, thereby controlling the operating state of the differential amplifier.

[0039] Preferably, the comparator circuit 20 employs a StrongARM Latch comparator. As will be understood by those skilled in the art, the StrongARM Latch comparator has extremely low static power consumption, can directly generate rail-to-rail output signals to ensure signal integrity, and its input signal comes from the differential pair signal output by the differential amplifier circuit 10, ensuring the comparator's high-precision performance.

[0040] Figure 3 is a schematic diagram of a comparator circuit according to an embodiment of the present invention. As an example, the comparator circuit 20 includes eighteenth to eighteenth MOS transistors, with the eighth to thirteenth MOS transistors being PMOS transistors and the fourteenth to eighteenth MOS transistors being NMOS transistors. The sources of each of the eighth to thirteenth MOS transistors are connected to the power supply voltage (VDD). The drains of the tenth MOS transistor M10, the ninth MOS transistor M9, the fourteenth MOS transistor M14, the gate of the eleventh MOS transistor M11, and the gate of the fifteenth MOS transistor M15 are connected together. The drains of the eleventh MOS transistor M11, the twelfth MOS transistor M12, the fifteenth MOS transistor M15, the gate of the tenth MOS transistor M10, and the gate of the fourteenth MOS transistor M14 are connected together. The source of the fourteenth MOS transistor M14, the drain of the eighth MOS transistor M8, and the drain of the sixteenth MOS transistor M16 are connected together. The source of the fifteenth MOSFET M15, the drain of the seventeenth MOSFET M17, and the drain of the thirteenth MOSFET M13 are connected together. The sources of the sixteenth MOSFET M16 and the seventeenth MOSFET M17 are both connected to the drain of the eighteenth MOSFET M18, and the source of the eighteenth MOSFET M18 is grounded. The gates of the eighth MOSFET M8, the ninth MOSFET M9, the twelfth MOSFET M12, the thirteenth MOSFET M13, and the eighteenth MOSFET M18 are all connected to the clock signal (Clk). The gate of the sixteenth MOSFET M16 serves as the positive input terminal (Vin2+) of the comparator circuit 20, the seventeenth MOSFET M17 serves as the negative input terminal (Vin2-) of the comparator circuit 20, the drain of the tenth MOSFET M10 leads to the negative output terminal (Vout2-) of the comparator circuit 20, and the drain of the eleventh MOSFET M11 leads to the positive output terminal (Vout2+) of the comparator circuit 20. Furthermore, the substrates of the eighth to fifteenth MOSFETs are all connected to the power supply voltage VDD, and the substrates of the sixteenth to eighteenth MOSFETs are all grounded. Thus, when the clock signal Clk is high, the comparator circuit 20 enters the comparison state and compares the amplified EEG signal with the reference signal; when the clock signal Clk is low, the comparator circuit 20 does not compare the EEG signal with the reference signal, and both outputs of the comparator circuit 20 will be at a high level.

[0041] Figure 4 is a schematic diagram of a logic circuit according to an embodiment of the present invention. Referring to Figure 4, the signal shaping unit 30 includes multiple first inverters U1 and multiple second inverters U2. The set terminal (i.e., the S terminal of the SR flip-flop 40) is connected to the positive output terminal of the comparator circuit 20 through an even number of cascaded first inverters U1, and the reset terminal (i.e., the R terminal of the SR flip-flop 40) is connected to the negative output terminal of the comparator circuit 20 through an even number of cascaded second inverters U2. In this way, the signal output by the comparator circuit 20 is shaped and strengthened through the inverter chain.

[0042] Referring to Figure 4, the SR flip-flop 40 is a NAND gate SR flip-flop 40, that is, the SR flip-flop 40 in this embodiment is composed of two cross-connected NAND gates.

[0043] Referring to Figure 4, the signal flipping unit 50 includes multiple third inverters U3, and the two outputs of the SR flip-flop 40 are respectively connected to an odd number of cascaded third inverters U3.

[0044] While the present invention has been disclosed above with reference to preferred embodiments, these embodiments are not intended to limit the invention. For any person skilled in the art, many possible variations and modifications can be made to the technical solutions of the present invention based on the disclosed technical content, or equivalent embodiments can be modified accordingly, without departing from the scope of the present invention. Therefore, any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of the present invention, without departing from the content of the present invention, shall still fall within the scope of protection of the present invention.

Claims

1. A brainwave signal processing circuit, characterized in that, include: A differential amplifier circuit, wherein an EEG signal is input to the positive input terminal of the differential amplifier circuit, and a reference signal is input to the negative input terminal of the differential amplifier circuit; A comparator circuit is connected to the positive and negative output terminals of the differential amplifier circuit. When the amplified EEG signal is greater than the reference signal, the positive output terminal of the comparator circuit outputs a high level, and the negative output terminal outputs a low level. When the amplified EEG signal is less than or equal to the reference signal, the positive output terminal of the comparator circuit outputs a low level, and the negative output terminal outputs a high level. The logic circuit includes a signal shaping unit, an SR flip-flop, and a signal toggling unit. The set terminal of the SR flip-flop is connected to the positive output terminal of the comparator circuit through the signal shaping unit, and the reset terminal of the SR flip-flop is connected to the negative output terminal of the comparator circuit through the signal shaping unit. The signal toggling unit flips the signals output from both output terminals of the SR flip-flop before outputting them.

2. The EEG signal processing circuit according to claim 1, characterized in that, The comparator circuit is connected to a clock signal to control its own working state. When the clock signal is high, the comparator circuit compares the amplified EEG signal with the reference signal, and outputs corresponding high and low levels at the two output terminals of the comparator circuit. When the clock signal is low, both output terminals of the comparator circuit output high levels, and the output state of the SR flip-flop remains the same as the output state of the SR flip-flop when the previous high-level clock signal was received.

3. The EEG signal processing circuit according to claim 1, characterized in that, The differential amplifier circuit is a differential amplifier circuit with cross-coupled MOS transistors.

4. The EEG signal processing circuit according to claim 3, characterized in that, The differential amplifier circuit includes a first MOS transistor, a second MOS transistor, a third MOS transistor, a fourth MOS transistor, a fifth MOS transistor, a sixth MOS transistor, and a seventh MOS transistor. The first MOS transistor to the third MOS transistor are all PMOS transistors, and the fourth NMOS transistor to the seventh MOS transistor are all NMOS transistors. The source of the first MOSFET is connected to the power supply voltage, the gate of the first MOSFET is connected to the control signal, and the drain of the first MOSFET is connected to the source of the second MOSFET and the third MOSFET. The source of the MOSFET, the gate of the second MOSFET serves as the positive input terminal of the differential amplifier circuit, the gate of the third MOSFET serves as the negative input terminal of the differential amplifier circuit, the drain of the second MOSFET is connected to the drain of the fifth MOSFET, the drain of the third MOSFET is connected to the drain of the sixth MOSFET, the drain and gate of the fourth MOSFET are both connected to the gate of the sixth MOSFET, and the drain and gate of the seventh MOSFET are both connected to the gate of the fifth MOSFET. The sources of the fourth, fifth, sixth, and seventh MOSFETs are all grounded. The drain of the fourth MOSFET leads to the negative output terminal of the differential amplifier, and the drain of the seventh MOSFET leads to the positive output terminal of the differential amplifier.

5. The EEG signal processing circuit according to claim 1, characterized in that, The gain of the differential amplifier circuit is greater than or equal to 6 times.

6. The EEG signal processing circuit according to claim 1, characterized in that, The comparison circuit includes a StrongARM Latch comparator.

7. The EEG signal processing circuit according to claim 1, characterized in that, The comparator circuit includes an eighth MOS transistor, a ninth MOS transistor, a tenth MOS transistor, an eleventh MOS transistor, a twelfth MOS transistor, a thirteenth MOS transistor, a fourteenth MOS transistor, a fifteenth MOS transistor, a sixteenth MOS transistor, a seventeenth MOS transistor, and an eighteenth MOS transistor, wherein the eighth to the thirteenth MOS transistors are all PMOS transistors, and the fourteenth to the eighteenth MOS transistors are all NMOS transistors; The sources of each of the eighth to thirteenth MOS transistors are connected to the power supply voltage. The drains of the tenth, ninth, and fourteenth MOS transistors, the gate of the eleventh MOS transistor, and the gate of the fifteenth MOS transistor are connected together. The drains of the eleventh, twelfth, and fifteenth MOS transistors, the gate of the tenth MOS transistor, and the gate of the fourteenth MOS transistor are connected together. The sources of the fourteenth MOS transistor, the drain of the eighth MOS transistor, and the drain of the sixteenth MOS transistor are connected together. The sources of the fifteenth, seventeenth, and thirteenth MOS transistors are connected together. The sources of the sixteenth and seventeenth MOS transistors are both connected to the drain of the eighteenth MOS transistor. The source of the eighteenth MOS transistor is grounded. The eighth MOS transistor, the ninth MOS transistor, the twelfth MOS transistor, the tenth MOS transistor The gates of the three MOS transistors and the eighteenth MOS transistor are all connected to the clock signal; The gate of the sixteenth MOS transistor serves as the positive input terminal of the comparator circuit, the seventeenth MOS transistor serves as the negative input terminal of the comparator circuit, the drain of the tenth MOS transistor leads to the negative output terminal of the comparator circuit, and the drain of the eleventh MOS transistor leads to the positive output terminal of the comparator circuit.

8. The EEG signal processing circuit according to claim 1, characterized in that, The signal shaping unit includes multiple first inverters and multiple second inverters. The set terminal of the SR flip-flop is connected to the positive output terminal of the comparator circuit through an even number of cascaded first inverters, and the reset terminal of the SR flip-flop is connected to the negative output terminal of the comparator circuit through an even number of cascaded second inverters.

9. The EEG signal processing circuit according to claim 1, characterized in that... The SR trigger is a NAND gate SR trigger.

10. The EEG signal processing circuit according to claim 1, characterized in that, The signal flipping unit includes multiple third inverters, and the two outputs of the SR flip-flop are respectively connected to an odd number of cascaded third inverters.

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