Sensing circuit, memory and access control method therefor, and electronic device

Abstract

A sensing circuit, a memory and an access control method therefor, and an electronic device. The sensing circuit comprises: a first sense amplifier (41), a second sense amplifier (42), a first reference memory cell (11), a first gating sub-circuit (21), a second reference memory cell (12), and a second gating sub-circuit (22), the first reference memory cell (11) being connected to a first reference bit line (BLR1), and then being connected to a first input terminal (S11) of the first sense amplifier (41) by means of the first gating sub-circuit (21), the second reference memory cell (12) being connected to a second reference bit line (BLR0), and then being connected to a third input terminal (S21) of the second sense amplifier (42) by means of the second gating sub-circuit (22), and a second input terminal (S12) of the first sense amplifier (41) and a fourth input terminal (S22) of the second sense amplifier (42) being connected to a memory cell to be accessed; and the first reference memory cell (11) stores a logic "1," and the second reference memory cell (12) stores a logic "0."

Description

Sensing circuit, memory and access control method thereof, and electronic device

[0001] The present application claims priority to the Chinese patent application No. 2024110465742, filed on July 31, 2024, and entitled "Sensing circuit, memory and access control method thereof, and electronic device", the content of which is hereby incorporated by reference into the present application. TECHNICAL FIELD

[0002] The embodiments of the present disclosure relate to, but are not limited to, device design in the field of semiconductor technology, and in particular to a sensing circuit, a memory and an access control method thereof, and an electronic device. BACKGROUND

[0003] With the development of integrated circuit technology, the critical dimension of devices is increasingly shrinking, and the types and quantities of devices contained in a single chip are increasing, so that any slight difference in process production can affect the performance of the device.

[0004] In order to reduce the cost of products as much as possible, people want to make as many device units as possible on a limited substrate. Since the advent of Moore's Law, various semiconductor structure designs and process optimizations have been proposed in the industry to meet people's current product needs.

[0005] SUMMARY

[0006] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0007] The embodiments of the present disclosure provide a sensing circuit, comprising: a first sensing amplifier, a second sensing amplifier, a first reference storage unit, a first gating sub-circuit, a second reference storage unit and a second gating sub-circuit, wherein: the first sensing amplifier comprises a first input end and a second input end, and the second sensing amplifier comprises a third input end and a fourth input end;

[0008] The first reference storage unit is connected to a first reference bit line, the first reference bit line is connected to the first input end of the first sensing amplifier through the first gating sub-circuit, the second reference storage unit is connected to a second reference bit line, the second reference bit line is connected to the third input end of the second sensing amplifier through the second gating sub-circuit, the second input end of the first sensing amplifier and the fourth input end of the second sensing amplifier are connected to a storage unit to be accessed; the first gating sub-circuit is connected to a first gating control line, the second gating sub-circuit is connected to a second gating control line, the first reference storage unit stores logical data "1", and the second reference storage unit stores logical data "0";

[0009] The first gating sub-circuit is configured to electrically connect or disconnect the first reference bit line and the first input terminal of the first sense amplifier under the control of the first gating control line, and electrically connect the first reference bit line and the first input terminal of the first sense amplifier in the signal sensing stage of the to-be-accessed memory cell;

[0010] The second gating sub-circuit is configured to electrically connect or disconnect the second reference bit line and the third input terminal of the second sense amplifier under the control of the second gating control line, and electrically connect the second reference bit line and the third input terminal of the second sense amplifier in the signal sensing stage of the to-be-accessed memory cell.

[0011] In some embodiments, the first gating control line and the second gating control line are the same gating control line.

[0012] In some embodiments, the sensing circuit further comprises a first data writing sub-circuit and a second data writing sub-circuit, wherein:

[0013] The first data writing sub-circuit is configured to load a voltage corresponding to logical data "1" to the first reference bit line in a data writing stage.

[0014] The second data writing sub-circuit is configured to load a voltage corresponding to logical data "0" to the second reference bit line in a data writing stage, and the data writing stage is a period of time outside the signal sensing stage of the to-be-accessed memory cell.

[0015] In some embodiments, the first data writing sub-circuit and the second data writing sub-circuit are connected to the same writing control line, and the writing control line is configured to control the following operations to be performed at the same time: the first data writing sub-circuit loads a voltage corresponding to logical data "1" to the first reference bit line, and the second data writing sub-circuit loads a voltage corresponding to logical data "0" to the second reference bit line.

[0016] In some embodiments, the bit line connected to the to-be-accessed memory cell is connected to the second input terminal of the first sense amplifier through a third gating sub-circuit, and connected to the fourth input terminal of the second sense amplifier through a fourth gating sub-circuit; the third gating sub-circuit is connected to a third gating control line, and the fourth gating sub-circuit is connected to a fourth gating control line, wherein,

[0017] The third gating sub-circuit is configured to electrically connect the bit line and the second input terminal of the first sense amplifier under the control of the third gating control line.

[0018] The fourth gating sub-circuit is configured to electrically connect the bit line and the second input terminal of the first sense amplifier under the control of the fourth gating control line.

[0019] In some embodiments, the second input terminal of the first sense amplifier is connected to a plurality of bit lines to which the storage cells to be accessed are connected, the fourth input terminal of the second sense amplifier is connected to a plurality of bit lines to which the storage cells to be accessed are connected, and each of the bit lines is connected to the second input terminal of the first sense amplifier through one of the third gating sub-circuits, and each of the bit lines is connected to the fourth input terminal of the second sense amplifier through one of the fourth gating sub-circuits.

[0020] In some embodiments, at least one of the plurality of storage cells to which the second input terminal of the first sense amplifier or the fourth input terminal of the second sense amplifier is connected belongs to the same storage array as the first reference storage cell, and at least one of the plurality of storage cells to which the second input terminal of the first sense amplifier or the fourth input terminal of the second sense amplifier is connected belongs to the same storage array as the second reference storage cell.

[0021] In some embodiments, the first reference storage cell and the second reference storage cell belong to the same storage array or different storage arrays.

[0022] In some embodiments, the first reference storage cell and the second reference storage cell are independent of the storage array in which the storage cells to be accessed are located.

[0023] In some embodiments, the first reference storage cell includes a first capacitor, the second reference storage cell includes a second capacitor, the storage cells to be accessed include a capacitor, the capacitance value of the first capacitor is smaller than that of the capacitor of the storage cells to be accessed, the capacitance value of the second capacitor is smaller than that of the capacitor of the storage cells to be accessed, the capacitance value of the first reference bit line is smaller than that of the bit line connected to the storage cells to be accessed, and the capacitance value of the second reference bit line is smaller than that of the bit line connected to the storage cells to be accessed.

[0024] The embodiments of the present disclosure provide a memory, which includes the sensing circuit and the storage cells connected to the sensing circuit.

[0025] In some embodiments, the memory includes a plurality of memory arrays distributed along a second direction on a substrate, each of the memory arrays includes a plurality of memory cell arrays stacked along a direction perpendicular to the substrate, each of the memory cell arrays includes a plurality of memory cells arrayed along a first direction and a second direction, a plurality of local bit lines extending along the second direction, a first reference bit line extending along the second direction, a second reference bit line extending along the second direction, the local bit lines, the first reference bit line, and the second reference bit line of a same layer are connected to a same common bit line, the first reference bit line is connected to the common bit line through a first gating sub-circuit, the second reference bit line is connected to the common bit line, adjacent memory arrays of an nth memory array are distributed as an (n-1)th memory array and an (n+1)th memory array, each of the common bit lines corresponds to a first sense amplifier and a second sense amplifier, a common bit line of a kth layer of the nth memory array is connected to a second input terminal of the corresponding first sense amplifier and a fourth input terminal of the corresponding second sense amplifier, a common bit line of the kth layer of the (n-1)th memory array is connected to a first input terminal of the corresponding first sense amplifier, a common bit line of the kth layer of the (n+1)th memory array is connected to a third input terminal of the corresponding second sense amplifier, n is greater than 1, k is from 1 to K, and K is a number of layers of the memory cell arrays included in the memory array.

[0026] The embodiment of the present disclosure provides a method for controlling access of the memory, which is characterized by comprising:

[0027] In a signal sensing phase of the memory cell, the first gating sub-circuit is controlled to be turned on to electrically connect the first reference bit line and the first input terminal of the first sense amplifier, and the second gating sub-circuit is controlled to be turned on to electrically connect the second reference bit line and the third input terminal of the second sense amplifier.

[0028] In some embodiments, the method further comprises: in a phase other than the signal sensing phase of the memory cell, the first gating sub-circuit is controlled to be turned off to disconnect the first reference bit line and the first input terminal of the first sense amplifier, and the second gating sub-circuit is controlled to be turned off to disconnect the second reference bit line and the third input terminal of the second sense amplifier, a voltage corresponding to logic data "1" is loaded to the first reference bit line, and a voltage corresponding to logic data "0" is loaded to the second reference bit line.

[0029] In some embodiments, the method further comprises: when the storage unit to be accessed is located at the kth layer of the nth storage array, controlling the first gating sub-circuit connected with the first reference bit line of the kth layer of the nth-1th storage array to be turned on to electrically connect the first reference bit line of the kth layer of the nth-1th storage array and the common bit line, and controlling the second gating sub-circuit connected with the second reference bit line of the kth layer of the nth+1th storage array to be turned on to electrically connect the second reference bit line of the kth layer of the nth+1th storage array and the common bit line; or, controlling the second gating sub-circuit connected with the second reference bit line of the kth layer of the nth-1th storage array to be turned on to electrically connect the second reference bit line of the kth layer of the nth-1th storage array and the common bit line, and controlling the first gating sub-circuit connected with the first reference bit line of the kth layer of the nth+1th storage array to be turned on to electrically connect the first reference bit line of the kth layer of the nth+1th storage array and the common bit line.

[0030] The electronic device provided by the embodiments of the present disclosure includes the memory described above.

[0031] Other features and advantages of the present application will be set forth in the following description, and in part will become apparent to those skilled in the art from the description, or can be learned by practice of the present application. Other advantages of the present application can be realized and obtained by means of the instrumentalities and combinations described in the description and appended claims.

[0032] Other aspects can become apparent to those of ordinary skill in the art upon reading and understanding the following detailed description.

[0033] SUMMARY

[0034] The accompanying drawings are included to provide a further understanding of the present application, and constitute a part of this specification that is included to explain the present application, and do not limit the present application.

[0035] FIG. 1 is a schematic diagram of a sensing circuit according to an example embodiment;

[0036] FIG. 2 is a schematic diagram of a sensing circuit according to an example embodiment;

[0037] FIG. 3 is a schematic diagram of a sensing circuit according to another example embodiment;

[0038] FIG. 4 is a schematic diagram of a sense amplifier logic circuit according to an example embodiment;

[0039] FIG. 5 is a schematic diagram of a sense amplifier logic circuit according to an example embodiment;

[0040] FIG. 6 is a schematic diagram of a memory according to an example embodiment.

[0041] DETAILED DESCRIPTION

[0042] The embodiments of the present disclosure will be described in detail below with reference to the drawings. The features of the embodiments of the present disclosure and the embodiments can be combined with each other as long as there is no conflict.

[0043] Unless otherwise defined, technical terms or scientific terms used in the present disclosure should be understood as having the same meaning as commonly understood by one of ordinary skill in the art to which the present disclosure belongs.

[0044] The embodiments of the present disclosure are not necessarily limited to the sizes of the components shown in the drawings, and the shapes and sizes of the components shown in the drawings do not reflect actual proportions. In addition, the drawings schematically show limited embodiments, and the embodiments of the present disclosure are not limited to the embodiments shown in the drawings.

[0045] In the present disclosure, ordinal numbers such as "first", "second", "third", and the like are set in order to avoid confusion of the components, and do not represent any order, number, or importance.

[0046] In the present disclosure, in order to facilitate the description, words indicating the orientation or positional relationship such as "middle", "upper", "lower", "front", "rear", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like are used to describe the positional relationship of the components with reference to the drawings, and are only for the convenience of describing the present specification and simplifying the description, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the present disclosure. The positional relationship of the components is appropriately changed according to the direction in which each component is described. Therefore, it is not limited to the words described in the disclosure, and can be appropriately replaced according to the situation.

[0047] In the present disclosure, unless otherwise explicitly defined and limited, the terms "mount", "connected", "connection" should be broadly understood. For example, it can be a physical connection or a signal connection, it can be a contact connection or an integrally connected connection; it can be directly connected, or indirectly connected through an intermediate, or the communication inside two elements. For those skilled in the art, the specific meaning of the above terms in the present disclosure can be understood according to the specific circumstances.

[0048] In the present disclosure, a transistor refers to an element including at least a gate electrode, a drain electrode, and a source electrode. The transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain electrode) and the source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. In the present disclosure, the channel region refers to a region through which current mainly flows.

[0049] In the present disclosure, it can be that the first electrode is a drain electrode and the second electrode is a source electrode, or it can be that the first electrode is a source electrode and the second electrode is a drain electrode. In the case of using a transistor of opposite polarity, or in the case of a change in the direction of current in circuit operation, the functions of the "source electrode" and the "drain electrode" are sometimes interchanged. Therefore, in the present disclosure, the "source electrode" and the "drain electrode" can be interchanged.

[0050] In the present disclosure, "connection" includes the case where the constituent elements are connected together through an element having some kind of electrical action. The "element having some kind of electrical action" is not particularly limited as long as it can perform the transmission and reception of an electrical signal between the connected constituent elements. Examples of the "element having some kind of electrical action" include not only electrodes and wiring but also switching elements such as transistors, resistors, inductors, capacitors, other elements having various functions, and the like.

[0051] Fig. 1 is a schematic diagram of a sensing circuit according to an embodiment of the present disclosure. As shown in Fig. 1, the sensing circuit can include a first sense amplifier (SA) 41, a second sense amplifier 42, a first reference sub-circuit 31, and a second reference sub-circuit 32. The first reference sub-circuit 31 can include a first reference storage unit 11 and a first gating sub-circuit 21. The second reference sub-circuit 32 can include a second reference storage unit 12 and a second gating sub-circuit 22. The first reference storage unit 11 is connected to a first reference bit line BLR1, which is connected to a first input terminal S11 of the first sense amplifier 41 through the first gating sub-circuit 21. The second reference storage unit 12 is connected to a second reference bit line BLR0, which is connected to a third input terminal S21 of the second sense amplifier 42 through the second gating sub-circuit 22. The first gating sub-circuit 21 is connected to a first gating control line. The second gating sub-circuit 22 is connected to a second gating control line. The first gating sub-circuit 21 is configured to electrically connect or disconnect the first reference bit line BLR1 and the first input terminal S11 of the first sense amplifier 41 under control of the first gating control line. The second gating sub-circuit 22 is configured to electrically connect or disconnect the second reference bit line BLR0 and the third input terminal S21 of the second sense amplifier 42 under control of the second gating control line. A second input terminal S12 of the first sense amplifier 41 and a fourth input terminal S22 of the second sense amplifier 42 are connected to a bit line connected to a storage unit to be accessed. The first reference storage unit 11 stores logical data "1", and the second reference storage unit 12 stores logical data "0". As shown in Fig. 1, a storage unit to be accessed can include a transistor and a capacitor, wherein a gate electrode of the transistor is connected to a word line, a first electrode of the transistor is connected to a bit line BL, and a second electrode of the transistor is connected to one end of the capacitor.

[0052] In some embodiments, the first gating control line and the second gating control line can be the same gating control line, i.e., the gating control line ISO 0 / 1 .

[0053] The first reference sub-circuit 31 is configured to electrically connect the first reference bit line BLR1 and the first input terminal S11 of the first sense amplifier 41 during a signal sensing phase of the storage unit to be accessed, and output a first voltage generated by charge sharing between the first reference bit line BLR1 and the first reference storage unit 11 to the first input terminal S11 of the first sense amplifier 41.

[0054] The second reference sub-circuit 32 is configured to electrically connect the second reference bit line BLR0 and the third input end S21 of the second sense amplifier 42 in the signal sensing stage of the storage unit to be accessed, and output a second voltage generated by charge sharing between the second reference bit line BLR2 and the second reference storage unit 12 to the third input end S21 of the second sense amplifier 42.

[0055] In some embodiments, the first gating sub-circuit 21 can include a first transistor T1, the gate electrode of the first transistor T1 is connected to the first gating control line, the first electrode is connected to the first reference bit line BLR1, and the second electrode is connected to the first input end S11 of the first sense amplifier 41.

[0056] In some embodiments, the second gating sub-circuit 22 can include a second transistor T2, the gate electrode of the second transistor T2 is connected to the second gating control line, the first electrode is connected to the second reference bit line BLR0, and the second electrode is connected to the third input end S21 of the second sense amplifier 42.

[0057] In some embodiments, the first reference storage unit 11 can include a first reference transistor TR1 and a first capacitor C1, the gate electrode of the first reference transistor TR1 is connected to the first reference word line, the first electrode is connected to the first reference bit line BLR1, and the second electrode is connected to the first end of the first capacitor C1, and the second end of the first capacitor C1 is connected to a common voltage terminal Vcom. The voltage of the common voltage terminal Vcom can be a fixed potential, such as a value between the voltage corresponding to the logic data "0" and the voltage corresponding to the logic data "1", for example, the voltage corresponding to the logic data "0" is "0", and the voltage corresponding to the logic data "1" is VDD, then the voltage of the common voltage terminal Vcom can be 1 / 2VDD.

[0058] In some embodiments, the second reference storage unit 12 can include a second reference transistor TR2 and a second capacitor C2, the gate electrode of the second reference transistor TR2 is connected to the second reference word line, the first electrode is connected to the second reference bit line BLR0, and the second electrode is connected to the first end of the second capacitor C2, and the second end of the second capacitor C2 is connected to the common voltage terminal Vcom.

[0059] In some embodiments, the first reference word line and the second reference word line can be the same control line, that is, the reference word line WL shown in FIG. 1. 0 / 1 .

[0060] The sensing circuit can further include a first data write sub-circuit 51 and a second data write sub-circuit 52, the first data write sub-circuit 51 is connected to a first write control line, and the second data write sub-circuit 52 is connected to a second write control line, wherein:

[0061] The first data write sub-circuit 51 is configured to write logical data "1" into the first reference storage unit 11 under the control of the first write control line;

[0062] The second data write sub-circuit 52 is configured to write logical data "0" into the second reference storage unit 12 under the control of the second write control line.

[0063] In some embodiments, the first data write sub-circuit 51 can include a third transistor T3, the gate electrode of the third transistor T3 is connected to the first write control line, the first electrode is connected to the first reference bit line BLR1, and the second electrode is connected to a first voltage terminal, the voltage of the first voltage terminal is the voltage corresponding to logical data "1", such as VDD.

[0064] In some embodiments, the second data write sub-circuit 52 can include a fourth transistor T4, the gate electrode of the fourth transistor T4 is connected to the second write control line, the first electrode is connected to the second reference bit line BLR0, and the second electrode is connected to a second voltage terminal, the voltage of the second voltage terminal is the voltage corresponding to logical data "0", such as the voltage of the ground terminal GND.

[0065] In some embodiments, the first write control line and the second write control line can be the same control line, such as the write control line W set0 / 1 . That is, logical data "1" can be written into the first reference storage unit 11 and logical data "0" can be written into the second reference storage unit 12 at the same time.

[0066] The following is described separately when the data stored in the storage unit to be accessed is "0" or "1".

[0067] When the storage unit to be accessed stores logical data "0", in the signal sensing stage, the first transistor T1 is turned on, the second transistor T2 is turned on, the first reference bit line BLR1 and the first reference storage unit 11 share the charge, so that the voltage of the first input end S11 of the first sensing amplifier 41 rises, the bit line BL connected to the storage unit to be accessed and the storage unit to be accessed share the charge, so that the voltage of the second input end S12 of the first sensing amplifier 41 decreases, and the voltage difference ΔV BL1 is approximately -VDD*Cs / (Cs+C BL), the voltage difference is twice the scheme of reading the data stored in the storage cell to be accessed using a sensing amplifier, i.e. the voltage difference is greatly increased. The second reference bit line BLR0 and the second reference storage cell 12 charge share, so that the voltage of the third input end S21 of the second sensing amplifier 42 is reduced, the bit line BL connected to the storage cell to be accessed and the storage cell to be accessed charge share, so that the voltage of the second input end S12 of the first sensing amplifier 41 is reduced, thereby the voltage difference ΔV BL0 can be ignored (both are the voltages after charge sharing with the storage cell storing logical data "0"), wherein Cs is the capacitance value of the capacitor of the storage cell to be accessed, C BL is the capacitance value of the bit line connected to the storage cell to be accessed. At this time, the first sensing amplifier 41 amplifies the voltage difference ΔV BL1 , pulls up the voltage of the first input end S11 of the first sensing amplifier 41 to the voltage corresponding to logical data "1", and pulls down the voltage of the second input end S12 of the first sensing amplifier 41 to the voltage corresponding to logical data "0", and correspondingly, the fourth input end S22 of the second sensing amplifier 42 is pulled down to the voltage corresponding to logical data "0", and the third input end S21 of the second sensing amplifier 42 is pulled up to the voltage corresponding to logical data "1", i.e. at this time, there is a negative voltage difference between the second input end S12 and the first input end S11 of the first sensing amplifier 41, and it is judged that the data stored in the storage cell to be accessed is "0", and there is a negative voltage difference between the fourth input end S22 and the third input end S21 of the second sensing amplifier 42, and it is judged that the data stored in the storage cell to be accessed is "0", so that the data of the storage cell to be accessed can be read out. After the signal amplification stage, the first transistor T1 is turned off, the second transistor T2 is turned off, the third transistor T3 and the fourth transistor T4 are turned on, the voltage of the first voltage end is loaded to the first reference bit line BLR1, the reference word line WL 0 / 1 loads an activation signal, and writes logical data "1" to the first reference storage cell 11, and the voltage of the second voltage end is loaded to the second reference bit line BLR0, and the reference word line WL 0 / 1 loads an activation signal, and writes logical data "0" to the second reference storage cell 12.

[0068] When the storage unit to be accessed stores logical data "1", in the signal sensing stage, the first transistor T1 is turned on, the second transistor T2 is turned on, the first reference bit line BLR1 and the first reference storage unit 11 charge share, so that the voltage of the first input end S11 of the first sensing amplifier 41 rises, the bit line BL of the storage unit to be accessed and the storage unit to be accessed charge share, so that the voltage of the second input end S12 of the first sensing amplifier 41 rises, and a voltage difference ΔV BL1 between the second input end S12 and the first input end S11 of the first sensing amplifier 41 is formed. The second reference bit line BLR0 and the second reference storage unit 12 charge share, so that the voltage of the third input end S21 of the second sensing amplifier 42 falls, the bit line BL of the storage unit to be accessed and the storage unit to be accessed charge share, so that the voltage of the second input end S12 of the first sensing amplifier 41 rises, and a voltage difference ΔV BL0 between the third input end S21 and the fourth input end S22 of the second sensing amplifier 42 is formed. The voltage difference ΔV BL is about VDD*Cs / (Cs+C BL0 ), which is twice the voltage difference of the conventional scheme of reading the data stored in the storage unit to be accessed using one sensing amplifier, that is, the voltage difference is greatly increased. At this time, the second sensing amplifier 42 amplifies the voltage difference ΔV BL0 , pulls up the voltage of the fourth input end S22 of the second sensing amplifier 42 to the voltage corresponding to the logical data "1", pulls down the voltage of the third input end S21 of the second sensing amplifier 42 to the voltage corresponding to the logical data "0", and correspondingly, pulls up the voltage of the second input end S12 of the first sensing amplifier 41 to the voltage corresponding to the logical data "1", and pulls up the voltage of the first input end S11 of the first sensing amplifier 41 to the voltage corresponding to the logical data "0", that is, at this time, there is a positive voltage difference between the second input end S12 and the first input end S11 of the first sensing amplifier 41, and there is a positive voltage difference between the fourth input end S22 and the third input end S21 of the second sensing amplifier 42, which judges that the data stored in the storage unit to be accessed is "1", so that the data of the storage unit to be accessed can be correctly read out. After the signal amplification stage, the first transistor T1 is turned off, the second transistor T2 is turned off, the third transistor T3 and the fourth transistor T4 are turned on, the voltage of the first voltage end is loaded to the first reference bit line BLR1, the reference word line WL 0 / 1 loads the activation signal, and the logical data "1" is written to the first reference storage unit 11. The voltage of the second voltage end is loaded to the second reference bit line BLR0, and the reference word line WL 0 / 1 loads the activation signal, and the logical data "0" is written to the second reference storage unit 12.

[0069] From the above working process, the scheme provided in this embodiment can realize at least one of the following: a smaller capacitor can be used for the storage unit, or more storage units can be connected to the bit line, which is conducive to increasing the device density or reducing the number of bit lines in the memory, or increasing the device density and reducing the number of bit lines in the memory. When the SA and the storage unit are manufactured on different dies, the scheme provided in this embodiment can greatly improve the device density. BL Without changing, the voltage difference is doubled. Therefore, if the voltage difference is unchanged, Cs can be reduced by half, or C BL may be doubled, or Cs is reduced by some, C BL is increased by some. That is, at least one of the following can be achieved: a smaller capacitor can be used for the storage unit, or more storage units can be connected to the bit line, which is conducive to increasing the device density or reducing the number of bit lines in the memory, or increasing the device density and reducing the number of bit lines in the memory. When the SA and the storage unit are manufactured on different dies, the scheme provided in this embodiment can greatly improve the device density.

[0070] In some embodiments, as shown in FIG. 2, the bit line BL connected to the storage unit to be accessed can be connected to the second input end S12 of the first sense amplifier 41 through a third gating sub-circuit 23, and can be connected to the fourth input end S22 of the second sense amplifier 42 through a fourth gating sub-circuit 24.

[0071] The third gating sub-circuit 23 is connected to a third gating control line. The fourth gating sub-circuit 24 is connected to a fourth gating control line. The third gating sub-circuit 23 is configured to electrically connect or disconnect the bit line BL and the second input end S12 of the first sense amplifier 41 under the control of the third gating control line. The fourth gating sub-circuit 24 is configured to electrically connect or disconnect the bit line BL and the fourth input end S22 of the second sense amplifier 42 under the control of the fourth gating control line. The scheme provided in this embodiment can realize the access or non-access of the bit line BL, which is conducive to the sharing of the first sense amplifier 41 and the second sense amplifier 42 by multiple BLs.

[0072] In some embodiments, the second input end S12 of the first sense amplifier 41 can be connected to multiple bit lines, and the fourth input end S22 of the second sense amplifier 42 can be connected to multiple bit lines BL. As shown in FIG. 2, the bit line BL and the word line WL are connected to the storage unit, and the bit line BL* and the word line WL* are connected to the same storage unit. The bit line BL and the bit line BL* are connected to the second input end S12 of the first sense amplifier 41 and the fourth input end S22 of the second sense amplifier 42 through different gating sub-circuits, respectively. Only 2 bit lines are shown in FIG. 2 to share the first sense amplifier 41 and the second sense amplifier 42, but the embodiments of the present disclosure are not limited thereto, and more bit lines can be shared. The multiple bit lines sharing the first sense amplifier 41 and the second sense amplifier 42 can come from different arrays, respectively.

[0073] In some embodiments, the first reference memory cell 11 and the second reference memory cell 12 are in the same memory array as one of the memory cells connected to the bit line connected to the first sense amplifier 41 or the second sense amplifier 42. That is, a memory array can include a plurality of memory cells, two of which are used as the first reference memory cell 11 and the second reference memory cell 12, and the rest of which are used for storage. The capacitor parameters and transistor parameters of the first reference memory cell 11 and the second reference memory cell 12 are the same as those of the other memory cells. The first reference memory cell 11 and the second reference memory cell 12 are manufactured in the same way as the other memory cells. Accordingly, the first reference bit line BLR1 and the second reference bit line BLR0 can be manufactured at the same time as the bit line BL. The bit line connected to the memory cell used as the first reference memory cell 11 in the memory array is used as the first reference bit line BLR1, and the bit line connected to the memory cell used as the second reference memory cell 12 in the memory array is used as the second reference bit line BLR0. The scheme provided in this embodiment does not require separate manufacturing of the first reference memory cell and the second reference memory cell, and can simplify the process.

[0074] In some embodiments, the first reference memory cell 11 and the second reference memory cell 12 can be located in different memory arrays.

[0075] In some embodiments, when there are multiple bit lines sharing the first sense amplifier 41 and the second sense amplifier 42, the first reference memory cell 11 and the second reference memory cell 12 can be located in different memory arrays from the memory cells to be accessed.

[0076] In some embodiments, the first reference memory cell 11 and the second reference memory cell 12 can be independent of the memory array. As shown in FIG. 3, the first reference memory cell 11 and the second reference memory cell 12 are arranged outside the memory array in which the memory cells to be accessed are located. That is, the first reference memory cell 11 and the second reference memory cell 12 can be manufactured separately, and the parameters of the first reference memory cell 11 and the second reference memory cell 12 can be different from those of the memory cells to be accessed. For example, compared with the memory cells to be accessed, the size of the capacitor of the first reference memory cell 11 can be reduced, the length of the first reference bit line BLR1 can be shortened so that the capacitance value of the first reference bit line BLR1 is reduced, the size of the capacitor of the second reference memory cell 12 can be reduced, and the length of the second reference bit line BLR0 can be shortened so that the capacitance value of the second reference bit line BLR0 is reduced, thereby reducing the occupied area, facilitating layout, and increasing the device density.

[0077] In some embodiments, the third gate control line and the fourth gate control line can be the same control line, i.e. the signal line ISO or ISO* shown in FIG. 2. The solution provided by the present embodiments can simplify the control logic.

[0078] In some embodiments, the third gate sub-circuit 23 can include a fifth transistor T5, a gate electrode of the fifth transistor T5 being connected to the third gate control line, a first electrode of the fifth transistor T5 being connected to the bit line BL, and a second electrode of the fifth transistor T5 being connected to a second input end S12 of the first sense amplifier 41.

[0079] In some embodiments, the fourth gate sub-circuit 24 can include a sixth transistor T6, a gate electrode of the sixth transistor T6 being connected to the fourth gate control line, a first electrode of the sixth transistor T6 being connected to the bit line BL, and a second electrode of the sixth transistor T6 being connected to a fourth input end S22 of the second sense amplifier 42.

[0080] FIG. 4 is an equivalent circuit diagram of the first sense amplifier 41 provided by some embodiments. As shown in FIG. 4, the first sense amplifier 41 is connected to the first input end S11, the second input end S12, the first enable end SAP EN, the first voltage control end SAP, the second enable end SAN EN, and the second voltage control end SAN, and is configured to amplify a differential input between the first input end S11 and the second input end S12 and output the amplified differential input through the first input end S11 and the second input end S12 under the control of the first enable end SAP EN, the second enable end SAN EN, the first voltage control end SAP, and the second voltage control end SAN.

[0081] In some embodiments, the first sense amplifier 41 can include a seventh transistor T7, an eighth transistor T8, a ninth transistor T9, a tenth transistor T10, an eleventh transistor T11, and a twelfth transistor T12, wherein:

[0082] A gate electrode of the seventh transistor T7 and a gate electrode of the ninth transistor T9 are connected to the second input end S12, a first electrode of the seventh transistor T7 is connected to a first electrode of the eleventh transistor T11, and a second electrode of the seventh transistor T7 is connected to the first input end S11.

[0083] A gate electrode of the eighth transistor T8 and a gate electrode of the tenth transistor T10 are connected to the first input end S11, a first electrode of the eighth transistor T8 is connected to the first electrode of the eleventh transistor T11, and a second electrode of the eighth transistor T8 is connected to the second input end S12.

[0084] A first electrode of the ninth transistor T9 is connected to the first input end S11, and a second electrode of the ninth transistor T9 is connected to a first electrode of the twelfth transistor T12.

[0085] The first electrode of the tenth transistor T10 is connected with the second input terminal S12, and the second electrode of the tenth transistor T10 is connected with the first electrode of the twelfth transistor T12;

[0086] The second electrode of the eleventh transistor T11 is connected with the first voltage control terminal SAP, and the gate electrode of the eleventh transistor T11 is connected with the first enable terminal SAP EN;

[0087] The second electrode of the twelfth transistor T12 is connected with the second voltage control terminal SAN, and the gate electrode of the twelfth transistor T12 is connected with the second enable terminal SAN EN.

[0088] In some embodiments, the seventh transistor T7, the eighth transistor T8 and the eleventh transistor T11 can be P-type transistors, and the ninth transistor T9, the tenth transistor T10 and the twelfth transistor T12 can be N-type transistors.

[0089] In some embodiments, the first voltage control terminal SAP can be, for example, VDD, and the second voltage control terminal SAN can be, for example, the ground terminal GND.

[0090] Fig. 5 is an equivalent circuit schematic diagram of the first sense amplifier 41 provided by another exemplary embodiment. As shown in Fig. 5, in the present embodiment, compared with the circuit shown in Fig. 4, the thirteenth transistor T13 and the fourteenth transistor T14 are added, wherein the gate electrode of the eighth transistor T8 and the gate electrode of the tenth transistor T10 are connected with the first input terminal S11, and are connected with the first electrode of the thirteenth transistor T13, the second electrode of the thirteenth transistor T13 is connected with the second electrode of the seventh transistor T7 and the first electrode of the ninth transistor T9; the gate electrode of the seventh transistor T7 and the gate electrode of the ninth transistor T9 are connected with the second input terminal S12, and are connected with the first electrode of the fourteenth transistor T14, the second electrode of the fourteenth transistor T14 is connected with the second electrode of the eighth transistor T8 and the first electrode of the tenth transistor T10, and the gate electrode of the thirteenth transistor T13 and the gate electrode of the fourteenth transistor T14 are connected with the sense control line ISO SA .

[0091] In some embodiments, the thirteenth transistor T13 and the fourteenth transistor T14 can be P-type transistors or N-type transistors.

[0092] Only part of the circuit of the first sense amplifier 41 is shown in Figs. 4 and 5. The first sense amplifier 41 can further include a pre-charging circuit for pre-charging the first input terminal S11 and the second input terminal S12 to a preset voltage before the signal sensing stage.

[0093] The second sense amplifier 42 circuit is similar to the first sense amplifier 41 circuit, and will not be described again.

[0094] The sense amplifier circuits shown in FIG. 4 and FIG. 5 are merely examples, and embodiments of the present disclosure are not limited thereto. Any circuit that can implement sensing can be applied in embodiments of the present disclosure.

[0095] Embodiments of the present disclosure provide a memory including a memory including a sensing circuit and a memory cell connected to the sensing circuit.

[0096] FIG. 6 is a schematic diagram of a memory according to some embodiments. As shown in FIG. 6, in the present embodiment, the memory includes a plurality of memory arrays, the plurality of memory arrays are distributed along a second direction on a substrate, the memory array includes a plurality of memory cell arrays stacked along a direction perpendicular to the substrate, each layer of the memory cell array includes a plurality of memory cells arrayed along a first direction and a second direction, a plurality of local bit lines LBL extending along the second direction, a first reference bit line BLR1 extending along the second direction, and a second reference bit line BLR0 extending along the second direction, the local bit lines LBL, the first reference bit line BLR1, and the second reference bit line BLR0 of the same layer are connected to the same common bit line CBL, the first reference bit line BLR1 is connected to the common bit line CBL through a first gating sub-circuit 21, the second reference bit line BLR0 is connected to the common bit line CBL through a second gating sub-circuit 22, and the local bit line LBL is connected to the common bit line CBL through a gating sub-circuit 20. The adjacent memory arrays of the nth memory array are the (n-1)th memory array and the (n+1)th memory array, respectively, each common bit line CBL corresponds to one first sense amplifier 41 and one second sense amplifier 42, the common bit line CBL of the kth layer of the nth memory array is connected to the second input end S12 of the corresponding first sense amplifier 41 and the fourth input end S22 of the corresponding second sense amplifier 42, and the common bit line CBL of the kth layer of the (n-1)th memory array is connected to the first input end S11 of the corresponding first sense amplifier 41, the common bit line CBL of the kth layer of the (n+1)th memory array is connected to the third input end S13 of the corresponding second sense amplifier 42, n is greater than 1, k is 1 to K, and K is the number of layers of the memory cell array included in the memory array. That is, the signals of the common bit lines CBL of the adjacent memory arrays are the reference signals of the first sense amplifier 41 and the reference signals of the second sense amplifier 42, respectively.

[0097] For example, when the storage unit to be accessed is located at the kth layer of the nth storage array, the first gating sub-circuit 21 connected to the first reference bit line BLR1 of the kth layer of the (n-1)th storage array is controlled to be turned on to electrically connect the first reference bit line BLR1 of the kth layer of the (n-1)th storage array and the common bit line CBL, and the second gating sub-circuit 22 connected to the second reference bit line BLR0 of the kth layer of the (n+1)th storage array is controlled to be turned on to electrically connect the second reference bit line BLR0 of the kth layer of the (n+1)th storage array and the common bit line CBL; or, the second gating sub-circuit 22 connected to the second reference bit line BLR0 of the kth layer of the (n-1)th storage array is controlled to be turned on to electrically connect the second reference bit line BLR0 of the kth layer of the (n-1)th storage array and the common bit line CBL, and the first gating sub-circuit 21 connected to the first reference bit line BLR1 of the kth layer of the (n+1)th storage array is controlled to be turned on to electrically connect the first reference bit line BLR1 of the kth layer of the (n+1)th storage array and the common bit line CBL.

[0098] In some embodiments, when the storage unit of the kth layer of the nth storage array is accessed, the gating sub-circuit 20 connected to the storage unit to be accessed is turned on, so that the local bit line LBL connected to the storage unit to be accessed is connected to the common bit line CBL_(n). The first gating sub-circuit 21 connected to the common bit line CBL_(n-1) of the kth layer of the (n-1)th storage array can be turned on, and the second gating sub-circuit 22 connected to the common bit line CBL_(n+1) of the kth layer of the (n+1)th storage array can be turned on.

[0099] Alternatively, the second gating sub-circuit 22 connected to the common bit line CBL_(n-1) of the kth layer of the (n-1)th storage array can be turned on, and the first gating sub-circuit 21 connected to the common bit line CBL_(n+1) of the kth layer of the (n+1)th storage array can be turned on. As shown in FIG. 6, the second reference bit line BLR0 of the (n-1)th storage array is electrically connected to CBL_(n-1), and the first reference bit line BLR1 of the (n+1)th storage array is electrically connected to CBL_(n+1). That is, one of the two adjacent storage arrays selects the first reference storage unit storing logical data "1", and the other selects the second reference storage unit storing logical data "0".

[0100] The embodiment of the present disclosure provides a memory access control method, which can include:

[0101] In a signal sensing phase of the memory cell, the first gating sub-circuit is controlled to be turned on to electrically connect the first reference bit line and the first input terminal of the first sense amplifier, and the second gating sub-circuit is controlled to be turned on to electrically connect the second reference bit line and the third input terminal of the second sense amplifier.

[0102] In some embodiments, the method further comprises: in a phase other than the signal sensing phase of the memory cell, controlling the first gating sub-circuit to be turned off to disconnect the first reference bit line and the first input terminal of the first sense amplifier, and controlling the second gating sub-circuit to be turned off to disconnect the second reference bit line and the third input terminal of the second sense amplifier, loading a voltage corresponding to logic data "1" to the first reference bit line, and loading a voltage corresponding to logic data "0" to the second reference bit line.

[0103] The embodiments of the present disclosure further provide an electronic device comprising the memory as described in the foregoing embodiments. The electronic device can be a storage device, a smart phone, a computer, a tablet computer, an artificial intelligence device, a wearable device, a mobile power supply, or the like. The storage device can comprise a memory in a computer, and the like, which is not limited herein.

[0104] In some embodiments, the electronic device can further comprise a control circuit configured to perform the access control method as described in any of the foregoing embodiments on the memory. The control circuit can comprise a circuit capable of generating a control signal and a control line to control the switching sub-circuit, thereby achieving access control of the memory. The control circuit together with the SA and the like achieves access control of the memory.

[0105] Although the embodiments of the present disclosure are as described above, the content described is only used to facilitate understanding of the present disclosure, and is not intended to limit the present disclosure. Any person skilled in the art of the present disclosure can make any modification and change in the implementation form and details without departing from the spirit and scope of the present disclosure. The patent protection scope of the present disclosure shall be subject to the scope defined by the appended claims.

Claims

1. A sensing circuit, comprising: The first sensing amplifier comprises a first input end and a second input end, and the second sensing amplifier comprises a third input end and a fourth input end; The first reference storage unit is connected to a first reference bit line, the first reference bit line is connected to the first input end of the first sensing amplifier through the first gating sub-circuit, the second reference storage unit is connected to a second reference bit line, the second reference bit line is connected to the third input end of the second sensing amplifier through the second gating sub-circuit, and the second input end of the first sensing amplifier and the fourth input end of the second sensing amplifier are connected to the storage unit to be accessed; the first gating sub-circuit is connected to a first gating control line, the second gating sub-circuit is connected to a second gating control line, the first reference storage unit stores logical data "1", and the second reference storage unit stores logical data "0"; The first gating sub-circuit is configured to electrically connect or disconnect the first reference bit line and the first input end of the first sensing amplifier under the control of the first gating control line, and electrically connect the first reference bit line and the first input end of the first sensing amplifier in the signal sensing stage of the storage unit to be accessed. The second gating sub-circuit is configured to electrically connect or disconnect the second reference bit line and the third input end of the second sensing amplifier under the control of the second gating control line, and electrically connect the second reference bit line and the third input end of the second sensing amplifier in the signal sensing stage of the storage unit to be accessed.

2. The sensing circuit of claim 1, wherein, The first gating control line and the second gating control line are the same gating control line.

3. The sensing circuit of claim 1, wherein, The sensing circuit further comprises a first data writing sub-circuit and a second data writing sub-circuit, wherein: The first data writing sub-circuit is configured to load a voltage corresponding to logical data "1" to the first reference bit line in a data writing stage; The second data writing sub-circuit is configured to load a voltage corresponding to logical data "0" to the second reference bit line in the data writing stage; and the data writing stage is a period of time outside the signal sensing stage of the storage unit to be accessed.

4. The sensing circuit of claim 3, wherein, The first data writing sub-circuit and the second data writing sub-circuit are connected to the same writing control line, and the writing control line is configured to control the first data writing sub-circuit to load a voltage corresponding to logical data "1" to the first reference bit line and the second data writing sub-circuit to load a voltage corresponding to logical data "0" to the second reference bit line at the same time.

5. The sensing circuit of claim 3, wherein, The bit line connected to the storage unit to be accessed is connected to the second input end of the first sensing amplifier through a third gating sub-circuit and connected to the fourth input end of the second sensing amplifier through a fourth gating sub-circuit; the third gating sub-circuit is connected to a third gating control line, and the fourth gating sub-circuit is connected to a fourth gating control line, wherein, The third gating sub-circuit is configured to electrically connect the bit line and the second input terminal of the first sense amplifier under the control of the third gating control line. The fourth gating sub-circuit is configured to electrically connect the bit line and the second input terminal of the first sense amplifier under the control of the fourth gating control line.

6. The sensing circuit of claim 5, wherein, The second input terminal of the first sense amplifier is connected to the bit line connected to the plurality of to-be-accessed storage units, the fourth input terminal of the second sense amplifier is connected to the bit line connected to the plurality of to-be-accessed storage units, and each bit line is connected to the second input terminal of the first sense amplifier through a third gating sub-circuit and is connected to the fourth input terminal of the second sense amplifier through a fourth gating sub-circuit.

7. The sensing circuit of claim 6, wherein, The first reference storage unit and at least one of the plurality of to-be-accessed storage units connected to the second input terminal of the first sense amplifier or the fourth input terminal of the second sense amplifier belong to the same storage array, and the second reference storage unit and at least one of the plurality of to-be-accessed storage units connected to the second input terminal of the first sense amplifier or the fourth input terminal of the second sense amplifier belong to the same storage array.

8. The sensing circuit of claim 7, wherein, The first reference storage unit and the second reference storage unit belong to the same storage array or different storage arrays.

9. The sensing circuit of claim 6, wherein, The first reference storage unit and the second reference storage unit are independent of the storage array in which the to-be-accessed storage unit is located.

10. The sensing circuit of claim 9, wherein, The first reference storage unit includes a first capacitor, the second reference storage unit includes a second capacitor, the to-be-accessed storage unit includes a capacitor, the capacitance value of the first capacitor is smaller than the capacitance value of the capacitor of the to-be-accessed storage unit, the capacitance value of the second capacitor is smaller than the capacitance value of the capacitor of the to-be-accessed storage unit, the capacitance value of the first reference bit line is smaller than the capacitance value of the bit line connected to the to-be-accessed storage unit, and the capacitance value of the second reference bit line is smaller than the capacitance value of the bit line connected to the to-be-accessed storage unit.

11. A memory comprising at least one sensing circuit as claimed in any one of claims 1 to 10 and a storage unit connected to the sensing circuit.

12. The memory of claim 11, wherein, The memory includes a plurality of memory arrays distributed along a second direction on a substrate, the memory arrays include a plurality of memory cell arrays stacked along a direction perpendicular to the substrate, each of the memory cell arrays includes a plurality of memory cells arrayed along a first direction and a second direction, a plurality of local bit lines extending along the second direction, a first reference bit line extending along the second direction, and a second reference bit line extending along the second direction, the local bit lines, the first reference bit line, and the second reference bit line of the same layer are connected to a same common bit line, the first reference bit line is connected to the common bit line through a first gating sub-circuit, the second reference bit line is connected to the common bit line through a second gating sub-circuit, adjacent memory arrays of an nth memory array are distributed as an (n-1)th memory array and an (n+1)th memory array, each of the common bit lines corresponds to a first sense amplifier and a second sense amplifier, a common bit line of a kth layer of the nth memory array is connected to a second input terminal of the corresponding first sense amplifier and a fourth input terminal of the corresponding second sense amplifier, a common bit line of the kth layer of the (n-1)th memory array is connected to a first input terminal of the corresponding first sense amplifier, and a common bit line of the kth layer of the (n+1)th memory array is connected to a third input terminal of the corresponding second sense amplifier, n is greater than 1, k is 1 to K, and K is a number of layers of the memory cell arrays included in the memory arrays.

13. A method for controlling access to a memory as claimed in any one of claims 11 or 12, comprising: in a signal sensing phase of the memory cell, controlling the first gating sub-circuit to be turned on to electrically connect the first reference bit line and the first input terminal of the first sense amplifier, and controlling the second gating sub-circuit to be turned on to electrically connect the second reference bit line and the third input terminal of the second sense amplifier.

14. The access control method of memory according to claim 13, wherein, The sensing circuit is as claimed in any one of claims 3 to 10, and the method further comprises: in a phase other than the signal sensing phase of the memory cell, controlling the first gating sub-circuit to be turned off to disconnect the first reference bit line and the first input terminal of the first sense amplifier, and controlling the second gating sub-circuit to be turned off to disconnect the second reference bit line and the third input terminal of the second sense amplifier, loading a voltage corresponding to logical data "1" to the first reference bit line, and loading a voltage corresponding to logical data "0" to the second reference bit line.

15. The access control method of memory according to claim 13, wherein, The memory as claimed in claim 12, the method further comprising: when the memory cell to be accessed is located at the kth layer of the nth memory array, controlling the first gating sub-circuit connected with the first reference bit line of the kth layer of the nth-1 memory array to be turned on to electrically connect the first reference bit line of the kth layer of the nth-1 memory array and the common bit line, and controlling the second gating sub-circuit connected with the second reference bit line of the kth layer of the nth+1 memory array to be turned on to electrically connect the second reference bit line of the kth layer of the nth+1 memory array and the common bit line; or, controlling the second gating sub-circuit connected with the second reference bit line of the kth layer of the nth-1 memory array to be turned on to electrically connect the second reference bit line of the kth layer of the nth-1 memory array and the common bit line, and controlling the first gating sub-circuit connected with the first reference bit line of the kth layer of the nth+1 memory array to be turned on to electrically connect the first reference bit line of the kth layer of the nth+1 memory array and the common bit line.

16. An electronic device comprising the memory as claimed in claim 11 or 12.

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