High-density fan-out packaging structure and manufacturing method therefor

Abstract

Disclosed is a high-density fan-out packaging structure, comprising: a chip; a first interconnect layer, disposed on a surface of the chip and comprising a redistributed circuit; an integrated device, disposed on the first interconnect layer; a metal pillar, a first end of which is connected to the first interconnect layer; a plastic packaging layer, covering the metal pillar and the integrated device, but exposing a second end surface of the metal pillar and a back portion of the integrated device; a second interconnect layer, disposed on a second surface of the plastic packaging layer and comprising a redistribution circuit, the redistribution circuit being electrically connected to a second end of the metal pillar and the integrated device; and an external solder ball, disposed at an external pad with the second interconnect layer. An ASIC, a DDR chip, and an IPD integrated passive device are integrated in the interior of the package. The package has a smaller area, is lower in cost, and has a shortened process cycle, and can be used in fields such as servers, data centers, and high-performance computing.

Description

A high-density fan-out packaging structure and its manufacturing method Technical Field

[0001] This invention relates to the field of semiconductor technology, and specifically to a high-density fan-out packaging structure and its manufacturing method. Background Technology

[0002] High-performance computing (HPC) is crucial for applications such as big data analytics, artificial intelligence, and cloud computing. Products like autonomous vehicles, edge computing servers, and data centers require high computing speeds, high memory access bandwidth and capacity, and high input / output (I / O) bandwidth. Due to its advantages in electrical performance, warp control, yield, and reliability, 2.5D silicon interposer technology has been successfully applied to heterogeneous integration and chip integration. As advanced packaging technologies achieve increasingly dense I / O per unit area, package sizes (e.g., 2.5D packages) are becoming larger. The largest silicon interposer area in current 2.5D packages is approximately 2500 mm². 2 The largest existing FCBGA substrate size is approximately 10000 mm. 2 Increasing the area of ​​silicon interposers and FCBGA substrates will present challenges in terms of yield and manufacturing. Summary of the Invention

[0003] To address some or all of the problems in the prior art, a first aspect of the present invention provides a high-density sector-shaped packaging structure, comprising:

[0004] chip;

[0005] A first interconnect layer is disposed on the surface of the chip and includes redistributed circuitry;

[0006] An integrated device, wherein the integrated device is disposed on the first interconnect layer;

[0007] A metal pillar, the first end of which is connected to the first interconnect layer;

[0008] A molding compound that covers the metal pillar and the integrated device, but exposes the second end face of the metal pillar and the back of the integrated device;

[0009] A second interconnect layer, disposed on the second surface of the molding compound, includes a redistribution circuit electrically connected to the second end of the metal pillar and an integrated device; and

[0010] External solder balls are disposed at the external solder pads of the second interconnect layer.

[0011] Furthermore, the chip includes at least one ASIC chip.

[0012] Furthermore, the integrated device includes one or more of the following: DDR stacked chip module, deep trench capacitor DTC, and integrated passive device IPD module.

[0013] Furthermore, the integrated device includes at least one DDR stacked chip module, and the second pad is located at the pad of the DDR chip.

[0014] Furthermore, the integrated device includes at least two deep trench capacitors (DTCs) and corresponding integrated passive device (IPD) modules, with the deep trench capacitors (DTCs) and integrated passive devices (IPDs) stacked vertically.

[0015] Furthermore, the DDR stacked chip module uses TSV (Through Silicon Via) technology to complete the electrical signal connection.

[0016] Furthermore, the first interconnect layer and / or the second interconnect layer include one or more conductive lines and an insulating medium disposed between the conductive lines.

[0017] A second aspect of the present invention provides a method for manufacturing the fan-out packaging structure as described above, comprising:

[0018] A first interconnect layer is formed on the surface of the chip;

[0019] The metal pillars and integrated devices are mounted on the surface of the first interconnect layer;

[0020] The integrated device and the metal pillar are encapsulated with a molding compound to form a molding layer;

[0021] Thin the molding compound to expose the second end face of the metal pillar and the back of the integrated device;

[0022] A second interconnect layer is formed on the surface of the molding layer to complete the electrical connection;

[0023] Balls are placed at the external pads of the second interconnect layer to form external solder balls; and

[0024] Cut into individual packages.

[0025] Furthermore, deep trench capacitors (DTCs) are fabricated on the surface of the wafer through processes such as etching and deposition.

[0026] Furthermore, the integrated passive device (IPD) is formed on the surface of the wafer using a damascus process, thereby realizing the stacked structure of the integrated passive device (IPD) and the deep trench capacitor (DTC).

[0027] This invention provides a high-density fan-out packaging structure and its manufacturing method, integrating various types of chips, such as ASIC chips, DDR chips, and IPD (Integrated Device Devices), into a single unit. The stacked DDR chips are electrically connected via TSVs (Through Silicon Vias); DTCs (Dual Tunneling Cells) are fabricated on the silicon surface using etching and deposition processes; and IPDs are connected via a damascus process. Finally, high-density integration of multiple chips is achieved through fan-out packaging. This fan-out packaging structure effectively improves system integration, reduces package size, lowers cost, and shortens the process cycle, making it applicable to servers, data centers, high-performance computing, and other fields. Attached Figure Description

[0028] To further illustrate the above and other advantages and features of the various embodiments of the present invention, a more specific description of the various embodiments of the present invention will be presented with reference to the accompanying drawings. It is to be understood that these drawings depict only typical embodiments of the invention and are therefore not intended to limit its scope. In the drawings, identical or corresponding parts will be indicated by identical or similar reference numerals for clarity.

[0029] Figure 1 shows a schematic diagram of a high-density fan-out packaging structure according to an embodiment of the present invention;

[0030] Figure 2 illustrates a flowchart of a method for manufacturing a high-density fan-out packaging structure according to an embodiment of the present invention; and

[0031] Figures 3A to 3F illustrate a process diagram of a manufacturing method for a high-density fan-out packaging structure according to an embodiment of the present invention. Detailed Implementation

[0032] In the following description, the invention is described with reference to various embodiments. However, those skilled in the art will recognize that the embodiments may be practiced without one or more specific details or with other alternatives and / or additional methods, materials, or components. In other instances, well-known structures, materials, or operations are not shown or described in detail so as not to obscure the inventive points of the invention. Similarly, for illustrative purposes, specific quantities, materials, and configurations are set forth to provide a comprehensive understanding of embodiments of the invention. However, the invention is not limited to these specific details. Furthermore, it should be understood that the embodiments shown in the drawings are illustrative representations and are not necessarily drawn to scale.

[0033] In this specification, references to "an embodiment" or "this embodiment" mean that a particular feature, structure, or characteristic described in connection with that embodiment is included in at least one embodiment of the invention. The phrase "in one embodiment" appearing throughout this specification does not necessarily refer to the same embodiment in all instances.

[0034] It should be noted that the embodiments of the present invention describe the process steps in a specific order; however, this is only for illustrating the specific embodiment and not for limiting the order of the steps. On the contrary, in different embodiments of the present invention, the order of the steps can be adjusted according to the process.

[0035] To address the limited integration of existing fan-out packaging structures, this invention provides a high-density fan-out packaging structure and its manufacturing method. By internally integrating ASIC, DDR chips, and IPD-integrated passive devices, it achieves high-density integration, resulting in a smaller package area, lower cost, and shorter process cycle. It can be applied to servers, data centers, high-performance computing, and other fields.

[0036] The technical solution of the present invention will be further described below with reference to the accompanying drawings of the embodiments.

[0037] Figure 1 shows a schematic diagram of a high-density fan-out packaging structure according to an embodiment of the present invention. As shown in Figure 1, the high-density fan-out packaging structure includes: a first chip 1, a first interconnect layer 2, a metal pillar 3, a second chip 5, a third chip, a molding compound 7, and a second interconnect layer 8.

[0038] In one embodiment of the present invention, the first chip 1 is an ASIC chip, the second chip 5 is a DDR stacked chip module, and the third chip is a stacked module of an integrated passive device IPD 4 and a deep trench capacitor DTC 6, i.e., the deep trench capacitor DTC and the integrated passive device IPD are stacked vertically. In other embodiments of the present invention, the first chip, the second chip, and the third chip may also be other types of chips or chip modules. The second chip and the third chip may be collectively referred to as an integrated device.

[0039] As shown in Figure 1, the first interconnect layer 2 is disposed on the first chip 1, and in one embodiment of the present invention, it includes at least one ASIC chip. In one embodiment of the present invention, the molding compound 7 can be made of epoxy resin, curing adhesive, EMC, or other materials.

[0040] In one embodiment of the present invention, the metal pillar 3, the IPD integrated passive device 4, the DDR stacked chip module 5, and the DTC deep trench capacitor 6 are mounted on the first interconnect layer 2 via surface mounting. In another embodiment of the present invention, the DDR stacked chip module 5 completes the electrical signal connection through TSV vias.

[0041] In one embodiment of the present invention, the deep trench capacitor DTC 6 is fabricated on a wafer using processes such as etching and deposition, while the integrated passive device IPD 4 is formed on the surface of the wafer using a damascus process. This achieves a stacked structure of the integrated passive device IPD 4 and the deep trench capacitor DTC 6. The outermost layer of the integrated passive device IPD 4 may have pads, allowing it to be mounted on the first interconnect layer 2 using surface mount technology or similar processes.

[0042] One end of the metal pillar 3 is connected to the first interconnect layer 2, and the other end is connected to the second interconnect layer 8, thus realizing an electrical signal connection. In one embodiment of the present invention, the material of the metal pillar 3 can be copper, aluminum, tungsten, etc.

[0043] The molding compound 7 covers the metal pillar 3 and integrates the passive device IPD 4, the DDR stacked chip module 5, and the deep trench capacitor DTC 6, but thins out the pads of the metal pillar 3 and the DDR stacked chip module 5 to facilitate subsequent interconnection.

[0044] The second interconnect layer 8 is disposed on the surface of the molding layer 7, completing the electrical signal connection between the devices and enabling the fan-out function. In one embodiment of the present invention, the second interconnect layer 8 includes conductive lines and an insulating medium disposed between the conductive lines. The conductive lines may be made of copper, aluminum, tungsten, etc., and the insulating medium may be, for example, an organic material such as resin or PI, or an inorganic insulating material such as silicon oxide or silicon nitride, to buffer thermal stress and protect the devices. In one embodiment of the present invention, the second interconnect layer 8 includes one or more layers of conductive lines, wherein the outermost layer may also be provided with pads for connection to external chips, chipsets, or circuits.

[0045] Figures 2 and 3A to 3F respectively show a flowchart and a process diagram of a manufacturing method for a high-density fan-out packaging structure according to an embodiment of the present invention. As shown in the figures, a manufacturing method for a high-density fan-out packaging structure as described above includes:

[0046] In step 1, as shown in FIG3A, multiple wirings are performed on the ASIC chip 1 to form a first interconnect layer 2. In one embodiment of the present invention, the first interconnect layer 2 includes conductive lines and an insulating medium disposed between the conductive lines. The material of the conductive lines can be copper, aluminum, tungsten, etc., and the insulating medium can be, for example, an organic material such as resin or PI, or an inorganic insulating material such as silicon oxide or silicon nitride. In one embodiment of the present invention, the first interconnect layer 2 includes one or more layers of conductive lines, wherein the outermost layer may also be provided with pads for connection with external chips, chipsets, or circuits.

[0047] In step 2, as shown in Figure 3B, metal pillars 3 are mounted on the first interconnect layer 2, integrating passive device IPD 4, DDR stacked chip module 5, and deep trench capacitor DTC 6. The DDR stacked chip module 5 achieves electrical signal connection through TSV vias. In one embodiment of the invention, the deep trench capacitor DTC 6 is fabricated on the wafer using etching, deposition, and other processes, while the integrated passive device IPD 4 is formed on the wafer surface using a damascus process. This achieves a stacked structure of integrated passive device IPD 4 and deep trench capacitor DTC 6. The outermost layer of the integrated passive device IPD 4 may have pads, allowing it to be mounted on the first interconnect layer 2 using surface mount technology.

[0048] In step 3, as shown in Figure 3C, a molding process is performed to form a molding layer 7, which is then thinned to expose the second end face of the metal pillar 3 and the pads of the DDR stacked chip module 5, facilitating subsequent connection.

[0049] In step 4, as shown in Figure 3D, multiple wiring layers are fabricated on the molding layer 7 to form the second interconnect layer 8, and the IPD integrated passive device 4, DDR stacked chip module 5 and ASIC chip 1 are electrically connected.

[0050] In one embodiment of the present invention, the formation of the second interconnect layer 8 includes: firstly, covering the surface of the molding compound 7 with a dielectric layer, but exposing the pads of the DDR stacked chip module 5 and the second end face of the metal pillar 3, wherein the material of the dielectric layer can be an organic material such as resin or PI, or an inorganic insulating material such as silicon oxide or silicon nitride.

[0051] Then, a metal interconnect layer is formed on the dielectric layer to electrically connect it to the DDR stacked chip module and metal pillars. Specifically, in one embodiment of the present invention, one or more conductive materials are formed on the dielectric layer, and then non-conductive areas are removed by photolithography and etching techniques to form the metal interconnect layer. In another embodiment of the present invention, multiple dielectric layers and metal interconnect layers can be fabricated using similar processes as needed. Specifically, a dielectric layer is further formed on the surface of the previous metal interconnect layer, a portion of the dielectric layer is removed by photolithography and etching techniques to expose at least one external pad of the metal interconnect layer, and then one or more conductive materials are formed on the dielectric layer. Then, non-conductive areas are removed by photolithography and etching techniques to form the next metal interconnect layer. This process is repeated until the outermost metal interconnect layer is formed.

[0052] Finally, a surface passivation layer is deposited on the metal interconnect layer. The formation process of the surface passivation layer is similar to that of the first dielectric layer, that is, an organic material such as resin or PI, or an inorganic insulating material such as silicon oxide or silicon nitride is used to form the surface passivation layer on the metal interconnect layer. Finally, an under-bump metallization (UBM) layer is formed on the surface passivation layer to electrically connect it to the metal interconnect layer. In one embodiment of the present invention, the UBM layer is formed by processes such as thin-film vacuum sputtering and electroplating. Specifically, one or more metal layers are formed on the surface passivation layer by processes such as thin-film vacuum sputtering, then photoresist is spin-coated and exposed to form a template for electroplating solder. After electroplating, the photoresist is removed and the exposed UBM layer is etched away.

[0053] In step 5, as shown in Figures 3E and 2, ball placement and cutting are performed. External solder balls are fabricated on the second interconnect layer 8, for example, on its under-bump metal layer, and then reflowed. In a specific embodiment of the invention, external solder balls can be formed on at least one external pad of the second interconnect layer 8 through processes such as electroplating and ball placement.

[0054] In step 6, as shown in Figure 2, the chips are divided to obtain individual chips, thus completing the packaging process.

[0055] The present invention provides a high-density fan-out packaging structure and its manufacturing method, which effectively improves the system integration and has a simple process, and can be applied to various portable electronic products.

[0056] Although various embodiments of the invention have been described above, it should be understood that they are presented by way of example only and not as limitations. It will be apparent to those skilled in the art that various combinations, modifications, and alterations can be made without departing from the spirit and scope of the invention. Therefore, the breadth and scope of the invention disclosed herein should not be limited by the exemplary embodiments disclosed above, but should be defined solely by the appended claims and their equivalents.

Claims

1. A high-density fan-out packaging structure, characterized in that, include: chip; A first interconnect layer is disposed on the surface of the chip and includes redistribution circuitry; An integrated device, wherein the integrated device is disposed on the first interconnect layer; A metal pillar, the first end of which is connected to the first interconnect layer; A molding compound that covers the metal pillar and the integrated device, but exposes the second end face of the metal pillar and the back of the integrated device; A second interconnect layer, disposed on the second surface of the molding compound, includes a redistribution circuit electrically connected to the second end of the metal pillar and an integrated device; and External solder balls are disposed at the external solder pads of the second interconnect layer.

2. The fan-out packaging structure as described in claim 1, characterized in that, The chip includes at least one ASIC chip.

3. The fan-out packaging structure as described in claim 1, characterized in that, The integrated device includes one or more of the following: DDR stacked chip module, deep trench capacitor DTC, and integrated passive device IPD module.

4. The fan-out packaging structure as described in claim 3, characterized in that, The integrated device includes at least one DDR stacked chip module, and the second pad is located at the pad of the DDR chip.

5. The fan-out packaging structure as described in claim 3, characterized in that, The integrated device includes at least two deep trench capacitors (DTCs) and corresponding integrated passive device (IPD) modules, with the deep trench capacitors (DTCs) and integrated passive devices (IPDs) stacked vertically.

6. The fan-out packaging structure as described in claim 3, characterized in that, The DDR stacked chip module uses TSV (Through Silicon Via) technology to complete the electrical signal connection.

7. The fan-out packaging structure as described in claim 1, characterized in that, The first interconnect layer and / or the second interconnect layer include one or more conductive lines and an insulating medium disposed between the conductive lines.

8. A method for manufacturing a fan-out packaging structure as described in any one of claims 1 to 7, characterized in that, Including the following steps: A first interconnect layer is formed on the surface of the chip; The metal pillars and integrated devices are mounted on the surface of the first interconnect layer; The integrated device and the metal pillar are encapsulated with a molding compound to form a molding layer; Thin the molding compound to expose the second end face of the metal pillar and the back of the integrated device; A second interconnect layer is formed on the surface of the molding layer to complete the electrical connection; Balls are placed at the external pads of the second interconnect layer to form external solder balls; as well as Cut into individual packages.

9. The method for manufacturing the fan-out packaging structure as described in claim 8, characterized in that, Deep trench capacitors (DTCs) are fabricated on the surface of a wafer through processes such as etching and deposition.

10. The method for manufacturing the fan-out packaging structure as described in claim 9, characterized in that, Integrated passive device (IPD) is formed on the surface of the wafer using a damascus process, thereby realizing a stacked structure of IPD and deep trench capacitor (DTC).

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