Power-on sequence control method and apparatus based on heterogeneous multi-core system, and vehicle

Abstract

The present invention relates to the technical field of vehicles, and in particular to a power-on sequence control method and apparatus based on a heterogeneous multi-core system, and a vehicle. The method comprises: when a heterogeneous multi-core system meets a preset power-on condition, enabling a first power supply management chip to control a corresponding first MCU and first SOC to be powered on, and enabling a second power supply management chip to control a corresponding second MCU and second SOC to be powered on; and when the first MCU, the first SOC, the second MCU, and the second SOC are powered on, respectively initializing the first MCU, the first SOC, the second MCU, and the second SOC and controlling, on the basis of the initialized first MCU, a third SOC to be powered on, and when the third SOC is initialized, respectively supplying power to corresponding camera modules on the basis of the initialized first SOC, second SOC and third SOC. In this way, the problems of the impact on starting time requirements of application functions and lowered user experience due to overlong system power-on / power-off time caused by the complexity of heterogeneous multi-core systems are solved.

Description

Power-on timing control method and device based on multi-core heterogeneous system and vehicle

[0001] Cross-reference to Related Applications

[0002] The present application is based on the Chinese patent application No. 202411034843.3, filed on July 31, 2024, and claims the priority of the Chinese patent application, the whole content of which is incorporated herein by reference. TECHNICAL FIELD

[0003] The present application relates to the technical field of vehicles, in particular to a power-on timing control method and device based on a multi-core heterogeneous system and a vehicle. BACKGROUND

[0004] With the rapid development of advanced automatic driving, the automatic driving computing power required by vehicles is becoming higher and higher. In order to develop an automatic driving domain controller capable of solving the current demand for perception, decision planning computing power and functional safety backup demand by constructing a multi-core heterogeneous chip, it is necessary to improve the power-on and power-off control technology of the large computing power platform.

[0005] However, due to the complexity of the multi-core heterogeneous system architecture, the system power-on and power-off time is too long, which affects the start time requirement of the upper-level application function and the user experience, and needs to be solved urgently. SUMMARY

[0006] The present application provides a power-on timing control method and device based on a multi-core heterogeneous system and a vehicle to solve the problem of too long system power-on and power-off time caused by the complexity of the multi-core heterogeneous system architecture, which affects the start time requirement of the application function and reduces the user experience.

[0007] The first aspect of the present application provides a power-on timing control method based on a multi-core heterogeneous system, which is applied to a domain controller. The multi-core heterogeneous system includes a plurality of SOC (System on Chip) and a plurality of MCU (Micro Controller Unit). The method mainly includes the following steps:

[0008] determining whether the multi-core heterogeneous system meets a preset power-on condition;

[0009] if the multi-core heterogeneous system meets the preset power-on condition, enabling a first power management chip to control the power-on of a corresponding first MCU and a first SOC, and simultaneously enabling a second power management chip to control the power-on of a corresponding second MCU and a second SOC;

[0010] After the first MCU, the first SOC, the second MCU and the second SOC are powered on, the first MCU, the first SOC, the second MCU and the second SOC are initialized respectively, the third SOC is powered on based on the initialized first MCU, and after the third SOC is initialized, the corresponding camera components are powered based on the initialized first SOC, the initialized second SOC and the initialized third SOC respectively.

[0011] According to an embodiment of the present application, the judging whether the multi-core heterogeneous system meets the preset power-on condition comprises:

[0012] judging whether the current vehicle is in a normal power state;

[0013] if the current vehicle is in the normal power state, judging whether the current vehicle meets a domain controller power-on condition or whether the current vehicle meets a network management wake-up condition;

[0014] if the current vehicle meets the domain controller power-on condition or the current vehicle meets the network management wake-up condition, it is determined that the multi-core heterogeneous chip system meets the preset power-on condition.

[0015] According to an embodiment of the present application, the judging whether the current vehicle meets the domain controller power-on condition or whether the current vehicle meets the network management wake-up condition comprises:

[0016] judging whether a switching power supply of the current vehicle is in an ON mode;

[0017] if the switching power supply of the current vehicle is in the ON mode, it is determined that the current vehicle meets the domain controller power-on condition, otherwise, whether the current vehicle meets the network management wake-up condition is judged, and when the current vehicle meets the network management wake-up condition, a power-on operation is performed on the multi-core heterogeneous system.

[0018] According to an embodiment of the present application, the judging whether the current vehicle meets the network management wake-up condition comprises:

[0019] judging whether the current vehicle receives a preset network wake-up request signal;

[0020] if the preset network wake-up request signal is received, it is determined that the current vehicle meets the network management wake-up condition.

[0021] According to an embodiment of the present application, after the corresponding camera components are powered based on the initialized first SOC, the initialized second SOC and the initialized third SOC respectively, the method further comprises:

[0022] respectively to the initialized first SOC, the initialized second SOC, and the initialized third SOC.

[0023] According to the power-on timing control method based on the multi-core heterogeneous system provided in the embodiments of the present application, when the multi-core heterogeneous system meets the preset power-on condition, the first power management chip is enabled to control the corresponding first MCU and first SOC to be powered on, and the second power management chip is enabled to control the corresponding second MCU and second SOC to be powered on; after the first MCU, the first SOC, the second MCU, and the second SOC are powered on, the first MCU, the first SOC, the second MCU, and the second SOC are initialized respectively, and the third SOC is powered on based on the initialized first MCU; after the third SOC is initialized, the corresponding camera components are powered based on the initialized first SOC, the initialized second SOC, and the initialized third SOC. Thus, the problem that the system power-on and power-off time is too long due to the complexity of the multi-core heterogeneous system architecture, thereby affecting the application function startup time requirement and reducing the user experience, is solved. The power management chip is used to power on the corresponding SOC and MCU, thereby ensuring the maximum power-on efficiency and saving the system power-on and power-off time.

[0024] The second aspect of the present application provides a power-on timing control device based on a multi-core heterogeneous system, which is applied to a domain controller, and includes a plurality of SOCs and a plurality of MCUs, wherein:

[0025] The judgment module is configured to judge whether the multi-core heterogeneous system meets a preset power-on condition.

[0026] The enabling module is configured to enable a first power management chip to control a corresponding first MCU and first SOC to be powered on if the multi-core heterogeneous system meets the preset power-on condition, and simultaneously enable a second power management chip to control a corresponding second MCU and second SOC to be powered on.

[0027] The control module is configured to initialize the first MCU, the first SOC, the second MCU, and the second SOC respectively after the first MCU, the first SOC, the second MCU, and the second SOC are powered on, control a third SOC to be powered on based on the initialized first MCU, and supply power to the corresponding camera components based on the initialized first SOC, the initialized second SOC, and the initialized third SOC after the third SOC is initialized.

[0028] According to an embodiment of the present application, the judgment module comprises:

[0029] The first judgment unit is configured to judge whether the current vehicle is in a normal power state.

[0030] a second judging unit, configured to judge whether the current vehicle meets a domain controller power-on condition or whether the current vehicle meets a network management wake-up condition if the current vehicle is in the normal power-on state;

[0031] a determining unit, configured to determine that the multi-core heterogeneous chip system meets the preset power-on condition if the current vehicle meets the domain controller power-on condition or the current vehicle meets the network management wake-up condition.

[0032] According to an embodiment of the present application, the second judging unit comprises:

[0033] a first judging sub-unit, configured to judge whether a switching power supply of the current vehicle is in an ON mode;

[0034] a second judging sub-unit, configured to determine that the current vehicle meets the domain controller power-on condition if the switching power supply of the current vehicle is in the ON mode, otherwise, judge whether the current vehicle meets the network management wake-up condition, and perform a power-on operation on the multi-core heterogeneous system if the current vehicle meets the network management wake-up condition.

[0035] According to an embodiment of the present application, the second judging sub-unit comprises:

[0036] a first judging sub-unit, configured to judge whether a preset network wake-up request signal is received by the current vehicle;

[0037] a determining sub-unit, configured to determine that the current vehicle meets the network management wake-up condition if the preset network wake-up request signal is received.

[0038] According to an embodiment of the present application, after the initialized first SOC, the initialized second SOC and the initialized third SOC supply power to the corresponding camera components respectively, the control module further comprises:

[0039] an initialization module, configured to initialize the camera component corresponding to the initialized first SOC, the camera component corresponding to the initialized second SOC and the camera component corresponding to the initialized third SOC respectively.

[0040] According to the power-on timing control device based on the multi-core heterogeneous system, when the multi-core heterogeneous system meets the preset power-on condition, the first power management chip is enabled to control the power-on of the corresponding first MCU and first SOC, and the second power management chip is enabled to control the power-on of the corresponding second MCU and second SOC; after the first MCU, the first SOC, the second MCU and the second SOC are powered on, the first MCU, the first SOC, the second MCU and the second SOC are initialized respectively, and the third SOC is powered on based on the initialized first MCU, and the corresponding camera components are powered based on the initialized first SOC, the second SOC and the third SOC after the third SOC is initialized. Therefore, the problem that the system power-on and power-off time is too long due to the complexity of the multi-core heterogeneous system architecture, thereby affecting the application function startup time requirement and reducing the user experience, etc. is solved, and the power management chip is used to power on the corresponding SOC and MCU, thereby ensuring the maximum power-on efficiency and saving the system power-on and power-off time.

[0041] The third aspect of the present application provides a vehicle, comprising a memory, a processor and a computer program stored in the memory and executable on the processor, and the processor executes the program to realize the power-on timing control method based on the multi-core heterogeneous system as described in the above embodiments.

[0042] The fourth aspect of the present application provides a computer readable storage medium, which stores computer instructions for making the computer execute the power-on timing control method based on the multi-core heterogeneous system as described in the above embodiments.

[0043] The fifth aspect of the present application provides a computer program product, comprising a computer program executed to realize the power-on timing control method based on the multi-core heterogeneous system as described in the above embodiments.

[0044] Additional aspects and advantages of the present application will be in part apparent and in part pointed out hereinafter. BRIEF DESCRIPTION OF DRAWINGS

[0045] The above and / or additional aspects and advantages of the present application will become apparent and be readily appreciated from the following description, including the appended drawings.

[0046] Fig. 1 is a schematic diagram of a multi-core heterogeneous chip architecture according to an embodiment of the present application;

[0047] Fig. 2 is a block diagram of a multi-core heterogeneous chip system architecture according to an embodiment of the present application;

[0048] Fig. 3 is a flowchart of a power-on timing control method based on a multi-core heterogeneous system according to an embodiment of the present application;

[0049] Fig. 4 is a power-on diagram based on KL15 conditions of a multi-core heterogeneous system according to an embodiment of the present application;

[0050] Fig. 5 is a power-on diagram based on network management wake-up conditions of a multi-core heterogeneous system according to an embodiment of the present application;

[0051] Fig. 6 is a system power-on timing diagram according to an embodiment of the present application;

[0052] Fig. 7 is a block diagram of a power-on timing control device based on a multi-core heterogeneous system according to an embodiment of the present application;

[0053] Fig. 8 is a structural diagram of a vehicle according to an embodiment of the present application.

[0054] 20 - a power-on timing control device based on a multi-core heterogeneous system; 100 - a judging module; 200 - an enabling module; 300 - a control module; 801 - a memory; 802 - a processor; 803 - a communication interface. Embodiments of the present application

[0055] Embodiments of the present application are described in detail below with reference to the accompanying drawings, in which like or similar elements or elements having the same or similar functions are denoted by the same reference numerals throughout the drawings. The embodiments described below by reference to the drawings are exemplary and are intended to explain the present application, and cannot be understood as limiting the present application.

[0056] A power-on timing control method, device, vehicle and storage medium based on a multi-core heterogeneous system according to an embodiment of the present application are described below with reference to the accompanying drawings. In view of the problem that the system power-on and power-off time is too long due to the complexity of the multi-core heterogeneous system architecture, thereby affecting the application function startup time requirement and reducing user experience, the present application provides a power-on timing control method based on a multi-core heterogeneous system, in which when the multi-core heterogeneous system meets a preset power-on condition, a first power management chip is enabled to control a corresponding first MCU and a first SOC to power on, and a second power management chip is enabled to control a corresponding second MCU and a second SOC to power on; after the first MCU, the first SOC, the second MCU and the second SOC are powered on, they are initialized respectively, and the third SOC is powered on based on the initialized first MCU, and the corresponding camera components are powered based on the initialized first SOC, the second SOC and the third SOC after the third SOC is initialized. Thus, the problem that the system power-on and power-off time is too long due to the complexity of the multi-core heterogeneous system architecture, thereby affecting the application function startup time requirement and reducing user experience, etc. is solved, and the SOC and MCU are powered by the power management chip respectively, thereby ensuring the maximum power-on efficiency and saving the system power-on and power-off time.

[0057] Specifically, before introducing the embodiments of the present application, first of all, relevant introduction is made based on a multi-core heterogeneous system, which refers to a system that integrates multiple processor cores with different functions and different performances at the same time. These cores can include general-purpose processors, special-purpose accelerators, graphics processors, etc. Through the above-mentioned processors, the multi-core heterogeneous system can process different types of tasks at the same time, thereby improving the overall performance of the multi-core heterogeneous system. In actual application, the multi-core heterogeneous system is widely used in the domain controller of automatic driving. The domain controller is the core component of the automatic driving system, responsible for receiving sensor data, running automatic driving algorithms and outputting control instructions. At the same time, it can provide powerful computing power and flexible application support for the multi-core heterogeneous system to ensure the safety and reliability of the end-to-end automatic driving technology.

[0058] Further, as shown in FIGS. 1 and 2, the multi-core heterogeneous system of the present application is composed of multiple SOCs (such as SOC-1, SOC-2 and SOC-3) and multiple MCUs (such as MCU-1 and MCU-2), wherein SOC-1, SOC-2 and MCU-1 form a corresponding driving group, and SOC-1 and SOC-2 are respectively connected to corresponding camera components (such as front-view camera, surround-view camera, side-view camera, rear-view camera, etc.), SOC-3 and MCU-2 form a corresponding parking group, and SOC-3 is connected to corresponding camera components (such as front-view camera, surround-view camera, side-view camera, rear-view camera, etc.). In this way, through the design of multiple SOCs and multiple MCUs, the safety requirements of automatic driving functions are met, and the power-on time based on the multi-core heterogeneous system is saved.

[0059] It should be noted that when the power supply group is designed to be controlled respectively in the embodiments of the present application, it is not limited to being divided into driving groups or parking groups. It can be grouped according to the design architecture of the multi-core heterogeneous system. The design principle of power-on control is the same. The embodiments of the present application take the SOC of the driving group as an example. If the SOC of the parking group or other power supply group has other SOC power-on problems mentioned in the present application during the design process, the method proposed in the present application can be applied. The specific embodiments will be described in detail below.

[0060] Specifically, FIG. 3 is a flowchart of a power-on timing control method based on a multi-core heterogeneous system according to an embodiment of the present application.

[0061] As shown in FIG. 3, the power-on timing control method based on a multi-core heterogeneous system is applied in a domain controller, and the multi-core heterogeneous system includes multiple SOCs and multiple MCUs. The method mainly includes the following steps:

[0062] In step S301, it is judged whether the multi-core heterogeneous system meets the preset power-on condition.

[0063] According to one embodiment of the present application, the method for determining whether the preset power-on condition of the multi-core heterogeneous system is met comprises: determining whether the current vehicle is in a normal power state; if the current vehicle is in the normal power state, determining whether the current vehicle meets the domain controller power-on condition or whether the current vehicle meets the network management wake-up condition; and if the current vehicle meets the domain controller power-on condition or the current vehicle meets the network management wake-up condition, determining that the multi-core heterogeneous chip system meets the preset power-on condition.

[0064] According to one embodiment of the present application, the method for determining whether the current vehicle meets the domain controller power-on condition or whether the current vehicle meets the network management wake-up condition comprises: determining whether the switching power supply of the current vehicle is in an ON mode; if the switching power supply of the current vehicle is in the ON mode, determining that the current vehicle meets the domain controller power-on condition; otherwise, determining whether the current vehicle meets the network management wake-up condition, and performing a power-on operation on the multi-core heterogeneous system when the current vehicle meets the network management wake-up condition.

[0065] The preset power-on condition can be set by a person skilled in the art according to actual power-on requirements, and is not specifically limited herein.

[0066] Specifically, in order to save the power-on time of the multi-core heterogeneous system, provide strong computing power and flexible application support for the domain controller, and ensure the safety and reliability of the end-to-end autonomous driving technology, the embodiment of the present application is based on multiple SOCs and multiple MCUs integrated in the multi-core heterogeneous system, and the power management chip PMIC (Power Management Integrated Circuits) is used to supply power to the multiple SOCs and the multiple MCUs to realize the power-on process of the multiple SOCs and the multiple MCUs, thereby ensuring the maximum control power-on efficiency.

[0067] Specifically, the embodiment of the present application first needs to determine the preset power-on condition of the multi-core heterogeneous system. As shown in FIGS. 4 and 5, the preset power-on condition of the embodiment of the present application can mainly include two cases. For example, in the first case, the current vehicle is in a normal power state, and the switching power supply of the current vehicle is in an ON mode, and at this time, it can be determined that the current vehicle meets the domain controller power-on condition. In the second case, the current vehicle is in a normal power state, and the switching power supply of the current vehicle is not in the ON mode, that is, in the OFF mode, and at this time, the current vehicle meets the network management wake-up condition.

[0068] It should be noted that the two power-on conditions of the present application only need to meet one of them, that is, when either of the two power-on conditions is met, the domain controller meets the preset power-on condition, that is, the multi-core heterogeneous system meets the preset power-on condition.

[0069] For example, when the current vehicle is in the normal power state, such as KL30, and the switch power KL15 is in the ON mode from 0 to 1, the multi-core heterogeneous system meets the preset power-on condition. Secondly, as shown in FIG. 5, when the current vehicle is in the normal power state, such as KL30, and the switch power KL15 is in the OFF mode, and the current vehicle meets the network management wake-up condition, it is determined that the multi-core heterogeneous system meets the preset power-on condition.

[0070] According to an embodiment of the present application, the method for determining whether the current vehicle meets the network management wake-up condition comprises: determining whether the current vehicle receives a preset network wake-up request signal; and if the preset network wake-up request signal is received, determining that the current vehicle meets the network management wake-up condition.

[0071] The preset network wake-up request signal can be set by those skilled in the art according to actual power-on requirements, and is not specifically limited herein.

[0072] Specifically, in the embodiment of the present application, if the current vehicle receives a preset network wake-up request signal (such as a CAN (Controller Area Network) network), it is determined that the current vehicle meets the network management wake-up condition. The network wake-up request signal in the embodiment of the present application can include a network management message signal or a specific diagnostic message signal, and the wake-up of the network node is triggered by other nodes through the CAN network signal, so that the current vehicle realizes network management wake-up.

[0073] In step S302, if the multi-core heterogeneous system meets the preset power-on condition, the first power management chip is enabled to control the power-on of the corresponding first MCU and first SOC, and the second power management chip is enabled to control the power-on of the corresponding second MCU and second SOC.

[0074] Specifically, as shown in FIG. 4 and FIG. 5, in the embodiment of the present application, the multi-core heterogeneous system is controlled to power on by the power management chip, in order to ensure the maximum efficiency of the power-on completion of the multi-core heterogeneous system, the power management chip of the embodiment of the present application can be divided into a first power management chip (PMIC_1) and a second power management chip (PMIC_2), based on the two power management chips respectively supplying power to the corresponding SOC and MCU, so that the corresponding SOC and MCU complete the power-on action, at the same time, considering that in the actual autonomous driving development process, according to the connection state of the heterogeneous topology chip, the selected SOC-1 and SOC-2 are mostly connected by SPI (Serial Peripheral Interface, serial peripheral interface) or PCIE (peripheral component interconnect express, high-speed serial computer expansion bus standard) or GPIO (General Purpose Input Output, general purpose input / output port) or RGMI (Reduced Gigabit Media Independent Interface, Gigabit Media Independent Interface) pin, and when the multi-core heterogeneous system meets the preset power-on condition, the first power management chip is controlled to supply power to the corresponding first MCU (MCU-1) and first SOC (SOC-2), at the same time, the second power management chip is controlled to supply power to the corresponding second MCU (MCU-2) and second SOC (SOC-3), thereby completing the power-on action of the first MCU (MCU-1), the first SOC (SOC-2), the second MCU (MCU-2) and the second SOC (SOC-3), that is, enabling the first power management chip to control the power-on of the corresponding first MCU (MCU-1) and first SOC (SOC-2), at the same time, enabling the second power management chip to control the power-on of the corresponding second MCU (MCU-2) and second SOC (SOC-3).

[0075] Specifically, as shown in FIG. 4, if the multi-core heterogeneous system in the embodiment of the application is in the KL30 state, and the switch power supply KL15 is in the ON mode from 0 (low level) to 1 (high level), the multi-core heterogeneous system meets the preset power-on condition, at this time, after the first power management chip PMIC_1 and the second power management chip PMIC_2 work stably, the first power management chip PMIC_1 and the second power management chip PMIC_2 output stable voltage, thereby enabling the first power management chip PMIC_1 to control the corresponding first MCU (MCU-1) and the first SOC (SOC-2) to power on, and simultaneously enabling the second power management chip PMIC_2 to control the corresponding second MCU (MCU-2) and the second SOC (SOC-3) to power on; similarly, as shown in FIG. 5, if the multi-core heterogeneous system in the embodiment of the application is in the KL30 state, and the switch power supply KL15 is in the OFF mode, the CAN network management wake-up condition is met, the multi-core heterogeneous system meets the preset power-on condition, at this time, the first power management chip PMIC_1 and the second power management chip PMIC_2 are enabled to power on the corresponding SOC and MCU by the above power-on method, wherein the first power management chip PMIC_1 and the second power management chip PMIC_2 correspond to the same SOC and MCU respectively, which will not be described in detail here.

[0076] In step S303, after the first MCU, the first SOC, the second MCU and the second SOC are powered on, the first MCU, the first SOC, the second MCU and the second SOC are initialized respectively, and the third SOC is powered on based on the initialized first MCU, and after the third SOC is initialized, the corresponding camera components are powered based on the initialized first SOC, the initialized second SOC and the initialized third SOC respectively.

[0077] According to an embodiment of the application, after the corresponding camera components of the initialized first SOC, the initialized second SOC and the initialized third SOC are powered respectively, it further includes: initializing the corresponding camera components of the initialized first SOC, the initialized second SOC and the initialized third SOC respectively.

[0078] Specifically, in the embodiment of the application, after the first power management chip PMIC_1 controls the corresponding first MCU (MCU-1) and the first SOC (SOC-2) to power on, and the second power management chip PMIC_2 controls the corresponding second MCU (MCU-2) and the second SOC (SOC-3) to power on, it can be known that the first MCU (MCU-1), the first SOC (SOC-2), the second MCU (MCU-2) and the second SOC (SOC-3) in the embodiment of the application are powered on earliest, which can be represented as T power_MCU and T power_SOC-2 / 3At this time, the first MCU (MCU-1), the first SOC (SOC-2), the second MCU (MCU-2) and the second SOC (SOC-3) are respectively initialized, so as to supply power to the third SOC (SOC-1) according to the initialized first MCU (MCU-1), which can be represented as T power_SOC-1 , to complete the power-on action of the third SOC (SOC-1), at this time, after the power-on of the third SOC (SOC-1) is completed, a weak current is injected to the first SOC (SOC-2) through a pin, and the weak current passes through the first SOC (SOC-2) and generates a residual voltage at the power output pin of the corresponding front-end power supply chip. In order to solve the problem of the generated residual voltage, the first SOC (SOC-2) of the embodiment of the application selects a functional safety ASIL D chip to meet the functional safety requirement, so that the first SOC (SOC-2) enters an abnormal protection state due to the residual voltage at the power-on moment, thereby avoiding outputting the voltage to the first SOC (SOC-2).

[0079] Further, as shown in FIG. 6, after the first MCU (MCU-1), the second MCU (MCU-2), the third SOC (SOC-1), the first SOC (SOC-2) and the second SOC (SOC-3) of the embodiment of the application are powered on, first, the first MCU and the second MCU will complete the initialization first, which can be represented as T MCU , if the initialization time of the third SOC (SOC-1) itself is faster than that of the first SOC (SOC-2) or the second SOC (SOC-3), at this time, the multi-core heterogeneous system will continue to initialize the third SOC (SOC-1), and the initialization is completed when the output of the third SOC (SOC-1) is high, and the initialization completion time point can be represented as T SOC-1 After the initialization of the third SOC (SOC-1) is completed, the POC (Power Over Coax, coaxial cable power supply) power supply is performed on the camera assembly corresponding to the third SOC (SOC-1), and the camera assembly corresponding to the third SOC (SOC-1) is initialized, and the initialization completion time point can be represented as T Camera(SOC-1) , and after the initialization of the camera assembly corresponding to the third SOC (SOC-1) is completed, the internal program of the third SOC (SOC-1) is pulled up, at this time, the camera assembly is normally started.

[0080] Further, if the initialization time of the first SOC (SOC-2) and the second SOC (SOC-3) is flat, the initialization of the first SOC (SOC-2) and the second SOC (SOC-3) will be performed immediately after the initialization of the third SOC (SOC-1) is completed, and the initialization completion time can be represented as T SOC(SOC-2 / 3)and after the first SOC (SOC-2) and the second SOC (SOC-3) are initialized, the corresponding camera components are powered by POC, and the corresponding camera components of the first SOC (SOC-2) and the second SOC (SOC-3) are initialized at this time, and the initialization completion time point can be represented as T camera(SOC-2 / 3) , and the internal program of the first SOC (SOC-2) and the second SOC (SOC-3) is pulled up, at this time, the first MCU (MCU-1), the second MCU (MCU-2), the third SOC (SOC-1), the first SOC (SOC-2) and the second SOC (SOC-3) are all initialized, and after the corresponding internal program is pulled up, it means that the multi-core heterogeneous system initialization is completed, and at the same time, it represents that the power-on of the whole domain controller is completed.

[0081] In order to enable those skilled in the art to further understand the power-on timing control method of the multi-core heterogeneous system based on the embodiments of the present application, the following will be described in detail in conjunction with specific embodiments.

[0082] As shown in FIG. 4 and FIG. 5, if the multi-core heterogeneous system is in the KL30 state, and the switch power supply KL15 is in the ON mode from 0 to 1, or the multi-core heterogeneous system is in the KL30 state, and the switch power supply KL15 is in the OFF mode and meets the CAN network management wake-up condition, at this time, the multi-core heterogeneous system meets the preset power-on condition, at this time, after the first power management chip PMIC_1 and the second power management chip PMIC_2 work stably, the stable voltage is output, so as to enable the first power management chip PMIC_1 to control the corresponding first MCU (MCU-1) and the first SOC (SOC-2) to be powered on, at the same time, enable the second power management chip PMIC_2 to control the corresponding second MCU (MCU-2) and the second SOC (SOC-3) to be powered on, and perform the corresponding chip initialization work, after the first MCU (MCU-1) is initialized, enable the third SOC (SOC-1) to be powered on, and perform the corresponding initialization, after the third SOC (SOC-1) is initialized, immediately supply power to the corresponding camera assembly (for example, a driving camera), at the same time, after the third SOC (SOC-1) corresponding camera assembly is initialized, the internal program of the third SOC (SOC-1) is pulled up, at this time, the third SOC (SOC-1) corresponding camera assembly (for example, a driving camera) is normally started; similarly, after the first SOC (SOC-2) and the second SOC (SOC-3) are initialized, the corresponding camera assemblies are powered, and after the first SOC (SOC-2) and the second SOC (SOC-3) corresponding camera assemblies are initialized, the internal program of the first SOC (SOC-2) and the second SOC (SOC-3) is pulled up, at this time, the first SOC (SOC-2) corresponding camera assembly (for example, a driving camera) is normally started, and the second SOC (SOC-3) corresponding camera assembly (for example, a parking camera) is normally started, thereby completing the power-on action of the entire multi-core heterogeneous system.

[0083] It should be noted that the SOC proposed in the embodiment of the present application is placed after the MCU is powered on for control, which is not limited to one SOC, and a plurality of SOCs can be controlled by the MCU to be powered on at the same time according to the demand of the multi-core heterogeneous system, which is not limited here.

[0084] Therefore, through the above-mentioned power supply process of the multi-core heterogeneous system, it is ensured that in the starting process of the multi-core heterogeneous system, each chip can be powered on and initialized in the designed grouping order and timing, so as to ensure that the multi-core heterogeneous system can realize the shortest power-on time of the current vehicle on the basis of meeting the functional demand.

[0085] In summary, through the above-mentioned embodiment, the present application can realize the following beneficial effects:

[0086] (1) The multi-core heterogeneous system of the application controls the corresponding MCU, SOC of the driving group and the corresponding MCU, SOC of the parking group to start power-on through two power management chips PMIC-1 and PMIC-2, so as to ensure maximum power-on efficiency;

[0087] (2) Each power supply group such as MCU and SOC is controlled by PMIC to be powered on at the first time, so as to ensure maximum control efficiency;

[0088] (3) Each group is controlled by PMIC to be powered on on the basis of the corresponding MCU and SOC control group, and meanwhile, in the actual automatic driving development process, according to the connection state of the heterogeneous topology chip, the SOC and the SOC are mostly connected by any pin in SPI, PCIE, GPIO and RGMI, and after the third SOC (SOC-1) is powered on, a weak current is injected to the first SOC (SOC-2) through the connected pin, the weak current passes through the first SOC (SOC-2) chip, and a residual voltage is generated at the power output pin of the front-stage power supply chip corresponding to the first SOC (SOC-2), which causes power-on failure, therefore, the first SOC (SOC-2) of the application is an ASIL D chip for functional safety, so as to make the first SOC (SOC-2) enter an abnormal protection state when the residual voltage is generated, so as to meet the functional safety requirement, that is, on the basis of the control of the main SOC (such as SOC-2 and SOC-3) and MCU to be powered on at the same time, the application further proposes the power-on control sequence of the system design between individual SOCs (such as SOC-1) according to the chip architecture design, and the SOC which has an influence on the main SOC during power-on is controlled by the MCU subsequently, so as to complete the power-on process of the multi-core heterogeneous system and save the power-on time.

[0089] According to the power-on timing control method based on the multi-core heterogeneous system, when the multi-core heterogeneous system meets the preset power-on condition, the first power management chip is enabled to control the corresponding first MCU and first SOC to be powered on, and the second power management chip is enabled to control the corresponding second MCU and second SOC to be powered on; after the first MCU, first SOC, second MCU and second SOC are powered on, they are initialized respectively, and the third SOC is powered on based on the initialized first MCU, and after the third SOC is initialized, the initialized first SOC, second SOC and third SOC supply power to the corresponding camera assemblies. Therefore, the problem that the system power-on and power-off time is too long due to the complexity of the multi-core heterogeneous system architecture, which further affects the start time requirement of the application function and reduces the user experience, is solved, the corresponding SOC and MCU are powered on by the power management chip, so as to ensure the maximum power-on efficiency and save the system power-on and power-off time.

[0090] Secondly, the power-on timing control device based on a multi-core heterogeneous system according to an embodiment of the present application is described with reference to the accompanying drawings.

[0091] Fig. 7 is a block schematic diagram of the power-on timing control device based on a multi-core heterogeneous system according to an embodiment of the present application.

[0092] As shown in Fig. 7, the power-on timing control device 20 based on a multi-core heterogeneous system is applied to a domain controller, and the multi-core heterogeneous system includes a plurality of SOCs and a plurality of MCUs, and comprises a judging module 100, an enabling module 200 and a control module 300.

[0093] The judging module 100 is configured to judge whether the multi-core heterogeneous system meets a preset power-on condition.

[0094] The enabling module 200 is configured to enable a first power management chip to control a corresponding first MCU and a first SOC to be powered on, and simultaneously enable a second power management chip to control a corresponding second MCU and a second SOC to be powered on, if the multi-core heterogeneous system meets the preset power-on condition.

[0095] The control module 300 is configured to initialize the first MCU, the first SOC, the second MCU and the second SOC respectively after the first MCU, the first SOC, the second MCU and the second SOC are powered on, control a third SOC to be powered on based on the initialized first MCU, and supply power to corresponding camera components based on the initialized first SOC, the initialized second SOC and the initialized third SOC respectively after the third SOC is initialized.

[0096] According to an embodiment of the present application, the judging module 100 comprises:

[0097] The first judging unit is configured to judge whether the current vehicle is in a normal power state.

[0098] The second judging unit is configured to judge whether the current vehicle meets a domain controller power-on condition or whether the current vehicle meets a network management wake-up condition, if the current vehicle is in the normal power state.

[0099] The determining unit is configured to determine that the multi-core heterogeneous chip system meets the preset power-on condition, if the current vehicle meets the domain controller power-on condition or the current vehicle meets the network management wake-up condition.

[0100] According to an embodiment of the present application, the second judging unit comprises:

[0101] The first judging sub-unit is configured to judge whether the switching power supply of the current vehicle is in an ON mode.

[0102] The second judging subunit is configured to determine whether the current vehicle satisfies the network management wake-up condition if the switch power supply of the current vehicle is in the ON mode, and perform a power-on operation on the multi-core heterogeneous system if the current vehicle satisfies the network management wake-up condition.

[0103] According to an embodiment of the present application, the second judging subunit comprises:

[0104] The first judging subunit is configured to determine whether the current vehicle receives a preset network wake-up request signal.

[0105] The determining subunit is configured to determine that the current vehicle satisfies the network management wake-up condition if the preset network wake-up request signal is received.

[0106] According to an embodiment of the present application, after the initialized first SOC, the initialized second SOC and the initialized third SOC supply power to the corresponding camera components respectively, the control module 300 further comprises:

[0107] The initialization module is configured to initialize the camera components corresponding to the initialized first SOC, the camera components corresponding to the initialized second SOC and the camera components corresponding to the initialized third SOC respectively.

[0108] According to the power-on timing control device based on the multi-core heterogeneous system, when the multi-core heterogeneous system satisfies the preset power-on condition, the first power management chip is enabled to control the corresponding first MCU and the first SOC to be powered on, and the second power management chip is enabled to control the corresponding second MCU and the second SOC to be powered on. After the first MCU, the first SOC, the second MCU and the second SOC are powered on, they are initialized respectively, and the third SOC is powered on based on the initialized first MCU. After the third SOC is initialized, the corresponding camera components are powered on based on the initialized first SOC, the second SOC and the third SOC. Thus, the problem that the system power-on and power-off time is too long due to the complexity of the multi-core heterogeneous system architecture, which affects the application function start time requirement and reduces the user experience, is solved. The power management chip is used to power on the corresponding SOC and MCU, so as to ensure the maximum power-on efficiency and save the system power-on and power-off time.

[0109] FIG. 8 is a structural schematic diagram of a vehicle according to an embodiment of the present application. The vehicle can comprise:

[0110] The memory 801, the processor 802 and the computer program stored in the memory 801 and executable on the processor 802.

[0111] The processor 802 implements the power-on timing control method based on the multi-core heterogeneous system provided in the above embodiments when executing the program.

[0112] Further, the vehicle further comprises:

[0113] The communication interface 803 is configured to communicate between the memory 801 and the processor 802.

[0114] The memory 801 is configured to store a computer program executable on the processor 802.

[0115] The memory 801 can include a high-speed RAM memory, and can further include a non-volatile memory, for example, at least one disk memory.

[0116] If the memory 801, the processor 802 and the communication interface 803 are independently implemented, the communication interface 803, the memory 801 and the processor 802 can be connected to each other through a bus and complete the communication between each other. The bus can be an Industry Standard Architecture (ISA) bus, a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus, etc. The bus can be divided into an address bus, a data bus, a control bus, etc. For the convenience of representation, only one thick line is used in FIG. 8, but it does not mean that there is only one bus or only one type of bus.

[0117] Optionally, in a specific implementation, if the memory 801, the processor 802 and the communication interface 803 are integrated on a chip, the memory 801, the processor 802 and the communication interface 803 can complete the communication between each other through an internal interface.

[0118] The processor 802 can be a central processing unit (CPU), or an application specific integrated circuit (ASIC), or one or more integrated circuits configured to implement the embodiments of the present application.

[0119] The embodiment further provides a computer readable storage medium, which stores a computer program, and the program is executed by the processor to implement the power-on timing control method based on the multi-core heterogeneous system as above.

[0120] The embodiment also provides a computer program product comprising a computer program, the computer program being executed to implement the power-on timing control method based on a multi-core heterogeneous system of the above-mentioned embodiment.

[0121] In the description of the specification, the description of the terms "one embodiment", "some embodiments", "an example", "a specific example", or "some examples" and the like means that the specific features, structures, materials or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present application. In the specification, the illustrative description of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any appropriate manner in any one or N embodiments or examples. In addition, the person skilled in the art can combine and combine the different embodiments or examples described in the specification and the features of the different embodiments or examples, without contradiction.

[0122] In addition, the terms "first", "second" are only for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined with "first", "second" can explicitly or implicitly include at least one of the features. In the description of the present application, the meaning of "N" is at least two, for example, two, three, etc., unless otherwise specifically limited.

[0123] Any process or method descriptions in flow charts or otherwise described herein can be understood as representing code modules, segments, or portions of code that include one or more executable instructions for performing a specified logic function or process, and the various embodiments of the present application also include the possibility that the functions described can be implemented using a plurality of separate program components or objects to perform the described functions, and that these components or objects can be written in accordance with the present application and can be implemented with hardware that is specifically constructed to store and perform the executable instructions, or alternatively can be implemented with a general purpose receiver or a general purpose computer that is programmed to be a special purpose computer according to the present application.

[0124] The logic and / or steps represented in the flowcharts and / or described herein, for example, can be considered as a sequence of instructions to implement logical functions, and can be embodied in any computer-readable medium for use by an instruction execution system, apparatus, or device, such as a computer-based system, processor- based system, or other system that can fetch the instructions from the instruction execution system, apparatus, or device and execute the instructions. For purposes of this specification, a "computer-readable medium" can be any apparatus that can contain, store, communicate, propagate, or transport the program for use by or in connection with the instruction execution system, apparatus, or device. The computer-readable medium can be a computer- readable storage medium or a computer-readable signal medium. The computer- readable storage medium can be, for example, but not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any suitable combination of the foregoing. More specific examples (a non-exhaustive list) of the computer-readable storage medium include the following: an electrical connection having one or more wires (electrical connections), a portable computer diskette (a magnetic device), a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or Flash memory), an optical fiber, and a portable compact disc read-only memory (CD-ROM). In addition, the computer-readable medium can even be paper or another suitable medium upon which the program is printed, as the program can be electronically captured, for example, via optical scanning of the paper or other medium, then compiled, interpreted, or otherwise processed in a suitable manner, if necessary, and then stored in a computer memory.

[0125] It should be understood that aspects of the application can be implemented in hardware, software, firmware or combinations thereof. In the above embodiments, the N steps or methods can be implemented in software or firmware stored in a memory and executed by a suitable instruction execution system. As such, if implemented in hardware, and in another embodiment, any of the following technologies, known in the art, or combinations thereof, can be used: discrete logic circuitry having logic gates for implementing logic functions on data signals, application specific integrated circuits having appropriate combinational logic gates, programmable gate arrays (PGA), field programmable gate arrays (FPGA), and the like.

[0126] Those of ordinary skill in the art can understand that all or part of the steps carried out by the above-mentioned embodiment methods can be completed by programs instructing related hardware, and the programs can be stored in a computer-readable storage medium. When the programs are executed, they include one or a combination of the steps of the method embodiments.

[0127] In addition, each function unit in each embodiment of the present application can be integrated in one processing module, or each unit can be physically present separately, or two or more units can be integrated in one module. The integrated module can be realized in the form of hardware or in the form of a software function module. If the integrated module is realized in the form of a software function module and sold or used as an independent product, it can also be stored in a computer readable storage medium.

[0128] The storage medium mentioned above can be a read-only memory, a magnetic disk or an optical disk, etc. Although the embodiments of the present application have been shown and described above, it should be understood that the above embodiments are exemplary and should not be construed as limiting the present application, and those skilled in the art can make changes, modifications, replacements and variations to the above embodiments within the scope of the present application.

Claims

1. A method for power-on timing control based on a multi-core heterogeneous system, characterized in that, The multi-core heterogeneous system is applied to a domain controller, and the multi-core heterogeneous system comprises a plurality of system-on-chip (SOC) and a plurality of micro control unit (MCU), wherein the power-on sequence control method based on the multi-core heterogeneous system mainly comprises the following steps: determining whether the multi-core heterogeneous system meets a preset power-on condition; if the multi-core heterogeneous system meets the preset power-on condition, enabling a first power management chip to control power-on of a corresponding first MCU and a first SOC, and simultaneously enabling a second power management chip to control power-on of a corresponding second MCU and a second SOC; after the first MCU, the first SOC, the second MCU and the second SOC are powered on, initializing the first MCU, the first SOC, the second MCU and the second SOC respectively, and based on the initialized first MCU, controlling power-on of a third SOC, and after the third SOC is initialized, based on the initialized first SOC, the initialized second SOC and the initialized third SOC, supplying power to corresponding camera assemblies respectively.

2. The power-on timing control method based on a multi-core heterogeneous system according to claim 1, characterized in that, The determination of whether the multi-core heterogeneous system meets the preset power-on condition comprises: determining whether the current vehicle is in a normal power state; if the current vehicle is in the normal power state, determining whether the current vehicle meets a domain controller power-on condition or whether the current vehicle meets a network management wake-up condition; if the current vehicle meets the domain controller power-on condition or the current vehicle meets the network management wake-up condition, it is determined that the multi-core heterogeneous chip system meets the preset power-on condition.

3. The power-on timing control method based on a multi-core heterogeneous system according to claim 2, characterized in that, The determination of whether the current vehicle meets the domain controller power-on condition or whether the current vehicle meets the network management wake-up condition comprises: determining whether a switching power supply of the current vehicle is in an ON mode; if the switching power supply of the current vehicle is in the ON mode, it is determined that the current vehicle meets the domain controller power-on condition, otherwise, it is determined whether the current vehicle meets the network management wake-up condition, and when the current vehicle meets the network management wake-up condition, the multi-core heterogeneous system is powered on.

4. The power-on timing control method based on a multi-core heterogeneous system according to claim 3, characterized in that, The determination of whether the current vehicle meets the network management wake-up condition comprises: determining whether the current vehicle receives a preset network wake-up request signal; if the preset network wake-up request signal is received, it is determined that the current vehicle meets the network management wake-up condition.

5. The power-on timing control method based on a multi-core heterogeneous system according to claim 1, wherein, After the corresponding camera assemblies are supplied with power based on the initialized first SOC, the initialized second SOC and the initialized third SOC respectively, the method further comprises: initializing the camera assemblies corresponding to the initialized first SOC, the initialized second SOC and the initialized third SOC respectively.

6. A power-on timing control device based on a multi-core heterogeneous system, characterized in that, The multi-core heterogeneous system is applied to a domain controller, and the multi-core heterogeneous system comprises a plurality of SOC and a plurality of MCU, wherein the method comprises: a determination module configured to determine whether the multi-core heterogeneous system meets a preset power-on condition; The enabling module is configured to enable a first power management chip to control power-on of a corresponding first MCU and a first SOC, and enable a second power management chip to control power-on of a corresponding second MCU and a second SOC, if the multi-core heterogeneous system meets the preset power-on condition. The control module is configured to initialize the first MCU, the first SOC, the second MCU and the second SOC after the first MCU, the first SOC, the second MCU and the second SOC are powered on, control a third SOC to be powered on based on the initialized first MCU, and supply power to corresponding camera assemblies based on the initialized first SOC, the initialized second SOC and the initialized third SOC after the third SOC is initialized.

7. The power-on timing control apparatus based on a multi-core heterogeneous system according to claim 6, wherein, The judging module comprises: The first judging unit is configured to judge whether the current vehicle is in a normal power state. The second judging unit is configured to judge whether the current vehicle meets a domain controller power-on condition or whether the current vehicle meets a network management wake-up condition, if the current vehicle is in the normal power state. The determining unit is configured to determine that the multi-core heterogeneous chip system meets the preset power-on condition, if the current vehicle meets the domain controller power-on condition or the current vehicle meets the network management wake-up condition.

8. A vehicle characterized by comprising: The computer program is stored in the memory and executable on the processor, and the processor executes the program to implement the power-on timing control method based on the multi-core heterogeneous system according to any one of claims 1-5. The program is executed by the processor to implement the power-on timing control method based on the multi-core heterogeneous system according to any one of claims 1-5.

9. A computer readable storage medium having stored thereon a computer program, characterized in that, The computer program is executed to implement the power-on timing control method based on the multi-core heterogeneous system according to any one of claims 1-5.

10. A computer program product comprising a computer program, characterized in that, ​

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