2.5d packaging structure and preparation method therefor

Abstract

Provided in the present invention are a 2.5D packaging structure and a preparation method therefor. In the process of preparing the 2.5D packaging structure, a large-sized base is directly bonded to a redistribution layer to realize the electrical connection between the base and the redistribution layer. Compared with a traditional process of performing packaging first and then performing base surface-mounting, the problem of a high-performance and large-sized chip packaging structure warping can be effectively solved, thereby avoiding the problem of a cold solder joint caused by mismatch in thermal expansion coefficients.

Description

2.5D packaging structure and preparation method thereof TECHNICAL FIELD

[0001] The present application belongs to the technical field of semiconductor manufacturing, and relates to a 2.5D packaging structure and a preparation method thereof. BACKGROUND

[0002] The 2.5D packaging structure is an advanced packaging technology mainly used for the packaging of integrated circuits (IC). This technology combines the advantages of two-dimensional (2D) and three-dimensional (3D) packaging technologies, improving the performance and integration of chips. The 2.5D packaging technology is widely used in high-performance computing, mobile devices, automotive electronics, medical devices, etc., and can meet the needs of these fields for high performance, high integration and low power consumption.

[0003] Based on the increasing integration density of various electronic components such as transistors, diodes, resistors, capacitors, etc., the semiconductor industry has experienced rapid growth. High-performance AI products require higher and higher performance, and chip performance is becoming more and more important. As chip performance improves, advanced 2.5D packaging will have larger and larger packaging sizes. The preparation of existing 2.5D packaging structures usually involves first preparing a 2.5D packaging monomer, and then bonding the 2.5D packaging monomer to the substrate through flip chip (FC) for electrical connection. However, traditional 2.5D packaging will face process challenges when facing ultra-large size packaging structures. For example, the current 2.5D packaging structure with 1 times performance (2xSoC+4xHBM) has a packaging size of about 30x40mm and a substrate size of about 50x60mm. The existing 2.5D packaging technology can complete mass production, but for future needs such as 2.5D packaging structure with 4 times performance (8xSoC+16xHBM), the packaging size is about 60x80mm, and the substrate size is about 120x120mm. Therefore, traditional 2.5D packaging technology faces challenges in ultra-large size packaging, which may result in: 1) substrate warping; 2) mismatch between the thermal expansion coefficient (CTE) of the 2.5D packaging monomer and the substrate, causing false soldering problems.

[0004] Therefore, it is necessary to provide a 2.5D packaging structure and a preparation method thereof. SUMMARY

[0005] In view of the above-mentioned shortcomings of the prior art, the present application aims to provide a 2.5D packaging structure and a preparation method thereof, which can solve the problem that the existing 2.5D packaging structure is difficult to realize large size 2.5D packaging.

[0006] To achieve the above-mentioned objects and other related objects, the present application provides a preparation method of a 2.5D packaging structure, comprising the following steps:

[0007] A first support substrate is provided;

[0008] forming a first redistribution layer on the first support substrate;

[0009] forming a metal column on the first redistribution layer, and a first end of the metal column is electrically connected with the first redistribution layer;

[0010] providing a TSV composite adapter plate, the TSV composite adapter plate comprises a TSV adapter plate, and a second redistribution layer and a third redistribution layer located on opposite sides of the TSV adapter plate and electrically connected with the TSV adapter plate respectively, the TSV composite adapter plate is bonded on the first redistribution layer, and the third redistribution layer is electrically connected with the first redistribution layer;

[0011] forming a first packaging layer on the first redistribution layer, the first packaging layer covers the metal column and the TSV composite adapter plate, and exposes a second end of the metal column and the second redistribution layer;

[0012] forming a fourth redistribution layer on the first packaging layer, and the fourth redistribution layer is electrically connected with the metal column and the second redistribution layer;

[0013] providing a first chip, and bonding the first chip on the fourth redistribution layer, and the first chip is electrically connected with the fourth redistribution layer;

[0014] providing a substrate, and bonding the substrate on the fourth redistribution layer, and the substrate is electrically connected with the fourth redistribution layer;

[0015] forming a second packaging layer on the fourth redistribution layer, the second packaging layer covers the substrate and the first chip, and exposes a surface of the substrate;

[0016] providing a second support substrate, and bonding the second support substrate on the second packaging layer;

[0017] removing the first support substrate, and exposing the first redistribution layer;

[0018] providing a second chip and a virtual chip, and bonding the second chip and the virtual chip on the first redistribution layer, and the second chip is electrically connected with the TSV composite adapter plate through the first redistribution layer;

[0019] forming a third packaging layer on the first redistribution layer, the third packaging layer covers the second chip and the virtual chip, and exposes surfaces of the second chip and the virtual chip;

[0020] removing the second support substrate, and exposing the substrate;

[0021] forming a metal bump on the substrate surface, and the metal bump is electrically connected with the substrate.

[0022] Optionally, the method further comprises the step of forming a heat dissipation member on the third encapsulation layer and in contact with the dummy chip.

[0023] Optionally, the method for preparing the 2.5D packaging structure is a wafer-level preparation method.

[0024] Optionally, the size of the substrate comprises 100-300 mm.

[0025] Optionally, the first chip comprises a passive chip, and the second chip comprises an SoC chip and / or an HBM chip.

[0026] Optionally, the line width / space of the TSV composite adapter board ranges from 0.4 μm / 0.4 μm to 1 μm / 1 μm; the line width / space of the fourth re-distribution layer ranges from 2 μm / 2 μm to 10 μm / 10 μm; and the line width / space of the substrate ranges from 15 μm / 15 μm to 50 μm / 50 μm.

[0027] Optionally, the dummy chip comprises a semiconductor dummy chip or a metal dummy chip.

[0028] The application further provides a 2.5D packaging structure, which comprises:

[0029] a first re-distribution layer, comprising a first surface and an opposite second surface;

[0030] a metal column, located on the second surface of the first re-distribution layer, and having a first end electrically connected with the first re-distribution layer;

[0031] a TSV composite adapter board, comprising a TSV adapter board, a second re-distribution layer and a third re-distribution layer located on opposite surfaces of the TSV adapter board and electrically connected with the TSV adapter board respectively, the TSV composite adapter board being bonded on the first re-distribution layer, and the third re-distribution layer being electrically connected with the first re-distribution layer;

[0032] a first encapsulation layer, located on the second surface of the first re-distribution layer, covering the metal column and the TSV composite adapter board, and exposing a second end of the metal column and the second re-distribution layer;

[0033] a fourth re-wiring layer, the fourth re-wiring layer comprising a first surface and an opposite second surface, the first surface of the fourth re-wiring layer being in contact with the first packaging layer, and the fourth re-wiring layer being electrically connected with the metal column and the second re-wiring layer;

[0034] a first chip, the first chip being bonded on the second surface of the fourth re-wiring layer, and the first chip being electrically connected with the fourth re-wiring layer;

[0035] a substrate, the substrate being bonded on the second surface of the fourth re-wiring layer, and the substrate being electrically connected with the fourth re-wiring layer;

[0036] a second packaging layer, the second packaging layer being on the second surface of the fourth re-wiring layer, covering the substrate and the first chip, and exposing a surface of the substrate;

[0037] a second chip and a virtual chip, the second chip and the virtual chip being both bonded on the first surface of the first re-wiring layer, and the second chip being electrically connected with the TSV complex adapter through the first re-wiring layer;

[0038] a third packaging layer, the third packaging layer being on the first re-wiring layer, covering the second chip and the virtual chip, and exposing surfaces of the second chip and the virtual chip;

[0039] a metal bump, the metal bump being on the surface of the substrate and being electrically connected with the substrate.

[0040] Optionally, the size of the substrate comprises 100-300mm.

[0041] Optionally, further comprising a heat dissipation member being on the third packaging layer and being in contact with the virtual chip.

[0042] As described above, the 2.5D packaging structure and the preparation method thereof, in the process of preparing the 2.5D packaging structure, a large-size substrate is directly bonded on the re-wiring layer to realize the electrical connection between the substrate and the re-wiring layer, compared with the traditional process of packaging first and then mounting the substrate, the warping problem of the high-performance and large-size chip packaging structure can be effectively solved, and the false welding problem caused by the mismatch of the thermal expansion coefficient can be avoided. BRIEF DESCRIPTION OF DRAWINGS

[0043] Fig. 1 shows a preparation process flow diagram of the 2.5D packaging structure in the embodiment of the present application.

[0044] Fig. 2 shows a structure diagram after forming a metal column in the embodiment of the present application.

[0045] Figure 3 shows a structure schematic diagram after forming a TSV composite adapter plate in an embodiment of the present application.

[0046] Figure 4 shows a structure schematic diagram after forming a first packaging layer in an embodiment of the present application.

[0047] Figure 5 shows a structure schematic diagram after forming a fourth re-wiring layer in an embodiment of the present application.

[0048] Figure 6 shows a structure schematic diagram after forming a first chip in an embodiment of the present application.

[0049] Figure 7 shows a structure schematic diagram after forming a substrate in an embodiment of the present application.

[0050] Figure 8 shows a structure schematic diagram after forming a second packaging layer in an embodiment of the present application.

[0051] Figure 9 shows a structure schematic diagram after forming a second support substrate in an embodiment of the present application.

[0052] Figure 10 shows a structure schematic diagram after forming a second chip and a virtual chip in an embodiment of the present application.

[0053] Figure 11 shows a top view structure schematic diagram of Figure 10.

[0054] Figure 12 shows a structure schematic diagram after forming a third packaging layer in an embodiment of the present application.

[0055] Figure 13 shows a structure schematic diagram after forming a metal bump in an embodiment of the present application.

[0056] Figure 14 shows a structure schematic diagram after forming a heat dissipation member in an embodiment of the present application.

[0057] 110 first support substrate 120 second support substrate 210 first rewiring layer 220 second rewiring layer 230 third rewiring layer 240 fourth rewiring layer 300 metal pillar 400 TSV interposer 510 first encapsulation layer 520 second encapsulation layer 530 third encapsulation layer 610 first chip 620 second chip 700 substrate 800 dummy chip 900 metal bump 100 heat sink DETAILED DESCRIPTION

[0058] Other advantages and benefits of the present application will become apparent to those skilled in the art upon reading the following detailed description of the application, and in particular after understanding the following detailed description of the preferred embodiments, exemplifying the principles of the present application. The present application may, however, be carried out in ways other than those specifically set forth herein without departing from the spirit and scope of the present application. Numerous modifications and adaptations will become apparent to those skilled in the art, and it is in now intended to limit the present application to the specific embodiments contained herein, but rather to cover all adaptations and modifications that fall within the scope of the present application.

[0059] In the detailed description of the embodiments of the application, the cross-sectional views of the device structure are shown in a partially enlarged manner without the general scale for the convenience of explanation, and the schematic views are only examples and should not limit the scope of the protection of the present application. In addition, the three-dimensional spatial dimensions of length, width and depth should be included in the actual fabrication.

[0060] For convenience of description, spatial relationship words such as "under", "below", "lower", "underneath", "above", "upper" and the like can be used herein to describe the relationship of one element or feature to another element or feature as shown in the drawings. It will be understood that these spatial relationship words are intended to encompass different orientations of the device in use or operation, in addition to the orientations depicted in the drawings. The device can be implemented in other orientations than those depicted in the drawings, and the spatial relationship words are intended to include at least those other orientations. For example, the device can be implemented in a first orientation and then inverted to a second orientation, and the spatial relationship words are intended to include both the first and second orientations. In addition, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers can also be present.

[0061] It should be noted that the diagrams provided in the embodiments only schematically illustrate the basic concepts of the present application, and thus only components related to the present application are shown in the diagrams, rather than being drawn according to the number, shape and size of the components in actual implementation. The shapes, number and proportion of the components in actual implementation can be arbitrarily changed, and the layout pattern of the components can be more complex.

[0062] As shown in FIG. 1, the present embodiment provides a preparation method of a 2.5D packaging structure. In the process of preparing the 2.5D packaging structure, a large-size substrate is directly bonded to a re-routed layer to realize electrical connection between the substrate and the re-routed layer. Compared with the traditional process of packaging first and then mounting the substrate, the warping problem of the packaging structure of a high-performance and large-size chip can be effectively solved, and the problem of false welding caused by mismatch of thermal expansion coefficients can be avoided.

[0063] The preparation of the 2.5D packaging structure will be further described below with reference to FIGS. 2-14. Specifically, the preparation includes the following steps:

[0064] First, referring to FIGS. 1 and 2, a first support substrate 110 is provided in step S1.

[0065] Specifically, the material of the first support substrate 110 can include materials such as glass, silicon, epoxy resin, metal and the like, and the specific type is not limited herein, as long as it has a certain supporting effect.

[0066] Preferably, the size of the first support substrate 110 is wafer-level, so that subsequent preparation can be based on wafer-level preparation. After the cutting and separation process, a plurality of independent packaging bodies can be prepared at the same time, so as to improve the working efficiency of the process. For example, as shown in FIG. 14, the structure can be regarded as an independent packaging body formed after cutting, but is not limited thereto. For example, according to needs, the first support substrate 110 can also be non-wafer-level.

[0067] When the first support substrate 110 is in wafer level, the size of the first support substrate 110 can include 4 inches, 6 inches, 8 inches, 12 inches, etc. without limitation.

[0068] In order to facilitate the subsequent removal of the first support substrate 110, in the embodiment, a separation layer is preferably formed on the surface of the first support substrate 110, such as a light-heat conversion layer formed by a light-heat conversion (LTHC) coating material, so that the LTHC coating material can be decomposed under heat, such as light / radiation (e.g. laser), to release the first support substrate 110, thereby achieving the convenience of separation operation.

[0069] Next, referring to FIGS. 1 and 2, step S2 is performed to form a first re-wiring layer 210 on the first support substrate 110.

[0070] Specifically, the first re-wiring layer 210 includes metal wires and a dielectric layer, and the material of the dielectric layer can include polymers such as polybenzoxazole and polyimide, or inorganic dielectric materials such as silicon nitride and silicon oxide, without limitation; and the material of the metal wires can include aluminum, copper, tungsten, or alloys thereof, without limitation.

[0071] The specific structure, material and preparation method of the first re-wiring layer 210 are not limited here, and can be referred to the prior art, such as using a combination of photolithography, etching, electroplating or deposition to form the first re-wiring layer 210.

[0072] Next, referring to FIGS. 1 and 2, step S3 is performed to form a metal pillar 300 on the first re-wiring layer 210, and the first end of the metal pillar 300 is electrically connected to the first re-wiring layer 210. The preparation of the metal pillar 300 is not limited here, and the material of the metal pillar 300 can include copper, aluminum, etc.

[0073] Next, referring to FIGS. 1 and 3, step S4 is performed to provide a TSV composite adapter plate, which includes a TSV adapter plate 400, a second re-wiring layer 220 and a third re-wiring layer 230 located on opposite sides of the TSV adapter plate 400 and electrically connected to the TSV adapter plate 400, respectively, the TSV composite adapter plate is bonded to the first re-wiring layer 210, and the third re-wiring layer 230 is electrically connected to the first re-wiring layer 210.

[0074] Specifically, the TSV transfer board 400 is provided with a TSV column, and the second re-wiring layer 220 and the third re-wiring layer 230 are electrically connected with the first end and the second end of the TSV column respectively, so that the TSV composite transfer board has smaller line width / line spacing through the second re-wiring layer 220 and the third re-wiring layer, to meet the needs of subsequent high-density electrical connection, wherein the line width of the TSV composite transfer board can be 0.4-1 μm, such as 0.4 μm, 0.5 μm, 0.8 μm, 1 μm, etc., and the line spacing of the TSV composite transfer board can be 0.4-1 μm, such as 0.4 μm, 0.5 μm, 0.8 μm, 1 μm, etc.

[0075] Wherein, when the TSV composite transfer board is bonded on the first re-wiring layer 210, the third re-wiring layer 230 is electrically connected with the first re-wiring layer 210, and the bonding method is not described here.

[0076] The material, structure, etc. of the second re-wiring layer 220 and the third re-wiring layer 230 can be referred to the first re-wiring layer 210, which is not described here.

[0077] Then, referring to FIG. 1 and FIG. 4, step S5 is performed to form a first packaging layer 510 on the first re-wiring layer 210, the first packaging layer 510 covering the metal column 300 and the TSV composite transfer board, and exposing the second end of the metal column 300 and the second re-wiring layer 220.

[0078] Specifically, the method for forming the first packaging layer 510 can include but not limited to compression molding, transfer molding and spin coating, and the material of the first packaging layer 510 can include but not limited to epoxy resin and polyamide, and the material and preparation method of the first packaging layer 510 are not limited here.

[0079] Wherein, when forming the first packaging layer 510, it is preferred to have a polishing process step, such as chemical mechanical polishing (CMP), to expose the metal wiring in the second end of the metal column 300 and the second re-wiring layer 220, to facilitate subsequent electrical connection, and to make the surface flat, thereby facilitating subsequent process operation.

[0080] Then, referring to FIG. 1 and FIG. 5, step S6 is performed to form a fourth re-wiring layer 240 on the first packaging layer 510, and the fourth re-wiring layer 240 is electrically connected with the metal column 300 and the second re-wiring layer 220.

[0081] Specifically, the material, structure, etc. of the fourth re-wiring layer 240 can be referred to the first re-wiring layer 210, which is not described here.

[0082] The line width of the fourth re-wiring layer 240 can be 2-10 μm, such as 2 μm, 4 μm, 6 μm, 10 μm, etc., and the line spacing of the fourth re-wiring layer 240 can be 2-10 μm, such as 2 μm, 4 μm, 6 μm, 10 μm, etc.

[0083] Next, referring to FIGS. 1 and 6, a first chip 610 is provided and bonded to the fourth re-wiring layer 240, and the first chip 610 is electrically connected to the fourth re-wiring layer 240, in step S7.

[0084] Specifically, the first chip 610 can include passive chips, such as capacitors, inductors, resistors, etc., and after the first chip 610 is bonded to the fourth re-wiring layer 240, a bottom filling layer can be formed between the first chip 610 and the fourth re-wiring layer 240 to form a stable bond, but is not limited thereto.

[0085] Next, referring to FIGS. 1 and 7, a substrate 700 is provided and bonded to the fourth re-wiring layer 240, and the substrate 700 is electrically connected to the fourth re-wiring layer 240, in step S8.

[0086] The size of the substrate 700 can be 100-300 mm, such as 100 mm, 200 mm, 300 mm, etc., and the specific type of the substrate 700 is not limited here. The substrate 700 can also be a wafer level size, which can be set as needed, and the specific topography, size, etc. of the substrate 700 are not limited here.

[0087] The line width of the substrate 700 can be 15-50 μm, such as 15 μm, 25 μm, 30 μm, 50 μm, etc., and the line spacing of the substrate 700 can be 15-50 μm, such as 15 μm, 25 μm, 30 μm, 50 μm, etc.

[0088] In this embodiment, the substrate 700 is directly bonded to the fourth re-wiring layer 240 to achieve electrical connection between the substrate 700 and the fourth re-wiring layer 240. Compared to the traditional process of first packaging and then mounting the substrate 700, the warping problem of high-performance, large-size chip packaging structures can be effectively solved, and the problem of false welding caused by mismatching of the thermal expansion coefficient can be avoided, thereby improving the quality of the final product.

[0089] Then, referring to FIG. 1 and FIG. 8, step S9 is performed to form a second encapsulation layer 520 on the fourth re-distribution layer 240, the second encapsulation layer 520 covering the substrate 700 and the first chip 610, and exposing the surface of the substrate 700.

[0090] Specifically, the preparation, material, etc. of the second encapsulation layer 520 can refer to the first encapsulation layer 510, which will not be repeated here.

[0091] Then, referring to FIG. 1 and FIG. 9, step 10 is performed to provide a second support substrate 120 and bond the second support substrate 120 on the second encapsulation layer 520.

[0092] Specifically, the type, bonding and removal method of the second support substrate 120 can refer to the first support substrate 110, which will not be repeated here.

[0093] Then, referring to FIG. 1 and FIG. 10, step 11 is performed to remove the first support substrate 110 to expose the first re-distribution layer 210, and step 12 is performed to provide a second chip 620 and a virtual chip 800, and bond the second chip 620 and the virtual chip 800 on the first re-distribution layer 210, and the second chips 620 are electrically connected through the first re-distribution layer 210 and the TSV composite adapter.

[0094] The second chip 620 can include a system on chip technology (SoC) and / or a high bandwidth memory (HBM), and the SoC chip is a chip containing a processor, a memory and an on-chip logic. The specific type of the second chip 620 can be selected as needed, as shown in FIG. 11, in this embodiment, the SoC chip and the HBM chip are bonded on the first re-distribution layer 210 at the same time, forming a 2.5D packaging structure of 8xSoC+16xHBM, but not limited thereto. As shown in FIG. 11, the dashed box A area schematically shows the interconnection area of the SoC chip, i.e. the schematic area of the electrical connection between the second chips 620 through the first re-distribution layer 210 and the TSV composite adapter, so that the high-speed signal connection between the second chips 620 is realized through the high-density distribution of the TSV composite adapter.

[0095] The virtual chip 800 can include a semiconductor virtual chip or a metal virtual chip. In this embodiment, a plurality of virtual chips 800 are formed around the second chip 620 to increase rigidity and further reduce warping probability by using the virtual chips 800 in the empty area. The specific type, number, size, and distribution of the virtual chip 800 are not limited here.

[0096] The bonding sequence of the second chip 620 and the virtual chip 800 can be selected as needed, and is not limited here.

[0097] Further, after the second chip 620 and the virtual chip 800 are bonded to the first re-distribution layer 210, a bottom filling layer can be formed between the second chip 620, the virtual chip 800, and the first re-distribution layer 210 to form stable bonding, but is not limited to this.

[0098] Next, referring to FIG. 1 and FIG. 12, step 13 is performed to form a third packaging layer 530 on the first re-distribution layer 210, the third packaging layer 530 covering the second chip 620 and the virtual chip 800, and exposing the surfaces of the second chip 620 and the virtual chip 800.

[0099] Specifically, the preparation and material of the third packaging layer 530 can refer to the first packaging layer 510, and is not repeated here.

[0100] Next, referring to FIG. 1 and FIG. 13, step 14 is performed to remove the second support substrate 120 to expose the substrate 700, and step 15 is performed to form a metal bump 900 on the surface of the substrate 700, and the metal bump 900 is electrically connected to the substrate 700.

[0101] Further, a cutting step can be included to form an independent 2.5D packaging structure.

[0102] Specifically, when wafer-level preparation is performed, after the metal bump 900 is formed, one or a combination of mechanical cutting or laser cutting can be used to divide the wafer-level 2.5D packaging structure into a plurality of 2.5D packaging structures with single structures. The cutting method can be selected as needed, and is not limited here.

[0103] Further, referring to FIG. 14, a step of forming a heat sink 100 in contact with the virtual chip 800 on the third packaging layer 530 can also be included, wherein the heat sink 100 can include a patterned metal heat sink, but is not limited thereto, and the type of the heat sink 100 is not limited herein. The heat sink 100 can improve the heat dissipation effect.

[0104] Referring to FIGS. 2-14, the embodiment further provides a 2.5D packaging structure, which includes:

[0105] a first redistribution layer 210, including a first surface and an opposite second surface;

[0106] a metal pillar 300, located on the second surface of the first redistribution layer 210, and having a first end electrically connected to the first redistribution layer 210;

[0107] a TSV composite adapter, including a TSV adapter 400, a second redistribution layer 220, and a third redistribution layer 230, the second redistribution layer 220 and the third redistribution layer 230 being located on opposite surfaces of the TSV adapter 400 and electrically connected to the TSV adapter 400 respectively, the TSV composite adapter being bonded to the first redistribution layer 210, and the third redistribution layer 230 being electrically connected to the first redistribution layer 210;

[0108] a first packaging layer 510, located on the second surface of the first redistribution layer 210, covering the metal pillar 300 and the TSV composite adapter, and exposing a second end of the metal pillar 300 and the second redistribution layer 220;

[0109] a fourth redistribution layer 240, including a first surface and an opposite second surface, the first surface of the fourth redistribution layer 240 being in contact with the first packaging layer 510, and the fourth redistribution layer 240 being electrically connected to the metal pillar 300 and the second redistribution layer 220;

[0110] a first chip 610, bonded to the second surface of the fourth redistribution layer 240, and electrically connected to the fourth redistribution layer 240;

[0111] a substrate 700, bonded to the second surface of the fourth redistribution layer 240, and electrically connected to the fourth redistribution layer 240;

[0112] A second encapsulation layer 520 is located on a second surface of the fourth re-distribution layer 240, encapsulates the substrate 700 and the first chip 610, and exposes a surface of the substrate 700;

[0113] A second chip 620 and a virtual chip 800 are both bonded on a first surface of the first re-distribution layer 210, and the second chip 620 is electrically connected with the TSV composite adapter through the first re-distribution layer 210;

[0114] A third encapsulation layer 530 is located on the first re-distribution layer 210, encapsulates the second chip 620 and the virtual chip 800, and exposes surfaces of the second chip 620 and the virtual chip 800;

[0115] A metal bump 900 is located on a surface of the substrate 700 and is electrically connected with the substrate 700.

[0116] Specifically, the 2.5D packaging structure can be prepared by the above preparation method, but is not limited thereto. In the embodiment, the 2.5D packaging structure is prepared by the above preparation method, so the preparation, material, etc. of the 2.5D packaging structure can be referred to the above preparation method.

[0117] For example, the size of the substrate 700 includes 100-300 mm.

[0118] Specifically, the size of the substrate 700 can include, for example, 100 mm, 200 mm, 300 mm, etc. The specific type of the substrate 700 is not limited here. The specific topography, size, etc. of the substrate 700 are not limited here.

[0119] For example, the heat dissipation member 100 can also be located on the third encapsulation layer 530 and in contact with the virtual chip 800.

[0120] Specifically, the heat dissipation member 100 can include a patterned metal heat dissipation member, but is not limited thereto. The type of the heat dissipation member 100 is not limited here. The heat dissipation member 100 can improve the heat dissipation effect and help to improve the problem of thermal stress accumulation.

[0121] In summary, the 2.5D packaging structure and the preparation method thereof directly bond the large-size substrate to the re-routed layer to realize the electrical connection between the substrate and the re-routed layer in the process of preparing the 2.5D packaging structure, compared with the traditional process of packaging first and then mounting the substrate, the warping problem of the high-performance and large-size chip packaging structure can be effectively solved, and the false welding problem caused by the mismatch of the thermal expansion coefficients can be avoided.

[0122] The above embodiments only illustrate the principles and effects of the present application, and are not intended to limit the present application. Any person skilled in the art can modify or change the above embodiments without departing from the spirit and scope of the present application. Therefore, all equivalent modifications or changes made by those skilled in the art without departing from the spirit and technical idea disclosed by the present application should be covered by the claims of the present application.

Claims

1. A method for fabricating a 2.5D packaging structure, characterized in that, Includes the following steps: Provide a first support substrate; A first redistribution layer is formed on the first support substrate; A metal pillar is formed on the first redistribution layer, and the first end of the metal pillar is electrically connected to the first redistribution layer. A TSV composite adapter board is provided, the TSV composite adapter board including a TSV adapter board and a second rerouting layer and a third rerouting layer located on opposite sides of the TSV adapter board and electrically connected to the TSV adapter board respectively, the TSV composite adapter board being bonded to the first rerouting layer, and the third rerouting layer being electrically connected to the first rerouting layer. A first encapsulation layer is formed on the first redistribution layer, the first encapsulation layer covers the metal pillar and the TSV composite adapter board, and exposes the second end of the metal pillar and the second redistribution layer; A fourth redistribution layer is formed on the first encapsulation layer, and the fourth redistribution layer is electrically connected to both the metal pillar and the second redistribution layer. A first chip is provided and bonded to the fourth redistribution layer, and the first chip is electrically connected to the fourth redistribution layer; A substrate is provided and bonded to the fourth redistribution layer, and the substrate is electrically connected to the fourth redistribution layer; A second encapsulation layer is formed on the fourth redistribution layer, the second encapsulation layer covers the substrate and the first chip, and exposes the surface of the substrate; A second support substrate is provided, and the second support substrate is bonded to the second packaging layer; Remove the first support substrate to expose the first redistribution layer; A second chip and a virtual chip are provided, and both the second chip and the virtual chip are bonded to the first redistribution layer, and the second chips are electrically connected to the TSV composite adapter board through the first redistribution layer. A third encapsulation layer is formed on the first redistribution layer, the third encapsulation layer covering the second chip and the virtual chip, and exposing the surfaces of the second chip and the virtual chip; Remove the second support substrate to expose the substrate; Metal bumps are formed on the surface of the substrate, and the metal bumps are electrically connected to the substrate.

2. The method for fabricating the 2.5D packaging structure according to claim 1, characterized in that: It also includes the step of forming a heat sink on the third encapsulation layer that contacts the virtual chip.

3. The method for fabricating the 2.5D packaging structure according to claim 1, characterized in that: The 2.5D packaging structure is fabricated using a wafer-level method.

4. The method for fabricating the 2.5D packaging structure according to claim 1, characterized in that: The size of the substrate ranges from 100 to 300 mm.

5. The method for fabricating the 2.5D packaging structure according to claim 1, characterized in that: The first chip includes a passive chip, and the second chip includes a SoC chip and / or an HBM chip.

6. The method for fabricating the 2.5D packaging structure according to claim 1, characterized in that: The linewidth / spacing of the TSV composite adapter board ranges from 0.4μm / 0.4μm to 1μm / 1μm; the linewidth / spacing of the fourth redistribution layer ranges from 2μm / 2μm to 10μm / 10μm; and the linewidth / spacing of the substrate ranges from 15μm / 15μm to 50μm / 50μm.

7. The method for fabricating the 2.5D packaging structure according to claim 1, characterized in that: The virtual chip includes a semiconductor virtual chip or a metal virtual chip.

8. A 2.5D packaging structure, characterized in that, The 2.5D packaging structure includes: A first redistribution layer, the first redistribution layer including a first surface and an opposite second surface; A metal pillar, the metal pillar being located on the second surface of the first redistribution layer, and the first end of the metal pillar being electrically connected to the first redistribution layer; The TSV composite adapter board includes a TSV adapter board and a second rerouting layer and a third rerouting layer located on opposite sides of the TSV adapter board and electrically connected to the TSV adapter board respectively. The TSV composite adapter board is bonded to the first rerouting layer, and the third rerouting layer is electrically connected to the first rerouting layer. A first encapsulation layer is located on the second surface of the first redistribution layer, covering the metal pillar and the TSV composite adapter board, and exposing the second end of the metal pillar and the second redistribution layer. The fourth redistribution layer includes a first side and an opposite second side. The first side of the fourth redistribution layer is in contact with the first encapsulation layer, and the fourth redistribution layer is electrically connected to both the metal pillar and the second redistribution layer. A first chip is bonded to the second surface of the fourth redistribution layer and is electrically connected to the fourth redistribution layer. A substrate, the substrate being bonded to the second surface of the fourth redistribution layer, and the substrate being electrically connected to the fourth redistribution layer; The second encapsulation layer is located on the second surface of the fourth redistribution layer, covers the substrate and the first chip, and exposes the surface of the substrate; The second chip and the virtual chip are both bonded to the first surface of the first redistribution layer, and the second chips are electrically connected to the TSV composite adapter board through the first redistribution layer. A third encapsulation layer is located on the first redistribution layer, covering the second chip and the virtual chip, and exposing the surfaces of the second chip and the virtual chip; Metal bumps, which are located on the surface of the substrate and electrically connected to the substrate.

9. The 2.5D packaging structure according to claim 8, characterized in that: The size of the substrate ranges from 100 to 300 mm.

10. The 2.5D packaging structure according to claim 8, characterized in that: It also includes a heat sink located on the third encapsulation layer and in contact with the virtual chip.

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