Driving circuit, display panel, and electronic device

Abstract

A driving circuit (13), a display panel (10), and an electronic device (100). The driving circuit (13) comprises m scan driving units (130) which are arranged in sequence and are cascaded. An i-th stage scan driving unit (130) is used for outputting a scan signal (Gsi) and a compensation scan signal (Gri). The scan signal (Gsi) is a pulse signal lasting for a first preset duration, and the compensation scan signal (Gri) is a pulse signal lasting for a second preset duration. The scan signal (Gsi) is used for loading a pixel unit (P) at a first position during a data-loading period (H3), so as to control the pixel unit (P) to receive a data signal (Data) to execute image display. The compensation scan signal (Gri) is used for being loaded to the pixel unit (P) during a compensation period (H2), so as to perform data signal (Data) compensation on the pixel unit (P). The second preset duration is longer than the first preset duration.

Description

Driving circuit, display panel and electronic device

[0001] The present application claims priority to the Chinese patent application No. 202411035463.1, filed on July 30, 2024, and entitled "Driving circuit, display panel and electronic device", the whole content of which is incorporated herein by reference. TECHNICAL FIELD

[0002] The present application relates to the technical field of display, in particular to a driving circuit, a display panel and an electronic device. BACKGROUND

[0003] Display technology has always been one of the important research directions in electronic devices. For a display panel, since the circuit for driving the pixel unit to work is usually also arranged in the display area of the display panel, in the case of fixed display area size, the more complex the driving circuit is, the fewer pixel units can be added in the display area.

[0004] At present, the circuit structure for driving the pixel unit has a large number of electronic components, which leads to difficulty in achieving high efficiency of the driving circuit outputting the driving signal and difficulty in achieving the effect of narrow frame in the case of fixed display panel size. SUMMARY

[0005] Based on the foregoing technical problems, the present application provides a driving circuit with high efficiency and high integration for outputting the driving signal used by the pixel unit when performing image display.

[0006] In a first aspect, the present application provides a driving circuit, comprising m scan driving units arranged in sequence and cascaded, in the i-th scan period in m continuous scan periods within a frame image display period, the i-th level scan driving unit is used for outputting a scan signal and a compensation scan signal, the scan signal is a pulse signal with a first preset time length, the compensation scan signal is a pulse signal with a second preset time length, the scan signal is used for loading a pixel unit at a first position in a data loading period in the i-th scan period to control the pixel unit to receive a data signal to perform image display, the compensation scan signal is used for loading to the pixel unit in a compensation period of the i-th scan period to compensate the pixel unit for the data signal, wherein the second preset time length is greater than the first preset time length, the compensation period and the data loading period are sequentially continuous in time, m is a positive integer greater than 1, and i is a positive integer greater than or equal to 1 and less than m.

[0007] In an embodiment, the scan driving unit comprises an enable trigger end, a first clock signal input end, a second clock signal input end, a first signal output end and a second signal output end. The enable trigger end is configured to receive an enable trigger signal to enable the scan driving unit to work. The first clock signal input end and the second clock signal input end are configured to receive two clock signals with a preset interval of a unit time length. The scan driving unit outputs the scan signal from the first signal output end according to the clock signal of the first clock signal input end, and outputs the compensation scan signal from the second signal output end at the same time. The scan driving unit stops the compensation scan signal according to the clock signal of the second clock signal input end. The clock signal is a periodic pulse signal with a pulse width of a unit time length.

[0008] In an embodiment, the clock signals received by the first clock signal input end and the second clock signal input end have an interval of b unit time lengths. The first preset time length corresponding to the scan signal is 1 unit time length, and the second preset time length corresponding to the compensation scan signal is b unit time lengths.

[0009] In an embodiment, the scan driving unit comprises a first pull-up module, a first clock signal output module and a first reset scan output module. The first pull-up module is connected to the enable trigger end, a high-voltage power supply end and a first control node, and is configured to pull up the voltage of the first control node to a high level under the control of the enable trigger signal provided by the enable trigger end. The first clock signal output module is connected to the first control node, the first clock signal input end and the first signal output end, and is configured to output the clock signal as the scan signal when the voltage of the first control node is at a high level, and maintain the voltage of the first control node at a high level within the second preset time length. The first reset scan output module is connected to the first control node, the first clock signal input end, the high-voltage power supply end and the second signal output end, and is configured to output the power supply signal provided by the high-voltage power supply end as the compensation scan signal within the second preset time length under the control of the clock signal when the voltage of the first control node is at a high level.

[0010] In an embodiment, the scan driving unit further comprises a second pull-down module. The second pull-down module is connected to the first control node, a low-voltage power supply end and a second control node, and is configured to connect the low-voltage power supply end to the second control node to pull down the voltage of the second control node to a low level when the voltage of the first control node is at a high level.

[0011] In an embodiment, the scan driving unit further comprises a first pull-down module and a second pull-up module.

[0012] The second pull-up module is connected with the high-voltage power supply end and the second control node, and is used for loading the high-voltage provided by the high-voltage power supply end to the second control node to pull up the voltage of the second control node when the second control node is not loaded with low voltage; and the first pull-down module is connected with the first control node, the second control node and the second clock signal input end, and is used for pulling down the voltage of the first control node under the control of the clock signal provided by the second clock signal input end or when the voltage of the second control node is high.

[0013] In an embodiment, the scan driving unit further comprises a second clock signal output module and a second reset scan output module. The second clock signal output module is connected with the second control node, the low-voltage power supply end and the first signal output end, and is used for transmitting low voltage to the first signal output end to stop outputting the scan signal when the voltage of the second control node is high. The second reset scan output module is connected with the second control node, the low-voltage power supply end and the second signal output end, and is used for transmitting low voltage to the second signal output end to stop outputting the compensation scan signal when the voltage of the second control node is high.

[0014] In an embodiment, the scan driving unit further outputs a reset scan signal, and the first signal output end outputs the scan signal as the reset scan signal, which is used for loading to the pixel unit at the second position in the reset period of the i+bth scan period to control the pixel unit to receive reset voltage to perform reset.

[0015] In an embodiment, f continuous virtual scan periods are further included in the one frame image display period, and the f continuous virtual scan periods are sequentially continuous in time with the first scan period. The scan driving circuit further comprises f virtual scan driving units, the f virtual scan driving units are sequentially cascaded, the virtual scan driving unit at the fth stage is connected with the scan driving unit at the first stage, and the virtual scan driving unit at the fth stage outputs an enable trigger signal to trigger the scan driving unit at the first stage to work. The virtual scan driving units at the first to fth stages are used for sequentially outputting the reset scan signal and the compensation scan signal in the reset period and the compensation period of the first to fth virtual scan periods.

[0016] In an embodiment, the driving circuit further comprises m sequentially arranged light-emitting driving units, in the ith scanning period, the ith light-emitting driving unit is configured to output a light-emitting signal, the light-emitting signal is configured to be provided to the pixel unit in the compensation period to compensate the pixel unit with the compensation scanning signal, and the light-emitting signal is further configured to control the pixel unit to emit light according to the data signal to display an image, wherein the light-emitting signal is a pulse signal lasting for the second preset time length, and the compensation period, the data loading period and the light-emitting period are sequentially and continuously in time.

[0017] In an embodiment, the light-emitting driving unit comprises a light-emitting clock signal input end, a first light-emitting input end, a second light-emitting input end, a light-emitting output end, a first light-emitting pull-up module and a first light-emitting signal output module. The light-emitting clock signal input end is configured to receive a light-emitting clock signal, the first light-emitting input end and the second light-emitting input end are connected to the first signal output ends of two scanning driving units at a preset level interval to respectively receive two scanning signals. The first light-emitting pull-up module is connected to the light-emitting clock signal input end, a light-emitting high-voltage power supply end and a first light-emitting control node, and is configured to load a high potential voltage provided by the light-emitting high-voltage power supply end to the first light-emitting control node under the control of the light-emitting clock signal. The first light-emitting signal output module is connected to the first light-emitting control node, the light-emitting high-voltage power supply end and the light-emitting output end, and is configured to output the high potential voltage provided by the light-emitting high-voltage power supply end as a light-emitting signal from the light-emitting output end within the second preset time length under the control of the high potential voltage of the first light-emitting control node.

[0018] In an embodiment, the light-emitting driving unit further comprises a second light-emitting pull-down module, the second light-emitting pull-down module is connected to the first light-emitting control node, a second light-emitting control node and a light-emitting low-voltage power supply end, and is configured to load a low potential voltage provided by the light-emitting low-voltage power supply end to the second light-emitting control node when the first light-emitting control node is at a high potential voltage.

[0019] In an embodiment, the light emitting driving unit further comprises a second light emitting pull-up module and a second light emitting signal output module. The second light emitting pull-up module is connected to the first light emitting input terminal, the second light emitting input terminal and the second light emitting control node, for pulling up the voltage level of the second light emitting control node when the scanning signal received by the first light emitting input terminal or the second light emitting input terminal is high. The second light emitting signal output module is connected to the second light emitting control node, the light emitting low voltage power supply terminal, the light emitting clock signal input terminal and the light emitting output terminal, and the second light emitting signal output module is configured to stop outputting the light emitting signal when the voltage of the second light emitting control node is high or the light emitting clock signal is received.

[0020] In an embodiment, the light emitting driving unit further comprises a first light emitting pull-down module, which is connected to the first light emitting control node, the second light emitting control node and the light emitting low voltage power supply terminal, for loading the low voltage provided by the light emitting low voltage power supply terminal to the first light emitting control node when the voltage of the second light emitting control node is high, so as to control the first light emitting signal output module to stop outputting the light emitting signal.

[0021] In an embodiment, the light emitting driving unit further comprises a first light emitting pull-down module, which is connected to the light emitting high voltage power supply terminal, the first light emitting control node, the second light emitting control node and the light emitting low voltage power supply terminal, for disconnecting the conductive path between the first light emitting control node and the light emitting low voltage power supply terminal by the high voltage provided by the light emitting high voltage power supply terminal when the voltage of the first light emitting control node is high, and for loading the low voltage provided by the light emitting low voltage power supply terminal to the first light emitting control node when the voltage of the second light emitting control node is high, so as to control the first light emitting signal output module to stop outputting the light emitting signal.

[0022] In a second aspect, a pixel unit applied to a display panel is provided, and at least includes a sub-pixel. The sub-pixel includes a control switch tube, a driving switch tube, a light emitting element, a first energy storage element and a second energy storage element. The driving switch tube is connected to the control switch tube through a first node, and is further connected to a first power supply end through a second node and to the light emitting element through a third node. The light emitting element is connected to the third node and a second power supply end. The first energy storage element is connected to the first node and the third node. The second energy storage element is connected to the third node and the second power supply end. The control switch tube is used to receive a scanning signal and a data signal during a data writing period of a frame image display period. The scanning signal is used to control the control switch tube to transmit the received data signal to the first energy storage element and the second energy storage element. The data signal is used to control the driving switch tube to provide a corresponding driving current to the light emitting element from a driving power output of the first power supply end during a light emitting period of the frame image display period, so as to drive the light emitting element to emit light to display an image. The data writing period and the light emitting period are sequentially continuous in time.

[0023] In an embodiment, the first energy storage element includes a first energy storage connection end and a second energy storage connection end. The first energy storage connection end is connected to the first node, and the second energy storage connection end is connected to the third node. The second energy storage element includes a third energy storage connection end and a fourth energy storage connection end. The third energy storage connection end is connected to the third node, and the fourth energy storage connection end is connected to the second power supply end.

[0024] In an embodiment, the pixel unit further includes a compensation switch tube connected to a compensation power supply end and the first node. The compensation switch tube is used to transmit a compensation signal to the first node when a compensation scanning signal is received during a compensation period of the frame image display period. The compensation period and the data writing period are sequentially continuous in time.

[0025] In an embodiment, the pixel unit further includes a light emitting switch tube connected to the second node and the first power supply end. The light emitting switch is used to transmit the driving power to the driving switch tube when a light emitting signal is received during the light emitting period.

[0026] In an embodiment, the pixel unit further includes a reset switch tube connected to the second node. The light emitting switch is used to transmit a reset voltage to the second node when a reset signal is received during a reset period of the frame image display period. The reset voltage is transmitted to the third node through the driving switch tube to reset the light emitting element. The reset period and the compensation period are sequentially continuous in time.

[0027] In an embodiment, the pixel unit comprises a plurality of sub-pixels, the plurality of sub-pixels share the same light-emitting switch tube; the plurality of sub-pixels respectively comprise a red sub-pixel, a green sub-pixel and a blue sub-pixel, wherein the red sub-pixel emits red light, the green sub-pixel emits green light, and the blue sub-pixel emits blue light.

[0028] In a third aspect, a display panel is provided, comprising m scan lines, n data lines, m light-emitting lines, m compensation scan lines, m compensation lines, m reset scan lines, m reset lines, a data driving circuit, a compensation circuit, a reset circuit and the aforementioned driving circuit, and the display panel further comprises m*n pixel units, each pixel unit is connected to one of the scan lines, the data lines, the light-emitting lines, the compensation scan lines, the compensation lines, the reset scan lines and the reset lines.

[0029] The driving circuit comprises m scan driving units connected to the m scan lines, m compensation scan lines and m reset scan lines respectively, and m light-emitting driving units connected to the m scan lines respectively.

[0030] The m light-emitting driving units of the light-emitting driving circuit are connected to the pixel units through the m light-emitting lines.

[0031] The compensation circuit is connected to the compensation lines and outputs a compensation signal to the pixel units when the pixel units receive a compensation scan signal, so as to perform data signal compensation on the pixel units.

[0032] The reset circuit is connected to the reset lines and outputs a reset signal to the pixel units when the pixel units receive a reset scan signal, so as to reset the pixel units.

[0033] In one embodiment, the scan line and the data line are connected to the control switch transistor within the pixel unit. The scan line outputs a scan signal to control the control switch transistor to turn on, and the data line outputs a data signal that is transmitted to the first node through the control switch transistor. The light-emitting line is connected to the light-emitting switch transistor, and the light-emitting switch transistor outputs a light-emitting signal to control its conduction. When the control switch transistor is turned on, the driving power supplied by the first power supply terminal is applied to the second node. The compensation scan line and the compensation line are connected to the compensation switch transistor. The compensation scan line outputs a compensation scan signal to the compensation switch transistor, and the compensation scan signal is used to control the compensation switch transistor to turn on. The compensation line outputs a compensation signal, which is transmitted to the first node through the compensation switch transistor. The first node controls the driving switch transistor to turn on and charges and compensates the third node through the second power supply terminal. The reset scan line and the reset line are connected to the reset switch transistor. The reset scan line outputs a reset signal to control the reset switch transistor to turn on, and the reset line outputs a reset voltage to the second node. The reset voltage is transmitted to the third node through the driving switch transistor to reset the light-emitting element.

[0034] Thirdly, an electronic device is provided, the electronic device including a housing and the aforementioned display panel, the housing being used to support the display panel.

[0035] Compared to existing technologies, in this embodiment, the scan driving unit can simultaneously output scan signals and compensation scan signals of different durations. That is, a single scan driving unit can output both scan signals and compensation scan signals, while ensuring that the durations of the scan signals and compensation scan signals are different. This effectively simplifies the circuit structure of the scan driving unit, improves its signal output efficiency, and increases the integration and design space of the scan driving circuit. Furthermore, the light-emitting driving unit further included in the driving circuit can output corresponding light-emitting signals, thereby effectively improving the image display effect of the pixel unit and providing more space for the design of narrow bezels on the display panel. Attached Figure Description

[0036] To more clearly illustrate the technical solutions in the embodiments of this application, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0037] Figure 1 is a schematic diagram of a display device provided in an embodiment of this application;

[0038] Fig. 2 is a functional module diagram of the display device shown in Fig. 1;

[0039] Fig. 3 is a planar layout diagram of the display panel shown in Fig. 2;

[0040] Fig. 4 is a layout diagram of any one pixel unit shown in Fig. 3;

[0041] Fig. 5 is a specific circuit structure diagram of any one sub-pixel shown in Fig. 3;

[0042] Fig. 6 is a working timing diagram of the pixel unit shown in Fig. 5;

[0043] Fig. 7 is a connection diagram of the scan driving circuit and the light emitting driving circuit shown in Fig. 3;

[0044] Fig. 8 is a circuit structure diagram of any one scan driving unit shown in Fig. 7;

[0045] Fig. 9 is a working timing diagram of the scan driving unit shown in Fig. 8;

[0046] Fig. 10 is a circuit structure diagram of any one light emitting driving unit shown in Fig. 6;

[0047] Fig. 11 is a working timing diagram of the light emitting driving unit shown in Fig. 10;

[0048] Fig. 12 is a circuit structure diagram of the light emitting driving unit in a modified embodiment shown in Fig. 7.

[0049] Explanation of reference numerals: display device 100, display panel 10, support frame 30, first circuit board 310, second circuit board 320, power supply circuit 17, timing control circuit 11, data drive circuit 12, scan drive circuit 13, light emission drive circuit 14, compensation circuit 15, reset circuit 16, power supply circuit 17, display area 10a, non-display area 10b, scan clock signal CK, light emission clock signal ECK, first direction F1, second direction F2, data line D1-Dn, scan line G1-Gm, compensation scan line Gc1-Gcm, light emission line E1-Em, compensation line Dc1-Dcm, reset scan line Rg1-Rgm, reset line Rv1-Rvm, data signal Data, scan signal Gs1-Gsn, compensation scan signal Gr1-Grm, light emission signal Et1-Etm, reset scan signal Rsi, reset signal INI, pixel unit P, red sub-pixel R, green sub-pixel G, blue sub-pixel B, control switch tube M1, drive switch tube M2, compensation switch tube M3, light emission element L, first energy storage element C1, second energy storage element C2, first node N1, second node N2, third node N3, first power supply terminal VDD, second power supply terminal VSS, reset period H1, compensation period H2, data loading period H3, light emission period H4, GOA unit 130, virtual GOA unit 131, clock signal CK1-CK8, enable trigger terminal En, first clock signal input terminal CI1, second clock signal input terminal CI2, first signal output terminal SO1, second signal output terminal SO2, first pull-up module 31, first switch tube T1, first control terminal T10, first conduction terminal T11, second conduction terminal T12, first control node PU, second control node PU, third control node PU, high-voltage power supply terminal VGH, low-voltage power supply terminal VGL, first pull-down module 32, seventh switch tube T7, seventh control terminal T70, seventh pull-up conduction terminal T71, seventh pull-down conduction terminal T72, eighth switch tube T8, eighth control terminal T80, eighth pull-up conduction terminal T81, eighth pull-down conduction terminal T82, second pull-up module 33, second switch tube T2, second control terminal T20, second pull-up conduction terminal T21, second pull-down conduction terminal T22, second pull-down module 34, sixth switch tube T6, sixth control terminal T60, sixth pull-up conduction terminal T61, sixth pull-down control terminal T62, first clock signal output module 35, third clock output switch tube T3a, third clock output control terminal T310, first clock output conduction terminal T311, second clock output conduction terminal T312, energy storage capacitor Cc, second clock signal output module 36, fourth clock output switch tube T4a,fourth clock output control end-T410, third clock output conductive end-T413, fourth clock output conductive end-T414, first reset scan output module-37, third compensation scan output switch tube-T3b, third compensation scan output control end-T320, first compensation scan output conductive end-T321, second compensation scan output conductive end-T322, fifth compensation scan output switch tube-T5a, fifth compensation scan output control end-T510, fifth compensation scan output conductive end-T515, sixth compensation scan output conductive end-T516, second reset scan output module-38, fourth compensation scan off switch tube-T4b, fourth compensation off control end-T420, first compensation scan off conductive end-T421, second compensation scan off conductive end-T422, fifth compensation scan off switch tube-T5b, fifth compensation scan off control end-T520, third compensation scan output conductive end-T523, fourth compensation scan off conductive end-T524, light emitting clock signal input end-EKI, first light emitting input end-EI1, second light emitting input end-EI2, light emitting output end-EO, light emitting high-voltage power supply end-EVGH, light emitting low-voltage power supply end-EVGL, first light emitting pull-up module-41, first light emitting switch tube-ET1, first light emitting control end-ET10, first light emitting conductive end-ET11, second light emitting conductive end-ET12, first light emitting pull-down module-42, seventh light emitting switch tube-ET7, seventh light emitting control end-ET70, seventh light emitting pull-up conductive end-ET71, seventh light emitting pull-down conductive end-ET72, seventh upper link light emitting switch tube-ET7a, seventh lower link light emitting switch tube-ET7b, intermediate node-Nm, eighth light emitting switch tube-ET8, eighth light emitting control end-ET80, eighth pull-up conductive end-ET81, eighth light emitting pull-down conductive end-ET82, second light emitting pull-up module-43, second pull-up reset switch tube-ET2a, second pull-up reset control end-ET210, first pull-up reset conductive end-ET211, second pull-up reset conductive end-ET212, second pull-up write switch tube-ET2b, second pull-up write control end-ET220, first pull-up write conductive end-ET221, second pull-up write conductive end-ET222, second light emitting pull-down module-44, sixth light emitting switch tube-ET6, sixth light emitting control end-ET60, sixth light emitting pull-up conductive end-ET61, sixth light emitting pull-down conductive end-ET62, first light emitting signal output module-45, third light emitting clock output switch tube-ET3, third light emitting output control end-ET30, first light emitting output conductive end-ET31, second light emitting output conductive end-ET32, second light emitting signal output module-46, first light emitting off switch tube-ET4, first light emitting off control end-ET40, first light emitting off conductive end-ET41, second light emitting off conductive end-ET42, second light emitting off switch tube-ET5,Second light-emitting-off control terminal - ET50, third light-emitting-off conductive terminal - ET53, fourth light-emitting-off conductive terminal - ET54. DETAILED DESCRIPTION

[0050] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work fall within the scope of protection of the present application.

[0051] Please refer to FIG. 1, which is a structural schematic diagram of a display device according to an embodiment of the present application. The display device 100 comprises a display panel 10 and a support frame 30, and the display panel 10 is fixed to the support frame 30. The support frame 30 provides fixing and protection for the display panel 10. In other embodiments of the present application, the display device 100 can not be provided with the support frame 30, for example, portable electronic devices such as mobile phones, tablet computers, etc.

[0052] Please refer to FIG. 2, which is a functional module schematic diagram of the display device 100 shown in FIG. 1.

[0053] As shown in FIG. 2, the display device 100 comprises the display panel 10, a first circuit board 310 and a second circuit board 320. The first circuit board 310 is electrically connected with the display panel 10 and the second circuit board 320. The first circuit board 310 and the display panel 10 can be connected through flexible conductive wires or flexible conductive films, so that the first circuit board 310 can be rotated or turned relative to the display panel 10 and fixed to the display panel 10. Correspondingly, the first circuit board 310 and the second circuit board 320 are also connected through soft wires, so that the second circuit board 320 can first rotate the first circuit board 310 and be fixed to the display panel 10.

[0054] In the embodiment, the first circuit board 310 is a driving circuit board (X-board), and the second circuit board 320 is a control circuit board (C-board). The first circuit board 310 and the second circuit board 320 can be a driving circuit board (X-board) or a control circuit board (C-board) alone, or can be integrated to obtain a driving circuit board (X-board) and a control circuit board (C-board).

[0055] The second circuit board 320 is a control circuit board (C-board) and mainly includes a power supply circuit 17 (PMIC), a timing control circuit 11, etc. The second circuit board 320 is mainly used for receiving a display signal for image display provided from outside and outputting a data signal, a control signal and a power supply signal correspondingly. In this embodiment, the timing control circuit TCON is also connected to an image processing module (GPU) and obtains image data for image display from the image processing module and transmits the image data to pixel units in a display area of the display panel 10 after coding and decoding to perform corresponding image display. It can be understood that the image processing module is arranged in a host device independent of the display device 100, for example, the image processing module is arranged in a host computer or the image processing module can also be arranged in the display device 100 together.

[0056] The second circuit board 320 is a driving circuit board (X-board) and is mainly used for receiving a data signal and a control signal provided by the first circuit board 310 and transmitting the data signal and the control signal to a plurality of data driving chips (data driving circuit). In this embodiment, the first circuit board 310 includes a memory (not shown in the figure), the first circuit board 310 is connected to the display panel 10 through a chip on flex (COF), and the data driving chip is arranged on the COF. The data driving chip is connected to the pixel unit P (shown in FIG. 3) through a data line (shown in FIG. 3) to transmit the data signal to the pixel unit P for image display.

[0057] The display panel 10 is also provided with a scan driving circuit 13 corresponding to the display area 10a, and the scan driving circuit 13 is connected to the timing control circuit 11 through a corresponding signal line.

[0058] The display panel 10 is also provided with a timing control circuit 11 (shown in FIG. 3), a data driving circuit 12 (shown in FIG. 3), a scan driving circuit 13 (shown in FIG. 3), a light-emitting driving circuit 14 (shown in FIG. 3) and other functional circuits corresponding to the non-display area 10b outside the display area 10a.

[0059] Referring to FIG. 3, FIG. 3 is a schematic diagram of a planar layout structure of the display panel shown in FIG. 2.

[0060] The display area 10a of the display panel 10 includes a plurality of pixel units P arranged in an m*n matrix, n data lines D1-Dn extending along a second direction F2, m scan lines G1-Gm extending along a first direction F1, m compensation scan lines Gc1-Gcm, m light-emitting lines E1-Em, m compensation lines Dc1-Dcm and m reset scan lines Rg1-Rgm, m reset lines Rv1-Rvm, m and n are natural numbers greater than 1. The first direction F1 and the second direction F2 are perpendicular to each other. The pixel unit P is located at the intersection position of the scan line G1-Gm and the data line D1-Dn.

[0061] The display panel 10 is provided with a scan driving circuit 13 in the non-display area, and the timing control circuit 11, the data driving circuit 12, the light emitting driving circuit 14, the compensation circuit 15, the reset circuit 16 and the power supply circuit 17 are correspondingly provided in the first circuit board 310 and the second circuit board 320.

[0062] The timing control circuit 11 receives the image signal representing the image information from the external signal source, obtains the scan clock signal CK, the light emitting clock signal ECK, the horizontal synchronization signal and the vertical synchronization signal for synchronization, and outputs the control signals for the scan signal and the data signal of the scan driving circuit 13 and the data driving circuit 12.

[0063] The data driving circuit 12 is used for storing, amplifying and digital-to-analog converting the data signal received from the timing control circuit 11 and then outputting to the pixel unit P of the display area 10a.

[0064] The scan driving circuit 13 is used for outputting the corresponding scan signal to the pixel unit P of the display area 10a according to the clock signal CK, and also outputting the corresponding compensation scan signal to the pixel unit P.

[0065] The light emitting driving circuit 14 is used for outputting the corresponding light emitting signal Et to the pixel unit P of the display area 10a according to the light emitting clock signal ECK.

[0066] In the embodiment, the scan driving circuit 13 and the light emitting driving circuit 14 can be synchronously formed in the same area of the display panel 10 through the same process, that is, the scan driving circuit 13 and the light emitting driving circuit 14 are integrated in the same preset area to form a scan driving circuit (not marked).

[0067] The compensation circuit 15 is used for providing the corresponding compensation signal to the pixel unit P according to the scan compensation signal.

[0068] The reset circuit 16 is used for providing the reset signal to all the pixel units P in the blanking time between any two adjacent image display times of the display panel 10, so as to eliminate the residual charge in each pixel unit P in the previous image display period.

[0069] The power supply circuit 17 is used for providing the driving power supply for the working circuits in the display panel 10, for example, the power supply circuit 17 provides the high potential voltage VGH and the low potential voltage VGL for the scan driving circuit, provides the high potential voltage EVGH and the low potential voltage EVGL for the light emitting driving circuit 14, and provides the data power supply VDD for the data driving circuit 12.

[0070] Specifically, n data lines D1~Dn are connected to the data driving circuit 12 for receiving data signals Data provided by the data driving circuit 12 in the form of gray scale values.

[0071] m scan lines G1~Gn are connected to the scan driving circuit 13 for receiving scan signals Gs1~Gsn from the scan driving circuit 13. m compensation scan lines Gc1~Gcm are connected to the scan driving circuit 13 for receiving compensation scan signals Gr1~Grm from the scan driving circuit 13. m light emitting lines E1~Em are connected to the light emitting driving circuit 14 for receiving light emitting signals Et1~Etm from the light emitting driving circuit 14. m compensation lines Dc1~Dcm are connected to the compensation circuit 15 for receiving compensation signals from the compensation circuit 15. m reset scan lines Rg1~Rgm are connected to the scan driving circuit 13 for receiving reset scan signals Rs (Rs1~Rsm) from the scan driving circuit 13. m reset lines Rv1~Rvm are connected to the reset circuit 16 for receiving reset signals INI from the reset circuit 16. Each frame image display period includes a reset period H1, a compensation period H2, a data loading period H3 and a light emitting period H4 in time sequence.

[0072] In the reset period H1, the scan driving circuit 13 outputs reset scan signals Rs1~Rsm through the reset scan lines Rg1~Rgm and loads the reset signals INI into the pixel units P, so as to reset each pixel unit P to eliminate the residual charges in the previous frame image display period.

[0073] In the compensation period H2, the scan driving circuit 13 outputs compensation scan signals Gr1~Grm through the compensation scan lines Gc1~Gcm, and the compensation circuit 15 outputs compensation signals through the compensation lines Dc1~Dcm to the pixel units P, so as to compensate the data signals of the pixel units P to eliminate the situation that the data signals of each element in each pixel unit P cannot be uniformly and accurately displayed due to aging, process difference or working characteristics.

[0074] In the data loading period H3, the data voltages of the gray scale values in the corresponding data signals provided by the data lines D1~Dn are received in a predetermined time period under the control of the scan lines G1~Gm.

[0075] In the light emitting period H4, the light emitting driving circuit 14 outputs light emitting signals Et1~Etm through the light emitting lines E1~Em to the pixel units P, so as to provide driving power to each pixel unit P. The driving power cooperates with the data signals to provide corresponding driving currents to the pixel units, and accordingly drives the light emitting elements to emit light with corresponding brightness, so as to achieve image display by emitting light with corresponding brightness according to the data signals.

[0076] Please refer to FIG. 4-FIG. 5, FIG. 4 is a layout structure diagram of any one pixel unit P as shown in FIG. 3, and FIG. 5 is a specific circuit structure diagram of any one sub-pixel as shown in FIG. 3. As shown in FIG. 4, the pixel unit P includes three sub-pixels, which can be a red sub-pixel R emitting red light, a green sub-pixel G emitting green light, and a blue sub-pixel B emitting blue light.

[0077] As shown in FIG. 5, for any one sub-pixel, it includes a control switch tube M1, a driving switch tube M2, a light emitting element L, a first energy storage element C1, and a second energy storage element C2.

[0078] The driving switch tube M2 is connected to the control switch tube M1 through a first node N1, and is also connected to a first power supply end VDD through a second node N2 and to the light emitting element L through a third node N3. The light emitting element L is connected to the third node N3 and a second power supply end VSS. The first energy storage element C1 is connected to the first node N1 and the third node N3. The second energy storage element C2 is connected to the third node N3 and the second power supply VSS.

[0079] The control switch tube M1 is used to receive a scanning signal Gsi and a data signal Data during a data writing period of a frame image display period, the scanning signal Gsi is used to control the control switch tube M1 to transmit the received data signal Data to the first energy storage element C1 and the second energy storage element C2, and the data signal Data is used to control the driving switch tube M2 to cooperate with a driving power supply output provided by the first power supply end VDD to provide a corresponding driving current to the light emitting element L during a light emitting period of a frame image display period, so as to drive the light emitting element L to emit light to display an image.

[0080] The pixel unit P further includes a compensation switch tube M3, which is connected to a compensation scanning line Gci and a compensation line Dci, and is also connected to the first node N1. The compensation switch tube M3 is used to transmit a compensation signal to the first node N1 when a compensation scanning signal Gri is received during a compensation period.

[0081] The pixel unit P further includes a light emitting switch tube M4, which is connected to the second node N2 and the first power supply end VDD. The light emitting switch M4 is used to transmit a driving power supply to the driving switch tube M2 when a light emitting signal Et is received during a light emitting period.

[0082] The pixel unit P further comprises a reset switch transistor M5 connected to the reset scan line Rgi, the reset line Rvi and the second node N2. The reset switch transistor M5 is configured to transmit a reset voltage to the second node N2 when receiving the reset signal INI from the reset line Rvi under the control of the reset scan signal Rsi provided by the reset scan line Rgi during the reset period, and the reset voltage is transmitted to the third node N3 through the drive switch transistor M2 to reset the light emitting element L.

[0083] In the embodiment, the three sub-pixels in one pixel unit P share the same light emitting switch transistor M4, and meanwhile, the multiple pixel units P in the same row share the same reset switch M5.

[0084] In the embodiment, the light emitting element L in the pixel unit P is an organic light-emitting diode (OLED).

[0085] In the embodiment, the control switch transistor M1, the drive switch transistor M2, the compensation switch transistor M3, the light emitting switch transistor M4 and the reset switch transistor M5 are N-type thin film transistors. Of course, in other embodiments of the present application, the control switch transistor M1, the drive switch transistor M2, the compensation switch transistor M3, the light emitting switch transistor M4 and the reset switch transistor M5 can also be P-type thin film transistors.

[0086] In the embodiment, the first energy storage element C1 and the second energy storage element C2 are energy storage capacitors.

[0087] More specifically, the gate of the control switch transistor M1 is connected to the scan line Gi as a control terminal to receive the scan signal Gsi, and the control switch transistor M1 is turned on or turned off under the control of the scan signal Gsi. Meanwhile, the source and the drain of the control switch transistor M1 are connected to the data line Dj and the first node N1 respectively as two conductive terminals, so that the data signal Data is transmitted to the first node N1 through the source and the drain of the control switch transistor M1 when the control switch transistor M1 is turned on. In the embodiment, the source of the control switch transistor M1 is connected to the data line Dj, and the drain of the control switch transistor M1 is connected to the first node N1.

[0088] The gate of the driving switch tube M2 is connected to the first node N1 as a control terminal to receive the data signal Data through the first node N1 and to be turned on or turned off under the voltage control of the first node N1. Meanwhile, the source and the drain of the driving switch tube M2 are connected to the second node N2 and the third node N3 as two conductive terminals, respectively, wherein the second node N2 is connected to the first power terminal VDD through the light-emitting switch tube M4. In this embodiment, the drain of the driving switch tube M2 is connected to the second node N2, and the source of the driving switch tube M2 is connected to the third node N3. When the driving switch tube M2 is turned on, the driving power provided by the first power terminal VDD forms a driving current through the driving switch tube M2 to the light-emitting element L under the voltage control of the first node, so as to drive the light-emitting element L to correspondingly emit light. Of course, in other embodiments, the source and the drain of the driving switch tube M2 can be connected in a reciprocal position, that is, the source of the driving switch tube M2 is connected to the second node N2, and the drain of the driving switch tube M2 is connected to the third node N3.

[0089] The gate of the compensation switch tube M3 is connected to the compensation scan line Gci as a control terminal to receive the compensation scan signal Gri from the compensation scan line Gci, and the compensation switch tube M3 is turned on or turned off under the control of the compensation scan signal Gri. Meanwhile, the source and the drain of the compensation switch tube M3 are connected to the compensation line Dci and the first node N1 as conductive terminals, respectively. In this embodiment, the source of the compensation switch tube M3 is connected to the compensation line Dci, and the drain of the compensation switch tube M3 is connected to the first node N1. When the compensation switch tube M3 is turned on, the compensation signal is transmitted to the first node N1 through the source and the drain of the compensation switch tube M3. Of course, in other embodiments, the source and the drain of the compensation switch tube M3 can be connected in a reciprocal position, that is, the drain of the compensation switch tube M3 is connected to the compensation line Dci, and the source of the compensation switch tube M3 is connected to the first node N1.

[0090] The gate of the reset switch tube M5 is connected to the reset scan line Rgi as a control terminal and is turned on or turned off under the control of the reset scan signal Rsi provided by the reset scan line Rgi. Meanwhile, the source and the drain of the reset switch tube M5 are connected to the reset line Rvi and the second node N2 as conductive terminals, respectively, so as to transmit the reset voltage provided by the reset line Rvi to the second node N2 through the reset switch tube M5 when the reset switch tube M5 is turned on. In this embodiment, the source of the reset switch tube M5 is connected to the reset line Rvi, and the drain of the reset switch tube M5 is connected to the second node N2. Of course, in other embodiments, the source and the drain of the reset switch tube M5 can be connected in a reciprocal position, that is, the drain of the reset switch tube M5 is connected to the reset line Rvi, and the source of the reset switch tube M5 is connected to the second node N2.

[0091] The gate of the light-emitting switch tube M4 is connected to the light-emitting line Ei as a control terminal, and the light-emitting switch tube M4 is turned on or turned off under the control of the light-emitting signal Esi provided by the light-emitting line Ei. Meanwhile, the source and the drain of the light-emitting switch tube M4 are connected to the first power supply terminal VDD and the second node N2 as conductive terminals, and when the light-emitting switch tube M4 is turned on, the driving power provided by the first power supply terminal VDD is provided to the second node N2 through the light-emitting switch tube M4 and then transmitted to the driving switch tube M2 to provide the driving power for the driving switch tube M2.

[0092] The first energy storage element C1 includes a first energy storage connection terminal C11 and a second energy storage connection terminal C12, and the first energy storage connection terminal C11 is connected to the first node N1, and the second energy storage connection terminal C12 is connected to the third node N3. The second energy storage element C2 includes a third energy storage connection terminal C23 and a fourth energy storage connection terminal C24, and the third energy storage connection terminal C23 is connected to the third node N3, and the fourth energy storage connection terminal C24 is connected to the second power supply terminal VSS. The first energy storage element C1 and the second energy storage element C2 cooperate to accurately maintain the voltage of the first node N1 or the third node N3 when the voltage is loaded.

[0093] Please refer to FIG. 6, which is a working timing diagram of the pixel unit as shown in FIG. 5. The working process of the pixel unit P will be described in detail in combination with FIG. 5 and FIG. 6.

[0094] It should be noted that for the display panel 10 as shown in FIG. 2-3, any one frame image display period Frame includes f virtual scanning periods and m continuous scanning periods, for example, the rth frame image display period includes f virtual scanning periods and m continuous scanning periods in time, and the f virtual scanning periods are used to sequentially load part of the control signals to the f rows of pixel units before the scanning period, so as to reset and compensate before the scanning signal is formally loaded, or in other words, the f virtual scanning periods are used to sequentially load part of the control signals to the pixel units corresponding to the 1st to fth scanning lines arranged in sequence before the scanning period. In this embodiment, the f virtual scanning periods are used to load the reset scanning signal and the compensation scanning signal as control signals to the f rows of pixel units. The m continuous scanning periods correspond to the m scanning lines G1-Gm (m rows of pixel units P) in a one-to-one manner in sequence, and each scanning period can be used for the working process and timing stage of resetting, data compensation, data writing and light-emitting for the row of pixel units connected to the same scanning line. For example, in any one scanning period, for example, in the ith scanning period, it includes the reset period H1, the compensation period H2, the data loading period H3 and the light-emitting period H4 in time sequence. Wherein, i is a positive integer greater than or equal to 1 and less than or equal to m.

[0095] In the reset period H1, the reset scan line Rgi outputs a reset scan signal Rsi, which in this embodiment is a high-level pulse signal lasting a first preset time length, which in this embodiment is one unit time length (1H). The reset switch tube M5 is turned on under the control of the reset scan signal Rsi, and the reset signal INI provided by the reset line Rvi is transmitted to the second node N2 through the reset switch tube M5. Since the first node N1 still maintains the voltage of the previous frame (the (n-1)th frame) due to the energy storage effect of the first energy storage element C1 and the second energy storage element C2, the driving switch tube M2 is turned on since the voltage is higher than the reset voltage of the reset signal INI, and the reset voltage is written to the third node N3, so that the third node N3 is reset, that is, the light-emitting element L is reset, wherein the voltage of the third node N3 is the reset voltage Vint.

[0096] In the compensation period H2, the compensation scan line Gci outputs a compensation scan signal Gri, which in this embodiment is also a high-level pulse signal lasting a second preset time length, which in this embodiment is five unit time lengths 5H. The compensation switch tube M3 is turned on under the control of the compensation scan signal Gri, and the compensation signal provided by the compensation line Dci is transmitted to the first node N1 through the compensation switch tube M3, wherein the first node N1 loads the voltage of the written compensation signal, and the potential of the compensation signal can be the compensation voltage Vref. At the same time, the light-emitting switch tube M4 receives the light-emitting signal Ei provided by the light-emitting driving circuit 14 from the light-emitting line Ei and is turned on under the control of the light-emitting signal Ei, so as to provide the driving voltage provided by the first power supply end VDD to the second node N2. In this embodiment, the light-emitting signal Ei is also a high-level pulse signal lasting five unit time lengths (5H).

[0097] The first node N1 loads the compensation voltage Vref of the compensation signal to control the driving switch tube M2 to be turned on, and the driving voltage of the second node N2 charges the third node N3 through the driving switch tube M2. When the voltage of the third node N3 is charged to Vref-Vth, the driving switch tube M2 is turned off. Wherein, Vth is the threshold voltage of the driving switch tube M2. Thus, in the compensation period H2, the voltage of the third node N3 is compensated and charged to Vref-Vth.

[0098] It can be understood that in the compensation period H2, the reset scan line Rgi stops outputting the reset scan signal Rsi.

[0099] In the data loading period H3, the scan line Gi outputs the scan signal Gsi, and the control switch M1 is turned on under the control of the scan signal Gsi, so that the data voltage of the data signal Data is loaded to the first node N1 through the control switch M1 from the data line Dj. In the embodiment, the scan signal Gsi is a high-level pulse signal lasting a first preset time length, and the first preset time length is one unit time length 1H. Under the cooperation of the first energy storage element C1 and the second energy storage element C2, the voltage of the first node N1 is coupled to the voltage of the third node N3, and the voltage of the third node N3 is coupled as Vref-Vth+α(Vdata-Vref), so that the voltage VGS of the driving switch M2 gate and source is (1-α)(Vdata-Vref)+Vth, where α=C1 / (C1+C2), Vdata is the voltage of the data signal Data, and C1 and C2 are the capacitance values of the first energy storage element C1 and the second energy storage element C2 as capacitors.

[0100] It can be understood that in the data loading period H3, the compensation scan line Gci stops outputting the compensation scan signal Gri, and at the same time, the light-emitting line Ei stops outputting the light-emitting signal.

[0101] In the light-emitting period H4, the light-emitting switch M4 again receives the light-emitting signal Ei provided by the light-emitting driving circuit 14 from the light-emitting line Ei and is turned on under the control of the light-emitting signal Ei, so as to provide the driving voltage provided by the first power supply end VDD to the second node N2. In the embodiment, the light-emitting signal Ei is a high-level pulse signal lasting one unit time length (1H).

[0102] The driving switch M2 is turned on under the control of the voltage loaded to the first node N1, and the driving power cooperates with the voltage of the first node N1 and the third node N3 to provide a corresponding driving current Ids through the driving switch M2, and the driving current Ids is transmitted to the light-emitting element L through the third node N3, so as to drive the light-emitting element L to emit light and correspondingly display the image of the data signal Data.

[0103] In the embodiment, the compensation scan signal and the scan signal are both output by the scan driving circuit 13, but the time lengths of the two are not the same.

[0104] Please refer to FIG. 7, which is a connection diagram of the scan driving circuit 13 and the light-emitting driving circuit 14 as shown in FIG. 3. As shown in FIG. 7, the scan driving circuit 13 includes a plurality of cascaded scan driving units (GOA units) 130, six virtual GOA units 131, eight clock signals CKq (q=1, 2, …8), and a start signal STV. For convenience of description, the scan driving unit in the following is denoted as a GOA unit, and the virtual scan driving unit is denoted as a virtual GOA unit.

[0105] The plurality of cascaded GOA units 130 are connected one-to-one with the scan lines and output corresponding plurality of scan driving signals. In this embodiment, when the number of corresponding scan lines m is 2160, the number of GOA units 130 is also 2160, and the plurality of scan signals can be represented as Gs1-Gs2160. The scan signals G1-G2160 are used to drive the scan lines of the corresponding row of pixel units in the display array substrate. In other embodiments of the present application, the number of scan lines can be set according to the actual resolution, and is not limited thereto.

[0106] In this embodiment, the eight clock signals CKq (q = 1, 2, …, 8) can be defined as clock signals CK1-CK8, which are periodically output respectively. The period of each clock signal is 8 unit time 8H. The period of the overall output of the eight clock signals is also 8 unit time 8H.

[0107] The clock signals CK1-CK8 are arranged in order according to the output timing. Each clock signal CK is a pulse signal lasting one unit time 1H, and the interval between adjacent two clock signals is one unit time 1H. For example, the clock signal CK1 is separated from the clock signal CK2 by one unit time 1H, the clock signal CK3 is separated from the clock signal CK2 by one unit time 1H, and so on. The clock signal CK8 is separated from the clock signal CK7 by one unit time 1H, or in other words, the time point of outputting the clock signal CK1 is separated from the time point of outputting the clock signal CK2 by one unit time 1H, the time point of outputting the clock signal CK3 is separated from the time point of outputting the clock signal CK2 by one unit time 1H, and so on. The time point of outputting the clock signal CK8 is separated from the time point of outputting the clock signal CK7 by one unit time 1H.

[0108] Each GOA unit 130 includes an enable trigger end En, a first clock signal input end CI1, a second clock signal input end CI2, a first signal output end SO1, and a second signal output end SO2. The enable trigger end En is used to receive an enable trigger signal STV, so that the GOA unit 130 starts to work. It should be noted that for the plurality of cascaded GOA units 130, the first-stage GOA unit 130 receives the enable trigger signal STV provided by the timing control circuit 11, the second-stage GOA unit 130 receives the scan signal Gsi output by the first signal output end SO1 of the first-stage GOA unit 130 as the enable trigger signal, and the enable trigger end En of the other cascaded GOA units 130 receives the enable trigger signal in the same way. This embodiment will not be described again.

[0109] The first clock signal input terminal CI1 and the second clock signal input terminal CI2 are configured to receive two clock signals with a preset interval, and the GOA unit 130 outputs signals from the first signal output terminal SO1 and the second signal output terminal SO2 according to the two clock signals. In this embodiment, the first signal output terminal SO1 outputs a scan signal Gs and a reset scan signal Rs, and the second signal output terminal SO2 outputs a compensation scan signal Gr. Specifically, the GOA unit 130 outputs the scan signal Gs from the first signal output terminal SO1 and the compensation scan signal Gr from the second signal output terminal SO2 according to the clock signal CKe received by the first clock signal input terminal CI1, and stops outputting the compensation scan signal Gr from the second signal output terminal SO2 when the clock signal CKe+a is received by the second clock signal input terminal CI2.

[0110] In this embodiment, the clock signals received by the first clock signal input terminal CI1 and the second clock signal input terminal CI2 have an interval of 5 units of time, that is, a is 5 in this embodiment, the first clock signal input terminal CI1 receives the clock signal CKe, and the second clock signal input terminal CI2 receives the clock signal CK(e+5). For example, the first clock signal input terminal CI1 receives the clock signal CK1, and the second clock signal input terminal CI2 receives the clock signal CK6; the first clock signal input terminal CI1 receives the clock signal CK2, and the second clock signal input terminal CI2 receives the clock signal CK7; and so on; the first clock signal input terminal CI1 receives the clock signal CK8, and the second clock signal input terminal CI2 receives the clock signal CK5.

[0111] The GOA unit 130 outputs the scan signal Gs from the first signal output terminal SO1 according to the clock signal CKa received by the first clock signal input terminal CI1, and the scan signal Gs also serves as the reset scan signal Rs of the GOA unit 130 which is m levels away from the current GOA unit 130. Meanwhile, the GOA unit 130 outputs the compensation scan signal Gr from the second signal output terminal SO2 according to the clock signal CKe received by the first clock signal input terminal CI1. The GOA unit 130 stops outputting the compensation scan signal Gr from the second signal output terminal SO2 after receiving the clock signal CKe+a from the second clock signal input terminal CI2. It can be understood that when the first clock signal input terminal CI1 does not receive the clock signal CKe, the GOA unit 130 stops outputting the scan signal Gs and the reset scan signal Rs from the first signal output terminal SO1.

[0112] In the embodiment, the GOA units 130 are cascaded in sequence, wherein the cascaded GOA units 130 are specifically cascaded in that any GOA unit 130 is cascaded with the GOA unit of the adjacent one GOA unit, for example, the GOA unit 130 of the first stage is cascaded with the GOA unit 130 of the second stage, and the GOA unit 130 of the third stage is cascaded with the GOA unit 130 of the second stage.

[0113] The circuit structure and working mode of the virtual GOA unit 131 are the same as those of the GOA unit 130, and the plurality of virtual GOA units 131 are also cascaded in sequence with the adjacent virtual GOA units 131, and the last-stage virtual GOA unit 131 is cascaded with the GOA unit 130 of the first stage. In the embodiment, the number of the virtual GOA units 131 corresponds to f virtual scanning periods, wherein f is 6.

[0114] Specifically, the enable trigger end En of the virtual GOA unit 131 of the first stage receives the trigger signal STV output from the self-timing driving circuit, at the same time, the virtual GOA unit 131 of the first stage outputs the stage transmission signal to the virtual GOA unit 131 of the second stage, and the last-stage virtual GOA unit 131 outputs the stage transmission signal to the enable trigger end En of the GOA unit 130 of the first stage, and the enable trigger end En of the GOA unit 130 of the second stage receives the stage transmission signal output from the GOA unit 130 of the first stage.

[0115] In the embodiment, the circuit structure and working principle of the virtual GOA unit 131 are the same as those of the GOA unit 130, and the difference is only that the second signal output end SO2 of the virtual GOA unit 131 is not directly connected with the scanning line, the first signal output end SO1 outputs the reset scanning signal Rs, and the compensation scanning signal Gr is output from the second signal output end SO2. Considering the timing requirement, in the embodiment, the six virtual GOA units 131 are used to output six groups of reset scanning signals Rs and compensation scanning signals Gr to the pixel units of the 1st to 6th rows, and the GOA units 130 of the last m-6 to m stages in the cascade do not need to output the corresponding reset scanning signals Rs and compensation scanning signals Gr to the pixel units of the m-6th to mth rows.

[0116] The corresponding relationship between the virtual GOA unit 131 and the GOA unit 130 and the f virtual scanning periods and the m scanning periods is that the f virtual scanning periods can be defined in sequence as the 1st to fth virtual scanning periods, the m scanning periods can be defined in sequence as the 1st to mth scanning periods, and the fth virtual scanning period is continuous in time with the 1st scanning period; the virtual GOA unit 131 corresponds to the f continuous virtual scanning periods respectively, and the 1st to fth virtual scanning driving units are used to output the reset scanning signal and the compensation scanning signal in the reset period and the compensation period of the 1st to fth virtual scanning periods in sequence.

[0117] Correspondingly, the light emitting driving circuit 14 comprises a plurality of light emitting driving units 140, for the convenience of description and understanding, the light emitting driving unit 140 in the embodiment can be represented as EOA unit 140. That is, the light emitting driving circuit 14 comprises a plurality of EOA units 140.

[0118] The EOA unit 140 comprises a light emitting clock signal input end EKI, a first light emitting input end EI1, a second light emitting input end EI2 and a light emitting output end EO. The light emitting clock signal input end EKI is used for receiving a light emitting clock signal EK. The first light emitting input end EI1 and the second light emitting input end EI2 are connected to the first signal output ends SO1 of two GOA units 130 spaced by a preset level to respectively receive two scanning signals Gs. The EOA unit 140 outputs a light emitting signal from the light emitting output end EO to the light emitting line according to the two scanning signals Gs. In the embodiment, the two scanning signals Gs are spaced by b unit time lengths. It can be understood that b is the same as the number f of the virtual GOA unit 131, for example, b can be 6, that is, the two scanning signals Gs are spaced by 6 unit time lengths 6H, that is, the first light emitting input end EI1 and the second light emitting input end EI2 are respectively connected to the first signal output ends SO1 of two GOA units 130 spaced by six levels. For example, the first signal output ends SO1 of the GOA unit 130 at the i-th level and the GOA unit 130 at the i-6th level.

[0119] In the embodiment, for the EOA unit 140 at the i-th level, the first light emitting input end EI1 is connected to the first signal output end SO1 of the GOA unit 130 at the i-6th level, and the second light emitting input end EI2 is connected to the first signal output end SO1 of the GOA unit 130 at the i-th level.

[0120] In the embodiment, in order to reduce the load of the light emitting clock signal, two light emitting clock signals EK are included, and two light emitting clock signal lines are respectively connected to different EOA units 140. The two light emitting clock signals EK are also periodic pulse signals, and the pulse width of each pulse signal is 1 unit time length 8H. The phase of the light emitting clock signal EK is opposite to that of the clock signal CK, but the period, frequency and duty cycle are the same.

[0121] More specifically, please refer to FIG. 8, which is a circuit structure schematic diagram of any one scanning driving unit as shown in FIG. 7. As shown in FIG. 8, the GOA unit 130 comprises a first pull-up module 31, a first pull-down module 32, a second pull-up module 33, a second pull-down module 34, a first clock signal output module 35, a second clock signal output module 36, a first reset scanning output module 37 and a second reset scanning output module 38.

[0122] The first pull-up module 31 is connected with the enable trigger end En, the high-voltage power supply end VGH and the first control node PU, and is used for loading the high potential voltage provided by the high-voltage power supply end VGH to the first control node PU under the control of the enable trigger signal provided by the enable trigger end En, so as to control the voltage of the first control node PU to be at a high potential.

[0123] The second pull-down module 34 is connected with the first control node PU, the low-voltage power supply end VSS and the second control node PD, and is used for connecting the low-voltage power supply end VSS to the second control node PD when the voltage of the first control node PU is at a high potential, so as to pull down the potential of the second control node PD, that is, to make the potential of the second control node PD at a low potential.

[0124] The first pull-down module 32 is connected with the first control node PU, the second control node PD and the second clock signal input end CI2, and is used for pulling down the potential of the first control node PU under the control of the clock signal CKe+a provided by the second clock signal input end CI2 or when the voltage of the second control node PD is at a high potential, that is, to make the potential of the first control node PU at a low potential.

[0125] The second pull-up module 33 is connected with the high-voltage power supply end VGH and the second control node PD, and is used for loading the high potential voltage provided by the high-voltage power supply end VGH to the second control node PD when the second control node PD is not loaded with a low potential, so as to pull up the potential of the second control node PD.

[0126] The first clock signal output module 35 is connected with the first control node PU, the first clock signal input end CI1 and the first signal output end SO1, and is used for outputting the clock signal CKa as the scan signal Gs and the reset scan signal Rs when the voltage of the first control node PU is at a high potential, and simultaneously maintaining the voltage of the first control node PU at a high potential within a preset time period.

[0127] The second clock signal output module 36 is connected with the second control node PD, the low-voltage power supply end VSS and the first signal output end SO1, and is used for transmitting the low potential voltage to the first signal output end SO1 when the voltage of the second control node PD is at a high potential, so as to stop outputting the scan signal Gs and the reset scan signal Rs.

[0128] The first reset scan output module 37 is connected with the first control node PU, the first clock signal input end CI1, the high-voltage power supply end VGH and the second signal output end SO2, and is used for outputting the voltage potential provided by the high-voltage power supply end VGH as the compensation scan signal Gr within a preset time period under the control of the clock signal when the voltage of the first control node PU is at a high potential.

[0129] The second reset scan output module 38 is connected with the second control node PD, the low-voltage power supply end VSS and the second signal output end SO2, and is used for transmitting the low-voltage to the second signal output end SO2 when the voltage of the second control node PD is high, so as to stop outputting the compensation scan signal Gr.

[0130] More specifically, the first pull-up module 31 includes a first switch tube T1, the first switch tube T1 includes a first control end T10, a first conduction end T11 and a second conduction end T12, the first control end T10 is connected with the enable trigger end En, the first conduction end T11 is connected with the high-voltage power supply end VGH, and the second conduction end T12 is connected with the first control node PU. Wherein, the first switch tube T1 is used for conducting under the control of the enable trigger signal, and loading the high-voltage provided by the high-voltage power supply end VGH to the first control node PU. Correspondingly, the first switch tube T1 is in the off state when not receiving the enable trigger signal, so as to stop loading the high-voltage provided by the high-voltage power supply end VGH to the first control node PU.

[0131] In the embodiment, the first switch tube T1 is a N-type thin film transistor (TFT), and the corresponding enable trigger signal is a high level. The gate of the first switch tube T1 can be directly connected with the first control end T10 as the first control end T10. The drain of the first switch tube T1 can be directly connected with the second conduction end T12 as the second conduction end T12. The source of the first switch tube T1 can be directly connected with the first conduction end T11 as the first conduction end T11. In other embodiments, the first switch tube T1 can also be a P-type thin film transistor, and the corresponding enable trigger signal is a low level.

[0132] The first pull-down module 32 includes a seventh switch tube T7 and an eighth switch tube T8.

[0133] The seventh switch tube T7 includes a seventh control end T70, a seventh pull-up conduction end T71 and a seventh pull-down conduction end T72. The seventh control end T70 is connected with the second clock signal input end CI2, the seventh pull-up conduction end T71 is connected with the first control node PU, and the seventh pull-down conduction end T72 is connected with the low-voltage power supply end VSS. The seventh switch tube T7 is turned on under the control of the clock signal CKe+a received by the second clock signal input end CI2, so as to load the low-voltage of the low-voltage power supply end VSS to the first control node PU. Correspondingly, the seventh switch tube T7 is in the off state when not receiving the clock signal CKe+a, so as to stop loading the low-voltage provided by the low-voltage power supply end VSS to the first control node PU.

[0134] In this embodiment, the seventh switch tube T7 is an N-type thin film transistor (TFT), so the corresponding clock signal CKe+a is high level on, the gate of which can be used as the seventh control end T70, or the gate is directly connected to the seventh control end T70; the drain of the seventh switch tube T7 can be used as the seventh pull-up conductive end T71, or the drain is directly connected to the seventh pull-up conductive end T71; the source of the seventh switch tube T7 can be used as the seventh pull-down conductive end T72, or the source is directly connected to the seventh pull-down conductive end T72. In other embodiments, the seventh switch tube T7 can also be a P-type thin film transistor, so the corresponding clock signal CKa+b is low level on.

[0135] The eighth switch tube T8 includes an eighth control end T80, an eighth pull-up conductive end T81 and an eighth pull-down conductive end T82, wherein the eighth control end T80 is connected to the second control node PD, the eighth pull-up conductive end T81 is connected to the first control node PU, and the eighth pull-down conductive end T82 is connected to the low-voltage power supply end VSS. The eighth switch tube T8 is turned on under the high-voltage control of the second control node PD, so as to load the low-voltage of the low-voltage power supply end VSS to the first control node PU. Correspondingly, the eighth switch tube T8 is in an off state when the second control node PD is low voltage, so as to stop loading the low-voltage provided by the low-voltage power supply end VSS to the first control node PU.

[0136] In this embodiment, the eighth switch tube T8 is an N-type thin film transistor (TFT), so the corresponding second control node PD is high level on, the gate of which can be used as the eighth control end T80, or the gate is directly connected to the eighth control end T80; the drain of the eighth switch tube T8 can be used as the eighth pull-up conductive end T81, or the drain is directly connected to the eighth pull-up conductive end T81; the source of the eighth switch tube T8 can be used as the eighth pull-down conductive end T82, or the source is directly connected to the eighth pull-down conductive end T82. In other embodiments, the eighth switch tube T8 can also be a P-type thin film transistor, so the voltage of the corresponding second control node PD is low voltage on.

[0137] The second pull-up module 33 includes a second switch tube T2, and the second switch tube T2 includes a second control end T20, a second pull-up conduction end T21 and a second pull-down conduction end T22. The second control end T20 and the second pull-up conduction end T21 are both connected to the high-voltage power supply end VGH, and the second pull-down conduction end T22 is connected to the second control node PD. Since the second control end T20 and the second pull-up conduction end T21 are both connected to the high-voltage power supply end VGH, the second switch tube T2 forms a diode connection, and the second switch tube T2 can be directly turned on under the control of the high-voltage power supply end VGH, so that the high potential voltage of the high-voltage power supply end VDD is loaded to the second control node PU. It should be noted that when the second control node PD is not connected to the low potential by other switch tubes, the second switch tube T2 will load the high potential voltage provided by the high-voltage power supply end VDD to the second control node PD only when it is turned on. If the second control node PD has been connected to the low-voltage power supply end VSS by other switch tubes or loaded with a low potential voltage, the second switch tube T2 will not load the high potential voltage provided by the high-voltage power supply end VDD to the second control node PD.

[0138] In the embodiment, the second switch tube T2 is an N-type thin film transistor, the gate electrode of which can be used as the second control end T20, or the gate electrode is directly connected to the second control end T20; the drain electrode of the second switch tube T2 can be used as the second pull-up conduction end T21, or the drain electrode is directly connected to the second pull-up conduction end T21; and the source electrode of the second switch tube T2 can be used as the second pull-down conduction end T22, or the source electrode is directly connected to the second pull-down conduction end T22.

[0139] The second pull-down module 34 includes a sixth switch tube T6, and the sixth switch tube T6 includes a sixth control end T60, a sixth pull-up conduction end T61 and a sixth pull-down conduction end T62. The sixth control end T60 is connected to the first control node PU, the sixth pull-up conduction end T61 is connected to the second control node PD, and the sixth pull-down conduction end T62 is connected to the low-voltage power supply end VSS. The sixth switch tube T6 is turned on under the control of the high potential voltage of the first control node PU, so as to provide the low potential voltage provided by the low-voltage power supply end VSS to the second control node PD, that is, to control the voltage of the second control node PD to be low. Correspondingly, the sixth switch tube T6 is in an off state when the first control node PU is at a low voltage, so as to stop loading the low potential voltage provided by the low-voltage power supply end VSS to the second control node PD.

[0140] In this embodiment, the sixth switch tube T6 is an N-type thin film transistor (TFT), so the corresponding first control node PU is turned on when it is high, and its gate can be used as the sixth control end T60, or its gate is directly connected to the sixth control end T60; the drain of the sixth switch tube T6 can be used as the sixth pull-up conductive end T61, or its drain is directly connected to the sixth pull-up conductive end T61; the source of the sixth switch tube T6 can be used as the sixth pull-down conductive end T62, or its source is directly connected to the sixth pull-down conductive end T62. In other embodiments, the sixth switch tube T6 can also be a P-type thin film transistor, so the corresponding first control node PD is turned on when the voltage is low.

[0141] The first clock signal output module 35 includes a third clock output switch tube T3a and an energy storage capacitor Cc. The third clock output switch tube T3a includes a third clock output control end T310, a first clock output conductive end T311, and a second clock output conductive end T312. The third clock output control end T310 is connected to the first control node PU, the first clock output conductive end T311 is connected to the first clock signal input end CI1, the second clock output conductive end T312 is connected to the first signal output end SO1, and the energy storage capacitor Cc is connected between the first control node PU and the first signal output end SO1. The energy storage capacitor Cc is used to maintain the voltage of the first control node PU at a high level, and the third clock output switch tube T3a is turned on under the control of the high voltage of the first control node PU, so that the clock signal CKa provided by the first clock signal input end CI1 is output as the scan signal Gs and the reset scan signal Rs from the first signal output end SO1. Correspondingly, it can be understood that when the third clock output switch tube T3a is turned on, if the first clock signal input end CI1 stops providing the clock signal CKa, the output of the scan signal Gs and the reset scan signal Rs from the first signal output end SO1 is stopped.

[0142] In this embodiment, the third clock output switch tube T3a is an N-type thin film transistor (TFT), so the corresponding first control node PU is turned on when it is high, and its gate can be used as the third clock output control end T310, or its gate is directly connected to the third clock output control end T310; the source of the third clock output switch tube T3a can be used as the first clock output conductive end T311, or its source is directly connected to the first clock output conductive end T311; the drain of the third clock output switch tube T3a can be used as the second clock output conductive end T312, or its drain is directly connected to the second clock output conductive end T312. In other embodiments, the third clock output switch tube T3a can also be a P-type thin film transistor, so the corresponding first control node PD is turned on when the voltage is low.

[0143] The second clock signal output module 36 comprises a fourth clock output switch tube T4a, which comprises a fourth clock output control end T410, a third clock output conductive end T413 and a fourth clock output conductive end T414. The fourth clock output control end T410 is connected to the second control node PD, the third clock output conductive end T413 is connected to the low-voltage power supply end VSS, and the fourth clock output conductive end T414 is connected to the first signal output end SO1. The fourth clock output switch tube T4a is turned on under the control of the high-potential voltage of the second control node PD, so as to provide the low-potential voltage provided by the low-voltage power supply segment VSS to the output first signal output end SO1, thereby ensuring that the first signal output end SO1 accurately stops outputting the scanning signal Gs and the reset scanning signal Rs. Correspondingly, when the second control node PD is at a low-potential voltage, the fourth clock output switch tube T4a is turned off, thereby stopping the low-potential voltage provided by the low-voltage conductive end VSS from being output from the first signal output end SO1.

[0144] In the embodiment, the fourth clock output switch tube T4a is an N-type thin film transistor, so that the corresponding second control node PD is turned on when it is at a high level, and the gate thereof can be used as the fourth clock output control end T410, or the gate thereof is directly connected to the fourth clock output control end T410; the source of the fourth clock output switch tube T4a can be used as the third clock output conductive end T413, or the source thereof is directly connected to the third clock output conductive end T413; and the drain of the fourth clock output switch tube T4a can be used as the fourth clock output conductive end T414, or the drain thereof is directly connected to the fourth clock output conductive end T414. In other embodiments, the fourth clock output switch tube T4a can also be a P-type thin film transistor, so that the corresponding second control node PD is turned on when it is at a low potential.

[0145] The first reset scanning output module 37 comprises a third compensation scanning output switch tube T3b, a fifth compensation scanning output switch tube T5a and a compensation capacitor Cm.

[0146] Specifically, the fifth compensation scan output switch tube T5a includes a fifth compensation scan output control end T510, a fifth compensation scan output conductive end T515, and a sixth compensation scan output conductive end T516. The fifth compensation scan output control end T510 is connected to the first clock signal input end CI1 through the compensation capacitor Cm, that is, the compensation capacitor Cm is connected between the first clock signal input end CI1 and the fifth compensation scan output control end T510 of the fifth compensation scan output switch tube T5a. The fifth compensation scan output conductive end T515 is connected to the first control node PU, and the sixth compensation scan output conductive end T516 is connected to the third control node PUB. The fifth compensation scan output switch tube T5a is turned on under the control of the clock signal CKa provided by the first clock signal input end CI1, so as to transmit and load the high potential voltage of the first control node PU to the third control node PUB, so that the voltage of the third control node PUB also corresponds to the high potential. In the embodiment, the width-length ratio (W / L) of the conductive channel in the fifth compensation scan output switch tube T5a is large, that is, the parasitic capacitance is large. After being turned on under the control of the clock signal CKa provided by the first clock signal input end CI1, the fifth compensation scan output switch tube T5a can maintain the turned-on state for a preset period of time, so as to continuously control the high potential voltage of the first control node PU to be transmitted and loaded to the third control node PUB for a preset period of time, so as to ensure that the voltage of the third control node PUB is at the high potential. In the embodiment, the length of the preset period of time is 5 unit lengths (5H). Of course, in other embodiments of the application, the preset period of time can be adjusted according to actual needs.

[0147] The third compensation scan output switch tube T3b includes a third compensation scan output control end T320, a first compensation scan output conductive end T321, and a second compensation scan output conductive end T322. The third compensation scan output control end T320 is connected to the third control node PUB, the first compensation scan output conductive end T321 is connected to the high-voltage power supply end VGH, and the second compensation scan output conductive end T322 is connected to the second signal output end SO2. The third compensation scan output switch tube T3b is turned on under the control of the high potential voltage provided by the third control node PUB, so as to transmit and load the high potential voltage provided by the high-voltage power supply end VGH to the second signal output end SO2, so as to output the compensation scan signal Gr.

[0148] In the embodiment, the fifth compensation scan output switch tube T5a and the third compensation scan output switch tube T3b are also N-type thin film transistors. In the fifth compensation scan output switch tube T5a, the clock signal CKa provided by the corresponding first clock signal input end CI1 is high when the clock signal CKa is turned on, the gate of the fifth compensation scan output switch tube T5a can be used as the fifth compensation scan output control end T510, or the gate of the fifth compensation scan output switch tube T5a is directly connected to the fifth compensation scan output control end T510; the source of the fifth compensation scan output switch tube T5a can be used as the fifth compensation scan output conductive end T515, or the source of the fifth compensation scan output switch tube T5a is directly connected to the fifth compensation scan output conductive end T515; the drain of the fifth compensation scan output switch tube T5a can be used as the sixth compensation scan output conductive end T516, or the drain of the fifth compensation scan output switch tube T5a is directly connected to the sixth compensation scan output conductive end T516. In the third compensation scan output switch tube T3b, the third control node PUB provides a high voltage when the third compensation scan output switch tube T3b is turned on, the gate of the third compensation scan output switch tube T3b can be used as the third compensation scan output control end T320, or the gate of the third compensation scan output switch tube T3b is directly connected to the third compensation scan output control end T320; the source of the third compensation scan output switch tube T3b can be used as the first compensation scan output conductive end T321, or the source of the third compensation scan output switch tube T3b is directly connected to the first compensation scan output conductive end T321; the drain of the third compensation scan output switch tube T3b can be used as the second compensation scan output conductive end T322, or the drain of the third compensation scan output switch tube T3b is directly connected to the second compensation scan output conductive end T322.

[0149] In other embodiments, the fifth compensation scan output switch tube T5a and the third compensation scan output switch tube T3b can also be P-type thin film transistors, and the clock signal CKa provided by the corresponding first clock signal input end CI1 and the voltage of the third control node PUB are low when the fifth compensation scan output switch tube T5a and the third compensation scan output switch tube T3b are turned on.

[0150] The second reset scan output module 38 includes a fourth compensation scan off switch tube T4b and a fifth compensation scan off switch tube T5b.

[0151] The fourth compensation scan off switch tube T4b includes a fourth compensation off control end T420, a first compensation scan off conductive end T421, and a second compensation scan off conductive end T422. The fourth compensation off control end T420 is connected to the second control node PD, the first compensation scan off conductive end T421 is connected to the low-voltage conductive end VSS, and the second compensation scan off conductive end T422 is connected to the second signal output end SO2. The fourth compensation scan off switch tube T4b is turned on under the high-potential voltage control of the second control node PD, so as to provide the low-potential voltage from the second signal output end SO2 by the low-voltage conductive end VSS, thereby ensuring that the second signal output end SO2 accurately stops outputting the compensation scan signal Gs. Correspondingly, when the second control node PD is at a low-potential voltage, the fourth compensation scan off switch tube T4b is turned off, thereby stopping the low-potential voltage from the second signal output end SO2 by the low-voltage conductive end VSS.

[0152] In the embodiment, the fourth compensation scan off switch tube T4b is an N-type thin film transistor (TFT), and the corresponding second control node PD is turned on when the voltage is at a high level. The gate of the fourth compensation scan off switch tube T4b can be used as the fourth compensation off control end T420, or the gate of the fourth compensation scan off switch tube T4b is directly connected to the fourth compensation off control end T420. The source of the fourth compensation scan off switch tube T4b can be used as the first compensation scan off conductive end T421, or the source of the fourth compensation scan off switch tube T4b is directly connected to the first compensation scan off conductive end T421. The drain of the fourth compensation scan off switch tube T4b can be used as the second compensation scan off conductive end T422, or the drain of the fourth compensation scan off switch tube T4b is directly connected to the second compensation scan off conductive end T422. In other embodiments, the fourth compensation scan off switch tube T4b can also be a P-type thin film transistor, and the corresponding second control node PD is turned on when the voltage is at a low level.

[0153] The fifth compensation scan off switch tube T5b includes a fifth compensation scan off control end T520, a third compensation scan output conductive end T523, and a fourth compensation scan off conductive end T524. The fifth compensation scan off control end T520 is connected to the second control node PD, the third compensation scan output conductive end T523 is connected to the first control node PU, and the fourth compensation scan off conductive end T524 is connected to the third control node PUB. The fifth compensation scan off switch tube T5b is turned on under the high-potential voltage control of the second control node PD, so as to transmit and load the low-potential voltage of the first control node PU to the third control node PUB, so that the voltage of the third control node PUB is also at a low level.

[0154] In this embodiment, the fifth compensation scan off switch tube T5b is an N-type thin film transistor. The fifth compensation scan off switch tube T5b is turned on when the high potential voltage provided by the second control node PD, the gate of the fifth compensation scan off switch tube T5b can be used as the fifth compensation scan off control end T520, or the gate of the fifth compensation scan off switch tube T5b is directly connected to the fifth compensation scan off control end T520; the source of the fifth compensation scan off switch tube T5b can be used as the third compensation scan output conductive end T523, or the source of the fifth compensation scan off switch tube T5b is directly connected to the third compensation scan output conductive end T523; the drain of the fifth compensation scan off switch tube T5b can be used as the fourth compensation scan off conductive end T524, or the drain of the fifth compensation scan off switch tube T5b is directly connected to the fourth compensation scan off conductive end T524. In other embodiments, the fifth compensation scan off switch tube T5b can also be a P-type thin film transistor, and the corresponding voltage of the second control node PD is low potential when turned on.

[0155] Please refer to FIG. 9, which is a timing diagram of the scan driving unit as shown in FIG. 8. In FIG. 9, STV / Gs(i-1) is a waveform diagram of the enable trigger signal provided by the enable signal end EN, CKe is a waveform diagram of the clock signal CKe loaded by the first clock signal input end CI1, CK(e+a) is a waveform diagram of the clock signal CKe+a loaded by the second clock signal input end CI2, PU is a voltage waveform diagram of the first control node PU, PUB is a voltage waveform diagram of the third control node PUB, PD is a voltage waveform diagram of the second control node PD, Si is a waveform diagram of the scan signal Gs and the reset scan signal Rs output by the first signal output end SO1, and R(n+m) is a waveform diagram of the compensation scan signal Gr output by the second signal output end SO2.

[0156] Now, the working process of the GOA unit 130 will be described in detail with reference to FIGS. 8-9.

[0157] In the enable trigger period EH, the enable trigger signal STV is output to the first control end T10 of the first switch tube T1, and the first switch tube T1 is turned on under the control of the enable trigger signal, so that the high potential voltage provided by the high voltage power supply end VGH is loaded to the first control node PU, and the voltage of the first control node PU is pulled up to a high potential.

[0158] Since the voltage of the first control node PU is high, the sixth switch tube T6 and the third clock output switch tube T3a are controlled to be turned on, the second control node PD is controlled to be low when the sixth switch tube T6 is turned on, and the first signal output end SO1 outputs the voltage of the first clock signal input end CI1 when the third clock output switch tube T3a is turned on. It can be understood that at this time, the first clock signal input end CI1 does not receive the clock signal CKa, and the first signal output end SO1 does not output the clock signal CKa.

[0159] The compensation period H2 and the data loading period H3, the first clock signal input end CI1 loads the clock signal CKa, and due to the storage effect of the storage capacitor Cc, the voltage of the first control node PU is further raised, so as to more accurately and stably control the third clock output switch tube T3a to be in the conductive state, and thus the clock signal CKa is output from the first signal output end SO1 through the third clock output switch tube T3a as the scanning signal Gsi of the current scanning line and the reset scanning signal Rsi of the GOA unit 130 of the interval preset level.

[0160] At the same time, the clock signal CKa is also transmitted from the first clock signal input end CI1 to the compensation capacitor Cm, and the fifth compensation scanning output switch tube T5a is in the conductive state under the control of the clock signal CKa provided by the compensation capacitor Cm at the first clock signal input end CI1, so as to transmit and load the high potential voltage of the first control node PU to the third control node PUB, so that the voltage of the third control node PUB also corresponds to the high potential, and thus the third compensation scanning output switch tube T3b is in the conductive state under the control of the high potential voltage provided by the third control node PUB, so as to transmit and load the high potential voltage provided by the high voltage power supply end VGH to the second signal output end SO2 as the compensation scanning signal Gr output.

[0161] After the clock signal CKa stops outputting after continuously outputting for one unit time 1H, the third clock output switch tube T3a is still in the conductive state, but since the clock signal CKa stops outputting, the corresponding first signal output end SO1 stops outputting the scanning signal Gs and the reset scanning signal Rs, but since the fifth compensation scanning output switch tube T5a can maintain the conductive state for a preset period after being turned on, it continuously controls the transmission and loading of the high potential voltage of the first control node PU to the third control node PUB within the preset period, so as to ensure that the voltage of the third control node PUB is at a high potential, and then the third compensation scanning output switch tube T3b can also be in the conductive state within the preset period, so as to continuously transmit and load the high potential voltage provided by the high voltage power supply end VGH to the second signal output end SO2 within the preset period as the compensation scanning signal Gr output, that is, the compensation scanning signal Gr is continuously output within the preset period, and in the embodiment, the compensation scanning signal Gr can be continuously output within a period of 5 unit time 5H.

[0162] After the compensation period H2, that is, after the preset period, the second clock signal input end CI2 receives the clock signal CKe+a, the seventh switch tube T7 and the eighth switch tube T8 are turned on, so as to load the low potential voltage of the low voltage power supply end VSS to the first control node PU, and the voltage of the first control node PU is pulled down to the low potential, thereby the corresponding third clock output switch tube T3a, the fifth compensation scan output switch tube T5a and the sixth switch tube T6 are all cut off.

[0163] At the same time, the second switch tube T2 is turned on under the control of the high voltage power supply end VGH, so as to load the high potential voltage of the high voltage power supply end VDD to the second control node PD, and the eighth switch tube T8 is turned on under the control of the high potential voltage of the second control node PD, so as to further pull down the voltage of the first control node PU to the low potential, and the fourth clock output switch tube T4a, the fourth compensation scan off switch tube T4b and the fifth compensation scan off switch tube T5b are all turned on, so as to accurately control the first signal output end SO1 and the second signal output end SO2 to stop outputting the corresponding scan signal Gs, the reset scan signal Rs and the compensation scan signal Gr.

[0164] In the embodiment, through the first clock signal output module 35, the second clock signal output module 36, the first reset scan output module 37 and the second reset scan output module 38 included in the GOA unit 130, the output of the scan signal Gs and the compensation scan signal Gr with different time lengths can be realized, that is, in a single GOA unit 130, the scan signal Gs and the reset scan signal Rs can be outputted, the compensation scan signal Gr can also be outputted, and the time lengths of the scan signal Gs and the compensation scan signal Gr can be ensured to be different, the circuit structure of the GOA unit 130 is effectively simplified, the signal output efficiency of the GOA unit 130 is improved, and the integration and design space of the scan driving circuit 13 are improved.

[0165] Please refer to FIG. 10, which is a circuit structure schematic diagram of any one of the light emitting driving units shown in FIG. 7.

[0166] As shown in FIG. 10, the EOA unit 140 includes a first light emitting pull-up module 41, a first light emitting pull-down module 42, a second light emitting pull-up module 43, a second light emitting pull-down module 44, a first light emitting signal output module 45 and a second light emitting signal output module 46.

[0167] The first light emitting pull-up module 41 is connected with the light emitting clock signal input end EKI, the light emitting high voltage power supply end EVGH and the first light emitting control node EPU, and is used for loading the high potential voltage provided by the light emitting high voltage power supply end EVGH to the first light emitting control node EPU under the control of the light emitting clock signal EK, so as to control the voltage of the first light emitting control node EPU to be at the high potential.

[0168] Specifically, the first light-emitting pull-up module 41 comprises a first light-emitting switch tube ET1, which comprises a first light-emitting control end ET10, a first light-emitting conductive end ET11 and a second light-emitting conductive end ET12. The first light-emitting control end ET10 is connected to the light-emitting clock signal input end EKI. The first light-emitting conductive end ET11 is connected to the light-emitting high-voltage power supply end EVGH. The second light-emitting conductive end ET12 is connected to the first light-emitting control node EPU. The first light-emitting switch tube ET1 is used to be turned on under the control of the light-emitting clock signal EK and load the high potential voltage provided by the light-emitting high-voltage power supply end EVGH to the first light-emitting control node EPU. Correspondingly, the first light-emitting switch tube ET1 is in a cut-off state when it does not receive the light-emitting clock signal EK, thereby stopping the high potential voltage provided by the light-emitting high-voltage power supply end EVGH from being loaded to the first light-emitting control node EPU.

[0169] In the embodiment, the first light-emitting switch tube ET1 is an N-type thin film transistor. The corresponding light-emitting clock signal EK is used to control the conduction when it is at a high level. The gate of the first light-emitting switch tube ET1 can be used as the first light-emitting control end ET10, or the gate is directly connected to the first light-emitting control end ET10. The drain of the first light-emitting switch tube ET1 can be used as the second light-emitting conductive end ET12, or the drain is directly connected to the second light-emitting conductive end ET12. The source of the first light-emitting switch tube ET1 can be used as the first light-emitting conductive end ET11, or the source is directly connected to the first light-emitting conductive end ET11. In other embodiments, the first light-emitting switch tube ET1 can also be a P-type thin film transistor, and the corresponding light-emitting clock signal EK is used to control the conduction when it is at a high level.

[0170] The first light-emitting pull-down module 42 is connected to the first light-emitting control node EPU, the second light-emitting control node EPD and the light-emitting low-voltage power supply end EVSS. When the second light-emitting control node EPD is at a high potential voltage, the first light-emitting pull-down module 42 is used to load the low potential voltage provided by the light-emitting low-voltage power supply end EVSS to the first light-emitting control node EPU, that is, to pull down the potential of the first light-emitting control node EPU.

[0171] The first light-emitting pull-down module 42 comprises a seventh light-emitting switch tube ET7, which comprises a seventh light-emitting control end ET70, a seventh light-emitting pull-up conductive end ET71 and a seventh light-emitting pull-down conductive end ET72. The seventh light-emitting control end ET70 is connected to the second light-emitting control node EPD, the seventh light-emitting pull-up conductive end ET71 is connected to the first light-emitting control node EPU, and the seventh light-emitting pull-down conductive end ET72 is connected to the light-emitting low-voltage power supply end EVSS. The seventh light-emitting switch tube ET7 is turned on under the control of the high-potential voltage of the second light-emitting control node EPD, so as to load the low-potential voltage of the light-emitting low-voltage power supply end EVSS to the first light-emitting control node EPU. Correspondingly, when the voltage of the second light-emitting control node EPD is low, the seventh light-emitting switch tube ET7 is in an off state, so as to stop loading the low-potential voltage provided by the light-emitting low-voltage power supply end EVSS to the first light-emitting control node EPU.

[0172] In the embodiment, the seventh light-emitting switch tube ET7 is an N-type thin film transistor (TFT), so that the corresponding clock signal CKe+a is a high-level conduction, the gate thereof can be used as the seventh control end T70, or the gate thereof is directly connected to the seventh light-emitting control end ET70; the drain of the seventh light-emitting switch tube ET7 can be used as the seventh light-emitting pull-up conductive end ET71, or the drain thereof is directly connected to the seventh light-emitting pull-up conductive end ET71; and the source of the seventh light-emitting switch tube ET7 can be used as the seventh light-emitting pull-down conductive end ET72, or the source thereof is directly connected to the seventh light-emitting pull-down conductive end ET72. In other embodiments, the seventh light-emitting switch tube ET7 can also be a P-type thin film transistor.

[0173] The second light-emitting pull-up module 43 is connected to the first light-emitting input end EI1, the second light-emitting input end EI2 and the second light-emitting control node EPD, and is used for pulling up the voltage potential of the second light-emitting control node EPD under the control of the scanning signal received by the first light-emitting input end EI1 or the second light-emitting input end EI2.

[0174] The second light-emitting pull-up module 43 comprises a second pull-up reset switch tube ET2a and a second pull-up write switch tube ET2b. The second pull-up reset switch tube ET2a comprises a second pull-up reset control end ET210, a first pull-up reset conductive end ET211 and a second pull-up reset conductive end ET212. The second pull-up reset control end ET210 and the first pull-up reset conductive end ET211 are simultaneously connected to the first light-emitting input end EI1, and the second pull-up reset conductive end ET212 is connected to the second light-emitting control node EPD. The second pull-up reset switch tube ET2a is turned on under the control of the high-potential voltage of the scanning signal Gs provided by the first light-emitting input end EI1, so as to transmit and load the high potential of the scanning signal Gs to the second light-emitting control node EPD.

[0175] Correspondingly, it can be understood that when the second pull-up reset switch tube ET2a is turned on, if the first light-emitting input end EIl stops providing the scanning signal Gs, the voltage of high potential loaded to the second light-emitting control node EPD is stopped. It should be noted that when the second light-emitting control node EPD is not connected to the low potential by other switch tubes, the second pull-up reset switch tube ET2a will load the high potential voltage provided by the scanning signal Gs to the second light-emitting control node EPD only when it is turned on. If the second light-emitting control node EPD has been connected to the light-emitting low-voltage power supply end EVSS by other switch tubes, the second pull-up reset switch tube ET2a will not load the high potential voltage in the scanning signal Gs to the second light-emitting control node EPD.

[0176] Similarly, the second pull-up write switch tube ET2b includes a second pull-up write control end ET220, a first pull-up write conductive end ET221, and a second pull-up write conductive end ET222. The second pull-up write control end ET220 is connected to the first pull-up write conductive end ET221 at the same time, and the second pull-up write conductive end ET222 is connected to the second light-emitting control node EPD. The second pull-up write switch tube T2b is turned on under the control of the high potential voltage of the scanning signal Gs provided by the second light-emitting input end EIl, so as to transmit and load the high potential of the scanning signal Gs to the second light-emitting control node EPD.

[0177] In this embodiment, the second pull-up reset switch tube ET2a and the second pull-up write switch tube ET2b are N-type thin film transistors, and the gates thereof can be connected to the second pull-up reset control end ET210 and the second pull-up write control end ET220, respectively, and the sources and drains thereof can be connected to the corresponding conductive ends, respectively. Of course, in other embodiments of the present application, the second pull-up reset switch tube ET2a and the second pull-up write switch tube ET2b can also be P-type thin film transistors.

[0178] The second light-emitting pull-down module 44 is connected to the first light-emitting control node EPU, the second light-emitting control node EPD, and the light-emitting low-voltage power supply end EVSS, and is used to load the low potential voltage provided by the light-emitting low-voltage power supply end EVSS to the second light-emitting control node EPD when the first light-emitting control node EPU is at a high potential voltage, that is, to pull down the potential of the second light-emitting control node EPD.

[0179] Specifically, the second light-emitting pull-down module 44 comprises a sixth light-emitting switch tube ET6, which comprises a sixth light-emitting control end ET60, a sixth light-emitting pull-up conductive end ET61 and a sixth light-emitting pull-down conductive end ET62. The sixth light-emitting control end ET60 is connected to the first light-emitting control node EPU, the sixth light-emitting pull-up conductive end ET61 is connected to the second light-emitting control node EPD, and the sixth light-emitting pull-down conductive end ET62 is connected to the light-emitting low-voltage power supply end EVSS. The sixth light-emitting switch tube ET6 is turned on under the control of the high potential voltage of the first light-emitting control node EPU, so as to provide the low potential voltage provided by the light-emitting low-voltage power supply end EVSS to the second light-emitting control node EPD, that is, to control the voltage of the second light-emitting control node EPD to be low. Correspondingly, the sixth light-emitting switch tube ET6 is in an off state when the first light-emitting control node EPU is at a low voltage, so as to stop loading the low potential voltage provided by the light-emitting low-voltage power supply end EVSS to the second light-emitting control node EPD.

[0180] In the embodiment, the sixth light-emitting switch tube ET6 is an N-type thin film transistor (TFT), so that the corresponding first light-emitting control node EPU is turned on when the high level, the gate of which can be directly connected to the sixth light-emitting control end ET60 as the sixth light-emitting control end ET60; the drain of the sixth light-emitting switch tube ET6 can be directly connected to the sixth light-emitting pull-up conductive end ET61 as the sixth light-emitting pull-up conductive end ET61; and the source of the sixth light-emitting switch tube ET6 can be directly connected to the sixth light-emitting pull-down conductive end ET62 as the sixth light-emitting pull-down conductive end ET62. In other embodiments, the sixth light-emitting switch tube ET6 can also be a P-type thin film transistor, which is turned on when the voltage of the corresponding first light-emitting control node EPD is low.

[0181] The first light-emitting signal output module 45 is connected to the first light-emitting control node EPU, the light-emitting high-voltage power supply end EVGH and the light-emitting output end EO, and is used for outputting the high potential voltage provided by the light-emitting high-voltage power supply end EVGH as a light-emitting signal from the light-emitting output end EO under the control of the voltage of the first light-emitting control node EPU being high within a second preset time length.

[0182] The first light-emitting signal output module 45 comprises a third light-emitting output switch tube ET3 and a light-emitting energy storage capacitor ECc. The third light-emitting clock output switch tube ET3 comprises a third light-emitting output control end ET30, a first light-emitting output conductive end ET31 and a second light-emitting output conductive end ET32. The third light-emitting output control end ET30 is connected to the first light-emitting control node EPU, the first light-emitting output conductive end ET31 is connected to the light-emitting high-voltage power supply end EVGH, and the second light-emitting output conductive end ET32 is connected to the light-emitting output end EO.

[0183] The light-emitting energy storage capacitor ECc is connected between the first light-emitting control node EPU and the light-emitting output terminal EO. The light-emitting energy storage capacitor ECc is used to maintain the voltage of the first light-emitting control node EPU at a high potential for a preset period. In this embodiment, the preset period is 5 unit time lengths (5H), and of course, in other embodiments of the present application, the preset period can be adjusted according to actual needs.

[0184] The third light-emitting output switch tube ET3 is turned on under the control of the high potential voltage of the first light-emitting control node EPU, so as to output the high potential voltage provided by the light-emitting high-voltage power supply terminal EVGH as the light-emitting signal Es from the light-emitting output terminal EO.

[0185] In this embodiment, the third light-emitting output switch tube ET3 is an N-type thin film transistor, the gate electrode of which can be used as the third light-emitting output control terminal ET30, or the gate electrode is directly connected to the third light-emitting output control terminal ET30; the source electrode and the drain electrode thereof can be used as two conductive terminals respectively. In other embodiments of the present application, the third light-emitting output switch tube ET3 can also be a P-type thin film transistor, which is turned on when the voltage of the corresponding first light-emitting control node EPD is at a low potential.

[0186] The second light-emitting signal output module 46 is connected to the second light-emitting control node EPD, the light-emitting low-voltage power supply terminal EVSS, the light-emitting clock signal input terminal EKI, and the light-emitting output terminal EO. The second light-emitting signal output module 46 is used to control the light-emitting output terminal EO to stop outputting the light-emitting signal when the voltage of the second light-emitting control node EPD is at a high potential or when the light-emitting clock signal is received.

[0187] The second light-emitting signal output module 46 includes a first light-emitting closing switch tube ET4 and a second light-emitting closing switch tube ET5. The second light-emitting signal output module 46 is used to connect the second light-emitting control node EPD, the second light-emitting input terminal EI2, and the light-emitting output terminal EO, and is used to control the light-emitting output terminal EO to stop outputting the light-emitting signal when the light-emitting clock signal EK is received or when the second light-emitting control node EPD is at an effective trigger potential.

[0188] The first light-emitting-off switch tube ET4 comprises a first light-emitting-off control end ET40, a first light-emitting-off conductive end ET41 and a second light-emitting-off conductive end ET42. The first light-emitting-off control end ET40 is connected to the second light-emitting control node EPD, the first light-emitting-off conductive end ET41 is connected to the light-emitting clock signal input end EKI, and the second light-emitting-off conductive end ET42 is connected to the light-emitting output end EO. The first light-emitting-off switch tube ET4 is turned on under the control of the high potential voltage of the second light-emitting control node EPD, so as to load the light-emitting clock signal provided by the light-emitting clock signal input end EKI to the output light-emitting output end EO, that is, to load the transmission of the light-emitting clock signal input end EKI to the output light-emitting output end EO. In the embodiment, when the second light-emitting control node EPD corresponds to a high potential, the light-emitting clock signal input end EKI does not output the light-emitting clock signal EK, and at this time, the light-emitting output end EO stops outputting the light-emitting signal Es.

[0189] In the embodiment, the first light-emitting-off switch tube ET4 is an N-type thin film transistor, which is turned on when the voltage of the second light-emitting control node EPD is high, and is turned off when the voltage of the second light-emitting control node EPD is low. The gate of the first light-emitting-off switch tube ET4 can be directly connected to the first light-emitting-off control end T40, and the source and the drain thereof are respectively connected to the two conductive ends. In other embodiments, the first light-emitting-off switch tube ET4 can also be a P-type thin film transistor, which is turned on when the voltage of the second light-emitting control node EPD is low, and is turned off when the voltage of the second light-emitting control node EPD is high.

[0190] The second light-emitting-off switch tube ET5 comprises a second light-emitting-off control end ET50, a third light-emitting-off conductive end ET53 and a fourth light-emitting-off conductive end ET54. The second light-emitting-off control end ET50 is connected to the light-emitting clock signal input end EKI, the third light-emitting-off conductive end ET53 is connected to the light-emitting low-voltage power supply end EVSS, and the fourth light-emitting-off conductive end ET54 is connected to the second light-emitting control node EPD.

[0191] The second light-emitting-off switch tube ET5 is turned on under the control of the high potential voltage of the light-emitting clock signal EK provided by the light-emitting clock signal input end EKI, so as to load the low potential voltage provided by the light-emitting low-voltage power supply end EVSS to the second light-emitting control node EPD, thereby controlling the first light-emitting-off switch tube ET4 to be in an off state, and further accurately preventing the light-emitting clock signal EK provided by the light-emitting clock signal input end EKI from being transmitted to the light-emitting output end EO through the first light-emitting-off switch tube ET4.

[0192] In this embodiment, the second light-emitting off switch transistor ET5 is an N-type thin film transistor, the gate of which can be directly connected to the second light-emitting off control terminal T50, and the source and the drain thereof are respectively two conductive terminals. In other embodiments, the second light-emitting off switch transistor ET5 can also be a P-type thin film transistor.

[0193] Please refer to FIG. 11, which is a timing diagram of the light-emitting driving unit shown in FIG. 10. In the diagram, Gs(i-b) is a waveform diagram of the scanning signal output by the first light-emitting input terminal EIl, Gsi is a waveform diagram of the scanning signal output by the second light-emitting input terminal EI2, ECK is a waveform diagram of the light-emitting clock signal, EPU is a voltage waveform diagram of the first light-emitting control node EPU, EPD is a voltage waveform diagram of the second light-emitting control node EPD, and Esi is a waveform diagram of the light-emitting signal Es output by the light-emitting output terminal EO.

[0194] Now, the working process of the EOA unit 140 will be described in detail with reference to FIGS. 10-11.

[0195] During the reset period H1, the scanning signal Gs provided by the first light-emitting input terminal EIl controls the second pull-up reset switch transistor ET2a to be turned on, and loads the high potential voltage in the scanning signal Gs to the second light-emitting control node EPD, thereby pulling up the voltage of the second light-emitting control node EPD to the high potential.

[0196] The high potential voltage of the first light-emitting control node EPU controls the seventh light-emitting transistor ET7 to be in the on state, thereby loading the low potential voltage provided by the light-emitting low voltage conductive terminal EVSS to the first light-emitting control node EPU. At the same time, the high potential voltage of the first light-emitting control node EPU controls the first light-emitting off switch transistor ET4 to be turned on, thereby transmitting the low voltage of the light-emitting clock signal EK in the light-emitting clock signal input terminal EKI to the light-emitting output terminal EO.

[0197] During the compensation scanning period H2 and the light-emitting period H4, the light-emitting clock signal input terminal EKI controls the first light-emitting switch transistor ET1 to be turned on, thereby loading the high potential voltage in the light-emitting high voltage power supply terminal EVGH to the first light-emitting control node EPU, thereby pulling up the voltage of the first light-emitting control node EPU to the high potential.

[0198] The high potential voltage of the first light-emitting control node EPU controls the third light-emitting output switch transistor ET3 to be turned on, thereby loading the high potential voltage in the light-emitting high voltage power supply terminal EVGH to the light-emitting output terminal EO as the light-emitting signal Es output. Due to the storage effect of the light-emitting storage capacitor ECc, the voltage of the first light-emitting control node EPU is accurately and stably kept in the high potential state, thereby controlling the third light-emitting output switch transistor ET3 to be continuously in the on state, thereby maintaining the light-emitting signal Es to be continuously output within a preset period.

[0199] Meanwhile, the high voltage of the first light-emitting control node EPU controls the sixth light-emitting switch transistor ET6 to be turned on, so that the low voltage provided by the light-emitting low-voltage power supply end EVSS is loaded to the second light-emitting control node EPD, i.e. the potential of the second light-emitting control node EPD is pulled down, ensuring the accurate output of the light-emitting signal Es.

[0200] During the data loading period H3, the scanning signal Gs provided by the second light-emitting input end EI2 controls the second pull-up write switch transistor ET2b to be turned on, and the high potential voltage in the scanning signal Gs is loaded to the second light-emitting control node EPD, thereby pulling up the voltage of the second light-emitting control node EPD to be high potential.

[0201] Similarly, the high voltage of the first light-emitting control node PU controls the seventh light-emitting transistor ET7 to be in the turned-on state, thereby loading the low potential voltage provided by the light-emitting low-voltage conduction end EVSS to the first light-emitting control node EPU, so that the third light-emitting output switch transistor ET3 is turned off, and the light-emitting output end EO stops outputting the high potential voltage provided by the light-emitting high-voltage power supply end EVGH.

[0202] Meanwhile, the high voltage of the first light-emitting control node PU controls the first light-emitting off switch transistor ET4 to be turned on, thereby transmitting the low voltage of the light-emitting clock signal EK in the light-emitting clock signal input end EKI to the light-emitting output end EO, accurately controlling the light-emitting signal Es to stop outputting.

[0203] Please refer to FIG. 12, which is a circuit structure schematic diagram of any one of the light-emitting driving units in a modified embodiment shown in FIG. 7. The EOA unit 140 shown in FIG. 12 has substantially the same circuit structure, working principle and working timing as the EOA unit shown in FIG. 10, and the only difference is that the circuit structure of the first light-emitting pull-down module 42 is different, while the first light-emitting pull-up module 41, the second light-emitting pull-up module 43, the second light-emitting pull-down module 44, the first light-emitting signal output module 45 and the second light-emitting signal output module 46 are all the same.

[0204] The first light-emitting pull-down module 42 is connected with the light-emitting high-voltage power supply end EVGH, the first light-emitting control node EPU, the second light-emitting control node EPD and the light-emitting low-voltage power supply end EVSS, and is used for loading the low potential voltage provided by the light-emitting low-voltage power supply end EVSS to the first light-emitting control node EPU when the voltage of the second light-emitting control node EPD is high potential, i.e. pulling down the potential of the first light-emitting control node EPU; meanwhile, when the first light-emitting control node EPU is high potential, the conduction path between the first light-emitting control node EPU and the light-emitting low-voltage conduction end is disconnected by the high potential voltage provided by the light-emitting high-voltage power supply end EVGH, preventing the current of the first light-emitting control node EPU from leaking, and ensuring that the voltage of the first light-emitting control node EPU is accurately positioned at high potential.

[0205] Specifically, the first light-emitting pull-down module 42 comprises two series-connected seventh light-emitting switch tubes, which can be defined as a seventh upper connection light-emitting switch tube ET7a and a seventh lower connection light-emitting switch tube ET7b connected in series through an intermediate node Nm. More specifically, one of the conductive ends of the seventh upper connection light-emitting switch tube ET7a is connected to the first light-emitting control node EPU, one of the conductive ends of the seventh lower connection light-emitting switch tube ET7b is connected to the light-emitting low-voltage power supply end EVSS, and the other two conductive ends are both connected to the intermediate node Nm. The control ends of the seventh upper connection light-emitting switch tube ET7a and the seventh lower connection light-emitting switch tube ET7b are both connected to the second light-emitting control node EPD. The two series-connected seventh light-emitting switch tubes are used to be turned on at the same time when the voltage of the second light-emitting control node EPD is high, thereby quickly pulling down the potential of the first light-emitting control node EPU and quickly releasing the charge of the first light-emitting control node EPU, which can effectively improve the safety of the current released by the first light-emitting control node EPU and prevent the switch tube from being damaged by a sharp or surge current.

[0206] It can be understood that the control ends of the seventh upper connection light-emitting switch tube ET7a and the seventh lower connection light-emitting switch tube ET7b are the gates of the two switch tubes, and the conductive ends are the source-drain electrodes of the two switch tubes. In the embodiment, the seventh upper connection light-emitting switch tube ET7a and the seventh lower connection light-emitting switch tube ET7b are both N-type thin film transistors, which are turned on when the voltage of the second light-emitting control node EPD is high, that is, the high potential voltage of the second light-emitting control node EPD serves as the turn-on trigger voltage thereof. In other embodiments, the seventh upper connection light-emitting switch tube ET7a and the seventh lower connection light-emitting switch tube ET7b can also be P-type thin film transistors, which are correspondingly turned on when the voltage of the second light-emitting control node EPD is low, that is, the low potential voltage of the second light-emitting control node EPD serves as the turn-on trigger voltage thereof.

[0207] The eighth light-emitting switch tube ET8 comprises an eighth light-emitting control end ET80, an eighth upper pull conductive end ET81, and an eighth light-emitting pull-down conductive end ET82. The eighth light-emitting control end ET80 is connected to the first light-emitting control node EPD, the eighth upper pull conductive end ET81 is connected to the light-emitting high-voltage power supply end EVGH, and the eighth light-emitting pull-down conductive end ET82 is connected to the intermediate node Nm between the two series-connected seventh light-emitting switch tubes.

[0208] The eighth light emitting switch transistor ET8 is turned on under the high potential voltage control of the first light emitting control node EPU, so as to load the high potential voltage of the high voltage power supply end EVGH to the intermediate node Nm. Correspondingly, the eighth light emitting switch transistor ET8 is turned off when the first light emitting control node EPU is low voltage, so as to stop loading the high potential voltage of the high voltage power supply end EVGH to the intermediate node Nm. The eighth light emitting switch transistor ET8 is used to load the high potential voltage of the high voltage power supply end EVGH to the intermediate node Nm under the high potential voltage of the first light emitting control node EPU, so as to effectively prevent the first light emitting control node EPU from forming a conductive path through the seventh upper light emitting switch transistor ET7a and the seventh lower light emitting switch transistor ET7b, and the current of the first light emitting control node EPU is discharged. In other words, the eighth light emitting switch transistor ET8 can effectively ensure that the potential of the first light emitting control node EPU is accurately maintained at a high potential.

[0209] In the embodiment, the eighth light emitting switch transistor ET8 is an N-type thin film transistor, wherein the gate electrode is the eighth light emitting control end ET80, and the source electrode and the drain electrode are respectively used as two conductive ends. In other embodiments, the eighth light emitting switch transistor ET8 can also be a P-type thin film transistor.

[0210] In the embodiment, in the driving circuit composed of the scan driving circuit 13 and the light emitting driving circuit 14, one GOA unit 130 can simultaneously output multiple scan signals in the form of pulses with different durations, effectively improving the integration and output signal efficiency of the GOA unit 130. At the same time, cooperating with the circuit structure of the EOA unit 140, the corresponding light emitting signals can also be output, thereby effectively improving the image display effect of the pixel unit and providing more space for the narrow frame design of the display panel 10.

[0211] The principles and implementation modes of the present application are described by using specific examples in the present application, and the above implementation mode is only used to help understand the core idea of the present application; at the same time, for those skilled in the art, according to the idea of the present application, the specific implementation mode and application range will be changed, and the above description should not be understood as limiting the present application.

Claims

1. A drive circuit comprising m scan drive units arranged in series and cascaded, characterized in that, In the i-th scanning period of m continuous scanning periods included in a frame image display period, the i-th level scanning driving unit is configured to output a scanning signal and a compensation scanning signal, the scanning signal is a pulse signal with a first preset time length, and the compensation scanning signal is a pulse signal with a second preset time length, the scanning signal is configured to load a pixel unit at a first position in a data loading period of the i-th scanning period to control the pixel unit to receive a data signal to perform image display, and the compensation scanning signal is configured to load the pixel unit in a compensation period of the i-th scanning period to compensate the pixel unit with the data signal, wherein the second preset time length is greater than the first preset time length, the compensation period and the data loading period are sequentially continuous in time, m is a positive integer greater than 1, and i is a positive integer greater than or equal to 1 and less than m.

2. The drive circuit of claim 1, wherein, The scanning driving unit comprises an enable trigger end, a first clock signal input end, a second clock signal input end, a first signal output end and a second signal output end, wherein the enable trigger end is configured to receive an enable trigger signal to enable the scanning driving unit to work, the first clock signal input end and the second clock signal input end are configured to receive two clock signals with a preset unit time interval, the scanning driving unit outputs the scanning signal from the first signal output end according to the clock signal of the first clock signal input end, and outputs the compensation scanning signal from the second signal output end at the same time, and stops the compensation scanning signal according to the clock signal of the second clock signal input end, the clock signal is a periodic pulse signal and the pulse width is a unit time length.

3. The drive circuit of claim 2, wherein, The clock signals received by the first clock signal input end and the second clock signal input end are separated by a unit time length, the first preset time length corresponding to the scanning signal is 1 unit time length, the second preset time length corresponding to the compensation scanning signal is a unit time length, and a is a positive integer greater than 1.

4. The drive circuit of claim 3, wherein, The scanning driving unit comprises a first pull-up module, a first clock signal output module and a first reset scanning output module, wherein: The first pull-up module is connected to the enable trigger end, a high-voltage power supply end and a first control node, and is configured to pull down the voltage of the first control node to a high level under the control of the enable trigger signal provided by the enable trigger end; The first clock signal output module is connected to the first control node, the first clock signal input end and the first signal output end, and is configured to output the clock signal as the scanning signal when the voltage of the first control node is at a high level, and maintain the voltage of the first control node at a high level in the second preset time length; The first reset scanning output module is connected to the first control node, the first clock signal input end, the high-voltage power supply end and the second signal output end, and is configured to output the power supply signal provided by the high-voltage power supply end as the compensation scanning signal in the second preset time length under the control of the voltage of the first control node being at a high level and the clock signal.

5. The drive circuit of claim 4, wherein, The scan driving unit further comprises a second pull-down module, which is connected with the first control node, a low-voltage power supply end and a second control node, and is used to connect the low-voltage power supply end with the second control node when the voltage of the first control node is high, so as to control the voltage of the second control node to be low.

6. The drive circuit of claim 5, wherein, The scan driving unit further comprises a first pull-down module and a second pull-up module, The second pull-up module is connected with the high-voltage power supply end and the second control node, and is used to load the high-voltage provided by the high-voltage power supply end to the second control node to pull up the voltage of the second control node when the second control node is not loaded with low voltage; The first pull-down module is connected with the first control node, the second control node and the second clock signal input end, and is used to pull down the voltage of the first control node under the control of the clock signal provided by the second clock signal input end or when the voltage of the second control node is high.

7. The drive circuit of claim 6, wherein, The scan driving unit further comprises a second clock signal output module and a second reset scan output module, wherein: The second clock signal output module is connected with the second control node, the low-voltage power supply end and the first signal output end, and is used to transmit low voltage to the first signal output end to stop outputting the scan signal when the voltage of the second control node is high; The second reset scan output module is connected with the second control node, the low-voltage power supply end and the second signal output end, and is used to transmit low voltage to the second signal output end to stop outputting the compensation scan signal when the voltage of the second control node is high.

8. The drive circuit according to any one of claims 4 to 7, wherein The scan driving unit further outputs a reset scan signal, the scan signal output by the first signal output end also serves as the reset scan signal, and the reset scan signal is used to be loaded to the pixel unit at the second position in the reset period of the i+bth scan period to control the pixel unit to receive a reset voltage to perform reset, wherein b is a positive integer greater than 1.

9. The drive circuit of claim 8, wherein, The one frame of image display period further comprises f continuous virtual scan periods, and the f continuous virtual scan periods are sequentially continuous in time with the first scan period, The scan driving circuit further comprises f virtual scan driving units, the f virtual scan driving units are sequentially cascaded, the virtual scan driving unit at the fth stage is connected with the scan driving unit at the first stage, and the virtual scan driving unit at the fth stage outputs an enable trigger signal to trigger the scan driving unit at the first stage to work. The virtual scan driving units at the first to fth stages are used to sequentially output the reset scan signal and the compensation scan signal in the reset period and the compensation period of the first to fth virtual scan periods, respectively, wherein f is a positive integer greater than 1.

10. The drive circuit according to any one of claims 1 to 7, characterized by The driving circuit further comprises m sequentially arranged light-emitting driving units, in the ith scanning period, the ith light-emitting driving unit is used to output a light-emitting signal, the light-emitting signal is used to provide to the pixel unit in the compensation period, so as to compensate the pixel unit with the compensation scanning signal, and the light-emitting signal is also used to control the pixel unit to emit light according to the data signal to display an image, wherein the light-emitting signal is a pulse signal lasting for the second preset time length, and the compensation period, the data loading period and the light-emitting period are sequentially continuous in time.

11. The drive circuit according to claim 10, characterized in that, The light-emitting driving unit comprises a light-emitting clock signal input end, a first light-emitting input end, a second light-emitting input end, a light-emitting output end, a first light-emitting pull-up module and a first light-emitting signal output module, The light-emitting clock signal input end is used to receive a light-emitting clock signal, the first light-emitting input end and the second light-emitting input end are connected to the first signal output ends of two scanning driving units with a preset interval, so as to respectively receive scanning signals with a preset interval of two scanning periods; The first light-emitting pull-up module is connected to the light-emitting clock signal input end, a light-emitting high-voltage power supply end and a first light-emitting control node, and is used to load a high-voltage provided by the light-emitting high-voltage power supply end to the first light-emitting control node under the control of the light-emitting clock signal. The first light-emitting signal output module is connected to the first light-emitting control node, the light-emitting high-voltage power supply end and the light-emitting output end, and is used to output the high-voltage provided by the light-emitting high-voltage power supply end as the light-emitting signal from the light-emitting output end under the control of the high-voltage of the first light-emitting control node within the second preset time length.

12. The drive circuit of claim 11, wherein, The light-emitting driving unit further comprises a second light-emitting pull-down module, the second light-emitting pull-down module is connected to the first light-emitting control node, a second light-emitting control node and a light-emitting low-voltage power supply end, and is used to load a low-voltage provided by the light-emitting low-voltage power supply end to the second light-emitting control node when the first light-emitting control node is a high-voltage.

13. The drive circuit of claim 11, wherein, The light-emitting driving unit further comprises a second light-emitting pull-down module, the second light-emitting pull-down module is connected to the first light-emitting control node, a second light-emitting control node and a light-emitting low-voltage power supply end, and is used to load a low-voltage provided by the light-emitting low-voltage power supply end to the second light-emitting control node when the first light-emitting control node is a high-voltage. The second light-emitting pull-down module is connected to the first light-emitting input end, the second light-emitting input end and the second light-emitting control node, and is used to pull up the voltage potential of the second light-emitting control node when the first light-emitting input end or the second light-emitting input end receives the scanning signal. The second light-emitting signal output module is connected to the second light-emitting control node, the light-emitting low-voltage power supply end, the light-emitting clock signal input end and the light-emitting output end, and is used to control the light-emitting output end to stop outputting the light-emitting signal when the voltage of the second light-emitting control node is a high-voltage or the light-emitting clock signal is received.

14. The driving circuit according to claim 13, characterized in that, The light-emitting driving unit further comprises a first light-emitting pull-down module connected to the first light-emitting control node, the second light-emitting control node and the light-emitting low-voltage power supply end, for loading a low-voltage voltage provided by the light-emitting low-voltage power supply end to the first light-emitting control node when the second light-emitting control node is at a high-voltage, and for controlling the first light-emitting signal output module to stop outputting the light-emitting signal. Or The first pull-down module is connected to the light-emitting high-voltage power supply end, the first light-emitting control node, the second light-emitting control node and the light-emitting low-voltage power supply end, for disconnecting the conductive path between the first light-emitting control node and the light-emitting low-voltage conductive end by the high-voltage voltage provided by the light-emitting high-voltage power supply end when the first light-emitting control node is at a high-voltage, and for loading a low-voltage voltage provided by the light-emitting low-voltage power supply end to the first light-emitting control node when the second light-emitting control node is at a high-voltage, and for controlling the first light-emitting signal output module to stop outputting the light-emitting signal.

15. A display panel, characterized by The display panel comprises m scan lines, n data lines, m light-emitting lines, m compensation scan lines, m compensation lines, m reset scan lines, m reset lines, a data driving circuit, a compensation circuit, a reset circuit and the driving circuit of any one of claims 1-14, and further comprises a plurality of pixel units, each of which is connected to one of the scan lines, the data lines, the light-emitting lines, the compensation scan lines, the compensation lines, the reset scan lines and the reset lines. The driving circuit comprises m scan driving units respectively connected to m scan lines, m compensation scan lines and m reset scan lines, and m light-emitting driving units respectively connected to the m scan lines. The m light-emitting driving units of the driving circuit are connected to the pixel units through the m light-emitting lines. The compensation circuit is connected to the compensation lines and outputs a compensation signal to the pixel units when the pixel units receive a compensation scan signal, so as to perform data signal compensation on the pixel units. The reset circuit is connected to the reset lines and outputs a reset signal to the pixel units when the pixel units receive a reset scan signal, so as to reset the pixel units.

16. An electronic device, comprising: The electronic device comprises a housing and the display panel of claim 15, wherein the housing is used to carry the display panel.

Images