Semiconductor structure and preparation method therefor, memory and storage system

Abstract

A semiconductor structure and a preparation method therefor, a memory and a storage system. The semiconductor structure comprises a transistor. The transistor comprises a semiconductor pillar and a gate. The semiconductor pillar extends in a first direction, which is the direction of the thickness of the semiconductor structure. The semiconductor pillar comprises a curved sidewall, which protrudes in a direction away from the semiconductor pillar. The gate is located on one side of the semiconductor pillar and arranged opposite the curved sidewall.

Description

Semiconductor structure and its fabrication method, memory, storage system

[0001] This application claims priority to Chinese patent application No. 202411053609.5, filed on August 1, 2024, the entire contents of which are incorporated herein by reference. Technical Field

[0002] This disclosure relates to the field of semiconductor technology, and in particular to a semiconductor structure and its fabrication method, a memory, and a storage system. Background Technology

[0003] Planar memory cells can be scaled to smaller sizes by improving process technology, circuit design, programming algorithms, and manufacturing processes. However, as the feature size of memory cells approaches its lower limit, planar processes and manufacturing technologies become challenging and costly, and the memory density for planar memory cells approaches its upper limit.

[0004] Three-dimensional (3D) memory architectures can address the density limitations of planar memory cells. 3D memory architectures consist of arrays of memory cells.

[0005] It should be noted that the information disclosed in the background section is only used to enhance the understanding of the background art of the technology described herein. Therefore, the background art may contain certain information that does not constitute technology known to those skilled in the art in this country. Summary of the Invention

[0006] On one hand, a semiconductor structure is provided, including at least one transistor. Each of the at least one transistor includes a semiconductor pillar and a gate. The semiconductor pillar extends along a first direction, which is the thickness direction of the semiconductor structure. The semiconductor pillar includes a curved sidewall that protrudes away from the semiconductor pillar. The gate is located on one side of the semiconductor pillar and is disposed opposite to the curved sidewall.

[0007] The semiconductor structure provided in the above embodiments of this disclosure includes curved sidewalls in the semiconductor pillars within the transistor. The curved sidewalls protrude in a direction away from the semiconductor pillars, and the gate is disposed opposite to the curved sidewalls. On the one hand, since the curved sidewalls of the semiconductor pillars are curved, the surface of the curved sidewalls of the semiconductor pillars is smooth, which allows the electric field to be evenly distributed on the curved sidewalls of the semiconductor pillars. This avoids the electric field from concentrating in a local area of ​​the curved sidewalls of the semiconductor pillars, which helps to reduce the probability of tip discharge phenomenon, and thus helps to reduce the probability of transistor failure in the semiconductor structure, thereby improving the yield of the semiconductor structure.

[0008] On the other hand, since the curved sidewalls of the semiconductor pillar bulge away from the semiconductor pillar, the curved sidewalls of the semiconductor pillar can transition relatively smoothly to other sidewalls of the semiconductor pillar that are connected to the curved sidewalls. That is, the connection interface between the curved sidewalls of the semiconductor pillar and the other sidewalls connected to them is relatively smooth. This can reduce the probability of electric field concentration at the connection position between the curved sidewalls of the semiconductor pillar and the other sidewalls connected to them, which is beneficial to reducing the probability of tip discharge phenomenon, and thus beneficial to reducing the probability of transistor failure in the semiconductor structure, thereby improving the yield of the semiconductor structure.

[0009] In some embodiments, the shape of the cross section of the gate perpendicular to the first direction is arc-shaped, and the gate protrudes in a direction away from the semiconductor pillar.

[0010] In some embodiments, the semiconductor structure further includes a gate dielectric layer located between the gate and the curved sidewall. The gate dielectric layer has an arc-shaped cross-section perpendicular to the first direction and protrudes away from the semiconductor pillar.

[0011] In some embodiments, the semiconductor structure further includes a connection layer located between the gate and the gate dielectric layer. The cross-section of the connection layer perpendicular to the first direction is arc-shaped and protrudes away from the semiconductor pillar.

[0012] In some embodiments, the semiconductor pillar further includes two first planar sidewalls, which are respectively connected to both sides of the curved sidewall.

[0013] In some embodiments, in a cross-section of the semiconductor pillar perpendicular to the first direction, the two first planar sidewalls have equal dimensions.

[0014] In some embodiments, the semiconductor pillar further includes a second planar sidewall connected between the two first planar sidewalls and disposed opposite to the curved sidewall. The semiconductor structure also includes a shielding structure located on the side of the semiconductor pillar away from the gate and disposed opposite to the second planar sidewall.

[0015] In some embodiments, the at least one transistor includes a plurality of transistors, wherein a plurality of semiconductor pillars of the plurality of transistors are arranged sequentially at intervals along a second direction, and the curved sidewalls of the plurality of semiconductor pillars are located on the same side, wherein the second direction is perpendicular to the first direction.

[0016] In some embodiments, multiple gates of the plurality of transistors are sequentially connected to form gate lines extending along the second direction, the gate lines being wavy.

[0017] On the other hand, a method for fabricating a semiconductor structure is provided, the method comprising forming a transistor.

[0018] The transistor formation includes: forming a semiconductor pillar on a substrate, the semiconductor pillar being perpendicular to the substrate. The semiconductor pillar includes curved sidewalls that bulge away from the semiconductor pillar. A gate is formed on one side of the semiconductor pillar, the gate being disposed opposite to the curved sidewalls.

[0019] In some embodiments, forming the semiconductor pillars includes: forming initial semiconductor pillars on the substrate, the initial semiconductor pillars being surrounded by a dielectric layer. A first trench extending in a second direction perpendicular to the thickness direction of the semiconductor structure is formed between two adjacent initial semiconductor pillars. The initial semiconductor pillars include initial sidewalls disposed opposite to the first trench. The dielectric layer is etched via the first trench in a direction close to the semiconductor pillar to expose the initial sidewalls. The initial sidewalls are etched to form curved sidewalls.

[0020] In another aspect, a memory is provided, comprising the aforementioned semiconductor structure and a capacitor. The capacitor is electrically connected to a transistor in the semiconductor structure.

[0021] In another aspect, a storage system is provided, including the aforementioned memory and controller. The controller is electrically connected to the memory.

[0022] It is understood that the beneficial effects that the semiconductor structure fabrication method, memory and storage system provided in the above embodiments of this disclosure can achieve can be referred to the beneficial effects of the semiconductor structure described above, and will not be repeated here. Attached Figure Description

[0023] To more clearly illustrate the technical solutions in this disclosure, the accompanying drawings used in some embodiments of this disclosure will be briefly described below. Obviously, the drawings described below are only drawings of some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams and are not intended to limit the actual size of the product, the actual flow of the method, the actual timing of the signals, etc. involved in the embodiments of this disclosure.

[0024] Figure 1 is a structural diagram of an electronic device according to some embodiments;

[0025] Figure 2 is a structural diagram of a storage system according to some embodiments;

[0026] Figure 3 is a three-dimensional structural diagram of a memory according to some embodiments;

[0027] Figure 4 is a planar structural diagram of a semiconductor structure according to some embodiments;

[0028] Figure 5 is a planar structural diagram of the AA region of the semiconductor structure in the embodiment shown in Figure 4;

[0029] Figure 6 is a flowchart of a method for fabricating a semiconductor structure according to some embodiments;

[0030] Figure 7 is a planar structural diagram of the semiconductor structure corresponding to step S1 in the flowchart of the semiconductor structure fabrication method in Figure 6.

[0031] Figure 8 is a planar structural diagram of the semiconductor structure corresponding to step S11 in the flowchart of the semiconductor structure fabrication method in Figure 6.

[0032] Figure 9 is a cross-sectional view of the semiconductor structure in Figure 8 along section line BB;

[0033] Figure 10 is a planar structural diagram of the semiconductor structure corresponding to step S12 in the flowchart of the semiconductor structure fabrication method in Figure 6.

[0034] Figure 11 is a cross-sectional view of the semiconductor structure in Figure 10 along section line CC;

[0035] Figure 12 is a planar structural diagram of the semiconductor structure corresponding to step S111 in the flowchart of the semiconductor structure fabrication method in Figure 6.

[0036] Figure 13 is a cross-sectional view of the semiconductor structure in Figure 12 along section line DD;

[0037] Figure 14 is a planar structural diagram of the semiconductor structure corresponding to step S112 in the flowchart of the semiconductor structure fabrication method in Figure 6.

[0038] Figure 15 is a cross-sectional view of the semiconductor structure in Figure 14 along section line EE;

[0039] Figure 16 is a planar structural diagram of the semiconductor structure corresponding to step S113 in the flowchart of the semiconductor structure fabrication method in Figure 6.

[0040] Figure 17 is a cross-sectional view of the semiconductor structure in Figure 16 along section line FF. Detailed Implementation

[0041] The technical solutions in some embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments provided in this disclosure are within the scope of protection of this disclosure.

[0042] In the description of this disclosure, it should be understood that the terms "upper", "lower", "front", "back", "horizontal", "top", "bottom", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this disclosure and simplifying the description, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this disclosure.

[0043] Unless the context otherwise requires, throughout the specification and claims, the term "comprising" is interpreted as open-ended and encompassing, meaning "including, but not limited to." In the description of the specification, terms such as "one embodiment," "some embodiments," "exemplary embodiment," "exemplary," or "some examples," etc., are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of this disclosure. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics mentioned may be included in any suitable manner in any one or more embodiments or examples.

[0044] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of embodiments of this disclosure, unless otherwise stated, "a plurality of" means two or more.

[0045] In describing some embodiments, the terms "coupled" and "connected," and their derivative expressions, may be used. For example, the term "connected" may be used in describing some embodiments to indicate that two or more components have direct physical or electrical contact with each other. Similarly, the term "coupled" may be used in describing some embodiments to indicate that two or more components have direct physical or electrical contact. However, the term "coupled" may also refer to two or more components that do not have direct contact with each other but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the content of this document.

[0046] In this disclosure, the meanings of “on,” “above,” and “above” should be interpreted in the broadest possible sense, such that “on” means not only “directly on” something, but also includes “on” something with intermediate features or layers in between, and that “above” or “above” means not only “above” or “above” something, but also “above” or “above” something without intermediate features or layers in between (i.e., directly on something).

[0047] In this disclosure, the term "substrate" refers to a material on which subsequent material layers are added. The substrate itself may be patterned. The material added on top of the substrate may be patterned, or may remain unpatterned. Furthermore, the substrate may include a variety of semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made of a non-conductive material such as glass, plastic, or sapphire wafer.

[0048] In this disclosure, the term "layer" refers to a portion of material comprising a region having thickness. A layer may extend over the entire lower or upper structure, or may have a extent smaller than that of the lower or upper structure. Furthermore, a layer may be a region of a homogeneous or heterogeneous continuous structure, with a thickness less than that of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure, or between any pair of horizontal planes at the top and bottom surfaces of a continuous structure. A layer may extend horizontally, vertically, and / or along a tapered surface. A substrate may be a layer, and may include one or more layers, and / or may have one or more layers on, above, and / or below it. A layer may include multiple layers. For example, an interconnect layer may include one or more conductor and contact layers (where interconnect lines and / or vertical interconnect vias (vias) are formed) and one or more dielectric layers.

[0049] This document describes exemplary embodiments with reference to cross-sectional views and / or plan views, which are idealized exemplary drawings. In the drawings, the thickness of layers and the area of ​​regions are enlarged for clarity. Therefore, variations in shape relative to the drawings are contemplated due to, for example, manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as being limited to the shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing processes. For example, etched areas shown as rectangular would typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shapes of the areas of the device, nor are they intended to limit the scope of the exemplary embodiments.

[0050] For ease of description below, an XYZ coordinate system is established. The first direction X represents the thickness direction of the semiconductor structure, the YZ plane is perpendicular to the first direction X, and the second direction Y intersects the third direction Z. For example, the second direction Y and the third direction Z are perpendicular to each other.

[0051] It should be noted that, for example, 11 / WL in the accompanying drawings of this disclosure indicates that the component is both 11 and WL, and other similar reference numerals in the drawings also follow the above description.

[0052] As shown in Figure 1, some embodiments of this disclosure provide an electronic device 1000. This electronic device 1000 may include a mobile phone, a tablet computer, a smart wearable product (e.g., a smartwatch, a smart bracelet), a virtual reality (VR) device, an augmented reality (AR) device, and other similar devices. This disclosure does not impose any special limitations on the form of the aforementioned electronic device 1000.

[0053] In some embodiments, referring to FIG1, the above-described electronic device 1000 may include a storage system 100 and a processor 200. The processor 200 is coupled to the storage system 100 to interact with the storage system 100.

[0054] For example, processor 200 can be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general-purpose processor can be a microprocessor or any conventional processor.

[0055] The storage system 100 described above will be described in detail below.

[0056] As shown in Figure 2, which is a structural diagram of a storage system 100 according to some embodiments, the storage system 100 may include a memory 10 and a controller 20. The memory 10 and the controller 20 are electrically connected.

[0057] For example, the aforementioned storage system 100 can be integrated into a memory card. The memory card may include any of the following: Personal Computer Memory Card International Association (PCMCIA) card, Compact Flash (CF) card, Smart Media (SM) card, Memory Stick, Multimedia Card (MMC), Secure Digital Memory Card (SD) card, and Universal Flash Storage (UFS).

[0058] The aforementioned storage system 100 can also be integrated into various types of storage devices, for example, included in the same package (e.g., UFS package or embedded Multi Media Card (eMMC package)). That is, the storage system 100 can be applied to and packaged into different types of electronic products, such as mobile phones (e.g., cell phones), desktop computers, tablets, laptops, servers, in-vehicle devices, game consoles, printers, positioning devices, wearable devices, smart sensors, power banks, virtual reality (VR) devices, augmented reality (AR) devices, or any other suitable electronic device having storage therein.

[0059] The aforementioned storage system 100 can also be integrated into a solid state drive (SSD).

[0060] For example, the controller 20 in the storage system 100 can be configured to operate in a low duty cycle environment, such as an SD card, CF card, Universal Serial Bus (USB) flash drive, or other media used in electronic devices such as personal calculators, digital cameras, and mobile phones.

[0061] The controller 20 can also be configured to operate in high duty cycle environments using SSDs or eMMCs, which are used as data storage for mobile devices such as smartphones, tablets, and laptops, as well as enterprise storage arrays.

[0062] For example, controller 20 can be configured to manage data stored in memory 10 and communicate with external devices (e.g., a host).

[0063] The controller 20 can also be configured to control the operation of the memory 10, such as read, erase and program operations.

[0064] Controller 20 can also be configured to manage various functions related to data stored or to be stored in memory 10, including at least one of bad block management, garbage collection, logical-to-physical address translation, and wear leveling.

[0065] The controller 20 can also be configured to process error correction codes for data read from or written to the memory 10.

[0066] Of course, controller 20 can also perform any other suitable function, such as formatting memory 10; or controller 20 can communicate with external devices (e.g., hosts) through at least one of various interface protocols.

[0067] It should be noted that the interface protocols include at least one of the following: USB protocol, MMC protocol, Peripheral Component Interconnect (PCI) protocol, Peripheral Component Interconnect Express (PCI-E) protocol, Advanced Technology Attachment (ATA) protocol, Serial Advanced Technology Attachment (SATA) protocol, Parallel Advanced Technology Attachment (PATA) protocol, Small Computer System Interface (SCSI) protocol, Enhanced Small Disk Interface (ESDI) protocol, Integrated Drive Electronics (IDE) protocol, and FireWire protocol.

[0068] The memory 10 described above will be described in detail below.

[0069] In some embodiments, as shown in FIG3, FIG3 is a perspective structural diagram of a memory 10 according to some embodiments. The memory 10 includes a semiconductor structure D and a capacitor C, the capacitor C being electrically connected to the semiconductor structure D. The capacitor C is used to store data bits as positive or negative charges.

[0070] Please refer to Figure 3. In memory 10, the semiconductor structure D and the capacitor C can form a memory cell array MC.

[0071] It should be noted that the embodiment shown in Figure 3 only illustrates the above-mentioned "memory cell array MC" as an example of a dynamic random access memory (DRAM) cell array. However, the type of "memory cell array MC" in this disclosure is not limited to this. "Memory cell array MC" can include any suitable type of memory cell array. For example, "memory cell array MC" can include phase-change memory (PCM) cell arrays, static random-access memory (SRAM) cell arrays, ferroelectric random access memory (FRAM) cells, resistive memory cell arrays, magnetic memory cell arrays, spin transfer torque (STT) memory cell arrays, etc.

[0072] In some embodiments, please continue to refer to FIG3, the memory 10 may also include multiple word lines WL and multiple bit lines BL.

[0073] The semiconductor structure D described above will be explained in detail below.

[0074] In some implementations, please refer to Figure 3. The semiconductor structure D includes transistor T.

[0075] When the memory 10 includes a semiconductor structure D and a capacitor C, the above-mentioned "capacitor C is electrically connected to semiconductor structure D" can mean that capacitor C is electrically connected to transistor T in semiconductor structure D.

[0076] In some embodiments, please continue to refer to Figure 3, the semiconductor structure D may include a plurality of transistors T.

[0077] In some embodiments, the transistor T in the semiconductor structure D can be a vertical transistor. For example, the transistor T in the semiconductor structure D can be a vertical metal-oxide-semiconductor field-effect transistor (MOSFET).

[0078] Using a vertical transistor as the transistor T in the semiconductor structure D can reduce the area occupied by the transistor T, the coupling capacitance, and the complexity of the interconnect wiring.

[0079] The following uses a vertical transistor as an example to illustrate some embodiments of this disclosure. However, the type of transistor T in the semiconductor structure D is not limited to this, and the type of transistor T in the semiconductor structure D can also be other suitable transistor types.

[0080] In some implementations, referring to Figure 3, transistor T includes semiconductor pillar 2. Semiconductor pillar 2 extends along a first direction X, which is the thickness direction of semiconductor structure D.

[0081] In some embodiments, please continue referring to FIG3, the semiconductor pillar 2 may include a first electrode region 21, a channel region 23, and a second electrode region 22. The first electrode region 21, the channel region 23, and the second electrode region 22 are arranged sequentially along a first direction (i.e., the thickness direction of the semiconductor structure D) X.

[0082] One of the first electrode region 21 and the second electrode region 22 can be the source electrode region of the semiconductor pillar 2, and the other of the first electrode region 21 and the second electrode region 22 can be the drain electrode region of the semiconductor pillar 2.

[0083] In some embodiments, please continue to refer to FIG3. When the memory 10 includes a semiconductor structure D, a capacitor C and a bit line BL, and the capacitor C is electrically connected to the transistor T in the semiconductor structure D, the bit line BL in the memory 10 can be coupled to the first pole region 21 or the second pole region 22 (i.e., the source region or the drain region) of the semiconductor pillar 2 in the transistor T. The bit line BL is used for charging or discharging the capacitor C in the memory 10.

[0084] In some embodiments, please continue to refer to FIG3. When the semiconductor structure D includes a plurality of transistors T, the plurality of semiconductor pillars 2 within the plurality of transistors T can be arranged sequentially at intervals along the second direction Y, which is perpendicular to the first direction X.

[0085] In some implementations, referring further to Figure 3, transistor T also includes a gate 11. Gate 11 is located on one side of the semiconductor pillar 2 within transistor T. For example, gate 11 is located on one side of the channel region 23 within the semiconductor pillar 2.

[0086] In some embodiments, the material of the gate 11 within the transistor T may include a conductive material. For example, the material of the gate 11 within the transistor T may include polysilicon, metal, metal compound, or silicide.

[0087] In some embodiments, please continue to refer to FIG3, when the memory 10 includes a semiconductor structure D and a word line WL, the word line WL in the memory 10 can be coupled to the gate 11 of the transistor T in the semiconductor structure D to control the transistor T to turn on or turn off.

[0088] Referring to Figure 3, when the word line WL in memory 10 is coupled to the gate 11 of transistor T in semiconductor structure D, the word line WL in memory 10 and the gate 11 of transistor T can be continuous conductive structures. That is, the gate 11 of transistor T can be regarded as a portion forming the word line WL, or the word line WL can be regarded as an extension of the gate 11 of transistor T.

[0089] Please refer to Figure 3. The gate 11 of transistor T within semiconductor structure D controls the electric field of semiconductor pillar 2 within transistor T by applying a voltage, thereby regulating the current. For example, the gate 11 of transistor T controls the electric field of the channel region 23 of semiconductor pillar 2 by applying a voltage, thus regulating the current.

[0090] Under high voltage, the electric field may concentrate near the sharp or irregular surface of the semiconductor pillar 2 within transistor T. This can easily cause the local electric field strength to exceed the breakdown voltage limit of the semiconductor pillar 2 material within transistor T, resulting in a breakdown phenomenon known as tip discharge. Tip discharge can easily lead to the failure of transistor T within semiconductor structure D, thereby causing a decrease in the yield of semiconductor structure D.

[0091] Based on this, in some embodiments, as shown in Figures 4 and 5, Figure 4 is a planar structural diagram of the semiconductor structure D according to some embodiments, and Figure 5 is a planar structural diagram of region AA of the semiconductor structure D in the embodiment shown in Figure 4. The semiconductor pillar 2 within the transistor T includes a curved sidewall 2a that protrudes away from the semiconductor pillar 2. The gate 11 within the transistor T is located on one side of the semiconductor pillar 2 and is disposed opposite to the curved sidewall 2a of the semiconductor pillar 2.

[0092] By including curved sidewalls 2a in the semiconductor pillar 2 within the transistor T, with the curved sidewalls 2a protruding away from the semiconductor pillar 2 and the gate 11 positioned opposite to the curved sidewalls 2a, the surface of the curved sidewalls 2a of the semiconductor pillar 2 becomes smooth due to the curved surface of the curved sidewalls 2a. This allows the electric field to be evenly distributed on the curved sidewalls 2a of the semiconductor pillar 2, preventing the electric field from concentrating in a local area of ​​the curved sidewalls 2a of the semiconductor pillar 2. This helps reduce the probability of tip discharge, thereby reducing the probability of transistor T failure within the semiconductor structure D and improving the yield of the semiconductor structure D.

[0093] On the other hand, since the curved sidewall 2a of the semiconductor pillar 2 protrudes away from the semiconductor pillar 2, the curved sidewall 2a of the semiconductor pillar 2 can transition to other sidewalls of the semiconductor pillar 2 connected to the curved sidewall 2a relatively smoothly. That is, the connection interface between the curved sidewall 2a of the semiconductor pillar 2 and the other sidewalls connected to it is relatively smooth. This can reduce the probability of electric field concentration at the connection position between the curved sidewall 2a of the semiconductor pillar 2 and the other sidewalls connected to it, which is beneficial to reduce the probability of tip discharge phenomenon, and thus beneficial to reduce the probability of transistor T failure in semiconductor structure D, thereby improving the yield of semiconductor structure D.

[0094] In some embodiments, please continue to refer to FIG5. When the semiconductor structure D includes a plurality of transistors T and the plurality of semiconductor pillars 2 within the plurality of transistors T are arranged sequentially at intervals along the second direction (i.e., the direction perpendicular to the first direction X) Y, the curved sidewalls 2a of the plurality of semiconductor pillars 2 may be located on the same side.

[0095] In some embodiments, please continue to refer to FIG5, the semiconductor pillar 2 in the transistor T further includes two first planar sidewalls 2b, which are respectively connected to the two sides of the curved sidewall 2a of the semiconductor pillar 2.

[0096] Because the curved sidewall 2a of the semiconductor pillar 2 protrudes away from the semiconductor pillar 2, when the semiconductor pillar 2 within the transistor T includes two first planar sidewalls 2b, and these two first planar sidewalls 2b are respectively connected to both sides of the curved sidewall 2a of the semiconductor pillar 2, the curved sidewall 2a of the semiconductor pillar 2 can transition to the first planar sidewall 2b of the semiconductor pillar 2 relatively smoothly. That is, the connection interface between the curved sidewall 2a and the first planar sidewall 2b of the semiconductor pillar 2 is not a sharp surface. This reduces the probability of electric field concentration at the connection point between the curved sidewall 2a and the first planar sidewall 2b of the semiconductor pillar 2, which helps reduce the probability of tip discharge, and consequently reduces the probability of transistor T failure within the semiconductor structure D, thereby improving the yield of the semiconductor structure D.

[0097] Please refer to Figure 5. In the cross-section of the semiconductor pillar 2 within the transistor T, perpendicular to the first direction (i.e., the thickness direction of the semiconductor structure D) X, the dimension h1 of one of the two first planar sidewalls 2b of the semiconductor pillar 2 can be equal to the dimension h2 of the other first planar sidewall 2b. That is, the dimensions of the two first planar sidewalls 2b of the semiconductor pillar 2 can be equal.

[0098] It should be noted that the statement "the dimension h1 of one of the two first planar sidewalls 2b of the semiconductor pillar 2 can be equal to the dimension h2 of the other first planar sidewall 2b" means that the difference between the dimension h1 of one of the two first planar sidewalls 2b of the semiconductor pillar 2 and the dimension h2 of the other first planar sidewall 2b is within a preset threshold range. The threshold range is a relatively small numerical range; for example, the threshold range could be the range of process precision required to form two first planar sidewalls 2b of equal size in the semiconductor pillar 2.

[0099] In some embodiments, referring to FIG5, the semiconductor pillar 2 within the transistor T may further include a second planar sidewall 2c. When the semiconductor pillar 2 includes two first planar sidewalls 2b, the second planar sidewall 2c of the semiconductor pillar 2 may be connected between the two first planar sidewalls 2b of the semiconductor pillar 2 and disposed opposite to the curved sidewall 2a of the semiconductor pillar 2.

[0100] In some embodiments, please continue to refer to FIG5, the shape of the cross section of the gate 11 in transistor T perpendicular to the first direction (i.e. the thickness direction of semiconductor structure D) X is arc-shaped, and the gate 11 in transistor T protrudes in a direction away from the semiconductor pillar 2 in transistor T.

[0101] Since the gate 11 and the curved sidewall 2a of the semiconductor pillar 2 within the transistor T are positioned opposite each other, and the curved sidewall 2a of the semiconductor pillar 2 protrudes away from the semiconductor pillar 2, by making the cross-section of the gate 11 within the transistor T perpendicular to the first direction (i.e., the thickness direction of the semiconductor structure D) arc-shaped, and by making the gate 11 within the transistor T protrude away from the semiconductor pillar 2, the gate 11 within the transistor T can fit more closely to the curved sidewall 2a of the semiconductor pillar 2 within the transistor T. This increases the gate control area of ​​the transistor T, enabling better channel control with a smaller subthreshold swing. Furthermore, during the off-state of the transistor T, the channel can be completely depleted, thereby reducing the off-state leakage current (It) of the transistor T. off This improves the tailing effect of transistor T, which is beneficial to improving the performance of semiconductor structure D and increasing the yield of semiconductor structure D.

[0102] In some embodiments, please continue to refer to FIG5. In the case that the semiconductor structure D includes a plurality of transistors T, and a plurality of semiconductor pillars 2 in the plurality of transistors T are arranged sequentially at intervals along the second direction (i.e., the direction perpendicular to the first direction X) Y, and the curved sidewalls 2a of the plurality of semiconductor pillars 2 are located on the same side, the gates 11 disposed opposite to the curved sidewalls 2a of the plurality of semiconductor pillars 2 are also located on the same side of the plurality of semiconductor pillars 2. The plurality of gates 11 of the plurality of transistors T can be sequentially connected to form gate lines 11a extending along the second direction (i.e., the direction perpendicular to the first direction X) Y.

[0103] Since the shape of the cross section of the gate 11 in transistor T perpendicular to the first direction (i.e. the thickness direction of semiconductor structure D) X is arc-shaped, and the gate 11 in transistor T protrudes in a direction away from the semiconductor pillar 2 in transistor T, the gate line 11a formed by the sequential connection of multiple gates 11 of multiple transistors T extending along the second direction (i.e. the direction perpendicular to the first direction X) Y is wavy.

[0104] In some embodiments, referring to FIG5, the transistor T within the semiconductor structure D further includes a gate dielectric layer 12. The gate dielectric layer 12 is located between the gate 11 within the transistor T and the curved sidewall 2a of the semiconductor pillar 2 within the transistor T. The shape of the cross section of the gate dielectric layer 12 perpendicular to the first direction (i.e., the thickness direction of the semiconductor structure D) X may be arc-shaped and bulge away from the semiconductor pillar 2.

[0105] In some embodiments, the material of the gate dielectric layer 12 may include an insulating material. For example, the material of the gate dielectric layer 12 may include silicon dioxide (SiO2) or the like.

[0106] In some embodiments, referring to FIG5, the transistor T within the semiconductor structure D further includes a connection layer 13. The connection layer 13 is located between the gate 11 and the gate dielectric layer 12 within the transistor T. The shape of the cross section of the connection layer 13 perpendicular to the first direction (i.e., the thickness direction of the semiconductor structure D) X may be arc-shaped and protrude in a direction away from the semiconductor pillar 2.

[0107] In some embodiments, the material of the interconnect layer 13 may include a conductive material. For example, the material of the interconnect layer 13 may include titanium nitride (TiN).

[0108] In some embodiments, referring to FIG5, the semiconductor structure D may further include a shielding structure 3. The shielding structure 3 is located on the side of the semiconductor pillar 2 within the transistor T away from the gate 11 within the transistor T, and is disposed opposite to the second planar sidewall 2c of the semiconductor pillar 2.

[0109] By setting a shielding structure 3 inside the semiconductor structure D, the semiconductor pillars 2 located on opposite sides of the shielding structure 3 inside the semiconductor structure D can be prevented from interfering with each other, which is beneficial to improving the performance of the transistor T, and thus beneficial to improving the performance of the semiconductor structure D.

[0110] In some embodiments, the material of the shielding structure 3 may include a conductive material. For example, the material of the shielding structure 3 may include titanium nitride (TiN).

[0111] The preparation method of the above semiconductor structure D is described in detail below.

[0112] In some embodiments, as shown in FIG6, FIG6 is a flowchart of a method for fabricating a semiconductor structure D according to some embodiments. It should be noted that the method for fabricating the semiconductor structure D shown in FIG6 is not exclusive, and other steps may be performed before, after, or between any step in the method for fabricating the semiconductor structure D shown in FIG6.

[0113] The method for fabricating semiconductor structure D includes the following steps S1.

[0114] S1: As shown in Figure 7, which is a planar structural diagram of the semiconductor structure D corresponding to step S1 in the flowchart of the fabrication method of semiconductor structure D in Figure 6, a transistor T is formed.

[0115] Step S1 in the method for fabricating semiconductor structure D includes steps S11 and S12.

[0116] S11: As shown in Figures 8 and 9, Figure 8 is a planar structural diagram of the semiconductor structure D corresponding to step S11 in the flowchart of the fabrication method of semiconductor structure D in Figure 6, and Figure 9 is a cross-sectional view of semiconductor structure D in Figure 8 along section line BB. A semiconductor pillar 2 is formed on the substrate 4, perpendicular to the substrate 4. The semiconductor pillar 2 includes curved sidewalls 2a, which bulge away from the semiconductor pillar 2.

[0117] S12: As shown in Figures 10 and 11, Figure 10 is a planar structural diagram of the semiconductor structure D corresponding to step S12 in the flowchart of the fabrication method of the semiconductor structure D in Figure 6, and Figure 11 is a cross-sectional view of the semiconductor structure D in Figure 10 along the section line CC. A gate 11 is formed on one side of the semiconductor pillar 2, and the gate 11 is disposed opposite to the curved sidewall 2a of the semiconductor pillar 2.

[0118] By including curved sidewalls 2a in the semiconductor pillar 2 within the transistor T, with the curved sidewalls 2a protruding away from the semiconductor pillar 2 and the gate 11 positioned opposite to the curved sidewalls 2a, the surface of the curved sidewalls 2a of the semiconductor pillar 2 becomes smooth due to the curved surface of the curved sidewalls 2a. This allows the electric field to be evenly distributed on the curved sidewalls 2a of the semiconductor pillar 2, preventing the electric field from concentrating in a local area of ​​the curved sidewalls 2a of the semiconductor pillar 2. This helps reduce the probability of tip discharge, thereby reducing the probability of transistor T failure within the semiconductor structure D and improving the yield of the semiconductor structure D.

[0119] On the other hand, since the curved sidewall 2a of the semiconductor pillar 2 protrudes away from the semiconductor pillar 2, the curved sidewall 2a of the semiconductor pillar 2 can transition to other sidewalls of the semiconductor pillar 2 connected to the curved sidewall 2a relatively smoothly. That is, the connection interface between the curved sidewall 2a of the semiconductor pillar 2 and the other sidewalls connected to it is relatively smooth. This can reduce the probability of electric field concentration at the connection position between the curved sidewall 2a of the semiconductor pillar 2 and the other sidewalls connected to it, which is beneficial to reduce the probability of tip discharge phenomenon, and thus beneficial to reduce the probability of transistor T failure in semiconductor structure D, thereby improving the yield of semiconductor structure D.

[0120] In some embodiments, please continue to refer to FIG6, step S11 in the method for preparing semiconductor structure D includes step S111, step S112 and step S113.

[0121] S111: As shown in Figures 12 and 13, Figure 12 is a planar structural diagram of the semiconductor structure D corresponding to step S111 in the flowchart of the fabrication method of the semiconductor structure D in Figure 6, and Figure 13 is a cross-sectional view of the semiconductor structure D in Figure 12 along the section line DD. Initial semiconductor pillars 2m are formed on the substrate 4, and the initial semiconductor pillars 2m are surrounded by a dielectric layer 62. A first trench 61 extending along a second direction Y is formed between two adjacent initial semiconductor pillars 2m, and the second direction Y is perpendicular to the thickness direction of the semiconductor structure D (i.e., the first direction X). The initial semiconductor pillars 2m include initial sidewalls 2d disposed opposite to the first trench 61.

[0122] S112: As shown in Figures 14 and 15, Figure 14 is a planar structural diagram of the semiconductor structure D corresponding to step S112 in the flowchart of the fabrication method of the semiconductor structure D in Figure 6, and Figure 15 is a cross-sectional view of the semiconductor structure D in Figure 14 along the section line EE. The dielectric layer 62 is etched towards the semiconductor pillar 2 via the first trench 61 to expose the initial sidewall 2d.

[0123] For example, the dielectric layer 62 can be etched via the first trench 61 toward the direction close to the semiconductor pillar 2 using a wet etching process to expose the initial sidewall 2d of the semiconductor pillar 2.

[0124] S113: As shown in Figures 16 and 17, Figure 16 is a planar structural diagram of the semiconductor structure D corresponding to step S113 in the flowchart of the fabrication method of the semiconductor structure D in Figure 6, and Figure 17 is a cross-sectional view of the semiconductor structure D in Figure 16 along the section line FF. The initial sidewall 2d is etched to form the curved sidewall 2a.

[0125] For example, the initial sidewall 2d of the semiconductor pillar 2 can be etched by a wet etching process to form the curved sidewall 2a of the semiconductor pillar 2.

[0126] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A semiconductor structure, comprising at least one transistor; each of the at least one transistor comprising: a semiconductor pillar extending along a first direction, the first direction being a thickness direction of the semiconductor structure; the semiconductor pillar comprising a curved sidewall, the curved sidewall being convex in a direction away from the semiconductor pillar; and a gate located at one side of the semiconductor pillar and opposite to the curved sidewall. A cross section of the gate perpendicular to the first direction is arc-shaped, and the gate is convex in a direction away from the semiconductor pillar.

2. The semiconductor structure of claim 1, wherein, 3.The semiconductor structure of claim 2, further comprising a gate dielectric layer located between the gate and the curved sidewall; A cross section of the gate dielectric layer perpendicular to the first direction is arc-shaped, and the gate dielectric layer is convex in a direction away from the semiconductor pillar. 4.The semiconductor structure of claim 3, further comprising a connection layer located between the gate and the gate dielectric layer; A cross section of the connection layer perpendicular to the first direction is arc-shaped, and the connection layer is convex in a direction away from the semiconductor pillar. The semiconductor pillar further comprises two first planar sidewalls respectively connected to two sides of the curved sidewall.

5. The semiconductor structure according to any one of claims 1 to 4, wherein In a cross section of the semiconductor pillar perpendicular to the first direction, the two first planar sidewalls are equal in size.

6. The semiconductor structure of claim 5, wherein, The semiconductor pillar further comprises a second planar sidewall connected between the two first planar sidewalls and opposite to the curved sidewall; 7. The semiconductor structure of claim 5 or 6, wherein, The semiconductor structure further comprises a shielding structure located at a side of the semiconductor pillar away from the gate and opposite to the second planar sidewall. The at least one transistor comprises a plurality of transistors, a plurality of semiconductor pillars of the plurality of transistors are arranged in sequence and spaced apart along a second direction, and curved sidewalls of the plurality of semiconductor pillars are located at the same side; the second direction is perpendicular to the first direction.

8. The semiconductor structure of any one of claims 1-7, wherein, A plurality of gates of the plurality of transistors are connected in sequence to form a gate line extending along the second direction, the gate line being wavy.

9. The semiconductor structure of claim 8, wherein, 10.A method for manufacturing a semiconductor structure, comprising forming a transistor; the forming a transistor comprising: forming a semiconductor pillar on a substrate, the semiconductor pillar being perpendicular to the substrate; the semiconductor pillar comprising a curved sidewall, the curved sidewall being convex in a direction away from the semiconductor pillar; forming a gate at one side of the semiconductor pillar, the gate being opposite to the curved sidewall. The forming a semiconductor pillar comprising:

11. The method of producing a semiconductor structure according to claim 10, wherein forming initial semiconductor pillars on the substrate, the initial semiconductor pillars being surrounded by a dielectric layer; a first trench extending along a second direction is formed between two adjacent initial semiconductor pillars, the second direction being perpendicular to a thickness direction of the semiconductor structure; the initial semiconductor pillars comprising initial sidewalls opposite to the first trench; etching the dielectric layer via the first trench to expose the initial sidewalls; etching the initial sidewalls to form the curved sidewall. 12.A memory, comprising: the semiconductor structure according to any one of claims 1-9; and a capacitor electrically connected to a transistor in the semiconductor structure. 13.A memory system, comprising: ​ ​ The memory of claim 12; And A controller, electrically connected with the memory.

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