Light-emitting diode and light-emitting device

Abstract

Provided in the present application is a light-emitting diode, comprising: a semiconductor stack, which comprises a first semiconductor layer, an active layer and a second semiconductor layer that are stacked in sequence; a transparent conductive layer, which is formed on the second semiconductor layer; a first pad electrode, which is formed on the first semiconductor layer and electrically connected to the first semiconductor layer; and a second pad electrode, which is formed on the second semiconductor layer and electrically connected to the second semiconductor layer, wherein the distance between the transparent conductive layer and the second semiconductor layer ranges from 0.5 μm to 3 μm, and the distance therebetween is equal at all points.

Description

Light emitting diode and light emitting device TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor manufacturing, in particular, to a light emitting diode and a light emitting device. BACKGROUND

[0002] Light emitting diodes are used in various products such as large back light units (BLUs), general lighting, and electronic devices, and are also used in various small household appliances and indoor decoration products. Furthermore, light emitting diodes are not only simply used as light sources, but also used for various purposes such as conveying information and evoking aesthetics. SUMMARY

[0003] The present application provides a light emitting diode, comprising a semiconductor stack, including a first semiconductor layer, an active layer, and a second semiconductor layer stacked in sequence; a transparent conductive layer formed on the second semiconductor layer; a first pad electrode formed on the first semiconductor layer and electrically connected to the first semiconductor layer; and a second pad electrode formed on the second semiconductor layer and electrically connected to the second semiconductor layer; wherein the distance between the transparent conductive layer and the second semiconductor layer is between 0.5 and 3 μm, and the distance between the transparent conductive layer and the second semiconductor layer is equal everywhere.

[0004] The present application also provides a light emitting diode, comprising a semiconductor stack, including a first semiconductor layer, an active layer, and a second semiconductor layer stacked in sequence; a transparent conductive layer formed on the second semiconductor layer; a first pad electrode formed on the first semiconductor layer and electrically connected to the first semiconductor layer; and a second pad electrode formed on the second semiconductor layer and electrically connected to the second semiconductor layer; wherein the surface of the second semiconductor layer includes a first side, a second side, and a first corner connecting the first side and the second side, the projection of the first pad electrode on the semiconductor stack covers the projection of the first corner on the semiconductor stack; the radius of the rounded corner of the first corner is ≥ 2.5 μm, the distance between the first corner and the transparent conductive layer is a first distance D1, the distance between the first side or the second side and the transparent conductive layer is a second distance D2, and D1 is between 75% D2 and 125% D2.

[0005] The present application also provides a light emitting device, comprising a substrate; a plurality of light emitting diodes formed on the substrate; and an encapsulation layer covering the light emitting diodes, wherein the light emitting diodes are the light emitting diodes described above. BRIEF DESCRIPTION OF DRAWINGS

[0006] FIG. 1 is a schematic top view of a light emitting diode chip used to illustrate an embodiment of the present application;

[0007] FIG. 2 is a schematic plan view of a light emitting diode chip to explain an embodiment of the present application;

[0008] FIG. 3 is an enlarged schematic view of regions I, II, and III of FIG. 2;

[0009] FIG. 4 is a schematic sectional view along FIG. 1;

[0010] FIG. 5 is a schematic plan view of a light emitting diode chip to explain another embodiment of the present application;

[0011] FIG. 6 is an enlarged schematic view of regions IV, V, and VI of FIG. 5

[0012] FIG. 7 is a schematic view of a light emitting device according to an embodiment of the present application;

[0013] FIG. 8 is a schematic plan view of a light emitting diode chip according to the related art. DETAILED DESCRIPTION

[0014] In order to make the description more concise, the projections described below are projections with reference to a semiconductor stack as a reference plane, and projections in the third direction Z.

[0015] FIG. 1 and FIG. 2 are schematic plan views of a light emitting diode chip to explain an embodiment of the present application, and FIG. 3 is an enlarged schematic view of regions I, II, and III of FIG. 2. FIG. 4 is a schematic sectional view along FIG. 1.

[0016] As shown in FIG. 1 and FIG. 4, the light emitting diode chip according to the embodiment includes a substrate 110, a semiconductor stack 120, a transparent conductive layer 130, a first contact electrode 141, a second contact electrode 142, an insulating layer 150, a first pad electrode 161, and a second pad electrode 162.

[0017] The substrate 110 can be an insulating substrate or a conductive substrate. The substrate 110 can be a growth substrate to grow the semiconductor stack 120, and can include a sapphire substrate, a silicon carbide substrate, a silicon substrate, a gallium nitride substrate, an aluminum nitride substrate, etc. In addition, the substrate 110 can include a plurality of protrusions formed on at least a portion of a region of an upper surface thereof. The plurality of protrusions of the substrate 110 can be formed in a regular or irregular pattern. For example, the substrate 110 can be a patterned sapphire substrate (PSS) including a plurality of protrusions formed on an upper surface. The substrate 110 can have a thickness in a range of approximately 100 μm to 200 μm.

[0018] As shown in FIG. 2, the substrate 110 has a first edge Yl, a second edge Y2, a third edge Y3, and a fourth edge Y4 connected in this order. The edges of the substrate 110 can be equivalent to the edges of the light emitting diode. The first edge Yl and the third edge Y3 extend in a first direction X, and the second edge Y2 and the fourth edge Y4 extend in a second direction Y. The thickness direction of the substrate 110 is a third direction Z.

[0019] The semiconductor stack 120 is located on the substrate 110. In addition, the area of the lower surface of the semiconductor stack 120 can be smaller than the area of the upper surface of the substrate 110, and the upper surface of the substrate 110 can be exposed along the outer edge of the semiconductor stack 120. Some of the plurality of protrusions (not shown) of the upper surface of the substrate 110 are located between the semiconductor stack 120 and the substrate 110, and the plurality of protrusions (not shown) not covered by the semiconductor stack 120 are exposed at the periphery of the semiconductor stack 120.

[0020] The semiconductor stack 120 includes a first semiconductor layer 121, a second semiconductor layer 123 located on the first semiconductor layer 121, and an active layer 122 located between the first semiconductor layer 121 and the second semiconductor layer 123, stacked in this order in the third direction Z of the substrate 110. The overall thickness of the semiconductor stack 120 can be in the range of approximately 3 μm to 10 μm.

[0021] The first semiconductor layer 121, the active layer 122, and the second semiconductor layer 123 can include a III-V nitride-based semiconductor, for example, a nitride-based semiconductor such as (Al, Ga, In)N. The first semiconductor layer 121 can include an n-type impurity (e.g., Si, Ge, Sn), and the second semiconductor layer 123 can include a p-type impurity (e.g., Mg, Sr, Ba). In addition, this can be reversed. The active layer 122 can include a multi-layer quantum well structure (MQW) capable of adjusting the composition ratio of the nitride-based semiconductor in a manner to emit a desired wavelength. In particular, in the present embodiment, the second semiconductor layer 123 can be a p-type semiconductor layer.

[0022] As shown in FIG. 2, the second semiconductor layer 123 surface includes a first edge El, a second edge E2, a third edge E3, and a fourth edge E4 connected in this order, a first corner Cl connecting the first edge El and the second edge E2, a second corner C2 connecting the second edge E2 and the third edge E3, a third corner C3 connecting the third edge E3 and the fourth edge E4, and a first corner C4 connecting the fourth edge E4 and the first edge El.

[0023] The first edge El and the third edge E3 extend in the first direction X, and the second edge E2 and the fourth edge E4 extend in the second direction Y. In an embodiment, the second edge E2 is composed of a plurality of curved lines, and as a whole can be regarded as extending in the second direction Y. The first edge El, the third edge E3, and the fourth edge E4 are composed of straight lines.

[0024] The semiconductor stack 120 includes a mesa M exposing a portion of the surface of the first semiconductor layer 121. Specifically, the semiconductor stack 120 can be formed by removing the second semiconductor layer 123, the active layer 122, and a portion of the first semiconductor layer 121 by etching or the like to form the mesa M exposing a portion of the surface of the first semiconductor layer 121. The mesa M can be located outside of the second semiconductor layer 123 and surround the second semiconductor layer 123. In another embodiment, the mesa M (a through-hole or a through-groove) can be formed inside the semiconductor stack 120 to expose a portion of the surface of the first semiconductor layer 121.

[0025] The mesa M includes a first region M1 and a second region M2. The first region M1 is distributed along the first edge E1, the third edge E3, and the fourth edge E4, and the second region M2 is distributed along the second edge E2.

[0026] As shown in FIGS. 1 and 4, a transparent conductive layer 130 is located on the second semiconductor layer 123. The transparent conductive layer 130 can be ohmic contact to the second semiconductor layer 123. The transparent conductive layer 130 can include, for example, a light-transmissive conductive oxide layer such as Indium Tin Oxide (ITO), Zinc Oxide (ZnO), Zinc Indium Tin Oxide (ZITO), Zinc Indium Oxide (ZIO), Zinc Tin Oxide (ZTO), Gallium Indium Tin Oxide (GITO), Gallium Indium Oxide (GIO), Gallium Zinc Oxide (GZO), Aluminum doped Zinc Oxide (AZO), Fluorine Tin Oxide (FTO), or the like. The conductive oxide can also include various dopants.

[0027] In the present embodiment, the thickness of the transparent conductive layer 130 is between 50 nm and 200 nm. The size of the light emitting diode is less than 300 μm * 150 μm, and if the thickness of the transparent conductive layer is less than 50 nm, the current can not be spread out, resulting in the light emitting diode not being able to obtain good ESD capability. If the thickness of the transparent conductive layer 130 is greater than 200 nm, the transparent conductive layer 130 will absorb light and cause loss.

[0028] The first contact electrode 141 is formed on the first semiconductor layer 121, and specifically, the first contact electrode 141 is formed on the second region M2. The first contact electrode 141 ohmically contacts the first semiconductor layer 121 and disperses current. To this end, the first contact electrode 141 includes a metal layer that ohmically contacts the first semiconductor layer 121.

[0029] In an embodiment, the first contact electrode 141 can be formed in a block shape in the second region M2.

[0030] The first contact electrode 141 does not overlap the active layer 122 or the second semiconductor layer 123 of the mesa M, and thus an insulating layer for insulating the first contact electrode 141 from the second semiconductor layer 123 is omitted. The first contact electrode 141 can be formed to the semiconductor stack 120 in which the transparent conductive layer 130 is formed, for example, using a lift-off process. At this time, the second contact electrode 142 described below can also be formed together.

[0031] The second contact electrode 142 is located on the transparent conductive layer 130 and electrically connected to the transparent conductive layer 130, thereby contributing to the dispersion of current in the second semiconductor layer 123.

[0032] The second contact electrode 142 can include a connection portion 142c and an extension portion 142b extending from the connection portion 142c.

[0033] In order to reduce light absorption caused by the second contact electrode 142, the second contact electrode 142 is formed on a part of the area of the transparent conductive layer 130 with limitation. The entire area of the second contact electrode 142 does not exceed 2 / 10 of the area of the transparent conductive layer 130. The second contact electrode 142 can include a start portion 142a, an extension portion 142b, and a connection portion 142c connecting the start portion 142a and the extension portion 142b.

[0034] The extension portion 142b has a width wider than that of the start portion 142a and the connection portion 142c, and the start portion 142a has a width wider than that of the connection portion 142c. In order to disperse current, the extension portion 142b can have various shapes.

[0035] The first contact electrode 141 and the second contact electrode 142 can be formed together using the same material in the same process, and thus can have the same layer structure as each other. For example, the first contact electrode 141 and the second contact electrode 142 can include an Al reflective layer and can include Au. Specifically, the first contact electrode 141 and the second contact electrode 142 can have a layer structure of Cr / Al / Ti / Ni / Ti / Ni / Au / Ti. In another embodiment, in order to reduce costs, the first contact electrode 141 and the second contact electrode 142 can not include Au.

[0036] The insulating layer 150 is formed on the semiconductor stack 120, and specifically, the insulating layer 150 can cover the semiconductor stack 120, the transparent conductive layer 130, the first contact electrode 141, and the second contact electrode 142. The insulating layer 150 has a first opening OP1 and a second opening OP2. The first opening OP1 exposes a part of the surface of the first contact electrode 141, and the second opening OP2 exposes a part of the surface of the second contact electrode 142, wherein the second opening OP2 exposes a part of the surface of the start portion 142a of the second contact electrode 142. The size of the first opening OP1 is smaller than the area of the first contact electrode 141, and the size of the second opening OP2 is smaller than the area of the second contact electrode start portion 142a.

[0037] The insulating layer 150 includes a distributed Bragg reflector. The distributed Bragg reflector can be formed by repeatedly laminating dielectric layers having different refractive indexes, which can include TiO2, SiO2, HfO2, ZrO2, Nb2O5, MgF2, etc. For example, the insulating layer 150 can have a configuration in which TiO2 layers / SiO2 layers are alternately laminated. The distributed Bragg reflector is fabricated in a manner to reflect light generated in the active layer 122, and a plurality of pairs are formed in order to improve reflectivity. In the present embodiment, the distributed Bragg reflector can include 10 to 25 pairs. The insulating layer 150 can include, together with the distributed Bragg reflector, another insulating layer, for example, in order to improve adhesion of the distributed Bragg reflector to its underlying layer, an interface layer at the lower portion of the distributed Bragg reflector and a protective layer covering the distributed Bragg reflector can be included. The interface layer can be formed of, for example, a SiO2 layer, and the protective layer can be formed of SiNx. The layer formed of SiNx has excellent moisture resistance, and thus can protect the light emitting diode chip from moisture.

[0038] The insulating layer 150 can have a thickness of about 2 to 5 μm. The reflectivity of the distributed Bragg reflector pair to light generated in the active layer 122 can be 90% or more, and a reflectivity close to 100% can be provided by controlling the kind, thickness, lamination period, etc. of the plurality of dielectric layers forming the distributed Bragg reflector. Further, the distributed Bragg reflector can also have a high reflectivity to other visible light in addition to light generated in the active layer 122.

[0039] The first pad electrode 161 and the second pad electrode 162 are located on the insulating layer 150, the first pad electrode 161 is in contact with the first contact electrode 141 through the first opening OP1, and thus is electrically connected to the first semiconductor layer 121, and the second pad electrode 162 is in contact with the second contact electrode 142 through the second opening OP2, and thus is electrically connected to the second semiconductor layer 123.

[0040] The first pad electrode 161 and the second pad electrode 162 can be formed together in the same process using the same material, and thus can have the same layer structure. The thickness of the first pad electrode 161 and the second pad electrode 162 can be thinner than the thickness of the insulating layer 150, for example, can be formed to a thickness of about 2 μm. The thickness of the first pad electrode 161 and the second pad electrode 162 can also be thinner than the thickness of the insulating layer 150,

[0041] The first pad electrode 161 and the second pad electrode 162 are arranged along the first direction X.

[0042] In an embodiment, as shown in FIG. 1, the first pad electrode 161 projects to cover the first corner C1 and the second corner C2, and the second pad electrode 162 projects to cover the third corner C2 and the fourth corner C4. Specifically, the first pad electrode 161 projects to cover the second edge E2, and part of the first edge E1 and the third edge E3, and the second pad electrode 162 projects to cover the fourth edge E4, and part of the first edge E1 and the third edge E3. In this way, the surface area of the first pad electrode 161 and the second pad electrode 162 can be increased, and the pushing force of the first pad electrode 161 and the second pad electrode 162 in the subsequent die bonding process can be greatly improved, that is, the bonding force between the first pad electrode 161 and the second pad electrode 162 and the substrate of the die bonding can be increased, which can prevent and avoid the light emitting element from falling off the substrate, and improve the reliability.

[0043] In an embodiment, as shown in FIG. 1, the first pad electrode 161 has a first long side 161a, a first short side 161b, a second long side 161c and a second short side 161d connected in sequence, the extension direction of the first short side 161b and the second short side 161d is consistent with the extension direction of the second edge E1 of the second semiconductor layer (the first direction X), and the extension direction of the first long side 161a is consistent with the extension direction of the second edge E2 of the second semiconductor layer (the second direction Y). The first long side 161a, the first short side 161b and the second short side 161d of the first pad electrode 161 are projected in the mesa M. Similarly, the first long side, the first short side and the second short side of the second pad electrode 162 are projected in the mesa M. Among them, the second long side 161c of the first pad electrode 161 and the second long side projected on the semiconductor stack 120 are projected in the second semiconductor layer. Through the design, the first pad electrode 161 and the second pad electrode 162 will not extend to the area of the substrate 110 not covered by the semiconductor stack 120. Therefore, during the cutting process of the light emitting diode, the area where the insulating layer 150 is cracked at the area of the substrate 110 not covered by the semiconductor stack 120 will not be blocked by the first pad electrode 161 and the second pad electrode 162, so that the cracking area is easy to be identified in the subsequent AOI detection, the yield of the light emitting diode is improved, the light emitting diode with cracking is avoided to enter the die bonding stage, and the tin paste after die bonding is also avoided to enter the cracking area, so as to cause the light emitting diode to leak, which is beneficial to improve the reliability of the device.

[0044] As shown in FIG. 8, which is a schematic top view of a light emitting diode chip in the prior art, the schematic top view ignores the transparent conductive layer and the insulating layer. In the prior art, in order to maximize the light emitting area of the light emitting diode, the mesa second area M2 is usually arranged at the corner between the second edge Y2 and the third edge Y3 of the light emitting diode. Among them, the overlapping area of the projection of the first pad electrode 161 and the projection of the second semiconductor layer 123 is S1, the overlapping area of the projection of the first pad electrode 161 and the projection of the first semiconductor layer 121 (the mesa second area M2) is S2, and the overlapping area S1 and the overlapping area S2 in the surface of the first pad electrode 161 are arranged along the second direction Y. As the size of the light emitting diode becomes smaller and smaller, the size of the light emitting diode is less than 300 μm*150 μm, especially the short side is less than 150 μm, the area of the pad electrode is also limited to become smaller and smaller. Due to the limited area of the pad electrode, and the mesa second area M2 needs to satisfy that the first contact electrode 161 is formed thereon, therefore the areas of S1 and S2 are approximately equal. However, S1 and S2 are mainly arranged along the second direction Y, and the tension of the die bonding material such as tin paste will cause the light emitting diode to be pulled in the second direction Y, so that the light emitting diode is prone to shift or skew in the second direction Y, thereby greatly affecting the display effect of the client.

[0045] In the present application, referring to FIG. 1 and FIG. 2, the mesa second region M2 is axisymmetric along a virtual center parallel line C, the first contact electrode 141 formed in the mesa second region M2 is axisymmetric along the virtual center parallel line C, the first opening OP1 of the insulating layer formed on the first contact electrode 141 and exposing part of the surface of the first contact electrode 141 is axisymmetric along the virtual center parallel line C. The virtual center parallel line C is parallel to and located at the middle position between the first edge Y1 and the third edge Y3 of the substrate 110, or in other words, the virtual center parallel line C is located at the middle position between the first edge Y1 and the third edge Y3 of the light emitting diode. Wherein, as shown in FIG. 1 and FIG. 2, the mesa second region M2 is composed of part of the first edge X1, the second edge X2, part of the third edge X3 of the first semiconductor layer 121 and the extension of the second long side 161c of the first pad electrode in the second direction. In a preferred embodiment, the light emitting diode is axisymmetric along the virtual center parallel line C.

[0046] Referring to FIG. 1 and FIG. 2, the projection of the first pad electrode 161 and the projection of the second semiconductor layer 123 overlap region S1, the projection of the first pad electrode 161 and the projection of the first semiconductor layer 121 (mesa M) overlap region S2, the overlap region S1 and the overlap region S2 are arranged along the first direction X, and the overlap region S1 and the overlap region S2 are axisymmetric along the virtual center parallel line C. The tension of the die bonding material such as solder paste is mainly affected by the area of the first pad electrode 161 and the second pad electrode 162 in the first direction X (the area of the first pad electrode 161 and the second pad electrode 162 is equal, and the tension is evenly distributed in the first direction X), and is not affected by the arrangement of the overlap region S1 and the overlap region S2 along the first direction X. In the second direction Y, since the overlap region S1 and the overlap region S2 are axisymmetric along the virtual center parallel line C, the tension of the die bonding material such as solder paste in the second direction Y is evenly distributed, so that the light emitting diode is not easily offset or skewed in the second direction Y.

[0047] In an embodiment, referring to FIG. 1 and FIG. 2, the area of S1 is less than the area of S2. More specifically, the area of S1 / the area of the first pad electrode 161 is less than 40%, and the area of S2 / the area of the first pad electrode 161 is greater than 60%, and theoretically the area of the first pad electrode 161 = the area of S1 + the area of S2. In a preferred embodiment, the area of S1 / the area of the first pad electrode 161 is less than 30%, and the area of S2 / the area of the first pad electrode 161 is greater than 70%. By controlling S1 to be much less than S2, and avoiding S1 and S2 being approximately equal, the probability of the light emitting diode being offset or skewed can be reduced. Where the size of the light emitting diode is greater than 300 μm*150 μm, controlling S1 to be greater than S2 can also reduce the probability of the light emitting diode being offset or skewed. However, the size of the light emitting diode in the present application is limited (size less than 300 μm*150 μm), and if S1 is controlled to be greater than S2, the area of the first contact electrode 161 is too small, which is not conducive to forming an ohmic contact.

[0048] In an embodiment, referring to FIG. 1 and FIG. 2, the radius of the rounded corner of the first corner C1 or the second corner C2 is greater than 2 μm. The first corner C1 of the second semiconductor layer 123 has an extension line A perpendicular to the first electrode first short side 161b, and the extension line A has the minimum distance from the first long side 161a of the first pad electrode 161. The extension line A overlaps the first contact electrode 141, and the extension line A does not overlap the insulating layer first opening OP1. Due to the limitation of the short side of the light emitting diode, in the embodiment of the present application, the short side of the light emitting diode is less than 150 nm, and it is necessary to ensure that the extension line A overlaps the first contact electrode 141, the extension line A does not overlap the insulating layer first opening OP1, and the radius of the rounded corner of the first corner C1 or the second corner C2 is greater than 2 μm, so as to ensure that the first corner C1 or the second corner C2 does not have a sharp corner, which can ensure that the current has sufficient space to diffuse at this position. If the first corner C1 or the second corner C2 has a sharp corner, it can cause the ESD capability of the first corner C1 or the second corner C2 to be poor, thereby causing a sharp end leakage effect.

[0049] In one embodiment, referring to FIG. 1 and FIG. 2, the transparent conductive layer 130 includes a fifth corner C5 adjacent to the first corner C1 of the second semiconductor layer 123, and the fifth corner C5 has a fillet radius greater than the fillet radius 1 μm of the first corner C1. The fifth corner C5 has an extension line B perpendicular to the first short side 161b of the first electrode 161, and the extension line B has a minimum distance to the first long side 161a of the first pad electrode 161. The extension line B does not overlap the first contact electrode 141, and the extension line B does not overlap the first opening OP1 of the insulating layer. By this design, the light emitting diode can have a maximum light emitting area while the first corner C1, the second corner C2 and the fifth corner C5 do not form sharp corners, which can cause poor ESD capability and sharp point leakage effect.

[0050] In one embodiment, referring to FIG. 1 and FIG. 2, the minimum distance between the extension line A and the first long side 161a of the first pad electrode 161 is greater than half of the length of the first short side 161b of the first pad electrode 161. The projection of the first pad electrode covers less than half of the length of the first short side 161b of the first pad electrode 161 on the first edge E1 of the second semiconductor layer 123.

[0051] In one embodiment, as shown in FIG. 3, which is an enlarged view of the region I, the region II and the region III in FIG. 2. The distance between the first corner C1 and the transparent conductive layer 130 is the first distance D1, the distance between the first edge E1 and the transparent conductive layer 130 is the second distance D2, and the distance between the fourth corner C4 and the transparent conductive layer 130 is the third distance D3. The first distance D1 is greater than the second distance D2, the third distance D3 is greater than the second distance D2, and the third distance D3 is greater than the second distance D2. Herein, D1 is between 1 μm and 5 μm, and D2 is between 0 μm and 4 μm. If the second distance is 0, the light emitting diode can have a leakage current, which can reduce the reliability.

[0052] However, since the size of the light emitting diode is less than 300 μm*150 μm, the light emitting area (i.e. the area of the active layer 122, which is equivalent to the area of the second semiconductor layer 123) is also getting smaller and smaller, and the area of the transparent conductive layer 130 formed on the second semiconductor layer 123 is also limited. In order to make the transparent conductive layer 130 spread the current as much as possible, on one hand, the thickness of the transparent conductive layer 130 is increased (the thickness of the transparent conductive layer is controlled in the range of 50 nm to 200 nm), and on the other hand, the distance between the transparent conductive layer 130 and the second semiconductor layer 123 is made as small as possible to expand the area of the transparent conductive layer 130.

[0053] In one embodiment, as shown in FIG. 5 and FIG. 6, FIG. 5 is a schematic top view of a light emitting diode chip used to illustrate another embodiment of the present application, and FIG. 6 is an enlarged view of region IV, region V, and region VI in FIG. 5. The distance between the transparent conductive layer 130 and the second semiconductor layer 123 is between 0.5 and 3 μm. The distance between the transparent conductive layer 130 and the second semiconductor layer 123 is controlled to be between 0.5 and 3 μm, and the area of the transparent conductive layer 130 is increased as much as possible while ensuring that the transparent conductive layer 130 and the second semiconductor layer 123 have a safe distance, i.e., the reliability of the light emitting diode is ensured. In addition, the distance between the transparent conductive layer 130 and the second semiconductor layer 123 is equal everywhere. In particular, at the corners (the first corner C1, the second corner C2, the third corner C3, or the fourth corner C4), for example, the first distance D1 between the first corner C1 and the transparent conductive layer 130, the second distance D2 between the first side E1 and the transparent conductive layer 130, and the third distance D3 between the fourth corner C4 and the transparent conductive layer 130, the first distance D1 is equal to the second distance D2, and the third distance D3 is equal to the second distance D2. Since the distance between the transparent conductive layer 130 and the second semiconductor layer 123 is in the order of microns, and there are measurement instruments and human errors, the first distance D1 is between 75% D2 and 125% D2, and the third distance D3 is between 75% D2 and 125% D2, which are all within the range of the first distance D1 being equal to the second distance D2 and the third distance D3 being equal to the second distance D2. Similarly, the distance between the transparent conductive layer 130 and the second semiconductor layer 123 is equal everywhere, which also satisfies the measurement error being within ±25%.

[0054] In order to ensure that the distance between the transparent conductive layer 130 and the second semiconductor layer 123 is equal everywhere, in the present application, the semiconductor stack 120 and the transparent conductive layer 130 use the same yellow light mask, and the transparent conductive layer 130 is etched inwardly using the principle of isotropic wet etching. By controlling the etching time and rate, the distance between the transparent conductive layer 130 and the second semiconductor layer 123 can be controlled to be between 0.5 and 3 μm, and it can be ensured that the distance between the transparent conductive layer 130 and the second semiconductor layer 123 is equal everywhere. Even at some corners, it can be ensured that the distance between the transparent conductive layer 130 and the second semiconductor layer 123 is equal everywhere.

[0055] In one embodiment, as shown in FIG. 5, no current blocking layer (insulating layer) is provided between the transparent conductive layer 130 and the second semiconductor layer 123, so that the transparent conductive layer 130 and the second semiconductor layer 123 are in full contact.

[0056] In an embodiment, as shown in FIG. 5, the corner radius of the four corners of the second semiconductor layer 123 is greater than the corner radius of the four corners of the transparent conductive layer 130. At the same time, it is necessary to ensure that the corner radius of the four corners of the second semiconductor layer 123 is greater than 2.5 μm, and the corner radius of the four corners of the transparent conductive layer 130 is greater than 1 μm, otherwise the first corner C1 or the second corner C2 of the second semiconductor layer 123 appears a sharp end, so that the fifth corner C5 adjacent to the first corner C1 or the sixth corner C6 adjacent to the second corner C2 will appear a more extreme sharp end, so that the sharp end leakage and other problems may occur at this point.

[0057] In an embodiment, a light emitting device is provided, referring to FIG. 7, the light emitting device includes a substrate 10, a plurality of light emitting diodes 20 formed on the substrate 10, and an encapsulation layer 30 covering the plurality of light emitting diodes 20. The light emitting diodes 20 can be fixed on the substrate 10 by means of tin paste or the like. Among them, the light emitting diode 20 is the light emitting diode in the above embodiment, and also has the above technical effects.

Claims

1. A light emitting diode, comprising: a semiconductor stack comprising a first semiconductor layer, an active layer, and a second semiconductor layer stacked in sequence; a transparent conductive layer formed on the second semiconductor layer; a first pad electrode formed on the first semiconductor layer and electrically connected to the first semiconductor layer; a second pad electrode formed on the second semiconductor layer and electrically connected to the second semiconductor layer; wherein a distance between the transparent conductive layer and the second semiconductor layer is between 0.5 and 3 μm, and the distance between the transparent conductive layer and the second semiconductor layer is uniform everywhere.

2. The light emitting diode of claim 1, wherein, a surface of the second semiconductor layer comprises a first side, a second side, and a first corner connecting the first side and the second side, a projection of the first pad electrode on the semiconductor stack covers a projection of the first corner on the semiconductor stack, the transparent conductive layer comprises a fifth corner adjacent to the first corner, a fillet radius of the first corner is greater than a fillet radius of the fifth corner.

3. The light emitting diode of claim 2, wherein, the fillet radius of the first corner is greater than or equal to 2.5 μm, and the fillet radius of the fifth corner is greater than or equal to 1 μm.

4. The light emitting diode of claim 1, wherein, the transparent conductive layer is in full contact with the second semiconductor layer. 5.A light emitting diode, comprising: a semiconductor stack comprising a first semiconductor layer, an active layer, and a second semiconductor layer stacked in sequence; a transparent conductive layer formed on the second semiconductor layer; a first pad electrode formed on the first semiconductor layer and electrically connected to the first semiconductor layer; a second pad electrode formed on the second semiconductor layer and electrically connected to the second semiconductor layer; wherein a surface of the second semiconductor layer comprises a first side, a second side, and a first corner connecting the first side and the second side, a projection of the first pad electrode on the semiconductor stack covers a projection of the first corner on the semiconductor stack; a fillet radius of the first corner is greater than or equal to 2.5 μm, a distance between the first corner and the transparent conductive layer is a first distance D1, a distance between the first side or the second side and the transparent conductive layer is a second distance D2, and D1 is between 75% D2 and 125% D2.

6. The light emitting diode of claim 5, wherein, D1 is between 0.5 μm and 3 μm, and D2 is between 0.5 μm and 3 μm.

7. The light emitting diode of claim 5, wherein the first and second semiconductor layers are formed of a nitride semiconductor. the transparent conductive layer comprises a fifth corner adjacent to the first corner of the second semiconductor layer, a fillet radius of the fifth corner is greater than or equal to 1 μm, and the fillet radius of the fifth corner is less than the fillet radius of the first corner.

8. The light emitting diode of any of claims 1 or 5, wherein the first and second layers of the first and second superlattices are made of InGaN. the surface of the second semiconductor layer comprises a first side, a second side, a third side, and a fourth side, and further comprises a first corner connecting the first side and the second side, a second corner connecting the second side and the third side, a third corner connecting the third side and the fourth side, and a fourth corner connecting the fourth side and the first side, the first pad electrode has a first long side, a first short side, a second long side, and a second short side connected in sequence, an extension direction of the first short side is consistent with an extension direction of the first side of the second semiconductor layer, and an extension direction of the first long side is consistent with an extension direction of the second side of the second semiconductor layer.

9. The light emitting diode of claim 8, wherein, A projection of the first pad electrode on the semiconductor stack covers a projection of the second side on the semiconductor stack, and a projection of the part of the first side and the third side on the semiconductor stack, and a projection of the second pad electrode on the semiconductor stack covers a projection of the fourth side on the semiconductor stack, and a projection of the part of the first side and the third side on the semiconductor stack.

10. The light emitting diode of claim 8, wherein, A projection of the first pad electrode on the semiconductor stack covers a projection of the first corner and the second corner on the semiconductor stack, and a projection of the second pad electrode on the semiconductor stack covers a projection of the third corner and the fourth corner on the semiconductor stack.

11. The light emitting diode of claim 8, wherein, The first corner has a minimum distance between an extension line A perpendicular to the first short side of the first pad electrode and a first long side of the first pad electrode, and the extension line A of the first corner overlaps the first contact electrode.

12. The light emitting diode of claim 11, wherein, The minimum distance between the extension line A and the first long side of the first pad electrode is greater than half of the length of the first short side of the first pad electrode.

13. The light emitting diode of claim 11, wherein, A length of the projection of the first pad electrode on the semiconductor stack covering the first side is less than half of the length of the first short side of the first pad electrode.

14. The light emitting diode of any of claims 1 or 5, wherein, The light emitting diode comprises a first edge, a second edge, a third edge and a fourth edge connected in sequence, and the light emitting diode is symmetrical along a central parallel line axis, and the central parallel line is parallel and located at a middle position between the first edge and the third edge.

15. The light emitting diode of any of claims 1 or 5, wherein, The transparent conductive layer has a thickness of 50-200 nm.

16. The light emitting diode of any of claims 1 or 5, wherein, The light emitting diode has a size of less than 300 μm*150 μm.

17. A light emitting device, comprising: a substrate; a plurality of light emitting diodes according to any one of claims 1 or 5, formed on the substrate; an encapsulation layer covering the light emitting diodes.

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