Semiconductor device

Abstract

In one embodiment of the semiconductor device (1) at an emitter side (3), a semiconductor body (2) comprises a plurality of emitter regions (31) and a plurality of well regions (32), each of the emitter regions (31) is embedded in one of the well regions (32), at a collector side (4), the semiconductor body (2) comprises a pilot region (41) which is uniformly of a same conductivity type and a mixed region (42) which is of of two conductivity types and which surrounds the pilot region (41), and a first area occupancy of the emitter side (3) by the emitter regions (31) is larger in the pilot region (41) than in the mixed region (42) and / or a second area occupancy of the well regions (32) by the emitter regions (31) is smaller in the pilot region (41) than in the mixed region (42).

Description

[0001] P2024,0624 WO N / P240041WO01 May28,2025 -1 - Description SEMICONDUCTOR DEVICE A semiconductordevice isprovided.Documents EP 2249392 A2 and WO 2015 / 097157 A1 ref er to Bi-mode Insulated Gate Transistors,BiGTs.A problem to be solved is to provide a semiconducto r devicethathasimproved electricalproperties.This object is achieved, inter alia, by a semicondu ctordevice as defined in the independent claim. Exempla ry furtherdevelopments constitute the subject-matter of the d ependentclaims.For example, the semiconductor device described her eincomprises a plurality of emitter regions at an emit ter sideembedded in well regions. At a collector side, ther e is apilot region and a mixed region. A first area occup ancy ofthe emitter side by the emitter regions is larger i n thepilotregion than in the mixed region.Reverse conducting insulated gate bipolar transisto rs, RC-IGBTs, can be used in high-power applications for i ncreasedpower densities, electrical and thermal performance . Thoughattractive for its potential full utilization of th e siliconarea, the use of the same chip for both IGBT and di odeoperational modes presents different limitations, c hallengesand opportunities in comparison to a two-chip diode / IGBTsolution. P2024,0624 WO N / P240041WO01 May28,2025 -2 -For example, a bi-mode insulated gate transistor, B iGT, atype of RC-IGBT, includes a large, central, and uni nterruptedp-doped backside anode region dedicated for IGBT co nductioncalled pilot-IGBT.Italso includesa mixed region ofdistributed n-doped cathode shorts and p-doped area ssurrounding the pilot-IGBT,forexample,optimized to reducesecondary snapback events and improve the thermal a nd safeoperation area,SOA,performance ofthe device. In the device described herein,an optimization of activecell design parameters, like an n-emitter ratio and a pitch,as a function of their position with respect to reg ionsdefined by the backside design, that is, the pilot- IGBT andthe shorts in the mixed region of a BiGT is enabled . It istherefore possible to improve the IGBT and diode pe rformanceof the device separately and where it matters most. The areaabove the pilot region can be optimized for IGBT pe rformancewhich hasalmostno influence in diode performance asitsitsabove the pilot area, independently of the area abo ve themixed region that would ideally be optimized for di odeperformance.In other implementations of BiGT devices, a uniform n-emitterratio and / orcellpitch isexclusivelyused in the entireactive area regardless of the backside design and f unction.With the semiconductordevice described herein,it ispossible to separately improve the IGBT and diode p erformanceofthe BiGT semiconductorbyoptimizing the active cellparameters, like n-emitter ratio and cell pitch, by takinginto consideration their position with respect to r egionsdefined by the backside design, namely pilot and mi xedregion. In this way, the reverse bias safe operatin g area,RBSOA, and the short circuit safe operating area, S CSOA, P2024,0624 WO N / P240041WO01 May28,2025 -3 -performance can be improved without losing on-stateperformance and better control of IGBT vs. diode pe rformancetrade-offs can be achieved and an extra level of op timizationisgiven.Thus, powerful optimization / trade-off knobs for dif ferentapplications are implemented, and improved RBSOA / SC SOAwithout losing on-state performance and better cont rol of theIGBT vs.diode performance trade-offsare enabled.According to at least one embodiment, the semicondu ctordevice comprises a semiconductor body. The semicond uctor bodymay include a substrate on which one or a plurality ofsemiconductor layers are grown or doped, for exampl e, so thatthe semiconductor body may be a semiconductor layer sequence.Doping may be realized, for example, by growth cond itionsand / or by implanting dopants. For example, the semi conductorbodyisofsilicon,Si.However,the semiconductor bodycanalternatively be of a wide-bandgap semiconductor ma teriallike SiC, Ga 2O3 or GaN as well. It is possible that thesemiconductorbodyisdesign asa chip so thatthe overall semiconductordevice maybe a semiconductorchip.According to at least one embodiment, the semicondu ctor bodyhas an emitter side and a collector side. The colle ctor sideisopposite the emitterside.The emitterside and the collectorside can be main sides,thatis,largest sides,ofthe semiconductor body. For example, a gate electro de of thesemiconductor device is located at the emitter side . The gateelectrode can be applied onto the emitter side so t hat thedevice is of plane design, or the gate electrode is of trenchdesign so that the gate electrode is partially or c ompletelyin a trench starting for example, at the emitter si de and P2024,0624 WO N / P240041WO01 May28,2025 -4 -running into the semiconductor body; in both cases, the gateelectrode is referred to as being at the emitter si de. Thegate electrode iselectricallyinsulated from thesemiconductor body by a gate insulation, like a gat e oxide.Thus, in the intended use of the device there is no flow ofcurrentdirectlyfrom the gate electrode into the semiconductorbody.According to at least one embodiment, at the emitte r side thesemiconductor body comprises a plurality of emitter regions.The emitter regions are of a first conductivity typ e, like n-conductive. For example, the emitter regions are hi ghlydoped, also referred to as n +-doped or n ++-doped.If the device is a metal-insulator-semiconductor fi eld-effecttransistor, MISFET, instead of a BiGT, then the emi tterregionsmaybe referred to assource regions,andcorrespondingly collector regions may be referred t o as drainregions. The same applies analogously for the namin g ofelectrodesand the like.According to at least one embodiment, at the emitte r side thesemiconductor body comprises a plurality of well re gions. Thewell regions are of a second conductivity type diff erent fromthe firstconductivitytype.Forexample,the well regionsare p-conductive. The well regions may moderately b e doped,referred to asp-doped.According to at least one embodiment, each of the e mitterregionsisembedded in one ofthe wellregions.It ispossible that there is a plurality of the emitter r egions perwellregion.Itisfurtherpossible thatthere are P2024,0624 WO N / P240041WO01 May28,2025 -5 -differently designed well regions, for example, hav ingdifferentnumbersofemitterregions.According to at least one embodiment, at the collec tor sidethe semiconductor body comprises a pilot region. Th e pilotregion is uniformly of the second conductivity type . Forexample, the pilot region is heavily doped, also re ferred toas p +-doped or p ++-doped.According to at least one embodiment, at the collec tor sidethe semiconductor body comprises a mixed region. Th e mixedregion comprises first sub-regions of the first con ductivitytype and second sub-regions of the second conductiv ity type.The sub-regions may heavily be doped. Thus, for exa mple, thefirst sub-regions may be n +-doped or n ++-doped and the secondsub-regions may be p +-doped or p ++-doped. Especially, thesecond sub-regions and the pilot regions can be dop ed in thesame manner.According to at least one embodiment, the mixed reg ionpartially or completely surrounds the pilot region,especiallyseen in top view ofthe collectorside. Thus,themixed region may be all around the pilot region, se en in topview. According to atleastone embodiment,a firstarea occupancyof the emitter side by the emitter regions is large r in thepilot region than in the mixed region or is the sam e in thepilot region and in the mixed region. In other word s, thepercentage ofthe emitterside made ofthe emitter regionscan be larger in the pilot regions than in the mixe d region.Thus, per area unit, there is more of the emitter r egions inthe pilotregion than in the mixed region,seen in top view. P2024,0624 WO N / P240041WO01 May28,2025 -6 -Alternatively or additionally, a second area occupa ncy of thewell regions by the emitter regions is smaller in t he mixedregion than in the pilot region. In other words, th epercentage of the well regions covered by the emitt er regionscan be smaller in the mixed region than in the pilo t region.For example, the difference between said percentage s. Thus,per area unit, there is more of the emitter regions on top ofthe well regions in the pilot region than in the mi xedregion,seen in top view. The respective ‘area occupancy’maymathematically beequivalent to a respective ‘occupancy proportion’ o f theassociated emitterregions.In at least one embodiment, the semiconductor devic ecomprises a semiconductor body having an emitter si de and acollectorside,wherein- at the emitter side, the semiconductor body compr ises aplurality of emitter regions of a first conductivit y type anda plurality of well regions of a second conductivit y typedifferent from the first conductivity type, each of theemitter regions is embedded in one of the well regi ons,- at the collector side, the semiconductor body com prises apilot region which is uniformly of the second condu ctivitytype and a mixed region which comprises first sub-r egions ofthe firstconductivitytype and second sub-regions ofthesecond conductivity type and which surrounds the pi lotregion,and- a first area occupancy of the emitter side by the emitterregions is larger in the pilot region than or is th e same asin the mixed region and / ora second area occupancy ofthe P2024,0624 WO N / P240041WO01 May28,2025 -7 -well regions by the emitter regions is smaller in t he mixedregion than oristhe same in the pilotregion.With this configuration of the emitter regions, wit hrelatively less emitter region proportion in the mi xed regionthan in the pilotregion,improved RBSOA and SCSOA can beachieved and the IGBT and diode modes can be optimi zed moreindependentlyofone another.According to at least one embodiment, the semicondu ctordevice is a bi-mode insulated gate transistor, BiGT .According to at least one embodiment, a pitch betwe enadjacent ones of the emitter regions is larger in t he pilotregion than in the mixed region, seen in top view o f theemitter side. For example, there is a first pitch P 1 in thepilot region and a second pitch P2 in the mixed reg ion, seenin top view,and P1 > P2.Forexample,1.2 ≤ P1 / P2 ≤ 10 or 1.3 ≤ P1 / P2 ≤ 5 or1.6 ≤ P1 / P2 ≤ 4.Itispossible thatthereare more than two different pitches. For example, a thirdpitch could be present in an edge region surroundin g both thepilotregion and the mixed region.For example, the pitch is a distance between said a djacentones of the emitter regions. It is also possible th at theabove applies for a grid dimension, that is, for ha lf a widthof the respective two adjacent emitter regions plus thepitch. Thus, the pitch may also be referred to as aperiodicity.For example, the respective pitch in the pilot regi on and inthe emitter region is a distance between adjacent o nes ofarrangementlinesofthe emitterregions,thatis, from P2024,0624 WO N / P240041WO01 May28,2025 -8 -middle to middle of lines along which the emitter r egions arearranged. For example, the arrangement lines are st raightlines or also curved lines. For example, per arrang ement linethere are at least two or at least five or at least tenand / or at most 10 4 or at most 10 3 or at most 10 2 of theemitter regions. For example, there are at least tw o or atleast five or at least ten and / or at most 10 4 or at most 10 3or at most 10 2 of the arrangement lines.In case that the pitch is not the same all across t he mixedregion and / or all across the pilot region, then the abovestated differences between the pitches, or analogou slybetween the occupancy proportion, may refer to a re spectivemean pitch and / ormean occupancyproportion ofthe pilotregion and the mixed region, respectively. The mean pitchand / or occupancy proportion may be a sum of all pit ches oroccupancy proportions of the mixed region and pilot region,respectively, divided by a number of the pitches or occupancyproportions.According to at least one embodiment, the emitter s idecomprises a pattern composed of a repeatedly placed unitcell. The unit cell comprises one or also a plurali ty of theemitter regions. It is possible that there is a fir st unitcell for the pilot region and a second unit cell fo r themixed region, seen in top view. The first and secon d unitcells may have a same size or a different size. Opt ionally,there can be a third unit cell for an edge region o f thesemiconductor device. It is possible that there are exact tounitcells,thatis,the firstand the second unit cells. According to atleastone embodiment,an occupancy proportionof the emitter regions in the unit cell is larger i n the P2024,0624 WO N / P240041WO01 May28,2025 -9 - pilotregion than in the mixed region,seen in top view ofthe emitter side. In other words, in the first unit cell theproportion of the emitter regions is larger than in thesecond unitcell.According to at least one embodiment, the pitch and / or theoccupancy proportion differ between the pilot regio n and themixed region by at least a factor of 1.1 or by at l east afactor of 1.2 or by at least a factor of 1.4. Alter nativelyor additionally, said difference is at most a facto r of 20 oris at most a factor of 10 or is at most a factor of 5 or isat most a factor of 2.0. For example, said factor i s between1.4 and 2.0 or is between 1.4 and 2 or is between 1 .2 and 5.According to at least one embodiment, some or all o f theemitter regions are arranged along one or a plurali ty ofarrangementlines,seen in top view ofthe emitter side.Forexample, in case of a plurality of arrangement line s, thearrangement lines are straight lines. It is possibl e that allthe arrangement lines or some of the arrangement li nes run inparallel with each other. Otherwise, the arrangemen t linesmay be curved and / or kinked. For example, the arran gementlines are lines at which one continuous well region and / orplug region isexposed from a gate electrode and a gateinsulation at the emitter side. Thus, the arrangeme nt linesmay be continuous areas of the emitter side being i n directcontact with a first electrode, like an emitter ele ctrode,for example. Hence, there may be exactly one contin uous areaof contact between the first electrode and the semi conductorbody per arrangement line. Further, there may be at least twoor at least five emitter regions per arrangement li ne, seenalong the arrangementline,forexample. P2024,0624 WO N / P240041WO01 May28,2025 -10 -According to at least one embodiment, the unit cell includesa portion of one or of a plurality of the arrangeme nt lines.For example, the unit cell includes one or two of t hearrangementlines.Thus,the arrangementlinescan define apattern of the emitter regions, of the well regions and / or ofplug regions at the emitter side. This may apply fo r thefirstand the second unitcell.According to at least one embodiment, if the emitte r regionsare arranged along a plurality of the arrangement l ines andseen in top view ofthe emitterside,in the mixed region theemitter regions are placed at different locations a longadjacent ones of the arrangement lines. Thus, for e xample, incase of the respective arrangement lines running in parallelseen in top view of the emitter side, a straight li ne runningperpendicular to the arrangement lines and crossing a firstone of the arrangement lines at a emitter region, s aidstraight line may cross the adjacent arrangement li nes out ofany emitter region. Put in other words, along adjac entarrangement lines the emitter regions may be offset from eachotherand,thus,could be displaced.According to at least one embodiment, the emitter s ide isstructured into a plurality of emitter cells each c omprisingone or a plurality of the emitter regions. For exam ple, thereis exactly one emitter region per emitter cell. Thu s, theremay be no arrangementlinesasdefined above. Byway ofexample,seen in top view ofthe emitter side,the emittercellsmaybe ofround shape,like elliptic orcircular, or may be of polygonal shape, like hexago nal ortrigonalorsquare orrectangular.Allthe emitter cellsinthe pilot region and in the mixed region, respectiv ely, can P2024,0624 WO N / P240041WO01 May28,2025 -11 -be of the same design or emitter cells of different designcan be combined with each other in the pilot region and inthe mixed region,respectively.According to at least one embodiment, the emitter c ellscorrespond to the unit cell. That is, each one of t he emittercells has the design of the respective unit cell. T his mayapply for the first and second unit cells, for exam ple.According to atleastone embodiment,in the pilot region andin the mixed region the pitch between adjacent ones of theemitter regions is the same, and in the pilot regio n theoccupancy proportion of the emitter regions is larg er than inthe mixed region. This may apply both for a semicon ductordevice of the arrangement lines design and of the e mittercells design. Thus, only the occupancy proportion m ay differbetween the mixed region and the pilot region and n ot thepitch. According to atleastone embodiment,in the pilot region the pitch between adjacentonesofthe emitterregions isbyatleast a factor of 1.2 or by at least a factor of 1. 9 largerthan in the mixed region, and in the pilot region t heoccupancy proportion of the emitter regions is larg er than inthe mixed region byatleasta factorof1.2 orby atleastafactor of 1.9. This may apply both for a semiconduc tor deviceofthe arrangementlinesdesign and ofthe emitter cellsdesign. Thus, both the pitch and the occupancy prop ortion maydifferfrom one anotherin the pilotregion and in the mixedregion wherein the increased pitch in the pilot reg ion iscompensated for by a decreased occupancy proportion in themixed region. P2024,0624 WO N / P240041WO01 May28,2025 -12 -According to at least one embodiment, the semicondu ctordevice is of a planar design. Hence, a gate electro de of thesemiconductor device is located on the emitter side and maythus not run into the semiconductor body. For an em itterelectrode it is possible to run into the semiconduc tor bodyjustto electricallycontactthe wellregion.According to at least one embodiment, the semicondu ctordevice is of a trench design. Hence, a gate electro de of thesemiconductor device is partially or completely arr anged intrenchesextending from the emitterside into thesemiconductor body, for example, seen in cross-sect ionperpendicular to the emitter side. The trenches may terminatedistantfrom the pilotregion and the mixed region and,thus, distantfrom the collectorside.According to at least one embodiment, seen in top v iew of theemitter side, in the mixed region there is no fixedcorrelation between the emitter regions and the fir st sub-regions and / or the second sub-regions. For example, thesecond unit cell is not an integer multiple of a co llectorside unitcellofa design ofthe firstand second sub- regions,and vice versa.In otherwords,there are notjustone or two lateral offsets between the emitter regi ons andthe first sub-regions, for example, seen in top vie w of thesemiconductorbody.Hence,the emitterregionsand the firstsub-regions may be placed relative to one another i n auniform distribution, for example, with the lateral offsetsasa parameterto define the distribution.According to at least one embodiment, the semicondu ctordevice is configured for a voltage between the emit ter sideand the collectorside ofatleast0.6 kV orofat least1.2 P2024,0624 WO N / P240041WO01 May28,2025 -13 -kV or of at least 3 kV. Alternatively or additional ly, saidvoltage is at most 10 kV or is at most 7 kV. Hence, forexample,the respective layerthicknessesofgate insulations,driftregions,wellregionsand so on are configured to withstand said voltage.Alternatively or additionally, the semiconductor de vice isconfigured for a current between the emitter electr ode and acollector electrode of at least 0.01 kA or of at le ast 0.1 kAofatleast1 kA and / orofatmost100 kA orofat most10 kA.Thus, the semiconductor device may be a power devic e. Forexample,the semiconductordevice isconfigured as a powerswitch in a power converter or in a power inverter, forexample,forconverting a directcurrent,DC,into analternating current, AC, and / or for converting a fi rst DC ina second DC ofa differentvoltage.A semiconductor device described herein is explaine d ingreater detail below by way of exemplary embodiment s withreference to the drawings. Elements which are the s ame in theindividual figures are indicated with the same refe rencenumerals. The relationships between the elements ar e notshown to scale, however, but rather individual elem ents maybe shown exaggeratedly large to assist in understan ding.In the figures: Figure 1 isa schematiccross-sectionalview ofan exemplary embodimentofa semiconductordevice described herein, P2024,0624 WO N / P240041WO01 May28,2025 -14 - Figure 2 isa schematicbottom view on a collector side of the semiconductordevice ofFigure 1,Figure 3 is a schematic top view on an emitter side of thesemiconductordevice ofFigure 1,Figure 4 is a schematic top view of a modified semi conductordevice,Figures 5 to 14 are schematic top view on emitter s ides inthe pilotregion and in the mixed region, respectively,ofexemplaryembodimentsof semiconductordevicesdescribed herein.Figure 15 is a schematic cross-sectional view of an exemplaryembodimentofa semiconductordevice described herein. Figure 1 illustratesan exemplaryembodimentofa semiconductordevice 1.The semiconductordevice 1 comprises a semiconductorbody2,like a semiconductorlayer sequence,with an emitter side 3 and a collector side 4 being based onsilicon,forexample.Atthe emitterside 3,there isa firstelectrode 51 which is an emitter electrode. Corresp ondingly,at the collector side 4 there is a second electrode 52 whichis a collector electrode. Further, at the emitter s ide 3there is a gate electrode 53 separated from the fir stelectrode 51 and the semiconductor body 2 by a gateinsulation 54, like a gate oxide. The first electro de 51 maycompletely or mostly cover the emitter side and the gateelectrode 53,forexample. P2024,0624 WO N / P240041WO01 May28,2025 -15 -The semiconductor body 2 includes emitter regions 3 1 at theemitter side 4. The emitter regions 31 are n-conduc tive, forexample, and are embedded in a well region 32 which is p-conductive.To electricallyfixthe wellregion 32 atanelectric potential of the first electrode 51, there isoptionally a p-conductive plug region 34 to connect the firstelectrode 51 and the well region 32. A largest part of thesemiconductor body 2 is made of a drift region 35 w hich is n-conductive. Optionally, on a side of the drift regi on 35 nextto the collector side 4 there can be a buffer regio n 36 beingn-conductive,forexample.At the collector side 4, the semiconductor body 2 h as acentrally arranged pilot region 41 and a circumfere ntialmixed region 42, see also Figure 2. In the pilot re gion 41,the semiconductorbody2 isuniformlyp-conductive nexttothe second electrode 52. In the mixed region 42, th ere are n-conductive first sub-regions 421 and p-conductive s econd sub-regions 422. Optionally, there is an edge region 43 allaround the mixed region 42. It is possible that the edgeregion 43 isp-conductive.In Figure 3 it can be seen that along an arrangemen t line 33which is a straight line the emitter regions 31 are arrangedin pairs.Thus,a unitcell62 bywhich the design oftheemitter regions 31 can be defined includes two of t he emitterregions31.Figures 1 and 3 refer to a sectional view and a top view ofthe mixed region 42 only, respectively. However, th e sameappliesanalogouslyforthe pilotregion 41.. P2024,0624 WO N / P240041WO01 May28,2025 -16 -It is possible that the semiconductor device 1 is a reverseconducting insulated gate bipolar transistor, RC-IG BT forshort, and may thus be referred to as a bi-mode ins ulatedgate transistor, BiGT for short. Concerning details on thedoping levels, dimensions of the respective regions ,variation possibilities of the pattern of the mixed region 42and the pilot region 41, reference is made to docum ents EP2249 392 A2 and WO 2015 / 097157 A1,the disclosure contentof which isherebyincluded byreference.In Figure 4, the emitter side 3 of a modified semic onductordevice 9 is illustrated. In this device 9, all over the pilotregion 41 and the mixed region 42 there is a same u nit cell 6so that the emitter regions 31 are distributed in a constantpattern allacrossthe emitterside 3.Contrary to that, in the semiconductor device 1 des cribedherein there are differentpatternsofthe emitter regions31and, thus, of the well regions 32 and / or the plug r egions 34in the pilotregion 41 and in the mixed region 42,respectively, as illustrated below in connection wi th Figures5 to 14. Not shown herein, in the edge region 43 th ere may beanother pattern of the emitter regions 31, the well regions32 and / orthe plug regions34.In the semiconductor device 1 of Figures 5 and 6, s een in topview,both in the pilotregion 41 and in the mixed region 42the arrangement lines 33 have a same pitch P at the emitterside 3. It is also possible that the areas along th earrangement lines 33 have a same width W in both re gions 41,42. Thus, the difference between the regions 41, 42 is anoccupancy proportion of the emitter regions 31 alon g thearrangementlines33. P2024,0624 WO N / P240041WO01 May28,2025 -17 -For example, the occupancy proportion of the emitte r regions31 at the emitter side assigned to the pilot region 41 isabout 0.8 in a first unit cell 61, and the occupanc yproportion assigned to the mixed region 42 is about 0.2 in asecond unitcell62.These valuesof,forexample, 0.8 and0.2 may refer to a proportion of the emitter region s 31 on anoverall area in which the first electrode 51 touche s theemitter side 3 along the respective arrangement lin e 33. Aseach unit cell 61, 62 include exactly one of the em itterregions 31 and as the pitch P is the same in the re gions 61,62, the first unit cell 61 may have the same size a nd shapeasthe unitcell62.By way of example, the width W of the areas along t hearrangementlines33 including the emitterregions 31 isatleast 1 µm and / or at most 20 µm, for example, is be tween 2 µmand 15 µm. The pitch P as drawn in the Figures is a distancebetween adjacentonesofthe arrangementlines33, thatis,from middle to middle of the lines exposed from the gateinsulation 54 and the gate electrode 53. For exampl e, thepitch P is at least 5 µm or is at least 10 µm and / o r is atmost 200 µm or is at most 100 µm. A distance betwee n adjacentones of the emitter regions 31 along the arrangemen t lines 33is, for example, at least 1 µm and / or at most 20 µm ,especiallybetween 2 µm and 15 µm.It is noted that in Figures 5 and 6 there is just o ne emitterregion 31 ata same position along the arrangement lines33,and not two emitter regions 31 as shown in Figure 3 . However,the statements above to Figures 5 and 6 apply analo gously tothe situation shown in Figure 3. The same is true f or allotherembodiments. P2024,0624 WO N / P240041WO01 May28,2025 -18 - Thus,there isa high n-emitterratio in an areacorresponding to the backside pilot region 41 and l ow n-emitter ratio in the area corresponding to backside mixedregion 42.With the high n-emitter ratio at the emitter side 3 in areascorresponding to the pilot region 41 at the collect or side 4,good IGBT performance can be achieved while there i s nostrong impact on the diode mode as this design of t he emitterregions 31 is limited to above the pilot region 41. With thelow n-emitterratio atthe emitterside 3 in areascorresponding to the mixed region 42 at the collect or side 4,good diode performance can be achieved due to less n-emitterproportion. Thus, improved overall balance is enabl ed to havethe total amount of n-emitter required in the respe ctivearea.Otherwise, the same as to Figures 1 to 3 may also a pply toFigures5 and 6,and vice versa.In the semiconductor device 1 of Figures 7 and 8 it is shownthat in the pilot region 41 the pitch P1 is increas edcompared to the pitch P2 in the mixed region 42. Fo r example,the pitches P1, P2 differ by at least a factor of 1 .5 and byat most a factor of 5, like a factor of 3. That is, comparedwith Figures 5 and 6, the pitch P1 is increased and the pitchP2 is decreased, compared with the pitch P. However , in bothregions 41, 42 the areas along the arrangement line s 33 mayhave the same width W. Forexample,asshown in Figures7 and 8 the first pitch P1is 100 µm and the corresponding occupancy proportio n is 0.8, P2024,0624 WO N / P240041WO01 May28,2025 -19 -seen along the arrangement lines 33, and the second pitch P2is40 µm with an occupancyproportion of0.2.As an option, along the arrangement lines 33 the em itterregions 31 may be displaced so that, for example, a t everysecond or, other than shown, alternatively at every third orfourth arrangement line 33 the emitter regions 31 a re at asame position.Thus, the first unit cell 61 may have a different s ize and adifferentshape compared with the second unitcell 62.Forexample, the second unit cell 62 is narrower and hi gher thanthe firstunitcell61. Byhaving a relativelylarge firstpitch P1 in the pilot region,a numberofelectriccontactsin the pilot region 41can be decreased which can simplify the electric wi ring.Accordingly,there isa high n-emitterratio and a large cellpitch P1 in the area corresponding to backside pilo t region41 and a low n-emitter ratio and a small cell pitch P2 in thearea corresponding to the backside mixed region 42.In Figures 7 and 8 it is exemplarily drawn that the areasalong the arrangement lines 33 and the emitter regi ons 31both have the width W. However, it is also possible that awidth of the emitter regions 31 is smaller than the width W,that is, the areas along the arrangement lines 33 c an bewider than the emitter regions 31. For example, the width ofthe emitterregions31 isatleast0.7 W and / oris atmost0.9 W. Further, it is possible that the areas along thearrangement lines 33 are at places, especially betw eenadjacent emitter regions 31, narrower than the emit ter P2024,0624 WO N / P240041WO01 May28,2025 -20 -regions 31 themselves, for example, with an interme diatewidth Wi> 0,like 0.1 W ≤ Wi ≤ 0.6 W,oralternativelyWi = 0 is possible. The same applies analogously fo r allother embodiments, especially for the widths W1 and / or W2 ofFigures9 and 10 below.Otherwise, the same as to Figures 1 to 6 may also a pply toFigures7 and 8,and vice versa. In the semiconductordevice 1 ofFigures9 and 10, the width W1,W2 ofthe areasalong the arrangementlines33 isvariedas a further parameter. That is, in the pilot regio n 41, seeFigure 9, the emitter regions 31 are broader and ha ve thewidth W1 and the pitch P1 isincreased so thatthe emitterregions 31 are narrower with the width W2 at a smal ler pitchP2 in the mixed region 42. The width W can be varie d in theembodiments of Figures 5 and 6 as well as of Figure s 7 and 8analogously. These embodimentsand implementationsofFigures7 to 10 withhigh n-emitter and large cell pitches located in th e areacorresponding to the pilot region 41 is good for IG BT modeand low on-states and has no strong impact on the d iode mode.The mixed region 42 can be optimized for a good dio deperformance with low n-emitter ratio to achieve a h igh on-state for good balance and small cell pitches P2. I n otherwords, regions with a diode on the back, that is, t he nshorts 421 of the mixed region 42, should have more p-dopedareas or high channel or p-well doping for good dio deperformance together optimized with the correspondi ng pilotarea with more n-emitter ratio optimized with the b est pitchP1 forIGBT performance,thatis,largestpossible pitch, which would likelybe limited bySOA. P2024,0624 WO N / P240041WO01 May28,2025 -21 -Otherwise, the same as to Figures 1 to 8 may also a pply toFigures9 and 10,and vice versa. In the semiconductordevices1 ofFigures5 to 10, there havebeen the arrangement lines 33. However, a design wi th emittercells is also possible in the same manner, the Figu res 11 to14. In these Figures 11 to 14, exemplarily the emit ter cellscorrespond to the first and second unit cells 61, 6 2, and areof hexagonal shape, seen in top view. However, othe r shapesare possible aswell.For example, optionally in each cell 61, 62 there i s acentral area in which the plug region 34 or alterna tivelydirectly the well region 32 can electrically be con tacted bymeans of the first electrode 51, compare Figure 1 w hichapplies to both the arrangement lines design and th e cellsdesign. Around said optional plug region 34, the em itterregion 31 is located. Around the emitter region 31, the gateelectrode 53 and the gate insulator 54 can be appli ed, forsimplicity not shown in Figures 11 to 14. The optio nal plugregions 34 and / or the emitter regions 31 may all ha ve thesame basic shape of the respective emitter cell, li kehexagonal,butotherdesignsare also possible.Thus, in Figures 11 and 12 it is drawn that the pit ch P2 froma center point to an adjacent center point of the c ells islarger in the pilot region 41 than in the mixed reg ion 42.The occupancyproportion can be adjusted byhaving relativelysmall emitter regions 31 in the mixed region 42, fo r example. P2024,0624 WO N / P240041WO01 May28,2025 -22 -Thus, analogously to Figures 7 and 8 or 9 and 10, i n Figures11 and 12 the pitch is varied, and the occupancy pr oportionisadapted accordingly. Otherwise,the same asto Figures1 to 10 mayalso applyto Figures11 and 12,and vice versa.In Figures 13 and 14 it is shown that the pitch P i s the samein the regions 41, 42, but that the size of the emi tterregions 31 has been changed corresponding to differ entoccupancy proportions. Hence, Figures 13 to 14 corr espond toFigures5 and 6.Mixtures of the embodiments of Figures 11 and 12 on the onehand and of Figures 13 and 14 on the other hand are possibleaswell. Otherwise,the same asto Figures1 to 12 mayalso applyto Figures13 and 14,and vice versa.The semiconductor device 1 of Figure 15 is a revers econducting insulated gate bipolar transistor, RC-IG BTs, of atrench design. Thus, the gate electrode 53 may be p laced infirst trenches 71 running from the emitter side 3 i nto thesemiconductor body 2 and terminating in the drift r egion 35.The first trenches 71 may run through the well regi on 32. Theemitter regions 31 may be limited to an area betwee n the twofirsttrenches71.Optional, there can be second trenches 72 which can be of thesame width and depth asthe firsttrenches71.For example,the second trenches 72 can accommodate an electrode materialat a same electric potential as the first electrode 51. The P2024,0624 WO N / P240041WO01 May28,2025 -23 - second trenches72 maybe located outside the well region 32, forexample.All the above-stated variations of the pitch P, P1, P2, theoccupancy proportion, the width W, W1, W2 and / or th e emittercell design, individually or in any combination, ca nanalogously be applied to the trench design of Figu re 15.Otherwise,the same asto Figures1 to 14 mayalso applyto Figure 15,and vice versa. The componentsshown in the figuresfollow,unless indicatedotherwise, exemplarily in the specified sequence di rectly oneon top of the other. Components which are not in co ntact inthe figures are exemplarily spaced apart from one a nother. Iflines are drawn parallel to one another, the corres pondingsurfaces may be oriented in parallel with one anoth er.Likewise, unless indicated otherwise, the positions of thedrawn components relative to one another are correc tlyreproduced in the figures.The invention described here is not restricted by t hedescription on the basis of the exemplary embodimen ts.Rather, the invention encompasses any new feature a nd alsoany combination of features, which includes in part icular anycombination offeaturesin the patentclaims,even ifthisfeature or this combination itself is not explicitl yspecified in the patent claims or exemplary embodim ents.This patent application claims the priority of Euro peanpatent application 24192360.6, the disclosure cont ent ofwhich isherebyincorporated byreference. P2024,0624 WO N / P240041WO01 May28,2025

[0002] P2024,0624 WO N / P240041WO01 May28,2025 -25 - ListofReference Signs 1 semiconductordevice 2 semiconductorbody 3 emitterside 31 emitterregion (n-conductive) 32 wellregion (p-conductive) 33 arrangementline 34 plug region 35 driftregion 36 bufferregion 4 collectorside 41 pilotregion (p-conductive) 42 mixed region421 n-conductive first sub-region of the mixed regi on422 p-conductive second sub-region of the mixed reg ion43 edge region 51 firstelectrode 52 second electrode 53 gate electrode 54 gate insulation 6 unitcell 61 firstunitcell 62 second unitcell 71 firsttrench (gate electrode) 72 second trench 9 modified semiconductordevice P pitch W width ofemitterregionsalong the respective arrangementline

Claims

P2024,0624 WO N / P240041WO01 May28,2025 -26 - PatentClaims1. A semiconductor device (1) comprising a semicond uctor body(2) having an emitter side (3) and a collector side (4),wherein- the semiconductor device (1) is a bi-mode insulat ed gatetransistor,BiGT,- at the emitter side (3), the semiconductor body ( 2)comprisesa pluralityofemitterregions(31)ofa firstconductivity type and a plurality of well regions ( 32) of asecond conductivitytype differentfrom the firstconductivity type, each of the emitter regions (31) isembedded in one ofthe wellregions(32), -atthe emitterside (3)the semiconductordevice (1)comprises a first electrode (51) which is an emitte relectrode that electrically contacts the emitter re gions(31),- at the collector side (4), the semiconductor body (2)comprises a pilot region (41) which is uniformly of thesecond conductivity type and a mixed region (42) wh ichcomprises first sub-regions (421) of the first cond uctivitytype and second sub-regions (422) of the second con ductivitytype and which surrounds the pilot region (41), and- a first area occupancy of the emitter side (3) by theemitterregions(31)islargerin the pilotregion (41)than in the mixed region (42),and- at least one of a pitch (P) between adjacent ones of theemitterregions(31)oran occupancyproportion of theemitter regions (31) differ between the pilot regio n (41) andthe mixed region (42) by at least a factor of 1.2 a nd by atmosta factorof10,the respective pitch (P)isa distance between adjacentonesofarrangementlines(33)of theP2024,0624 WO N / P240041WO01 May28,2025 -27 -emitter regions (31), that is, from middle to middl e of linesalong which the emitterregions(31)are arranged.

2. The semiconductor device (1) according to the pr ecedingclaim,wherein the semiconductor device (1) comprises a ga teelectrode (53)located atthe emitterside (3)and electricallyinsulated from the semiconductorbody (2)bya gate insulation (54), wherein,seen in top view ofthe emitterside (3), theemitter regions (31) overlap with at least one of t he mixedregion (42)orthe pilotregion (41),wherein the semiconductor body (2) further comprise s a driftregion (35) located between the emitter regions (31 ) and thepilotregion (41)and the mixed region (42),along a direction perpendicularwith the emitterside (3), the well regions(32)are embedded in the driftregion (35) being of the firstconductivitytype.

3. The semiconductor device (1) according to any on e of thepreceding claims,wherein a pitch (P) between adjacent ones of the em itterregions (31) is larger in the pilot region (41) tha n in themixed region (42),seen in top view ofthe emitter side (3).

4. The semiconductor device (1) according to any on e of thepreceding claims,wherein the emitter side (3) comprises a pattern co mposed ofa repeatedly placed unit cell (6), the unit cell (6 )comprises one or a plurality of the emitter regions (31),wherein the occupancy proportion of the emitter reg ions (31)in the unitcell(6)islargerin the pilotregion (41)thanP2024,0624 WO N / P240041WO01 May28,2025 -28 -in the mixed region (42), seen in top view of the e mitterside (3).

5. The semiconductor device (1) according to any on e of thepreceding claims,wherein at least one of the pitch (P) or the occupa ncyproportion differ between the pilot region (41) and the mixedregion (42) by at least a factor of 1.2 and by at m ost afactorof2.0.

6. The semiconductor device (1) according to any on e of thepreceding claims,wherein the emitter regions (31) are arranged along aplurality of arrangement lines (33), seen in top vi ew of theemitterside (3).

7. The semiconductor device (1) according to claims 4 and 6,wherein the unit cell (6) includes a portion of one or of apluralityofthe arrangementlines(33).

8. The semiconductor device (1) according to any on e of thetwo preceding claims, wherein in the mixed region (42),seen in top view oftheemitter side (3), the emitter regions (31) are plac ed atdifferent locations along adjacent ones of the arra ngementlines(33). 9.The semiconductordevice (1)according to claim 4 or7,wherein the emitter side (3) is structured into a p luralityof emitter cells each comprising one of the emitter regions(31),and the emittercellscorrespond to the unit cell(6).P2024,0624 WO N / P240041WO01 May28,2025 -29 -10. The semiconductor device (1) according to any o ne of thepreceding claims,wherein in the pilot region (41) and in the mixed r egion (42)the pitch (P)between adjacentonesofthe emitter regions (31)isthe same,andwherein in the pilot region (41) the occupancy prop ortion ofthe emitter regions (31) is larger than in the mixe d region(42).

11. The semiconductor device (1) according to any o ne ofclaims1 to 9,wherein in the pilot region (41) the pitch (P) betw eenadjacentonesofthe emitterregions(31)isbyat leastafactor of 1.2 larger than in the mixed region (42), andwherein in the pilot region (41) the occupancy prop ortion ofthe emitter regions (31) is larger than in the mixe d region(42)byatleasta factorof1.2.

12. The semiconductor device (1) according to any o ne of thepreceding claims,which is of a planar design so that a gate electrod e (53) ofthe semiconductor device (1) is located on the emit ter side(3) and so that the gate electrode (53) does not ru n into thesemiconductorbody(2).

13. The semiconductor device (1) according to any o ne ofclaims1 to 11,which is of a trench design so that a gate electrod e (53) ofthe semiconductor device (1) is arranged in trenche s (7)extending from the emitter side (3) into the semico nductorbody(2).P2024,0624 WO N / P240041WO01 May28,2025 -30 -14. The semiconductor device (1) according to any o ne of thepreceding claims, wherein in the mixed region (42),seen in top view oftheemitter side (3), there is no fixed correlation bet ween theemitter regions (31) and the first sub-regions (421 ) as wellasthe second sub-regions(422).

15. The semiconductor device (1) according to any o ne of thepreceding claims,which is configured for a voltage between the emitt er side(3) and the collector side (4) of at least 0.6 kV a nd of atmost 10 kV and / or which is configured for a current betweenan emitter electrode (51) and a collector electrode (52) ofatleast0.01 kA and ofatmost10 kA.

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