Semiconductor device and method for producing semiconductor device

Abstract

Provided is a highly reliable semiconductor device. The semiconductor device comprises: a first insulating layer; a semiconductor layer covering a side surface of the first insulating layer; a first conductive layer in contact with a part of a side surface of the semiconductor layer; a second conductive layer provided at a distance from the first conductive layer and in contact with another part of the side surface of the semiconductor layer; a second insulating layer covering the first insulating layer and a part of the semiconductor layer; and a third conductive layer on the second insulating layer. The third conductive layer covers the first insulating layer and a part of the semiconductor layer with the second insulating layer therebetween.

Description

Semiconductor device and method for manufacturing the same

[0001] 1. Field of the Invention One embodiment of the present invention relates to a semiconductor device, a memory device, and an electronic device. Another embodiment of the present invention relates to a manufacturing method of a semiconductor device.

[0002] One embodiment of the present invention is not limited to the above technical field, and examples of the technical field of one embodiment of the present invention include semiconductor devices, display devices, light-emitting devices, power storage devices, memory devices, electronic devices, lighting devices, input devices (e.g., touch sensors), input / output devices (e.g., touch panels), driving methods thereof, and manufacturing methods thereof.

[0003] In this specification and the like, a semiconductor device is a device that utilizes semiconductor characteristics, and refers to a circuit including a semiconductor element (transistor, diode, photodiode, etc.), a device having such a circuit, etc. Also, it refers to any device that can function by utilizing semiconductor characteristics. For example, an integrated circuit, a chip including an integrated circuit, and an electronic component in which a chip is housed in a package are examples of semiconductor devices. Furthermore, a memory device, a display device, a light-emitting device, a lighting device, and an electronic device may themselves be semiconductor devices and each may have a semiconductor device.

[0004] In recent years, the development of semiconductor devices has progressed, and large scale integration (LSI), central processing units (CPU), memories, etc. are mainly used in semiconductor devices. A CPU is an assembly of semiconductor elements that have integrated circuits (including transistors and capacitive elements) formed into chips by processing a semiconductor wafer and on which electrodes serving as connection terminals are formed.

[0005] 2. Description of the Related Art Integrated circuits (IC chips) such as LSIs, CPUs, and memories are mounted on circuit boards, such as printed wiring boards, and are used as components of various electronic devices.

[0006] Furthermore, a technology for constructing a transistor using a semiconductor thin film formed on a substrate having an insulating surface has attracted attention. Such transistors are widely applied to electronic devices such as integrated circuits (ICs) and display devices. While silicon-based semiconductor materials are widely known as semiconductor materials applicable to transistors, oxide semiconductors have also attracted attention as other materials.

[0007] Furthermore, it is known that a transistor using an oxide semiconductor has an extremely small leakage current in an off state. For example, Patent Document 1 discloses a CPU with low power consumption that utilizes the property of a transistor using an oxide semiconductor having a small leakage current. Furthermore, Patent Document 2 discloses a memory device that can retain stored data for a long period of time by utilizing the property of a transistor using an oxide semiconductor having a small leakage current.

[0008] JP 2012-257187 A JP 2011-151383 A

[0009] An object of one embodiment of the present invention is to provide a transistor with favorable electrical characteristics.An object of one embodiment of the present invention is to provide a transistor with high on-state current.An object of one embodiment of the present invention is to provide a transistor with low parasitic capacitance.An object of one embodiment of the present invention is to provide a highly reliable transistor, semiconductor device, or memory device.An object of one embodiment of the present invention is to provide a transistor, semiconductor device, or memory device that can be miniaturized or highly integrated.An object of one embodiment of the present invention is to provide a semiconductor device or memory device with low power consumption.An object of one embodiment of the present invention is to provide a memory device with high operating speed.An object of one embodiment of the present invention is to provide a manufacturing method of the transistor, semiconductor device, or memory device.

[0010] Note that the description of these problems does not preclude the existence of other problems. One embodiment of the present invention does not necessarily have to solve all of these problems. Problems other than these can be extracted from the description in the specification, drawings, and claims.

[0011] One embodiment of the present invention is a semiconductor device including a first insulating layer, a semiconductor layer covering a side surface of the first insulating layer, a first conductive layer in contact with a part of the side surface of the semiconductor layer, a second conductive layer spaced apart from the first conductive layer and in contact with another part of the side surface of the semiconductor layer, a second insulating layer covering a part of the first insulating layer and the semiconductor layer, and a third conductive layer on the second insulating layer. The third conductive layer covers a part of the first insulating layer and the semiconductor layer via the second insulating layer.

[0012] In the semiconductor device, the height of the semiconductor layer is preferably not less than 5 nm and not more than 200 nm.

[0013] In the semiconductor device, it is preferable that the first conductive layer and the second conductive layer are not in contact with the upper surface of the semiconductor layer.

[0014] In the semiconductor device, it is preferable that the third conductive layer does not overlap with either the first conductive layer or the second conductive layer, and that the third conductive layer has a portion located between the first conductive layer and the second conductive layer.

[0015] It is preferable that the semiconductor device has a third insulating layer, the third insulating layer has an opening, and at least a portion of each of the first insulating layer, the semiconductor layer, the first conductive layer, the second conductive layer, the second insulating layer, and the third conductive layer is located within the opening.

[0016] Preferably, the semiconductor device has a fourth insulating layer, the first insulating layer and the semiconductor layer are provided on the fourth insulating layer, the fourth insulating layer has a recess surrounding the first insulating layer and the semiconductor layer, the first conductive layer and the second conductive layer are each provided to fill a portion of the recess, and the second insulating layer is provided to fill another portion of the recess.

[0017] In the semiconductor device, the lower surface of the third conductive layer at a position overlapping with the recess is preferably located lower than the lower surface of the semiconductor layer.

[0018] In the above semiconductor device, the semiconductor layer preferably contains indium and oxygen.

[0019] In the above semiconductor device, the first insulating layer preferably contains hafnium and oxygen.

[0020] In the semiconductor device, each of the first conductive layer and the second conductive layer preferably contains indium, tin, and oxygen.

[0021] One embodiment of the present invention is a method for manufacturing a semiconductor device, including forming a first insulating layer, forming a first sacrificial layer covering side surfaces of the first insulating layer, forming a second sacrificial layer covering the side surfaces of the first sacrificial layer, forming a second insulating layer covering the side surfaces of the second sacrificial layer, removing the second sacrificial layer to form an opening in the second insulating layer, forming a first conductive layer to fill the opening, removing part of the first conductive layer to form a second conductive layer and a third conductive layer that are spaced apart from each other, forming a third insulating layer to cover part of the first insulating layer and the first sacrificial layer, forming a fourth conductive layer over the third insulating layer, removing the first sacrificial layer, and forming a semiconductor layer in a portion where the first sacrificial layer was located.

[0022] In the above-described method for manufacturing a semiconductor device, the semiconductor layer is preferably formed by atomic layer deposition.

[0023] In the above-described method for manufacturing a semiconductor device, the semiconductor layer is preferably formed to have a height of 5 nm to 200 nm.

[0024] In the above-described method for manufacturing a semiconductor device, the fourth conductive layer is preferably formed so as not to overlap with either the second conductive layer or the third conductive layer, and is preferably formed between the second conductive layer and the third conductive layer.

[0025] In the above-described method for manufacturing a semiconductor device, the second sacrificial layer preferably has a different material from that of the first sacrificial layer.

[0026] In the above-described method for manufacturing a semiconductor device, the semiconductor layer preferably contains indium and oxygen.

[0027] In the above-described method for manufacturing a semiconductor device, the first insulating layer preferably contains hafnium and oxygen.

[0028] In the above method for manufacturing a semiconductor device, the first conductive layer preferably contains indium, tin, and oxygen.

[0029] According to one embodiment of the present invention, a transistor with favorable electrical characteristics can be provided. According to one embodiment of the present invention, a transistor with large on-state current can be provided. According to one embodiment of the present invention, a transistor with small parasitic capacitance can be provided. According to one embodiment of the present invention, a highly reliable transistor, semiconductor device, or memory device can be provided. According to one embodiment of the present invention, a transistor, semiconductor device, or memory device that can be miniaturized or highly integrated can be provided. According to one embodiment of the present invention, a semiconductor device or memory device with low power consumption can be provided. According to one embodiment of the present invention, a memory device with high operating speed can be provided. According to one embodiment of the present invention, a manufacturing method of the above transistor, semiconductor device, or memory device can be provided.

[0030] Note that the description of these effects does not preclude the existence of other effects. One embodiment of the present invention does not necessarily have all of these effects. Effects other than these can be extracted from the description in the specification, drawings, and claims.

[0031] FIGS. 1A, 1B, 1C, 1D, 1E, and 1F are diagrams illustrating a structural example of a semiconductor device. FIGS. 2A, 2B, 2C, 2D, 2E, and 2F are diagrams illustrating a structural example of a semiconductor device. FIGS. 3A and 3B are diagrams illustrating a structural example of a semiconductor device. FIGS. 4A and 4B are diagrams illustrating a manufacturing method of a semiconductor device. FIGS. 5A and 5B are diagrams illustrating a manufacturing method of a semiconductor device. FIGS. 6A and 6B are diagrams illustrating a manufacturing method of a semiconductor device. FIGS. 7A and 7B are diagrams illustrating a manufacturing method of a semiconductor device. FIGS. 8A and 8B are diagrams illustrating a manufacturing method of a semiconductor device. FIGS. 9A, 9B, 9C, 9D, and 9E are diagrams illustrating a manufacturing method of a semiconductor device. FIGS. 10A, 10B, 10C, 10D, and 10E are diagrams illustrating a manufacturing method of a semiconductor device. 11A, 11B, 11C, 11D, and 11E are diagrams illustrating an example of a method for manufacturing a semiconductor device. 12A, 12B, 12C, 12D, and 12E are diagrams illustrating an example of a method for manufacturing a semiconductor device. 13A, 13B, 13C, 13D, and 13E are diagrams illustrating an example of a method for manufacturing a semiconductor device. 14A, 14B, 14C, 14D, and 14E are diagrams illustrating an example of a method for manufacturing a semiconductor device. 15A, 15B, 15C, 15D, and 15E are diagrams illustrating an example of a method for manufacturing a semiconductor device. 16A, 16B, 16C, 16D, and 16E are diagrams illustrating an example of a method for manufacturing a semiconductor device. 17A, 17B, 17C, 17D, and 17E are diagrams illustrating an example of a method for manufacturing a semiconductor device. 18A, 18B, 18C, 18D, and 18E are diagrams illustrating an example of a method for manufacturing a semiconductor device. 19A, 19B, 19C, 19D, and 19E are diagrams illustrating an example of a method for manufacturing a semiconductor device. 20A, 20B, 20C, 20D, and 20E are diagrams illustrating an example of a method for manufacturing a semiconductor device. 21A, 21B, 21C, 21D, and 21E are diagrams illustrating an example of a method for manufacturing a semiconductor device. 22A, 22B, 22C, 22D, and 22E are diagrams illustrating an example of a method for manufacturing a semiconductor device. 23A, 23B, 23C, 23D, and 23E are diagrams illustrating an example of a method for manufacturing a semiconductor device.24A, 24B, 24C, 24D, and 24E are diagrams illustrating an example of a method for manufacturing a semiconductor device. FIGS. 25A, 25B, 25C, 25D, and 25E are diagrams illustrating an example of a method for manufacturing a semiconductor device. FIGS. 26A, 26B, 26C, 26D, and 26E are diagrams illustrating an example of a method for manufacturing a semiconductor device. FIG. 27 is a diagram illustrating a structural example of a semiconductor device. FIGS. 28A and 28B are diagrams illustrating a structural example of a semiconductor device. FIGS. 29A, 29B, and 29C are diagrams illustrating a structural example of a semiconductor device. FIGS. 30A, 30B, and 30C are diagrams illustrating a structural example of a semiconductor device. FIGS. 31A, 31B, 31C, 31D, 31E, and 31F are diagrams illustrating a structural example of a semiconductor device. FIGS. 32A and 32B are diagrams illustrating a structural example of a semiconductor device. 33A and 33B are diagrams illustrating an example of a method for manufacturing a semiconductor device. FIGS. 34A, 34B, 34C, 34D, and 34E are diagrams illustrating an example of a method for manufacturing a semiconductor device. FIGS. 35A, 35B, 35C, 35D, and 35E are diagrams illustrating an example of a method for manufacturing a semiconductor device. FIGS. 36A, 36B, 36C, 36D, and 36E are diagrams illustrating an example of a method for manufacturing a semiconductor device. FIGS. 37A, 37B, 37C, 37D, and 37E are diagrams illustrating an example of a method for manufacturing a semiconductor device. FIGS. 38A, 38B, 38C, 38D, and 38E are diagrams illustrating an example of a method for manufacturing a semiconductor device. FIGS. 39A, 39B, 39C, 39D, and 39E are diagrams illustrating an example of a method for manufacturing a semiconductor device. FIG. 40 is a diagram illustrating a configuration example of a semiconductor device. Figs. 41A and 41B are diagrams illustrating a configuration example of a semiconductor device. Figs. 42A, 42B, and 42C are diagrams illustrating a configuration example of a semiconductor device. Figs. 43A and 43B are cross-sectional views showing a configuration example of a memory device. Figs. 44A and 44B are cross-sectional views showing a configuration example of a memory device. Figs. 45A and 45B are diagrams illustrating a configuration example of a memory device. Fig. 46 is a diagram illustrating a configuration example of a memory device. Fig. 47 is a cross-sectional view showing a configuration example of a semiconductor device. Fig. 48 is a cross-sectional view showing a configuration example of a memory device. Fig. 49A is an equivalent circuit diagram of a logic circuit. Fig. 49B is a diagram showing a circuit symbol for a logic circuit.FIG. 49C is a timing chart illustrating the operation of a logic circuit. FIGS. 50A and 50D are equivalent circuit diagrams of logic circuits. FIGS. 50B, 50C, 50E, and 50F are diagrams showing circuit symbols for logic circuits. FIG. 51A is a diagram showing the circuit symbol for a buffer circuit. FIG. 51B is a diagram showing an example configuration of a buffer circuit. FIG. 51C is a timing chart illustrating the operation of a buffer circuit. FIG. 51D is a diagram showing an example configuration of a ring oscillator. FIG. 51E is a diagram illustrating oscillation of a ring oscillator. FIG. 52A is an equivalent circuit diagram of a DFF circuit. FIG. 52B is a diagram showing the circuit symbol for a DFF circuit. FIG. 53A is a diagram showing an example configuration of a shift register circuit. FIG. 53B is a timing chart illustrating the operation of a shift register circuit. FIGS. 54A and 54B are diagrams showing an example configuration of a selector. FIG. 54C is a diagram showing an example configuration of an analog switch. FIG. 55A is a circuit diagram illustrating a configuration example of a logic circuit including a semiconductor device of one embodiment of the present invention, and FIG. 55B is a timing chart. FIGS. 56A and 56B are circuit diagrams illustrating a configuration example of a logic circuit including a semiconductor device of one embodiment of the present invention. FIG. 57 is a block diagram illustrating a configuration example of a semiconductor device. FIGS. 58A, 58B, 58C, 58D, 58E, 58F, 58G, 58H, and 58I are diagrams illustrating circuit configuration examples of memory cells. FIGS. 59A and 59B are diagrams illustrating examples of electronic components. FIGS. 60A, 60B, and 60C are diagrams illustrating an example of a mainframe computer. FIG. 60D is a diagram illustrating an example of space equipment. FIG. 60E is a diagram illustrating an example of a storage system that can be used in a data center.

[0032] The embodiments will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it will be readily understood by those skilled in the art that various changes can be made in form and detail without departing from the spirit and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the description of the embodiments shown below.

[0033] In the configuration of the invention described below, the same parts or parts having similar functions are denoted by the same reference numerals in different drawings, and repeated explanations thereof will be omitted. Furthermore, when referring to similar functions, the same hatching pattern may be used and no particular reference numeral may be assigned.

[0034] Furthermore, for ease of understanding, the position, size, range, etc. of each component shown in the drawings may not represent the actual position, size, range, etc. Therefore, the disclosed invention is not necessarily limited to the position, size, range, etc. disclosed in the drawings.

[0035] In this specification, the ordinal numbers "first" and "second" are used for convenience and do not limit the number of components or the order of the components (for example, the order of processes or the order of stacking). Furthermore, the ordinal numbers assigned to components in one part of this specification may not match the ordinal numbers assigned to the same components in other parts of this specification or in the claims.

[0036] A transistor is a type of semiconductor element that can amplify current or voltage, and perform a switching operation to control conduction or non-conduction. The term "transistor" as used herein includes an insulated gate field effect transistor (IGFET) and a thin film transistor (TFT).

[0037] In this specification and the like, a transistor using an oxide semiconductor or a metal oxide for a semiconductor layer and a transistor having an oxide semiconductor or a metal oxide for a channel formation region may be referred to as an OS transistor. A transistor having silicon for a channel formation region may be referred to as a Si transistor.

[0038] In this specification and the like, a transistor is an element having at least three terminals including a gate, a drain, and a source. A transistor has a region (also referred to as a channel formation region) where a channel is formed between the drain (drain terminal, drain region, or drain electrode) and the source (source terminal, source region, or source electrode), and current can flow between the source and the drain through the channel formation region. Note that in this specification and the like, the channel formation region refers to a region through which current mainly flows.

[0039] Furthermore, the functions of "source" and "drain" may be interchangeable when transistors of different polarities are used, or when the direction of current flow changes during circuit operation, etc. For this reason, the terms "source" and "drain" may be used interchangeably in this specification.

[0040] Note that impurities in a semiconductor refer to, for example, elements other than the main components constituting the semiconductor. For example, an element with a concentration of less than 0.1 atomic % can be considered an impurity. The presence of impurities may increase the density of defect states in the semiconductor or reduce the crystallinity, for example. When the semiconductor is an oxide semiconductor, impurities that change the characteristics of the semiconductor include, for example, Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, Group 15 elements, and transition metals other than the main components of the oxide semiconductor. Specific examples include hydrogen, lithium, sodium, silicon, boron, phosphorus, carbon, and nitrogen. Note that water may also function as an impurity. For example, the inclusion of impurities may cause oxygen deficiency (V Ｏ In some cases, a nucleus (also referred to as a nucleus) may be formed.

[0041] In this specification and the like, an oxynitride refers to a material having a composition in which oxygen is contained in a larger amount than nitrogen, and a nitride oxide refers to a material having a composition in which nitrogen is contained in a larger amount than oxygen.

[0042] To analyze the content of elements such as hydrogen, oxygen, carbon, or nitrogen contained in a film, for example, secondary ion mass spectrometry (SIMS) or X-ray photoelectron spectroscopy (XPS) can be used. XPS is suitable when the content of the target element is high (e.g., 0.5 atomic % or more, or 1 atomic % or more). On the other hand, SIMS is suitable when the content of the target element is low (e.g., 0.5 atomic % or less, or 1 atomic % or less). When comparing the content of elements, it is more preferable to perform a combined analysis using both SIMS and XPS analytical techniques.

[0043] In this specification and the like, the term "content" refers to the ratio of a component contained in a film. For example, when an oxide semiconductor layer contains a metal element X, a metal element Y, and a metal element Z, the number of atoms of each of the metal elements X, Y, and Z contained in the oxide semiconductor layer is expressed as A Ｘ , A Ｙ , A Ｚ When the content of the metal element X is Ｘ / (A Ｘ +A Ｙ +A Ｚ In addition, the ratio of the number of atoms of the metal element X, the metal element Y, and the metal element Z in the oxide semiconductor layer (atomic ratio) can be expressed as follows: Ｘ : B Ｙ : B Ｚ When the content of the metal element X is expressed as B Ｘ / (B Ｘ +B Ｙ +B Ｚ ) can be shown as

[0044] The terms "film" and "layer" can be interchangeable depending on the circumstances. For example, the term "conductive layer" can be changed to the term "conductive film." Or, for example, the term "insulating film" can be changed to the term "insulating layer."

[0045] Furthermore, in this specification, "parallel" refers to a state in which two straight lines are arranged at an angle of -10 degrees or more and 10 degrees or less. Therefore, it also includes cases in which the angle is -5 degrees or more and 5 degrees or less. Furthermore, "substantially parallel" refers to a state in which two straight lines are arranged at an angle of -20 degrees or more and 20 degrees or less. Furthermore, "perpendicular" refers to a state in which two straight lines are arranged at an angle of 80 degrees or more and 100 degrees or less. Therefore, it also includes cases in which the angle is 85 degrees or more and 95 degrees or less. Furthermore, "substantially perpendicular" refers to a state in which two straight lines are arranged at an angle of 70 degrees or more and 110 degrees or less.

[0046] In this specification, "connection" includes, as an example, "electrical connection." Note that the term "electrical connection" is sometimes used to define the connection relationship between circuit elements as a physical entity. Furthermore, "electrical connection" includes "direct connection" and "indirect connection." "A and B are directly connected" means that A and B are connected without the intervention of a circuit element (e.g., a transistor, a switch, etc.; wiring is not considered a circuit element). On the other hand, "A and B are indirectly connected" means that A and B are connected via one or more circuit elements.

[0047] For example, assuming that a circuit including A and B is operating, if there is a time during the operation of the circuit when an electrical signal is exchanged or an interaction of electrical potential occurs between A and B, then it can be defined that "A and B are indirectly connected" as objects. Note that even if there is a time during the operation of the circuit when no electrical signal is exchanged or an interaction of electrical potential occurs between A and B, it can still be defined that "A and B are indirectly connected" as long as there is a time during the operation of the circuit when an electrical signal is exchanged or an interaction of electrical potential occurs between A and B.

[0048] An example of a case where "A and B are indirectly connected" is when A and B are connected via the source and drain of one or more transistors. On the other hand, an example of a case where it cannot be said that "A and B are indirectly connected" is when an insulator is present in the path from A to B. Specifically, there are cases where a capacitive element is connected between A and B, and cases where a gate insulating film of a transistor is present between A and B. Therefore, it cannot be said that "the gate (A) of a transistor and the source or drain (B) of the transistor are indirectly connected."

[0049] Another example of a case where it cannot be said that "A and B are indirectly connected" is when multiple transistors are connected via their sources and drains to the path from A to B, and a constant potential V is supplied to a node between one transistor and another transistor from a power supply, GND, etc.

[0050] In this specification and the like, unless otherwise specified, the off-state current refers to the leakage current between the source and drain when the transistor is in an off state (also referred to as a non-conducting state or a cut-off state). Unless otherwise specified, the off-state current refers to the leakage current between the source and the gate when the voltage V ｇｓ is the threshold voltage V ｔｈ (For p-channel transistors, V ｔｈ This refers to a state of being (higher than)

[0051] In this specification, the term "normally-on" refers to a state in which a channel exists and a current flows through a transistor even when no voltage is applied to the gate, whereas the term "normally-off" refers to a state in which no current flows through a transistor when no potential is applied to the gate or when a ground potential is applied to the gate.

[0052] In this specification, a tapered shape refers to a shape in which at least a portion of the side surface of a structure is inclined relative to the substrate surface or the surface to be formed. For example, it is preferable to have a region in which the angle (also called the taper angle) between the inclined side surface and the substrate surface or the surface to be formed is greater than 0 degrees and less than 90 degrees. The side surface of the structure, the substrate surface, and the surface to be formed do not necessarily need to be completely flat, and may be approximately planar with a slight curvature or approximately planar with a slight unevenness.

[0053] In this specification, when it is stated that A is located on B, at least a portion of A is located on B. Therefore, for example, it can be rephrased as "A has a region located on B." Similarly, when it is stated that A contacts B or A overlaps B, at least a portion of A contacts B or overlaps B. Therefore, it can be rephrased as "A has a region contacting B" or "A has a region overlapping B," respectively. Similarly, in this specification, when it is stated that A covers B, at least a portion of A covers B. Therefore, for example, it can be rephrased as "A has a region covering B."

[0054] In this specification and the like, a step disconnection refers to a phenomenon in which a layer, a film, or an electrode is separated due to the shape of the surface on which it is formed (for example, a step or the like).

[0055] In the drawings and the like relating to this specification, arrows indicating the X direction, Y direction, and Z direction may be used. In this specification and the like, the "X direction" refers to the direction along the X axis, and there may be no distinction between the forward direction and the reverse direction unless explicitly stated. The same applies to the "Y direction" and the "Z direction." The X direction, Y direction, and Z direction are directions that intersect with each other. For example, the X direction, Y direction, and Z direction are directions that are perpendicular to each other.

[0056] Embodiment 1 In this embodiment, a semiconductor device of one embodiment of the present invention and a manufacturing method thereof will be described with reference to FIGS.

[0057] <Structural Example 1 of Semiconductor Device> A structure of a semiconductor device of one embodiment of the present invention will be described with reference to FIGS. 1A to 3A. FIG.

[0058] 1A to 1F are perspective views of a semiconductor device having a transistor 10. FIG. 1B shows a portion of FIG. 1A omitted. Each of FIGS. 1C to 1F shows only some components. FIG. 1D shows some components omitted.

[0059] 1A to 1F, the X direction, the Y direction, and the Z direction are indicated by arrows. Note that, for example, although the same X, Y, and Z symbols are used in FIGS. 1A to 1F, the directions do not necessarily have to match between them.

[0060] FIG. 2A is a plan view of a semiconductor device including a transistor 10. FIGS. 2B, 2C, 2D, and 2E are cross-sectional views taken along dashed-dotted lines A1-A2, A3-A4, B1-B2, and B3-B4, respectively, shown in FIG. 2A . FIGS. 2B and 2C are cross-sectional views of the transistor 10 in the channel length direction, and FIGS. 2D and 2E are cross-sectional views of the transistor 10 in the channel width direction. FIG. 2F is a cross-sectional view including dashed-dotted line C1-C2 shown in FIG. 2B . Note that some elements are omitted from the plan view of FIG. 2A for clarity. Some elements may also be omitted in subsequent plan views.

[0061] 1A to 2F includes an insulating layer 22 over a substrate 21, a transistor 10 over the insulating layer 22, insulating layers 16 and 17 over the insulating layer 22, insulating layers 18 over the insulating layers 16 and 17, and conductive layers 19a and 19b. The insulating layer 22, the insulating layer 17, and the insulating layer 18 function as interlayer films.

[0062] The transistor 10 includes an insulating layer 15, a semiconductor layer 11, conductive layers 14a and 14b, an insulating layer 12, and a conductive layer 13. Note that Figures 2A to 2D show an example in which the conductive layer 13 has a two-layer structure.

[0063] In the transistor 10, the semiconductor layer 11 functions as a semiconductor layer, the conductive layer 13 functions as a gate electrode, the insulating layer 12 functions as a gate insulating layer, the conductive layer 14a functions as one of a source electrode and a drain electrode, and the conductive layer 14b functions as the other of the source electrode and the drain electrode. The conductive layer 13 has a region that functions as a gate wiring.

[0064] 1C, the semiconductor layer 11 is provided so as to cover the side surfaces of the insulating layer 15. The insulating layer 15 and the semiconductor layer 11 are provided on the insulating layer 22.

[0065] 1C, the insulating layer 22 has a recess 26 surrounding the insulating layer 15 and the semiconductor layer 11. The inner sidewall of the recess 26 is flush with or approximately flush with the side surface of the semiconductor layer 11.

[0066] 1E, 2B, etc., the conductive layer 14a and the conductive layer 14b are provided separately on the insulating layer 22. Furthermore, each of the conductive layer 14a and the conductive layer 14b is provided so as to fill a part of the recess 26. A part of the side surface of the conductive layer 14a is aligned or approximately aligned with the outer side wall of the recess 26. A part of the side surface of the conductive layer 14b is aligned or approximately aligned with the outer side wall of the recess 26. Each of the conductive layer 14a and the conductive layer 14b does not contact the top surface of the semiconductor layer 11.

[0067] As shown in FIG. 2F , the conductive layer 14a contacts the C1-side side of the semiconductor layer 11, a portion of the B1-side side, and a portion of the B2-side side. By configuring the conductive layer 14a to contact three surfaces of the semiconductor layer 11 in this manner, the contact area between the conductive layer 14a and the semiconductor layer 11 can be increased. Therefore, the contact resistance between the semiconductor layer 11 and the conductive layer 14a can be reduced. Similarly, the conductive layer 14b contacts the C2-side side of the semiconductor layer 11, another portion of the B1-side side, and another portion of the B2-side side. By configuring the conductive layer 14b to contact three surfaces of the semiconductor layer 11 in this manner, the contact area between the conductive layer 14b and the semiconductor layer 11 can be increased. Therefore, the contact resistance between the semiconductor layer 11 and the conductive layer 14b can be reduced.

[0068] 1F, 2D, etc., the insulating layer 12 is provided so as to cover a portion of the insulating layer 15 and the semiconductor layer 11. The insulating layer 12 is provided so as to fill another portion of the recess 26. As shown in Fig. 2D, the insulating layer 12 has a recess in a portion that overlaps with the recess 26.

[0069] As shown in FIG. 2D and other figures, the conductive layer 13 is provided on the insulating layer 12. The conductive layer 13 is provided so as to fill a recess in the insulating layer 12. The conductive layer 13 is provided so as to cover a portion of the insulating layer 15 and the semiconductor layer 11 via the insulating layer 12. The conductive layer 13 does not overlap with either the conductive layer 14a or the conductive layer 14b. The conductive layer 13 also has a portion located between the conductive layer 14a and the conductive layer 14b.

[0070] The conductive layer 13 is preferably provided so as to extend so as to intersect with the semiconductor layer 11. With such a configuration, the conductive layer 13 can function as wiring when a plurality of transistors are provided. Note that, although FIG. 2A illustrates a configuration in which the longitudinal direction of the semiconductor layer 11 and the extending direction of the conductive layer 13 are orthogonal to each other, the present invention is not limited to this. For example, the conductive layer 13 can be provided so that the angle formed between the longitudinal direction of the semiconductor layer 11 and the extending direction of the conductive layer 13 in a plan view is greater than 0° and less than 90°, preferably 10° or greater and 75° or less, more preferably 10° or greater and 45° or less, and even more preferably 20° or greater and 35° or less.

[0071] The insulating layer 16 is provided so as to cover the side surfaces of the conductive layers 14a and 14b, and part of the side surface of the insulating layer 12. As shown in Fig. 1D, the insulating layer 16 has an opening 27. The side surface of the insulating layer 16 on the opening 27 side is flush or approximately flush with the outer sidewall of the recess 26.

[0072] At least a portion of each of the insulating layer 15, the semiconductor layer 11, the conductive layer 14a, the conductive layer 14b, the insulating layer 12, and the conductive layer 13 is located within the opening 27. That is, at least a portion of the transistor 10 is disposed within the opening 27.

[0073] 2F is shown in FIG. 3A. As shown in FIG. 3A, the semiconductor layer 11 has a region 11i facing the conductive layer 13 via the insulating layer 12, a region 11n1 near the conductive layer 14a of the semiconductor layer 11, and a region 11n2 near the conductive layer 14b of the semiconductor layer 11. In the transistor 10, at least a portion of the region 11i functions as a channel formation region, the region 11n1 functions as one of the source region and the drain region, and the region 11n2 functions as the other of the source region and the drain region. In other words, the channel formation region is sandwiched between the source region and the drain region.

[0074] The channel length of the transistor 10 is the distance between the source region and the drain region. That is, the channel length of the transistor 10 is determined by the distance between the conductive layer 14a and the conductive layer 14b. Here, as shown in FIG. 3A , the shortest distance between the conductive layer 14a and the conductive layer 14b is defined as the distance L. By reducing the distance L, the channel length of the transistor 10 can be shortened, thereby improving the on-current and frequency characteristics. In addition, the contact area between the conductive layer 14a and the semiconductor layer 11 and the contact area between the conductive layer 14b and the semiconductor layer 11 can be increased. Therefore, the contact resistance between the semiconductor layer 11 and the conductive layer 14a and the contact resistance between the semiconductor layer 11 and the conductive layer 14b can be reduced.

[0075] On the other hand, by increasing the distance L, the channel length of the transistor 10 can be increased and the off-state current (leakage current) of the transistor 10 can be reduced. Furthermore, the transistor 10 can have high saturation properties. Furthermore, the withstand voltage between the source and drain can be improved, and the reliability of the transistor 10 can be improved.

[0076] FIG. 3B shows an enlarged view of FIG. 2D . As shown in FIG. 3B , the height of the semiconductor layer 11 is defined as height H, and the width of the insulating layer 15 is defined as width T. Note that height H can also be referred to as the height of the insulating layer 15. The channel width of the transistor 10 is determined by height H. Therefore, increasing height H can increase the channel width per unit area. Height H can be, for example, more than 1 to 50 times, preferably 2 to 20 times, and more preferably 2 to 10 times, the width T. Width T can be, for example, 1 nm to 50 nm, preferably 2 nm to 30 nm, and more preferably 2.5 nm to 20 nm. Height H can be, for example, 2 nm to 1000 nm, preferably 2 nm to 300 nm, and more preferably 5 nm to 200 nm.

[0077] As shown in FIG. 3B , in a cross-sectional view in the channel width direction, the semiconductor layer 11 and the conductive layer 13 are provided on the B1-side side and the B2-side side of the insulating layer 15, facing each other with the insulating layer 12 interposed therebetween. That is, the B1-side side and the B2-side side of the semiconductor layer 11 each function as a channel formation region. Therefore, compared to a case where the insulating layer 15 is not provided, the channel width of the transistor 10 can be increased by the B1-side side and the B2-side side of the insulating layer 15. By increasing the channel width, the on-state current, field-effect mobility, frequency characteristics, and the like of the transistor 10 can be improved. This allows a semiconductor device with high operating speed to be provided. Furthermore, the operating speed of a memory device using the semiconductor device can be increased. Furthermore, by providing the insulating layer 15, the channel width can be increased without increasing the area occupied by the transistor 10. This allows for miniaturization or high integration of the semiconductor device. Furthermore, the storage capacity of a memory device using the semiconductor device can be increased.

[0078] The insulating layer 15 having a high aspect ratio shape can be formed, for example, by forming an insulating film that will become the insulating layer 15 in a sidewall shape on the side of a sacrificial layer (sacrificial layer 31 described later) and then removing the sacrificial layer.

[0079] As shown in FIG. 2D , by having the recess 26 in the insulating layer 22, the lower surface (which can also be referred to as the lower end or bottom edge) of the conductive layer 13 at the position overlapping with the recess 26 can be configured to be located lower (closer to the substrate 21) than the lower surface of the semiconductor layer 11, compared to when the recess 26 is not present. This configuration allows a sufficient gate electric field to be applied from the upper end to the lower end of the semiconductor layer 11. This reduces leakage current between the source electrode and the drain electrode via the bottom edge of the semiconductor layer 11. Furthermore, it is possible to suppress characteristic defects, such as normally-on transistor behavior, that are caused by this leakage current. In other words, it is possible to improve the electrical characteristics of the transistor 10.

[0080] The insulating layer 17 is provided on the outside of the insulating layer 16. The height of the upper surface of the insulating layer 17 is the same as or approximately the same as the height of the upper surface of the insulating layer 16.

[0081] The insulating layer 18 is provided on the insulating layer 15 , the semiconductor layer 11 , the conductive layer 14 a , the conductive layer 14 b , the insulating layer 16 , and the insulating layer 17 .

[0082] Conductive layer 19a is provided in an opening formed in insulating layer 18, and has a portion in contact with conductive layer 14a. Similarly, conductive layer 19b is provided in an opening formed in insulating layer 18, and has a portion in contact with conductive layer 14b. Conductive layer 19a functions as a plug connected to conductive layer 14a, and conductive layer 19b functions as a plug connected to conductive layer 14b. Note that Figures 2A and 2B show examples in which conductive layer 19a and conductive layer 19b each have a two-layer structure.

[0083] <Constituent Materials of Semiconductor Device> Materials that can be used in the semiconductor device of this embodiment will be described below. Note that each layer that constitutes the semiconductor device of this embodiment may have a single-layer structure or a multilayer structure.

[0084] [Semiconductor Layer] The transistor 10 preferably includes a metal oxide (also referred to as an oxide semiconductor) functioning as a semiconductor in the semiconductor layer 11 including a channel formation region. In this case, the transistor 10 can be said to be an OS transistor.

[0085] An OS transistor has an oxygen vacancy (V Ｏ ) and impurities, the electrical characteristics are likely to fluctuate and reliability may be reduced. Ｏ H) may generate electrons that serve as carriers. Therefore, if oxygen vacancies are present in the channel formation region of the oxide semiconductor, the OS transistor is likely to have normally-on characteristics. Therefore, it is preferable that oxygen vacancies and impurities are reduced as much as possible in the channel formation region of the oxide semiconductor. In other words, it is preferable that the carrier concentration of the channel formation region of the oxide semiconductor is reduced and the channel formation region of the oxide semiconductor is made i-type (intrinsic) or substantially i-type.

[0086] On the other hand, the source and drain regions of an OS transistor have more oxygen vacancies than the channel formation region. Ｏ The source and drain regions of an OS transistor are preferably n-type regions having a high carrier concentration and low resistance, as compared with a channel formation region, due to a high concentration of H or impurities such as hydrogen, nitrogen, or a metal element.

[0087] The band gap of a metal oxide functioning as a semiconductor is preferably 2.0 eV or more, more preferably 2.5 eV or more. By using a metal oxide having a band gap wider than that of silicon for the semiconductor layer 11, the off-state current of the transistor 10 can be reduced. Because the off-state current of an OS transistor is small, the power consumption of the semiconductor device can be sufficiently reduced. Furthermore, because the frequency characteristics of an OS transistor are high, the semiconductor device can operate at high speed.

[0088] The metal oxide that can be used for the semiconductor layer 11 preferably contains at least indium (In). The metal oxide preferably contains at least one of indium and zinc (Zn). The metal oxide preferably contains two or three elements selected from indium, element M, and zinc. The element M is a metal element or a metalloid element that has a high bond energy with oxygen, for example, a metal element or a metalloid element that has a higher bond energy with oxygen than indium.

[0089] Specific examples of the element M include aluminum, gallium, tin, yttrium, titanium, vanadium, chromium, manganese, iron, cobalt, nickel, zirconium, molybdenum, hafnium, tantalum, tungsten, lanthanum, cerium, neodymium, magnesium, calcium, strontium, barium, boron, silicon, germanium, antimony, etc. The element M contained in the metal oxide is preferably one or more of the above elements, more preferably one or more selected from aluminum, gallium, tin, and yttrium, and even more preferably gallium.

[0090] For example, indium oxide (In oxide) can be used as a metal oxide for the semiconductor layer 11. Examples of the metal oxide include zinc oxide (Zn oxide), indium zinc oxide (In—Zn oxide, also referred to as IZO (registered trademark)), indium tin oxide (In—Sn oxide, also referred to as ITO), indium titanium oxide (In—Ti oxide), indium gallium oxide (In—Ga oxide), indium gallium aluminum oxide (In—Ga—Al oxide), indium gallium tin oxide (In—Ga—Sn oxide), gallium zinc oxide (Ga—Zn oxide, also referred to as “GZO”), and aluminum zinc oxide (Al—Zn oxide, also referred to as “AZO”). Indium aluminum zinc oxide (In-Al-Zn oxide, also referred to as "IAZO"), indium tin zinc oxide (In-Sn-Zn oxide), indium titanium zinc oxide (In-Ti-Zn oxide), indium gallium zinc oxide (In-Ga-Zn oxide, also referred to as "IGZO"), indium gallium tin zinc oxide (In-Ga-Sn-Zn oxide, also referred to as "IGZTO"), indium gallium aluminum zinc oxide (In-Ga-Al-Zn oxide, also referred to as "IGAZO" or "IAGZO"), etc., can be used. Alternatively, silicon-containing indium tin oxide, gallium tin oxide (Ga-Sn oxide), aluminum tin oxide (Al-Sn oxide), etc. can be used.

[0091] Examples of the crystalline structure of a metal oxide that functions as a semiconductor include an amorphous structure, a c-axis-aligned crystalline (CAAC) structure, a nanocrystalline (nc) structure, a single crystal structure, and a polycrystalline structure.

[0092] Furthermore, by increasing the ratio of the number of zinc atoms to the total number of atoms of the metal elements among the main component elements contained in the metal oxide that functions as a semiconductor, the metal oxide can be made highly crystalline, and the diffusion of impurities in the metal oxide can be suppressed, thereby suppressing fluctuations in the electrical characteristics of the transistor and improving its reliability.

[0093] Furthermore, by increasing the ratio of the number of atoms of element M to the sum of the number of atoms of metal elements among the main component elements contained in the metal oxide, the formation of oxygen vacancies in the metal oxide can be suppressed. Therefore, carrier generation due to oxygen vacancies can be suppressed, and a transistor with a small off-state current can be obtained. Furthermore, fluctuations in the electrical characteristics of the transistor can be suppressed, and reliability can be improved.

[0094] By increasing the ratio of the number of indium atoms to the sum of the numbers of atoms of all metal elements contained in the metal oxide, the field-effect mobility of the transistor can be increased. Typically, by using single-crystal or polycrystalline indium oxide for the semiconductor layer, the field-effect mobility of the transistor can be significantly increased. Furthermore, a transistor using single-crystal or polycrystalline indium oxide for the semiconductor layer can achieve good frequency characteristics.

[0095] Here, the influence of each impurity in an oxide semiconductor will be described.

[0096] As described above, in a transistor using an oxide semiconductor for a semiconductor layer, oxygen vacancies (V Ｏ The presence of impurities may cause fluctuations in electrical characteristics and reduce reliability. Therefore, reducing the impurity concentration in the oxide semiconductor is effective for stabilizing the electrical characteristics of an OS transistor. To reduce the impurity concentration in the oxide semiconductor, it is preferable to also reduce the impurity concentration in a nearby film. Examples of impurities include hydrogen, carbon, and nitrogen. Note that the impurities in the oxide semiconductor refer to, for example, elements other than the main components constituting the oxide semiconductor. For example, an element with a concentration of less than 0.1 atomic % can be considered an impurity.

[0097] When an oxide semiconductor contains silicon or carbon, which is one of the Group 14 elements, defect levels are formed in the oxide semiconductor. Therefore, the carbon concentration in the channel formation region of the oxide semiconductor obtained by SIMS is 1×10 ２０ atoms / cm ３ Below 5 × 10, preferably １９ atoms / cm３ Less than or equal to 3×10 １９ atoms / cm ３ or less, more preferably 1 × 10 １９ atoms / cm ３ Less than or equal to 3×10 １８ atoms / cm ３ More preferably, 1×10 １８ atoms / cm ３ The silicon concentration in the channel formation region of the oxide semiconductor obtained by SIMS is 1×10 ２０ atoms / cm ３ Below 5 × 10, preferably １９ atoms / cm ３ Less than or equal to 3×10 １９ atoms / cm ３ or less, more preferably 1 × 10 １９ atoms / cm ３ Less than or equal to 3×10 １８ atoms / cm ３ More preferably, 1×10 １８ atoms / cm ３ The following applies.

[0098] Furthermore, when nitrogen is contained in an oxide semiconductor, electrons serving as carriers are generated, the carrier concentration increases, and the semiconductor is likely to become n-type. As a result, a transistor using an oxide semiconductor containing nitrogen as a semiconductor tends to have normally-on characteristics. Alternatively, when nitrogen is contained in an oxide semiconductor, trap states may be formed. As a result, the electrical characteristics of the transistor may become unstable. Therefore, the nitrogen concentration in the channel formation region of the oxide semiconductor obtained by SIMS is 1×10 ２０ atoms / cm ３ Below 5 × 10, preferably １９ atoms / cm ３ or less, more preferably 1 × 10 １９ atoms / cm ３ Less than or equal to 5 × 10, more preferably １８ atoms / cm ３ or less, more preferably 1 × 10 １８ atoms / cm３ or less, more preferably 5 × 10 １７ atoms / cm ３ The following applies.

[0099] Furthermore, hydrogen contained in an oxide semiconductor reacts with oxygen bonded to a metal atom to form water, which may form an oxygen vacancy. Hydrogen entering the oxygen vacancy may generate electrons as carriers. Furthermore, some of the hydrogen may bond with oxygen bonded to a metal atom to generate electrons as carriers. Therefore, a transistor using an oxide semiconductor containing hydrogen is likely to have normally-on characteristics. Therefore, it is preferable to reduce hydrogen as much as possible in the channel formation region of the oxide semiconductor. Specifically, the hydrogen concentration in the channel formation region of the oxide semiconductor obtained by SIMS is 1×10 ２０ atoms / cm ３ Less than 5×10 １９ atoms / cm ３ less than 1×10 １９ atoms / cm ３ less than 5×10 １８ atoms / cm ３ less than 1×10 １８ atoms / cm ３ less than 1×10 １７ atoms / cm ３ Less than.

[0100] Furthermore, when an oxide semiconductor contains an alkali metal or an alkaline earth metal, defect levels may be formed and carriers may be generated. Therefore, a transistor using an oxide semiconductor containing an alkali metal or an alkaline earth metal is likely to have normally-on characteristics. Therefore, when the concentration of the alkali metal or the alkaline earth metal in the channel formation region of the oxide semiconductor obtained by SIMS is set to 1×10 １８ atoms / cm ３ Below 2 × 10, preferably １６ atoms / cm ３ Do the following:

[0101] When an oxide semiconductor with sufficiently reduced impurities is used for a channel formation region of a transistor, stable electrical characteristics can be obtained.

[0102] Note that the semiconductor device of this embodiment may also be applied to a transistor using another semiconductor material for a channel formation region, such as a semiconductor made of a single element or a compound semiconductor.

[0103] Examples of semiconductors made of elemental elements that can be used as semiconductor materials include silicon and germanium. Examples of silicon that can be used as semiconductor materials include single-crystal silicon, polycrystalline silicon, microcrystalline silicon, and amorphous silicon. Examples of polycrystalline silicon include low-temperature polysilicon (LTPS).

[0104] Compound semiconductors that can be used for the semiconductor material include silicon carbide, silicon germanium, gallium arsenide, indium phosphide, boron nitride, and boron arsenide. Boron nitride that can be used for the semiconductor layer preferably has an amorphous structure. Boron arsenide that can be used for the semiconductor layer preferably has a cubic crystal structure. Other examples of compound semiconductors include organic semiconductors and nitride semiconductors. The aforementioned oxide semiconductors are also a type of compound semiconductor. These semiconductor materials may contain impurities as dopants.

[0105] Further, a transistor in which a layered substance functioning as a semiconductor is used for a channel formation region may be applied to the semiconductor device of this embodiment mode.

[0106] In this specification, the term "layered material" refers to a group of materials having a layered crystal structure. Such layered materials have high electrical conductivity within a single layer, i.e., high two-dimensional electrical conductivity. By using a material that functions as a semiconductor and has high two-dimensional electrical conductivity in the channel formation region, a transistor with a large on-state current can be provided.

[0107] In this specification and the like, the layered material may be referred to as a two-dimensional material. Examples of two-dimensional materials that can be used in one embodiment of the present invention include graphene, silicene (a substance in which carbon atoms in graphene are replaced with silicon atoms), germanene (a substance in which carbon atoms in graphene are replaced with germanium atoms), transition metal chalcogenides (TMDs), boron nitride (BN), and black phosphorus. The use of the two-dimensional material can enhance one or more physical properties, such as electron mobility, mechanical strength, and thermal conductivity, compared to semiconductors made of a single element such as silicon or germanium. Furthermore, the two-dimensional material has superior physical properties compared to semiconductors made of a single element such as silicon, and therefore may be referred to as a new materials channel (NMC).

[0108] The layered material may be a chalcogenide. A chalcogenide is a compound containing chalcogen. Chalcogen is a general term for elements belonging to Group 16, including oxygen, sulfur, selenium, tellurium, polonium, and livermorium. Examples of chalcogenides include transition metal chalcogenides and Group 13 chalcogenides.

[0109] Furthermore, it is preferable to use, for example, a transition metal chalcogenide that functions as a semiconductor as a material that can be used for the semiconductor layer 11. Specifically, the transition metal chalcogenide is molybdenum sulfide (typically, MoS ２ ), molybdenum selenide (typically MoSe ２ ), molybdenum telluride (typically MoTe ２ ), tungsten sulfide (typically WS ２ ), tungsten selenide (typically WSe ２ ), tungsten tellurium (typically WTe ２ ), hafnium sulfide (typically HfS ２ ), hafnium selenide (typically HfSe ２ ), zirconium sulfide (typically ZrS ２), zirconium selenide (typically ZrSe ２ ) etc.

[0110] The crystallinity of the semiconductor material used for the semiconductor layer 11 is not particularly limited, and any of an amorphous semiconductor, a single crystal semiconductor, and a semiconductor having crystallinity other than single crystal (a microcrystalline semiconductor, a polycrystalline semiconductor, or a semiconductor having a crystalline region in part) may be used. Use of a single crystal semiconductor or a crystalline semiconductor is preferable because it can suppress deterioration of transistor characteristics.

[0111] [Insulating Layer] It is preferable to use an inorganic insulating film for each of the insulating layers (insulating layer 12, insulating layer 15, insulating layer 16, insulating layer 17, insulating layer 18, insulating layer 22, etc.) included in the semiconductor device. Examples of inorganic insulating films include an oxide insulating film, a nitride insulating film, an oxynitride insulating film, and a nitride oxide insulating film. Examples of oxide insulating films include a silicon oxide film, an aluminum oxide film, a magnesium oxide film, a gallium oxide film, a germanium oxide film, a yttrium oxide film, a zirconium oxide film, a lanthanum oxide film, a neodymium oxide film, a hafnium oxide film, a tantalum oxide film, a cerium oxide film, a gallium zinc oxide film, and a hafnium aluminate film. Examples of nitride insulating films include a silicon nitride film and an aluminum nitride film. Examples of oxynitride insulating films include a silicon oxynitride film, an aluminum oxynitride film, a gallium oxynitride film, an yttrium oxynitride film, and a hafnium oxynitride film. Examples of nitride oxide insulating films include a silicon nitride oxide film and an aluminum nitride oxide film. Furthermore, an organic insulating film may be used for the insulating layer of the semiconductor device.

[0112] For example, as transistors become more miniaturized and highly integrated, problems such as leakage current may occur due to thinner gate insulating layers. Using a high-dielectric-constant (high-k) material for the gate insulating layer allows for lower voltage operation of the transistor while maintaining the physical film thickness. Furthermore, it also allows for thinner equivalent oxide thickness (EOT) of the gate insulating layer. On the other hand, using a material with a low dielectric constant for the insulating layer that functions as an interlayer film can reduce the parasitic capacitance that occurs between wirings. Therefore, it is preferable to select materials according to the function of the insulating layer. Note that materials with a low dielectric constant also have high dielectric strength.

[0113] Examples of materials with a high relative dielectric constant include aluminum oxide, gallium oxide, hafnium oxide, tantalum oxide, zirconium oxide, hafnium zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxynitrides containing silicon and hafnium, and nitrides containing silicon and hafnium.

[0114] Examples of materials with a low dielectric constant include inorganic insulating materials such as silicon oxide, silicon oxynitride, and silicon nitride oxide, and resins such as polyester, polyolefin, polyamide (nylon, aramid, etc.), polyimide, polycarbonate, and acrylic resin. Other inorganic insulating materials with a low dielectric constant include silicon oxide containing fluorine, silicon oxide containing carbon, and silicon oxide containing carbon and nitrogen. Another example is silicon oxide having vacancies. These silicon oxides may contain nitrogen.

[0115] Furthermore, a material that can exhibit ferroelectricity may be used for an insulating layer of a semiconductor device. As the material that can exhibit ferroelectricity, it is preferable to use an oxide containing one or both of hafnium and zirconium. Examples of such oxides include metal oxides such as hafnium oxide, zirconium oxide, and hafnium zirconium oxide. Furthermore, as the material that can exhibit ferroelectricity, a material obtained by adding an element J1 (here, the element J1 is one or more selected from the other of hafnium and zirconium, silicon, aluminum, gadolinium, yttrium, lanthanum, strontium, etc.) to a metal oxide containing one of hafnium and zirconium may be used.

[0116] Furthermore, adding a Group 3 element in the periodic table to an oxide containing one or both of hafnium and zirconium increases the oxygen vacancy concentration in the oxide, making it easier to form crystals with an orthorhombic crystal structure. This is preferable because it increases the proportion of crystals with an orthorhombic crystal structure and increases remanent polarization. On the other hand, adding too much of the Group 3 element may reduce the crystallinity of the oxide, making it difficult to exhibit ferroelectricity. Therefore, the content of the Group 3 element in the oxide containing one or both of hafnium and zirconium is preferably 0.1 atomic % to 10 atomic %, more preferably 0.1 atomic % to 5 atomic %, and even more preferably 0.1 atomic % to 3 atomic %. Here, the content of the Group 3 element refers to the ratio of the number of atoms of the Group 3 element to the sum of the number of atoms of all metal elements contained in the layer. The Group 3 element is preferably one or more selected from scandium, lanthanum, and yttrium, and more preferably one or both of lanthanum and yttrium.

[0117] Furthermore, examples of materials that can have ferroelectricity include metal nitrides containing at least one of element M1 and element M2 and nitrogen. Here, element M1 is one or more selected from aluminum, gallium, indium, etc. Furthermore, element M2 is one or more selected from boron, scandium, yttrium, lanthanum, cerium, neodymium, europium, titanium, zirconium, hafnium, vanadium, niobium, tantalum, chromium, etc. Furthermore, examples of materials that can have ferroelectricity include materials in which element M3 is added to the above metal nitrides. Note that element M3 is one or more selected from magnesium, calcium, strontium, zinc, cadmium, etc.

[0118] Furthermore, materials that can have ferroelectricity include SrTaO ２ N and BaTaO ２ Perovskite-type oxynitrides such as N, GaFeO with κ-alumina structure ３ Furthermore, examples of materials that can have ferroelectricity include lead titanate (PbTiO Ｘ Piezoelectric ceramics having a perovskite structure, such as barium strontium titanate (BST), strontium titanate, lead zirconate titanate (PZT), strontium bismuth tantalate (SBT), bismuth ferrite (BFO), or barium titanate, may also be used.

[0119] In the above description, metal oxides and metal nitrides are used as examples, but the present invention is not limited to these. For example, metal oxynitrides in which nitrogen is added to the aforementioned metal oxides, or metal oxynitrides in which oxygen is added to the aforementioned metal nitrides, may also be used.

[0120] Furthermore, as a material capable of exhibiting ferroelectricity, for example, a mixture or compound of a plurality of materials selected from the materials listed above can be used. However, since the crystal structure (characteristics) of the materials listed above may change depending not only on the film formation conditions but also on various processes, in this specification and the like, a material that exhibits ferroelectricity is not only called a ferroelectric but also called a material capable of exhibiting ferroelectricity.

[0121] In this specification, a layer of a material that can have ferroelectricity may be referred to as a ferroelectric layer, a metal oxide film, or a metal nitride film. Also, in this specification, a device having such a ferroelectric layer, a metal oxide film, or a metal nitride film may be referred to as a ferroelectric device.

[0122] The ferroelectric layer preferably contains crystals having an orthorhombic crystal structure, since this allows ferroelectricity to be exhibited. The crystal structure of the crystals contained in the ferroelectric layer may be one or more selected from the group consisting of tetragonal, orthorhombic, monoclinic, and hexagonal. The ferroelectric layer may also have an amorphous structure. In this case, the ferroelectric layer may have a composite structure having an amorphous structure and a crystalline structure.

[0123] A metal oxide containing one or both of hafnium and zirconium is also an insulating material that has the function of capturing or fixing hydrogen. Therefore, by using a metal oxide containing one or both of hafnium and zirconium for at least a part of a gate insulating layer, hydrogen contained in the oxide semiconductor layer can be captured or fixed, thereby reducing the hydrogen concentration in the oxide semiconductor layer. Furthermore, a transistor having the gate insulating layer can function as a ferroelectric field effect transistor (FeFET).

[0124] Furthermore, a transistor using a metal oxide can have stable electrical characteristics by being surrounded by an insulating layer that has a function of suppressing the permeation of impurities and oxygen. The insulating layer that has a function of suppressing the permeation of impurities and oxygen can be, for example, a single-layer or stacked insulating layer containing one or more elements selected from boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, and tantalum. Specifically, the insulating layer that has a function of suppressing the permeation of impurities and oxygen can be made of oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, or tantalum oxide; nitrides such as aluminum nitride and silicon nitride; or nitride oxides such as silicon nitride oxide.

[0125] Specifically, examples of materials for the insulating layer that function to suppress the permeation of impurities such as water and hydrogen, and oxygen include metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, tantalum oxide, and oxides containing aluminum and hafnium (hafnium aluminate). Other examples include nitrides such as aluminum nitride, aluminum titanium nitride, and silicon nitride. Other examples include nitride oxides such as silicon nitride oxide.

[0126] An insulating layer, such as a gate insulating layer, that is in contact with an oxide semiconductor layer or that is provided near the oxide semiconductor layer is preferably an insulating layer having a region containing oxygen that is released by heating (hereinafter, sometimes referred to as excess oxygen). For example, when an insulating layer having a region containing excess oxygen is in contact with an oxide semiconductor layer or is located near the oxide semiconductor layer, oxygen vacancies in the oxide semiconductor layer can be reduced. Examples of materials for an insulating layer that are likely to form a region containing excess oxygen include silicon oxide, silicon oxynitride, and silicon oxide having vacancies.

[0127] An insulating layer provided in contact with or near the oxide semiconductor layer is preferably a barrier insulating layer against hydrogen, which can suppress diffusion of hydrogen into the oxide semiconductor layer.

[0128] Examples of insulating materials having the function of capturing or fixing hydrogen include metal oxides such as oxides containing hafnium, oxides containing magnesium, oxides containing aluminum, oxides containing aluminum and hafnium (hafnium aluminate), oxides containing hafnium and silicon (hafnium silicate), etc. These metal oxides may further contain zirconium, such as oxides containing hafnium and zirconium.

[0129] An insulating layer having the function of capturing or fixing hydrogen preferably has an amorphous structure. In a metal oxide having an amorphous structure, some oxygen atoms have dangling bonds, which enhances the ability to capture or fix hydrogen. Therefore, when the insulating layer has an amorphous structure, the function of capturing or fixing hydrogen can be enhanced. For example, an amorphous structure may be realized by adding silicon to the metal oxide. For example, it is preferable to use an oxide containing hafnium and silicon (hafnium silicate).

[0130] By making the insulating layer an amorphous structure, it is possible to suppress the formation of crystal grain boundaries. By suppressing the formation of crystal grain boundaries, it is possible to improve the flatness of the insulating layer. This makes it possible to uniformize the film thickness distribution of the insulating layer and reduce areas with extremely thin film thickness, thereby improving the breakdown voltage of the insulating layer. It is also possible to uniformize the film thickness distribution of a film provided on the insulating layer. Furthermore, by suppressing the formation of crystal grain boundaries in the insulating layer, it is possible to reduce leakage current caused by defect levels at the crystal grain boundaries. Therefore, the insulating layer can function as an insulating film with low leakage current.

[0131] The ability to capture or fix a corresponding substance can also be said to have the property of making it difficult for the corresponding substance to diffuse. Therefore, the ability to capture or fix a corresponding substance can be rephrased as barrier properties.

[0132] In this specification and the like, a barrier insulating layer refers to an insulating layer having barrier properties. The barrier properties are also referred to as a property that makes it difficult for a corresponding substance to diffuse (a property that makes it difficult for a corresponding substance to permeate, a property that the permeability of a corresponding substance is low, or a function that suppresses the diffusion of a corresponding substance). Note that hydrogen when described as a corresponding substance includes, for example, a hydrogen atom, a hydrogen molecule, a water molecule, and OH. − Furthermore, unless otherwise specified, impurities when described as corresponding substances refer to impurities in the channel formation region or semiconductor layer, and include, for example, hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, and nitrogen oxide molecules (N ２ O, NO, NO ２ The term "oxygen" refers to at least one of an oxygen atom, an oxygen molecule, etc., when described as a corresponding substance.

[0133] Examples of materials for the barrier insulating layer against hydrogen include aluminum oxide, magnesium oxide, hafnium oxide, gallium oxide, silicon nitride, and silicon nitride oxide.

[0134] Examples of materials for the barrier insulating layer against oxygen include oxides containing one or both of aluminum and hafnium, magnesium oxide, gallium oxide, gallium zinc oxide, silicon nitride, and silicon nitride oxide. Examples of oxides containing one or both of aluminum and hafnium include aluminum oxide, hafnium oxide, oxides containing aluminum and hafnium (hafnium aluminate), and oxides containing hafnium and silicon (hafnium silicate).

[0135] It is preferable to use a barrier insulating layer against hydrogen as the insulating layer 12. When the insulating layer 12 provided on the semiconductor layer 11 has a barrier property against hydrogen, it is possible to suppress the diffusion of hydrogen contained in the conductive layer 13 into the semiconductor layer 11. For example, a silicon nitride film has a high barrier property against hydrogen and is therefore suitable as the insulating layer 12.

[0136] Furthermore, since the insulating layer 12 is in contact with the semiconductor layer 11, it is preferable to use an insulating layer having the function of capturing or fixing hydrogen. This allows the hydrogen contained in the semiconductor layer 11 to be captured or fixed more effectively. This reduces the hydrogen concentration in the semiconductor layer 11 (particularly in the region 11i). Therefore, the V in the channel formation region Ｏ By reducing H, the channel forming region can be made i-type or substantially i-type.

[0137] Furthermore, it is preferable to use an insulating layer having a region containing excess oxygen as the insulating layer 12. This allows oxygen to be supplied from the insulating layer 12 to the semiconductor layer 11, thereby reducing oxygen vacancies in the semiconductor layer 11. A silicon oxide film or a silicon oxynitride film, for example, has a structure that is stable against heat, and is therefore suitable as the insulating layer 12.

[0138] FIG. 3B and other figures show an example in which the insulating layer 12 has a single-layer structure. The insulating layer 12 can have a laminated structure of two or more layers. In this case, the insulating layer 12 is preferably formed of two or more types of films. By forming the insulating layer 12 into two or more types of films, multiple functions can be imparted to the insulating layer 12. Examples of the functions of the insulating layer 12 include a function of extracting hydrogen from the semiconductor layer 11 and a function of suppressing diffusion of hydrogen into the semiconductor layer 11.

[0139] For example, the insulating layer 12 can have a two-layer structure of a first insulating layer and a second insulating layer on the first insulating layer. In this case, the first insulating layer is in contact with the semiconductor layer 11. For example, it is preferable to use an insulating layer having a function of capturing or fixing hydrogen as the first insulating layer, and to use a barrier insulating layer against hydrogen as the second insulating layer. With such a structure, the hydrogen concentration in the semiconductor layer 11 can be reduced, and diffusion of hydrogen into the semiconductor layer 11 can be suppressed. Therefore, a highly reliable transistor can be realized.

[0140] Alternatively, for example, it is preferable to use an insulating layer having a region containing excess oxygen as the first insulating layer and a barrier insulating layer against hydrogen as the second insulating layer. Alternatively, for example, it is preferable to use an insulating layer having a region containing excess oxygen as the first insulating layer and an insulating layer having a function of capturing or fixing hydrogen as the second insulating layer. With such a structure, the amount of oxygen vacancies and the hydrogen concentration in the semiconductor layer 11 can be reduced, and diffusion of hydrogen into the semiconductor layer 11 can be suppressed. Therefore, a highly reliable transistor can be realized.

[0141] Furthermore, for example, the insulating layer 12 can have a third insulating layer between the semiconductor layer 11 and the first insulating layer. In other words, the insulating layer 12 can have a three-layer structure including the third insulating layer, the first insulating layer on the third insulating layer, and the second insulating layer on the first insulating layer.

[0142] For example, it is preferable to use an insulating layer having a region containing excess oxygen or an insulating layer made of a material with a low dielectric constant as the third insulating layer, an insulating layer having a function of capturing or fixing hydrogen as the first insulating layer, and an insulating layer having barrier properties against hydrogen and oxygen as the second insulating layer. The third insulating layer is preferably a silicon oxide film or a silicon oxynitride film. By using an oxide film for the third insulating layer in contact with the semiconductor layer 11, oxygen can be supplied to the semiconductor layer 11. Furthermore, providing a second insulating layer can suppress diffusion of oxygen contained in the third insulating layer into the conductive layer 13, thereby suppressing oxidation of the conductive layer 13. Furthermore, it is possible to suppress a decrease in the amount of oxygen supplied from the third insulating layer to the semiconductor layer 11.

[0143] Furthermore, for example, the insulating layer 12 can have a fourth insulating layer between the semiconductor layer 11 and the third insulating layer. In other words, the insulating layer 12 can have a four-layer structure including the fourth insulating layer, the third insulating layer on the fourth insulating layer, the first insulating layer on the third insulating layer, and the second insulating layer on the first insulating layer.

[0144] The fourth insulating layer is preferably an insulating layer having a barrier property against oxygen. The first to third insulating layers can have the same structure as the layers used in the three-layer structure described above. The fourth insulating layer is a layer in contact with the semiconductor layer 11, the conductive layer 14a, and the conductive layer 14b. The fourth insulating layer has a barrier property against oxygen, which can prevent oxygen from being released from the semiconductor layer 11. Furthermore, the side surfaces of the conductive layer 14a and the conductive layer 14b from being oxidized and forming an oxide film on the side surfaces can be prevented. This can prevent a decrease in the on-state current or the field-effect mobility of the transistor 10.

[0145] The insulating layer 12 is preferably a thin film. For example, by setting the thickness of the insulating layer 12 to be 1 nm or more and 20 nm or less, preferably 3 nm or more and 10 nm or less, the subthreshold swing value (also referred to as S value), which is one of the transistor characteristics, can be reduced. The S value refers to the amount of change in gate voltage when the drain current is changed by one order of magnitude while the drain voltage is constant in the subthreshold region.

[0146] The thickness of each layer constituting the insulating layer 12 is preferably 0.1 nm to 10 nm, more preferably 0.1 nm to 5 nm, more preferably 0.5 nm to 5 nm, more preferably 1 nm to less than 5 nm, and even more preferably 1 nm to 3 nm. Note that it is sufficient that each layer constituting the insulating layer 12 has a region with the above-mentioned thickness in at least a portion thereof.

[0147] The four-layer insulating layer 12 may not have the second insulating layer. For example, an insulating layer having a barrier property against oxygen may be used as the fourth insulating layer, an insulating layer made of a material with a low relative dielectric constant may be used as the third insulating layer, and an insulating layer having a function of capturing or fixing hydrogen may be used as the first insulating layer.

[0148] Since the insulating layer 22 functions as an interlayer film, it is preferable to use the above-mentioned material having a low relative dielectric constant. By using a material having a low relative dielectric constant for the interlayer film, the parasitic capacitance generated between wirings can be reduced.

[0149] It is preferable to use a barrier insulating layer against hydrogen as the insulating layer 22. When the insulating layer 22 provided below the semiconductor layer 11 has a barrier property against hydrogen, it is possible to suppress diffusion of hydrogen from below the insulating layer 22 to the semiconductor layer 11. As the insulating layer 22, for example, a silicon nitride film can be used.

[0150] It is preferable to use an insulating layer having a function of capturing or fixing hydrogen as the insulating layer 22. When the insulating layer 22 has the function of capturing or fixing hydrogen, hydrogen in the semiconductor layer 11 diffuses into the insulating layer 22, and the hydrogen can be captured or fixed. Therefore, the hydrogen concentration in the semiconductor layer 11 can be reduced. For example, a hafnium oxide film can be used as the insulating layer 22.

[0151] It is preferable that the concentration of impurities such as water and hydrogen in the insulating layer 22 is reduced, so that the intrusion of impurities such as water and hydrogen into the channel formation region of the semiconductor layer 11 can be suppressed.

[0152] 3B and the like show an example in which the insulating layer 22 has a single-layer structure. The insulating layer 22 can have a stacked structure of two or more layers. For example, the insulating layer 22 can have a two-layer structure of a first insulating layer and a second insulating layer on the first insulating layer. In this case, for example, it is preferable to use a barrier insulating layer against hydrogen as the first insulating layer and an insulating layer having a function of capturing or fixing hydrogen as the second insulating layer. Specifically, it is preferable to use a silicon nitride film as the first insulating layer and a hafnium oxide film, a hafnium silicate film, or an aluminum oxide film as the second insulating layer.

[0153] Alternatively, it is preferable to use a hafnium oxide film, a hafnium silicate film, or an aluminum oxide film as the first insulating layer, and a silicon oxide film or a silicon oxynitride film as the second insulating layer, so that the first insulating layer can function as an etching stopper when forming the recess 26.

[0154] Since the insulating layers 17 and 18 function as interlayer films, it is preferable to use the above-mentioned material with a low dielectric constant. By using a material with a low dielectric constant for the interlayer film, the parasitic capacitance generated between wirings can be reduced. For example, silicon oxide or silicon oxynitride can be used as the insulating layers 17 and 18.

[0155] It is preferable that the concentration of impurities such as water and hydrogen in the insulating layer 18 is reduced, thereby making it possible to prevent impurities such as water and hydrogen from entering the channel formation region of the semiconductor layer 11.

[0156] The insulating layer 18 is preferably an insulating layer having a region containing excess oxygen. The insulating layer having a region containing excess oxygen can be formed by, for example, sputtering in an oxygen-containing atmosphere. Furthermore, by using a sputtering method that does not require the use of hydrogen-containing molecules in the deposition gas, the hydrogen concentration in the insulating layer 18 can be reduced. In this way, by depositing at least a portion of the layers constituting the insulating layer 18 by sputtering, oxygen is supplied from the insulating layer 18 to the channel formation region of the semiconductor layer 11, and oxygen vacancies and V are reduced. ＯH can be reduced.

[0157] [Conductive Layer] The conductive layers (conductive layer 13, conductive layer 14a, conductive layer 14b, conductive layer 19a, conductive layer 19b, etc.) of the semiconductor device preferably contain a metal element selected from aluminum, chromium, copper, silver, gold, platinum, zinc, tantalum, nickel, titanium, iron, cobalt, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum, etc., or an alloy containing the above-mentioned metal element or an alloy combining the above-mentioned metal elements. As the alloy containing the above-mentioned metal element, a nitride of the alloy or an oxide of the alloy may be used. For example, tantalum nitride, titanium nitride, nitride containing titanium and aluminum, nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxide containing strontium and ruthenium, oxide containing lanthanum and nickel, etc. are preferably used. Furthermore, semiconductors with high electrical conductivity, such as polycrystalline silicon containing impurity elements such as phosphorus, and silicides such as nickel silicide may also be used.

[0158] Nitrogen-containing conductive materials, such as nitrides containing tantalum, nitrides containing titanium, nitrides containing molybdenum, nitrides containing tungsten, nitrides containing ruthenium, nitrides containing tantalum and aluminum, or nitrides containing titanium and aluminum; oxygen-containing conductive materials, such as ruthenium oxide, oxides containing strontium and ruthenium, or oxides containing lanthanum and nickel; and materials containing metal elements, such as titanium, tantalum, or ruthenium, are preferred because they are conductive materials that are resistant to oxidation, have a function of suppressing oxygen diffusion, or maintain conductivity even after absorbing oxygen. Examples of oxygen-containing conductive materials include indium oxide containing tungsten oxide, indium oxide containing titanium oxide (also referred to as indium titanium oxide), In—Sn oxide, indium tin oxide containing titanium oxide, indium tin oxide containing silicon (In—Si—Sn oxide, also referred to as ITSO), In—Zn oxide, and indium zinc oxide containing tungsten oxide. In this specification and the like, a conductive film formed using a conductive material containing oxygen may be referred to as an oxide conductive film.

[0159] Conductive materials containing tungsten, copper, or aluminum as a main component are preferred because they have high conductivity.

[0160] Furthermore, a plurality of conductive layers formed from the above materials may be stacked. For example, a stacked structure may be formed by combining the above-described material containing a metal element and a conductive material containing oxygen. A stacked structure may be formed by combining the above-described material containing a metal element and a conductive material containing nitrogen. A stacked structure may be formed by combining the above-described material containing a metal element, a conductive material containing oxygen, and a conductive material containing nitrogen.

[0161] When a metal oxide is used for the channel formation region of a transistor, the conductive layer that functions as a gate electrode preferably has a stacked structure that combines a material containing the metal element and a conductive material containing oxygen. In this case, the conductive material containing oxygen is preferably provided on the channel formation region side. By providing the conductive material containing oxygen on the channel formation region side, oxygen desorbed from the conductive material is easily supplied to the channel formation region.

[0162] The conductive layer 13 has a region that functions as a gate wiring. The conductive layer 13 is preferably made of a highly conductive material, such as tungsten. Furthermore, the conductive layer 13 is preferably made of a conductive material that is resistant to oxidation, or a conductive material that has a function of suppressing oxygen diffusion. As described above, examples of such conductive materials include conductive materials containing nitrogen (e.g., titanium nitride or tantalum nitride) and conductive materials containing oxygen (e.g., ruthenium oxide). This can suppress a decrease in the conductivity of the conductive layer 13.

[0163] Furthermore, the conductive layer 13 preferably uses a conductive material containing oxygen and a metal element contained in the metal oxide in which the channel is formed. Alternatively, the conductive material containing the aforementioned metal element and nitrogen (e.g., titanium nitride, tantalum nitride, etc.) may also be used. Alternatively, one or more selected from ITO, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, In—Zn oxide, and ITSO may also be used. Alternatively, indium gallium zinc oxide containing nitrogen may also be used. Using such a material may sometimes be able to capture hydrogen contained in the metal oxide in which the channel is formed. Alternatively, sometimes it may be able to capture hydrogen introduced from an outer insulating layer, etc.

[0164] 3B has a two-layer structure including a conductive layer 13_1 and a conductive layer 13_2 on the conductive layer 13_1. In this case, for example, it is preferable to use a titanium nitride film as the conductive layer 13_1 and a tungsten film as the conductive layer 13_2. Alternatively, it is preferable to use a tantalum nitride film as the conductive layer 13_1 and a copper film as the conductive layer 13_2. Such a structure can increase the conductivity of the conductive layer 13.

[0165] Alternatively, the conductive layer 13 may have a stacked structure of three or more layers, such as a three-layer structure of a tantalum nitride film, a titanium nitride film on the tantalum nitride film, and a tungsten film on the titanium nitride film.

[0166] The conductive layer 14a and the conductive layer 14b are each a conductive layer in contact with the semiconductor layer 11, and therefore are preferably made of a conductive material that is resistant to oxidation, a conductive material that maintains low electrical resistance even when oxidized, a metal oxide having conductivity (also referred to as an oxide conductor), or a conductive material that has a function of suppressing oxygen diffusion. Examples of such conductive materials include a conductive material containing nitrogen and a conductive material containing oxygen. This can suppress a decrease in the conductivity of the conductive layer 14a and the conductive layer 14b.

[0167] By using a conductive material containing oxygen for the conductive layers 14a and 14b, the conductive layers 14a and 14b can maintain their conductivity even when they absorb oxygen. Furthermore, even when an insulating layer containing oxygen, such as hafnium oxide, is used as the insulating layer 22, the conductive layers 14a and 14b are suitable because they can maintain their conductivity. For example, ITO, ITSO, In—Zn oxide, or the like is preferably used for the conductive layers 14a and 14b. When ITO or ITSO is used for the conductive layers 14a and 14b, the conductive layers 14a and 14b each contain indium, tin, and oxygen.

[0168] The conductive layers 19a and 19b are preferably made of a conductive material containing tungsten, copper, or aluminum as a main component. Each of the conductive layers 19a and 19b may have a layered structure in which a first conductive layer is provided in contact with the side surface of the insulating layer 18 and a second conductive layer is further provided inside. In this case, the above-mentioned conductive material can be used as the second conductive layer.

[0169] Furthermore, when the conductive layers 19a and 19b each have a laminated structure, the first conductive layer disposed near the insulating layer 18 is preferably made of the above-mentioned conductive material that is resistant to oxidation or a conductive material that has a function of suppressing oxygen diffusion, etc. This can suppress a decrease in the conductivity of the conductive layers 19a and 19b.

[0170] [Substrate] The substrate 21 on which the transistor is formed can be, for example, an insulating substrate, a semiconductor substrate, or a conductive substrate. Examples of insulating substrates include glass substrates, quartz substrates, sapphire substrates, stabilized zirconia substrates (e.g., yttria-stabilized zirconia substrates), and resin substrates. Examples of semiconductor substrates include semiconductor substrates made of silicon or germanium, or compound semiconductor substrates made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, or gallium oxide. Examples of semiconductor substrates include those having an insulating region within the semiconductor substrate, such as an SOI (Silicon-On-Insulator) substrate. Examples of conductive substrates include graphite substrates, metal substrates, alloy substrates, and conductive resin substrates. Other examples include substrates having a metal nitride or a metal oxide. Examples of other substrates include a substrate in which a conductor or semiconductor is provided on an insulating substrate, a substrate in which a conductor or insulator is provided on a semiconductor substrate, and a substrate in which a semiconductor or insulator is provided on a conductive substrate. Alternatively, a substrate provided with elements may be used. The elements provided on the substrate include a capacitor element, a resistor element, a switch element, a light-emitting element, a memory element, and the like.

[0171] The above is the description of the materials that can be used for the semiconductor device of this embodiment mode.

[0172] <Example 1 of Manufacturing Method of Semiconductor Device> Next, a manufacturing method of a semiconductor device of one embodiment of the present invention will be described. Specifically, an example of a manufacturing method of a semiconductor device including the transistor 10 shown in FIGS. 1A to 2F will be described with reference to FIGS. 4A to 26E. Note that with regard to the materials and formation methods of each element, descriptions of parts similar to those described above may be omitted.

[0173] Thin films (insulating films, semiconductor films, conductive films, etc.) constituting a semiconductor device can be formed using a sputtering method, a chemical vapor deposition (CVD) method, a vacuum evaporation method, a pulsed laser deposition (PLD) method, an atomic layer deposition (ALD) method, or the like.

[0174] RF sputtering is preferably used for film formation using an insulating target. DC sputtering is mainly used for film formation using a conductive target. In addition to forming conductive films, DC sputtering can also form insulating films by reactive sputtering using pulsed DC sputtering. Specifically, pulsed DC sputtering can be used for forming films of compounds such as oxides, nitrides, and carbides by reactive sputtering.

[0175] CVD methods can be further classified into plasma-enhanced CVD (PECVD), which utilizes plasma, thermal CVD (TCVD), which utilizes heat, and photo-CVD (photo-CVD), which utilizes light. CVD methods can also be further classified into metal CVD (MCVD) and metal organic CVD (MOCVD), depending on the source gas used.

[0176] The plasma CVD method can produce high-quality films at relatively low temperatures. Furthermore, the thermal CVD method is a film formation method that can minimize plasma damage to the workpiece because it does not use plasma. For example, wiring, electrodes, elements (transistors, capacitors, etc.) included in a semiconductor device may become charged up by receiving electric charge from the plasma. In this case, the accumulated electric charge may destroy the wiring, electrodes, elements, etc. included in the semiconductor device. On the other hand, the thermal CVD method, which does not use plasma, does not cause such plasma damage, and therefore can increase the yield of semiconductor devices. Furthermore, the thermal CVD method does not cause plasma damage during film formation, so films with fewer defects can be obtained.

[0177] As the ALD method, a thermal ALD method in which a precursor and a reactant are reacted using only thermal energy, a PEALD method in which a plasma-excited reactant is used, or the like can be used.

[0178] Note that some precursors used in the ALD method contain elements such as carbon or chlorine. Therefore, films formed by the ALD method may contain more elements such as carbon or chlorine than films formed by other film formation methods. The amounts of these elements can be quantified using XPS or SIMS. Note that the metal oxide film formation method of one embodiment of the present invention uses the ALD method, but employs one or both of the following conditions: a high substrate temperature during film formation and / or an impurity removal treatment. Therefore, the amounts of carbon and chlorine contained in the film may be smaller than those in the case of using the ALD method without these conditions.

[0179] Unlike film formation methods in which particles emitted from a target or the like are deposited, the ALD method is a film formation method in which a film is formed by a reaction on the surface of a workpiece. Therefore, it is a film formation method that is less affected by the shape of the workpiece and has good step coverage. In particular, the ALD method has excellent step coverage and excellent thickness uniformity, making it suitable for coating the surface of an opening with a high aspect ratio.

[0180] The CVD and ALD methods differ from sputtering, in which particles emitted from a target or the like are deposited. Therefore, they are film formation methods that are less affected by the shape of the workpiece and have good step coverage. In particular, the ALD method has excellent step coverage and excellent thickness uniformity, making it suitable for coating the surface of an opening with a high aspect ratio. However, because the ALD method has a relatively slow film formation rate, it may be preferable to use it in combination with other film formation methods, such as the CVD method, which has a faster film formation rate.

[0181] Furthermore, the CVD method allows deposition of a film with any composition by adjusting the flow rate ratio of the source gases. For example, the CVD method allows deposition of a film with a continuously changing composition by changing the flow rate ratio of the source gases during deposition. When deposition is performed while changing the flow rate ratio of the source gases, the time required for deposition can be shortened compared to deposition using multiple deposition chambers because no time is required for transport or pressure adjustment. Therefore, the productivity of semiconductor devices can be improved in some cases.

[0182] Furthermore, in the ALD method, a film of any composition can be formed by using multiple different precursors, or by controlling the number of cycles of each precursor when multiple different precursors are introduced.

[0183] There are two typical photolithography methods: one is to form a resist mask on the thin film to be processed, process the thin film by etching or the like, and then remove the resist mask; the other is to form a photosensitive thin film, and then process the thin film into the desired shape by exposure and development.

[0184] In photolithography, the light used for exposure may be, for example, i-line (wavelength 365 nm), g-line (wavelength 436 nm), h-line (wavelength 405 nm), or a mixture of these. Other light sources that can be used include ultraviolet light, KrF laser light, ArF laser light, etc. Exposure may also be performed by immersion exposure technology. Extreme ultraviolet (EUV) light or X-rays may also be used as the light used for exposure. An electron beam may also be used instead of the light used for exposure. Extreme ultraviolet light, X-rays, or an electron beam are preferred because they enable extremely fine processing. When exposure is performed by scanning a beam such as an electron beam, a photomask is not required.

[0185] For etching the thin film, dry etching, wet etching, sandblasting, or the like can be used.

[0186] 4A to 8B, (A) in each drawing shows a plan view, and (B) in each drawing shows a cross-sectional view corresponding to the portion indicated by the dashed dotted line B5-B6 in (A) in each drawing.

[0187] 9A to 26E, (A) in each figure shows a plan view. (B) in each figure shows a cross-sectional view corresponding to the portion indicated by the dashed line A1-A2 in (A) of each figure. (C) in each figure shows a cross-sectional view corresponding to the portion indicated by the dashed line A3-A4 in (A) of each figure. (D) in each figure shows a cross-sectional view corresponding to the portion indicated by the dashed line B1-B2 in (A) of each figure. (E) in each figure shows a cross-sectional view corresponding to the portion indicated by the dashed line B3-B4 in (A) of each figure.

[0188] First, as shown in FIGS. 4A and 4B, a substrate 21 is prepared, and an insulating layer 22 is formed on the substrate 21.

[0189] Subsequently, a sacrificial film is formed on the insulating layer 22 and then etched to form the sacrificial layer 31. In this embodiment, the sacrificial layer 31 is formed using a silicon oxide film formed by sputtering.

[0190] The sacrificial layer 31 can be processed into an island shape using lithography. For this processing, a dry etching method or a wet etching method can be used. Processing using the dry etching method is suitable for fine processing. In this specification, the term "island shape" refers to a state in which two or more layers made of the same material and formed in the same process are physically separated.

[0191] Subsequently, as shown in FIGS. 5A and 5B, an insulating film 15F that will become the insulating layer 15 is formed to cover the sacrificial layer 31.

[0192] Since the insulating film 15F is formed along the sacrificial layer 31, it is preferable that the insulating film 15F have good coverage. Furthermore, since the aspect ratio of the insulating layer 15 is preferably high, it is preferable that the insulating film 15F have a thin film thickness. Therefore, it is preferable that the insulating film 15F be formed using the ALD method, which has good coverage and allows for thin film thickness adjustment. In this embodiment, a hafnium oxide film is formed as the insulating film 15F using the thermal ALD method. Note that a hafnium oxide film is a material that is more difficult to etch than a silicon oxide film or a silicon oxynitride film. Furthermore, since the insulating film 15F is surrounded by the semiconductor layer 11 to be formed later and does not contact the conductive layer, a semiconductor material may be used for the insulating film 15F. For example, silicon germanium or the like may be used for the insulating film 15F.

[0193] 6A and 6B, anisotropic etching is then performed to remove a portion of the insulating film 15F, thereby exposing the upper surface of the sacrificial layer 31. This allows the formation of a sidewall-shaped insulating layer 15f. For the anisotropic etching, a dry etching method is preferably used.

[0194] As the etching gas for the dry etching process, an etching gas containing halogen can be used, and specifically, an etching gas containing one or more of fluorine, chlorine, and bromine can be used. For example, the etching gas may contain C ４ F ６ Gas, C ５ F ６ Gas, C ４ F ８ Gas, CF４ Gas, SF ６ Gas, CHF ３ Gas, CH ２ F ２ Gas, Cl ２ Gas, BCl ３ Gas, SiCl ４ Gas, or BBr ３ Gases such as fluorine-containing gases can be used alone or in combination of two or more gases. Oxygen gas, carbon dioxide gas, nitrogen gas, helium gas, argon gas, hydrogen gas, or hydrocarbon gas can be added to the above-mentioned etching gas as appropriate. Depending on the object to be dry-etched, gases containing no halogen gas but hydrocarbon gas or hydrogen gas can be used as the etching gas. Examples of hydrocarbons used in the etching gas include methane (CH ４ ), ethane (C ２ H ６ ), propane (C ３ H ８ ), butane (C ４ H １０ ), ethylene (C ２ H ４ ), propylene (C ３ H ６ ), acetylene (C ２ H ２ ), and propyne (C ３ H ４ The etching conditions can be appropriately set depending on the target to be etched.

[0195] As the dry etching apparatus, a capacitively coupled plasma (CCP) etching apparatus having parallel-plate electrodes can be used. The capacitively coupled plasma etching apparatus having parallel-plate electrodes may be configured to apply a high-frequency voltage to one of the parallel-plate electrodes. Alternatively, it may be configured to apply multiple different high-frequency voltages to one of the parallel-plate electrodes. Alternatively, it may be configured to apply a high-frequency voltage of the same frequency to each of the parallel-plate electrodes. Alternatively, it may be configured to apply high-frequency voltages of different frequencies to each of the parallel-plate electrodes. Alternatively, a dry etching apparatus having a high-density plasma source can be used. As the dry etching apparatus having a high-density plasma source, for example, an inductively coupled plasma (ICP) etching apparatus can be used. The etching apparatus can be appropriately configured depending on the object to be etched.

[0196] For example, when a hafnium oxide film is used for the insulating film 15F, a CCP etching apparatus is used with C ４ F ８ , H ２ A mixed gas of Ar and Ar can be used.

[0197] 7A and 7B, the insulating layer 15f is processed using lithography to form the insulating layer 15. In Figures 7A and 7B, portions of the sidewall-shaped insulating layer 15f that are not necessary for the configuration of the semiconductor device are removed to form the insulating layer 15. The insulating layer 15 formed from the insulating film 15F containing the hafnium oxide film contains hafnium and oxygen.

[0198] For the above processing, a dry etching method or a wet etching method can be used. Processing by the dry etching method is suitable for fine processing. Note that the above-mentioned contents can be referred to for the conditions of the dry etching method and the dry etching apparatus.

[0199] The method for forming the insulating layer 15 is not limited to the above-described method. For example, before anisotropic etching is performed on the insulating film 15F, portions of the insulating film 15F that are not necessary for the configuration of the semiconductor device may be removed, and then anisotropic etching may be performed to form the insulating layer 15.

[0200] 8A and 8B, the sacrificial layer 31 is removed. As described above, by using a silicon oxide film or a silicon oxynitride film as the sacrificial layer 31 and a hafnium oxide film, which is a material that is difficult to etch, as the insulating layer 15, it is possible to leave the insulating layer 15 in the step of removing the sacrificial layer 31.

[0201] As described above, the insulating layer 15 having a high aspect ratio can be formed. By using the insulating layer 15, the channel width of the transistor 10 can be increased without increasing the occupied area. This can improve the on-state current, field-effect mobility, and frequency characteristics of the transistor 10. Furthermore, a plurality of transistors 10 can be arranged in a matrix.

[0202] The distance between adjacent insulating layers 15 in the X direction can be set in accordance with the width of the sacrificial layer 31 in the X direction (length W31 shown in FIG. 7A ) and the distance between the side surfaces of the sacrificial layer 31 (length P31 shown in FIG. 7A ). For example, by reducing at least one of the width of the sacrificial layer 31 in the X direction and the distance between the sacrificial layers 31, the distance between adjacent insulating layers 15 in the X direction can be reduced, the area occupied by the transistor 10 can be reduced, and the semiconductor device can be highly integrated. Furthermore, the storage capacity of a storage device using the semiconductor device can be increased.

[0203] The subsequent steps of the method for manufacturing a semiconductor device will be described with reference to the region surrounded by the dashed line in FIG. 8A.

[0204] Next, a sacrificial film that will become the sacrificial layer 32 is formed to cover the insulating layer 15. Since the sacrificial film is formed along the insulating layer 15, it is preferable that the sacrificial film have good coverage. Furthermore, since the aspect ratio of the sacrificial layer 32 is preferably high, it is preferable that the sacrificial film have a thin film thickness. Therefore, it is preferable that the sacrificial film be formed using the ALD method, which has good coverage and allows for adjustment of the film thickness to a thin film. In this embodiment, an aluminum oxide film is formed as the sacrificial film using the thermal ALD method. Note that an aluminum oxide film is a material that is difficult to etch compared to a silicon oxide film or a silicon oxynitride film.

[0205] Subsequently, a portion of the sacrificial film is removed by anisotropic etching to expose the upper surface of the insulating layer 15. This allows the formation of a sidewall-shaped sacrificial layer 32 (see FIGS. 9A to 9E). The anisotropic etching is preferably performed by dry etching.

[0206] Next, a sacrificial film that will become the sacrificial layer 33 is formed to cover the insulating layer 15 and the sacrificial layer 32. Since the sacrificial film is formed along the sacrificial layer 32, it is preferable that the sacrificial film have good coverage. Therefore, it is preferable that the sacrificial film be formed using an ALD method or the like that has good coverage. In this embodiment, a silicon oxide film is formed as the sacrificial film using the PEALD method.

[0207] Subsequently, a portion of the sacrificial film is removed by anisotropic etching to expose the upper surfaces of the insulating layer 15 and the sacrificial layer 32. This allows the formation of a sidewall-shaped sacrificial layer 33 (see FIGS. 10A to 10E). A dry etching method is preferably used for the anisotropic etching.

[0208] Subsequently, an insulating film that will become the insulating layer 16 is formed to cover the insulating layer 15, the sacrificial layer 32, and the sacrificial layer 33. For materials that can be used for the insulating film and a method for forming the insulating film, the description regarding materials that can be used for the insulating film that will become the insulating layer 15 and a method for forming the insulating film can be referred to.

[0209] Subsequently, anisotropic etching is performed to remove a portion of the insulating film that will become insulating layer 16, thereby exposing the upper surfaces of insulating layer 15, sacrificial layer 32, and sacrificial layer 33. This allows the formation of sidewall-shaped insulating layer 16 (see FIGS. 11A to 11E). Dry etching is preferably used for the anisotropic etching.

[0210] Subsequently, an insulating film that will become the insulating layer 17 is formed to cover the insulating layer 15 , the sacrificial layer 32 , the sacrificial layer 33 , and the insulating layer 16 .

[0211] Subsequently, anisotropic etching is performed to remove a portion of the insulating film that will become the insulating layer 17, thereby exposing the top surfaces of the insulating layer 15, the sacrificial layer 32, the sacrificial layer 33, and the insulating layer 16. This allows the insulating layer 17 to be formed (see FIGS. 12A to 12E ). A dry etching method is preferably used for the anisotropic etching. Alternatively, the insulating layer 17 may be formed by polishing the insulating film that will become the insulating layer 17 by a chemical mechanical polishing (CMP) process (also referred to as a CMP process) until the insulating layer 15, the sacrificial layer 32, the sacrificial layer 33, and the insulating layer 16 are exposed.

[0212] 13A to 13E, the sacrificial layer 33 is removed. As a result, an opening 27 is formed in the insulating layer 16. At this time, the insulating layer 15 and the sacrificial layer 32 are located in the opening 27. The sacrificial layer 33 can be removed by, for example, lithography. Dry etching or wet etching can be used for this removal. Processing by dry etching is suitable for fine processing.

[0213] In order to leave the insulating layer 15 and the sacrificial layer 32 when removing the sacrificial layer 33, it is preferable that the sacrificial layer 33 be made of a material different from the insulating layer 15 and the sacrificial layer 32. For example, it is preferable that the etching rate of the material used for the sacrificial layer 33 be greater than 1 times the etching rate of each of the insulating layer 15 and the sacrificial layer 32. In other words, it is preferable that the etching selectivity of the sacrificial layer 33 relative to the insulating layer 15 and the etching selectivity of the sacrificial layer 33 relative to the sacrificial layer 32 are each greater than 1. By using silicon oxide for the sacrificial layer 33, hafnium oxide for the insulating layer 15, and aluminum oxide for the sacrificial layer 32, it is possible to leave the insulating layer 15 and the sacrificial layer 32 when removing the sacrificial layer 33.

[0214] It is also preferable that a portion of the insulating layer 22 exposed by removing the sacrificial layer 33 is removed. By removing a portion of the insulating layer 22, a recess 26 can be formed in the insulating layer 22.

[0215] 14A to 14E, a conductive film 14F that will become the conductive layers 14a and 14b is formed. The conductive film 14F is formed so as to fill the openings 27 and the recesses 26, so it is preferable that the conductive film 14F have good coverage. Therefore, it is preferable that the conductive film 14F be formed using an ALD method or the like, which has good coverage. For example, ITO, ITSO, or the like can be used as the conductive film 14F. In this embodiment, an ITO film is formed as the conductive film 14F using the ALD method.

[0216] 15A to 15E, anisotropic etching is performed to remove a portion of the conductive film 14F, thereby exposing the upper surfaces of the insulating layer 15, the sacrificial layer 32, the insulating layer 16, and the insulating layer 17. This allows the conductive layer 14f to be formed, embedded in the opening 27 and the recess 26. A dry etching method is preferably used for the anisotropic etching. Alternatively, the conductive layer 14f may be formed by polishing the conductive film 14F by CMP until the insulating layer 15, the sacrificial layer 32, the insulating layer 16, and the insulating layer 17 are exposed.

[0217] Next, insulating layers 34_1 and 34_2 are formed in this order on the insulating layer 15, the sacrificial layer 32, the conductive layer 14f, the insulating layer 16, and the insulating layer 17. Hereinafter, the insulating layers 34_1 and 34_2 may be collectively referred to as the insulating layer 34. The insulating layer 34_1 is preferably an insulating film that has a function of suppressing oxygen permeation. In this embodiment, a silicon nitride film is formed as the insulating layer 34_1 and a silicon oxide film is formed as the insulating layer 34_2 by sputtering.

[0218] The insulating layers 34_1 and 34_2 are preferably successively formed without being exposed to the air, which allows the vicinity of the interface between the insulating layers 34_1 and 34_2 to be kept clean.

[0219] 16A to 16E, the insulating layer 34 is processed using lithography to form an opening 28 in the insulating layer 34 that reaches the conductive layer 14f. This processing can be performed using dry etching or wet etching. Dry etching is suitable for fine processing. While the insulating layer 34 has a two-layer structure in FIGS. 16A, 16B, 16C, and 16E, it may have a single-layer structure or a stacked structure of three or more layers.

[0220] The insulating layer 34 is an inorganic insulating layer that functions as an etching stopper when the conductive layer 14f is processed and protects the conductive layers 14a and 14b.

[0221] Next, using the insulating layer 34 as a mask, a portion of the conductive layer 14f is removed. Specifically, the portion of the conductive layer 14f exposed through the opening 28 is removed. As a result, the conductive layer 14f is divided, and conductive layers 14a and 14b are formed (see FIGS. 17A to 17E).

[0222] 18A to 18E, an insulating film 12F that will become the insulating layer 12 is formed. Since the insulating film 12F is formed along the sidewalls of the openings 28, 27, and recesses 26, it is preferable that the insulating film 12F have good coverage. Furthermore, since the insulating layer 12 preferably has a recess in a position overlapping the opening 27 where the conductive layer 13 will be filled later, it is preferable that the insulating film 12F have a thin film thickness. Therefore, it is preferable that the insulating film 12F be formed using the ALD method, which has good coverage and allows for adjustment of the film thickness to a thin film.

[0223] It is preferable to use the ALD process two or more times in forming the insulating layer 12 having a stacked structure of multiple insulating films. For example, it is preferable that two or more of the multiple insulating films included in the insulating layer 12 are formed using the ALD process. By forming at least two or more insulating films using the ALD process, it is possible to improve the coverage and film thickness uniformity of the insulating layer 12. Furthermore, it is possible to increase productivity by successively forming two or more films, for example, two or more insulating films, using the ALD process.

[0224] 18A to 18E, a conductive film 13F that will become the conductive layer 13 is formed. When the conductive film 13F is a laminated film, it is preferable to form the film successively without exposing it to the atmospheric environment. By forming the film without exposing it to the atmosphere, the vicinity of the interface of the laminated film of the conductive film 13F can be kept clean. In this embodiment, a titanium nitride film and a tungsten film are formed in this order by the CVD method as the conductive film 13F.

[0225] Next, the insulating film 12F and the conductive film 13F are polished by CMP until the insulating layer 34_2 is exposed. That is, the portions of the insulating film 12F and the conductive film 13F exposed in the opening 28 are removed. This allows the insulating layer 12 and the conductive layer 13 to be formed in the opening 28, the opening 27, and the recess 26 (see FIGS. 19A to 19E). At this time, the conductive layer 13 is formed in a position that does not overlap with the conductive layer 14a and the conductive layer 14b. Furthermore, the conductive layer 13 is formed so as to be located between the conductive layer 14a and the conductive layer 14b.

[0226] 20A to 20E, the insulating layer 34 is removed. Dry etching or wet etching can be used to remove the insulating layer 34. When removing the insulating layer 34, the insulating layer 12 located on the side surface of the conductive layer 13 may also be removed.

[0227] 21A to 21E, the sacrificial layer 32 is removed. It is preferable to use a wet etching method to remove the sacrificial layer 32. By using the wet etching method, etching is performed isotropically, so that the sacrificial layer 32 located below the insulating layer 12 can be removed.

[0228] When wet etching is used, for example, an alkaline solution can be used. Alternatively, for example, an acid solution can be used. Specifically, a developer, a tetramethylammonium hydroxide (TMAH) aqueous solution, dilute hydrofluoric acid, or the like can be used. Alternatively, the sacrificial layer 32 may be etched by dissolving it in a solvent such as water or alcohol. Examples of alcohol include ethyl alcohol, methyl alcohol, isopropyl alcohol (IPA), and glycerin.

[0229] When aluminum oxide is used as the sacrificial layer 32, the sacrificial layer 32 can be removed by wet etching using a TMAH aqueous solution. At this time, by using hafnium oxide as the insulating layer 15, the insulating layer 15 can be left.

[0230] 22A to 22E , a semiconductor film 11F that will become the semiconductor layer 11 is formed. The semiconductor film 11F is formed so as to fill the region from which the sacrificial layer 32 has been removed. Therefore, it is preferable to form the semiconductor film 11F using a film formation method that has good coverage, and it is more preferable to use the ALD method.

[0231] When the ALD method is used as a method for forming the semiconductor film 11F, by adopting a condition in which the substrate temperature is high during film formation and / or by performing an impurity removal process, the amount of carbon and chlorine contained in the film can be reduced compared to when the ALD method is used without applying these conditions.

[0232] For example, it is preferable to perform an impurity removal treatment intermittently in an oxygen-containing atmosphere during the formation of the semiconductor film 11F. Furthermore, it is preferable to perform an impurity removal treatment in an oxygen-containing atmosphere after the formation of the semiconductor film 11F. By performing an impurity removal treatment either during or after the formation of the semiconductor film 11F, impurities in the film can be removed. This makes it possible to prevent impurities (such as hydrogen, carbon, and nitrogen) contained in raw materials such as precursors from remaining in the metal oxide. Therefore, the impurity concentration in the semiconductor layer 11 can be reduced. Furthermore, the crystallinity of the semiconductor layer 11 can be improved.

[0233] Examples of the impurity removal treatment include plasma treatment, microwave treatment, and heat treatment.

[0234] When performing the plasma treatment or microwave treatment, the substrate temperature is preferably set to room temperature (e.g., 25° C.) or higher, 100° C. or higher, 200° C. or higher, 300° C. or higher, or 400° C. or higher, and 500° C. or lower, or 450° C. or lower. The heat treatment temperature is preferably set to 100° C. or higher, 200° C. or higher, 300° C. or higher, or 400° C. or higher, and 500° C. or lower, or 450° C. or lower.

[0235] The temperature in the impurity removal treatment is preferably set to a temperature equal to or lower than the maximum temperature in the manufacturing process of a transistor or a semiconductor device, because the amount of impurities in the semiconductor layer 11 can be reduced without reducing productivity. For example, the productivity of the semiconductor device can be increased by setting the maximum temperature in the manufacturing process of the semiconductor device of one embodiment of the present invention to 500° C. or lower, preferably 450° C. or lower.

[0236] Here, the microwave treatment refers to a treatment using, for example, a device having a power source that generates high-density plasma using microwaves. In addition, in this specification, microwaves refer to electromagnetic waves having a frequency of 300 MHz or more and 300 GHz or less.

[0237] In the microwave treatment, it is preferable to use a microwave treatment device having a power supply that generates high-density plasma using microwaves. Here, the frequency of the microwave treatment device is preferably 300 MHz to 300 GHz, more preferably 2.4 GHz to 2.5 GHz, for example, it can be 2.45 GHz. By using high-density plasma, high-density oxygen radicals can be generated. Furthermore, the power of the power supply that applies microwaves to the microwave treatment device is preferably 1000 W to 10,000 W, preferably 2000 W to 5,000 W. Furthermore, the microwave treatment device may have a power supply that applies RF to the substrate side. Furthermore, by applying RF to the substrate side, oxygen ions generated by high-density plasma can be efficiently introduced into the film.

[0238] The microwave treatment is preferably carried out under reduced pressure, and the pressure is preferably from 10 to 1000 Pa, and more preferably from 300 to 700 Pa. The treatment temperature is preferably from room temperature (25°C) to 750°C, more preferably from 300 to 500°C, and even more preferably from 400 to 450°C.

[0239] Alternatively, after the microwave treatment or plasma treatment, a heat treatment may be performed successively without exposure to the outside air. The temperature of the heat treatment is, for example, preferably 100° C. or higher and 750° C. or lower, more preferably 300° C. or higher and 500° C. or lower, and even more preferably 400° C. or higher and 450° C. or lower.

[0240] The microwave treatment can be carried out using, for example, oxygen gas and argon gas. Here, the oxygen flow rate ratio (O ２ / (O ２ +Ar)) is preferably greater than 0% and less than or equal to 100%, more preferably greater than 0% and less than or equal to 50%, even more preferably greater than or equal to 10% and less than or equal to 40%, and even more preferably greater than or equal to 10% and less than or equal to 30%.

[0241] The heat treatment is carried out in a nitrogen gas or inert gas atmosphere, or in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas. For example, when the heat treatment is carried out in a mixed atmosphere of nitrogen gas and oxygen gas, the oxygen gas content is preferably about 20%. The heat treatment may be carried out under reduced pressure. Alternatively, after the heat treatment in a nitrogen gas or inert gas atmosphere, the heat treatment may be carried out in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas to compensate for the desorbed oxygen. The heat treatment may also be carried out in an atmosphere of ultra-dry air (air having a water content of 20 ppm or less, preferably 1 ppm or less, and preferably 10 ppb or less).

[0242] By carrying out the heat treatment in this manner, impurities such as hydrogen or carbon contained in the metal oxide can be removed. For example, carbon in the metal oxide can be converted to CO ２ and CO, and hydrogen in the metal oxide is released as H ２ Furthermore, at the same time as the removal of the impurities, rearrangement of metal atoms and oxygen atoms occurs, which can improve the crystallinity.

[0243] Next, a resist 36 is formed on the semiconductor film 11F, and a thinning process is performed to reduce the thickness of the resist 36. The thinning process may be performed by ashing using oxygen plasma, or the like. By performing the thinning process and reducing the thickness of the resist 36, a portion of the semiconductor film 11F, specifically, the portion of the semiconductor film 11F that overlaps with the conductive layer 13, is exposed. At this time, the upper surface of the resist 36 is positioned lower (closer to the substrate 21) than the upper surface of the semiconductor film 11F located on the conductive layer 13 (see FIGS. 23A to 23E ).

[0244] 24A to 24E, a portion of the semiconductor film 11F is removed. Specifically, the region of the semiconductor film 11F that is exposed from the resist 36 is removed. A dry etching method or a wet etching method can be used to remove the portion of the semiconductor film 11F. Processing using the dry etching method is suitable for fine processing.

[0245] Next, the resist 36 is removed. To remove the resist 36, a dry etching process such as ashing can be performed, a wet etching process can be performed, a dry etching process followed by a wet etching process, or a wet etching process followed by a dry etching process can be performed.

[0246] Next, a portion of the semiconductor film 11F is removed until the insulating layer 15, the semiconductor layer 11, the conductive layer 14a, the conductive layer 14b, and the insulating layer 12 are exposed. This allows the semiconductor layer 11 to be formed in the region from which the sacrificial layer 32 has been removed (see FIGS. 25A to 25E). Dry etching or wet etching can be used to remove the portion of the semiconductor film 11F.

[0247] Next, an insulating film is formed to cover the insulating layer 12 and the conductive layer 13, and the insulating film is subjected to CMP treatment to form an insulating layer 18 with a flat upper surface (see FIGS. 26A to 26E ). A silicon oxide film is preferably formed as the insulating film by sputtering. By forming the insulating film by sputtering in an oxygen-containing atmosphere, the insulating layer 18 containing excess oxygen can be formed. Furthermore, by using a sputtering method that does not require the use of hydrogen-containing molecules in the deposition gas, the hydrogen concentration in the insulating layer 18 can be reduced.

[0248] Next, openings reaching the conductive layer 14a and the conductive layer 14b are formed in the insulating layer 18. The openings can be formed using lithography. Dry etching is preferably used to form the openings. Dry etching is suitable for forming openings with a high aspect ratio because it allows for anisotropic etching. The shape of the openings in plan view can be a circle, a nearly circular shape such as an ellipse, a polygonal shape such as a rectangle, or a polygonal shape with rounded corners such as a rectangle.

[0249] Next, conductive films to be the conductive layers 19a and 19b are formed. The conductive films preferably have a stacked structure including a conductive film that has a function of suppressing the permeation of impurities such as water and hydrogen. For example, the conductive films may be stacked layers of a tantalum nitride film or a titanium nitride film and a tungsten film, a molybdenum film, or a copper film.

[0250] Next, a CMP process is performed to remove a portion of the conductive film and expose the upper surface of the insulating layer 18. As a result, the conductive film remains only in the opening, thereby forming conductive layers 19a and 19b with flat upper surfaces (see FIGS. 2A to 2F).

[0251] Through the above steps, a semiconductor device of one embodiment of the present invention can be manufactured.

[0252] According to the manufacturing method of one embodiment of the present invention, the semiconductor layer 11 is formed after the conductive layer 13, which functions as a gate electrode, is formed. Furthermore, the portion of the semiconductor layer 11 that will become a channel formation region is covered with the insulating layer 12 and the conductive layer 13. Therefore, in steps after the formation of the semiconductor layer 11, the insulating layer 12 and the conductive layer 13 function as channel protection layers. Therefore, damage to the portion of the semiconductor layer 11 that will become the channel formation region (such as film reduction due to plasma or an etchant during etching) can be prevented in subsequent steps. Therefore, the reliability of the transistor can be improved.

[0253] <Application Example 1 of Semiconductor Device> Fig. 27 shows an example in which a plurality of transistors 10 are arranged in a matrix. Specifically, Fig. 27 shows an example in which 4 x 2 transistors are arranged in the X direction and the Y direction. As shown in Fig. 27, the conductive layer 13 is provided extending in the X direction.

[0254] 7A and other figures, by forming the insulating layer 15 in the shape of a sidewall in contact with the side surface of the sacrificial layer 31, it is possible to form 2×n (n is an integer equal to or greater than 1) transistors per sacrificial layer 31. In other words, the distance between the insulating layers 15 facing each other with the sacrificial layer 31 therebetween can be set by the width of the sacrificial layer 31 in the X direction.

[0255] 7A, the width of the sacrificial layer 31 in the X direction is defined as a length W31, and the distance between the side surfaces of adjacent sacrificial layers 31 in the X direction is defined as a length P31. The lengths W31 and P31 are also shown in FIG.

[0256] For example, by shortening at least one of the length W31 and the length P31, the distance between adjacent transistors 10 in the X direction can be narrowed, thereby achieving a higher level of integration of the semiconductor device. 28A shows a configuration in which the length W31 is shortened so that the insulating layer 17 is not positioned between the transistors 10 adjacent in the X direction. Note that, because the transistors 10 adjacent in the X direction are separated from each other by the insulating layer 16, it is possible to prevent leakage current from occurring between the transistors 10.

[0257] Furthermore, for example, by shortening at least one of the length W31 and the length P31, a structure can be formed in which two or more semiconductor layers 11 are in contact with one conductive layer 14a and one conductive layer 14b and have an overlapping region with the conductive layer 13. This structure allows the transistor 10 to function as a multi-channel transistor. Therefore, the channel width of the transistor 10 can be further increased. FIG. 28B illustrates a structure in which the length W31 is shortened so that the transistor 10 has two semiconductor layers 11. Although FIG. 28B illustrates a structure in which the transistor 10 has two semiconductor layers 11, a transistor having three or more semiconductor layers 11 can also be formed by independently setting the length W31 for each sacrificial layer 31 and independently setting the length P31 between the sacrificial layers 31.

[0258] Here, the width of recess 26 is defined as length W26 (see FIG. 28B ). In order to provide a recess in which conductive layer 13 is embedded in insulating layer 12 in the region overlapping recess 26, length W26 is preferably greater than twice the film thickness of insulating layer 12. For example, length W26 is preferably greater than 2 nm. Specifically, length W26 is preferably 3 nm to 100 nm, more preferably 3 nm to 60 nm, even more preferably 5 nm to 60 nm, and even more preferably 5 nm to 30 nm.

[0259] 28B , the shortest distance between the side surfaces of two semiconductor layers 11 adjacent in the X direction and facing each other is preferably equal to or greater than the length W26. This allows a conductive layer 13 to be provided between the two semiconductor layers 11, thereby increasing the channel width of the transistor 10. Note that the shortest distance between the side surfaces of the two semiconductor layers 11 facing each other is equal to the length W31 minus twice the width of the semiconductor layer 11. Furthermore, the shortest distance between the side surfaces of the two semiconductor layers 11 facing each other is preferably equal to or smaller than twice the length W26. This allows for a configuration in which the insulating layer 16 and the insulating layer 17 are not located between the two semiconductor layers 11.

[0260] Here, the shortest distance between the opposing side surfaces of adjacent insulating layers 15 in the Y direction is defined as length D1 (see FIG. 27 ). For example, by shortening length D1, the distance between adjacent transistors 10 in the Y direction can be narrowed, thereby achieving a high level of integration of the semiconductor device. FIG. 29A shows a configuration in which, by shortening length D1, an insulating layer 17 is not positioned between adjacent transistors 10 in the Y direction. Note that, because adjacent transistors 10 in the Y direction are separated by insulating layer 16, leakage current between the transistors 10 can be prevented.

[0261] Alternatively, for example, the length D1 may be shortened, specifically, set to twice the length W26 or less. This allows the insulating layer 16 and the insulating layer 17 to be separated from the semiconductor layers 11 adjacent in the Y direction. In this case, for two transistors 10 adjacent in the Y direction, one conductive layer may serve as both the source electrode and the drain electrode of one transistor 10 and the source electrode and the drain electrode of the other transistor 10. This structure allows for a high level of integration of the semiconductor device. Note that FIG. 29B illustrates a configuration in which two transistors (transistors 10a and 10b) are provided within one insulating layer 16, and the conductive layer 14c functions as both the source electrode and the drain electrode of transistor 10a and the source electrode and the drain electrode of transistor 10b.

[0262] 29B illustrates a configuration in which the length D1 is greater than twice the width of the semiconductor layer 11, in other words, a configuration in which adjacent semiconductor layers 11 are spaced apart in the Y direction. This configuration increases the contact area between the conductive layer 14c and the semiconductor layer 11a or 11b. Therefore, the contact resistance between the conductive layer 14c and the semiconductor layer 11a or 11b can be reduced.

[0263] 29B, the transistor 10a includes a conductive layer 13a functioning as a gate electrode, an insulating layer 12a functioning as a gate insulating layer, and an insulating layer 15a, while the transistor 10b includes a conductive layer 13b functioning as a gate electrode, and an insulating layer 12b functioning as a gate insulating layer and an insulating layer 15b.

[0264] 28A and 29A, a high level of integration of the semiconductor device can be achieved by using a configuration in which no insulating layer 17 is provided between adjacent transistors 10. On the other hand, as shown in Fig. 27, by using a configuration in which an insulating layer 17 is provided between adjacent transistors 10, it is possible to further prevent leakage current from occurring between adjacent transistors 10, and a highly reliable semiconductor device can be provided.

[0265] It is possible to combine the above-described configuration examples as appropriate. For example, Fig. 29C shows an example in which the configuration shown in Fig. 28A is combined with the configuration shown in Fig. 29B. By using the configuration shown in Fig. 29C, it is possible to further increase the integration density of the semiconductor device.

[0266] <Structure Example 2 of Semiconductor Device> Another structure of a semiconductor device of one embodiment of the present invention will be described with reference to FIGS. 30A to 32B.

[0267] 30A to 30C are perspective views of a semiconductor device having a transistor 10A. Fig. 30B shows Fig. 30A with some components omitted, and Fig. 30C shows only some components.

[0268] 31A is a plan view of a semiconductor device including a transistor 10A. Figures 31B, 31C, 31D, and 31E are cross-sectional views taken along dashed-dotted lines A1-A2, A3-A4, B1-B2, and B3-B4, respectively, of FIG. 31A. Figures 31B and 31C are cross-sectional views of the transistor 10A in the channel length direction, and Figures 31D and 31E are cross-sectional views of the transistor 10A in the channel width direction. Figure 31F is a cross-sectional view including dashed-dotted line C1-C2 shown in FIG. 31B.

[0269] 30A to 31F differ from the semiconductor device shown in Figures 1A to 2F in that it does not have insulating layer 15. Hereinafter, differences from the above description will be mainly explained, and overlapping portions will be referred to and explanations thereof may be omitted.

[0270] The transistor 10A includes a semiconductor layer 11 , a conductive layer 14 a and a conductive layer 14 b , an insulating layer 12 , and a conductive layer 13 .

[0271] The semiconductor layer 11 is provided on an insulating layer 22. The insulating layer 22 has a recess 26 surrounding the semiconductor layer 11 (see FIG. 30C ). The insulating layer 12 is provided so as to cover a portion of the semiconductor layer 11. The conductive layer 13 is provided so as to cover a portion of the semiconductor layer 11 with the insulating layer 12 interposed therebetween.

[0272] At least a portion of each of the semiconductor layer 11, the conductive layer 14a, the conductive layer 14b, the insulating layer 12, and the conductive layer 13 is located within the opening 27. That is, at least a portion of the transistor 10A is disposed within the opening 27.

[0273] An enlarged view of Fig. 31F is shown in Fig. 32A. As shown in Fig. 32A, the semiconductor layer 11 has a region 11i facing the conductive layer 13 with the insulating layer 12 interposed therebetween, a region 11n1 in the vicinity of the conductive layer 14a of the semiconductor layer 11, and a region 11n2 in the vicinity of the conductive layer 14b of the semiconductor layer 11.

[0274] An enlarged view of Figure 31D is shown in Figure 32B. As shown in Figure 32B, the height of the semiconductor layer 11 is defined as height H, and the width of the semiconductor layer 11 is defined as width T11. The height H can be, for example, more than 1 time and not more than 50 times the width T11, preferably 2 times to 20 times, and more preferably 2 times to 10 times. The width T11 can be, for example, 3 nm to 50 nm, preferably 3 nm to 30 nm, and more preferably 5 nm to 20 nm.

[0275] By not providing the insulating layer 15, the width of the semiconductor layer 11 can be increased without increasing the area occupied by the transistor 10A, and the semiconductor layer 11 can be prevented from collapsing during the manufacture of the semiconductor device.

[0276] <Example 2 of Manufacturing Method of Semiconductor Device> Next, a manufacturing method of a semiconductor device of one embodiment of the present invention will be described. Specifically, an example of a manufacturing method of a semiconductor device including a transistor 10A shown in Figures 30A to 31F will be described with reference to Figures 33A to 39E. Note that with regard to the materials and formation methods of each element, descriptions of parts similar to those described above may be omitted.

[0277] 33A shows a plan view, and FIG. 33B shows a cross-sectional view corresponding to the portion indicated by the dashed dotted line B5-B6 in FIG. 33A.

[0278] 34A to 39E, (A) in each figure shows a plan view. (B) in each figure shows a cross-sectional view corresponding to the portion indicated by the dashed line A1-A2 in (A) of each figure. (C) in each figure shows a cross-sectional view corresponding to the portion indicated by the dashed line A3-A4 in (A) of each figure. (D) in each figure shows a cross-sectional view corresponding to the portion indicated by the dashed line B1-B2 in (A) of each figure. (E) in each figure shows a cross-sectional view corresponding to the portion indicated by the dashed line B3-B4 in (A) of each figure.

[0279] First, a substrate 21 is prepared, and an insulating layer 22 is formed on the substrate 21. Subsequently, a sacrificial layer 31 is formed on the insulating layer 22. For the manufacturing method up to the formation of the sacrificial layer 31, the contents described with reference to FIG. 4A can be referred to.

[0280] Next, a sacrificial film that will become the sacrificial layer 32 is formed to cover the sacrificial layer 31, and the sacrificial film is processed to form the sacrificial layer 32 (see FIGS. 33A and 33B ). For example, the sacrificial film is formed and then anisotropically etched to be processed into a sidewall shape, and then lithography is used to form the sacrificial layer 32. Note that the processing method for the sacrificial film can also refer to the processing method for the insulating film 15F or the sacrificial film that will become the sacrificial layer 32 described in <Example 1 of manufacturing method of semiconductor device>.

[0281] Subsequently, the sacrificial layer 31 is removed, thereby forming a sacrificial layer 32 with a high aspect ratio. For the manufacturing method from removing the sacrificial layer 31 to forming the insulating layer 12 and the conductive layer 13 and then removing the insulating layer 34, refer to the contents described with reference to Figures 8A to 20E. The structure after removing the insulating layer 34 is shown in Figures 34A to 34E.

[0282] Subsequently, the sacrificial layer 32 is removed (see FIGS. 35A to 35E).

[0283] Next, a semiconductor film 11F that will become the semiconductor layer 11 is formed (see FIGS. 36A to 36E).

[0284] Next, a resist 36 is formed on the semiconductor film 11F, and a thinning process is performed on the resist 36 so that the upper surface of the resist 36 is located lower (toward the substrate 21) than the upper surface of the semiconductor film 11F located on the conductive layer 13 (see Figures 37A to 37E).

[0285] Next, the regions of the semiconductor film 11F that are exposed from the resist 36 are removed (see FIGS. 38A to 38E). Next, the resist 36 is removed. Next, the semiconductor film 11F is partially removed until the semiconductor layer 11, the conductive layer 14a, the conductive layer 14b, and the insulating layer 12 are exposed, thereby forming the semiconductor layer 11 (see FIGS. 39A to 39E).

[0286] Subsequently, the insulating layer 18 is formed, followed by the formation of the conductive layer 19a and the conductive layer 19b.

[0287] Through the above steps, a semiconductor device including the transistor 10A can be manufactured.

[0288] 40 shows an example in which a plurality of transistors 10A are arranged in a matrix. Specifically, FIG. 40 shows an example in which 4×2 transistors are arranged in the X and Y directions.

[0289] 33A and other figures, by forming the sacrificial layer 32 in the shape of a sidewall in contact with the side surface of the sacrificial layer 31, it is possible to form 2×n (n is an integer equal to or greater than 1) transistors per sacrificial layer 31. In other words, the distance between the semiconductor layers 11 facing each other with the sacrificial layer 31 sandwiched therebetween can be set by the width of the sacrificial layer 31 in the X direction.

[0290] 33A, the width of the sacrificial layer 31 in the X direction is defined as length W31, and the distance between the side surfaces of adjacent sacrificial layers 31 in the X direction is defined as length P31. In a semiconductor device having a transistor 10A, length W31 is also the shortest distance between the side surfaces facing each other of two adjacent semiconductor layers 11 in the X direction. Length W31 and length P31 are shown in FIG.

[0291] For example, by shortening at least one of the length W31 and the length P31, the distance between the transistors 10A adjacent in the X direction can be narrowed. In Fig. 41A, the length W31 is shortened so that the insulating layer 17 is not positioned between the transistors 10A adjacent in the X direction.

[0292] Furthermore, for example, by shortening at least one of the length W31 and the length P31, a structure can be formed in which two or more semiconductor layers 11 are in contact with one conductive layer 14a and one conductive layer 14b and have a region overlapping with the conductive layer 13. With such a structure, the transistor 10A functions as a multi-channel transistor. Figure 41B shows a structure in which the length W31 is shortened so that the transistor 10A has two semiconductor layers 11.

[0293] 41B , the length W31 is preferably equal to or greater than the length W26. This allows the conductive layer 13 to be provided between the two semiconductor layers 11, thereby increasing the channel width of the transistor 10A. Furthermore, the length W31 is preferably equal to or smaller than twice the length W26. This allows the insulating layer 16 and the insulating layer 17 to be prevented from being located between the two semiconductor layers 11.

[0294] Here, the shortest distance between the side surfaces of adjacent semiconductor layers 11 facing each other in the Y direction is defined as length D2 (see FIG. 40 ). For example, by shortening length D2, the distance between adjacent transistors 10A in the Y direction can be narrowed. FIG. 42A shows a configuration in which, by shortening length D2, an insulating layer 17 is not positioned between adjacent transistors 10A in the Y direction.

[0295] Alternatively, for example, the length D2 may be shortened, specifically, set to twice the length W26 or shorter. This allows the insulating layer 16 and the insulating layer 17 to be separated from the semiconductor layers 11 adjacent in the Y direction. In this case, for two transistors 10A adjacent in the Y direction, a single conductive layer may serve as both the source electrode and the drain electrode of one transistor 10A and the source electrode and the drain electrode of the other transistor 10A. Note that FIG. 42B illustrates a configuration in which two transistors (transistors 10Aa and 10Ab) are provided within a single insulating layer 16, and the conductive layer 14c functions as both the source electrode and the drain electrode of the transistor 10Aa and the source electrode and the drain electrode of the transistor 10Ab.

[0296] 42B illustrates a configuration in which the length D2 is greater than 0 nm, in other words, a configuration in which the semiconductor layers 11 adjacent in the Y direction are spaced apart. With this configuration, it is possible to increase the area in which the conductive layer 14c contacts the semiconductor layer 11a or the semiconductor layer 11b.

[0297] It is possible to combine the above-described configuration examples as appropriate. For example, Fig. 42C shows an example in which the configuration shown in Fig. 41A is combined with the configuration shown in Fig. 42B. The configuration shown in Fig. 42C can further increase the integration density of the semiconductor device.

[0298] <Configuration Example 3 of Semiconductor Device> A semiconductor device including the above-described transistor 10 can be used as a memory cell of a memory device. A configuration example of a memory cell 30 that can be used in a memory device will be described with reference to FIG. 43A .

[0299] In FIG. 43A, the Y direction is parallel to the channel length direction of the illustrated transistor, the X direction is perpendicular to the Y direction, and the Z direction is perpendicular to the X and Y directions.

[0300] 43A, the memory cell 30 includes a transistor 10 and a capacitor element 40 on the transistor 10. For details of the transistor 10, see the above.

[0301] An insulating layer 61, an insulating layer 62, an insulating layer 63, an insulating layer 64, an insulating layer 65, an insulating layer 66, and an insulating layer 67 are provided over the transistor 10 in this order. The insulating layers 63, 65, 66, and 67 can be formed using the same insulating material as can be used for the insulating layer 17. The insulating layers 61, 62, and 64 can be formed using the same insulating material as can be used for the insulating layer 22.

[0302] A conductive layer 19a is provided so as to be embedded in insulating layer 18, insulating layer 61, insulating layer 62, insulating layer 63, and insulating layer 64. A conductive layer 19b is provided so as to be embedded in insulating layer 18, insulating layer 61, and insulating layer 62. A conductive layer 51a is provided so as to be embedded in insulating layer 65, and a conductive layer 51b is provided so as to be embedded in insulating layer 63. The conductive layer 51a is connected to the conductive layer 14a via the conductive layer 19a. The conductive layer 51a functions as a wiring or electrode that connects the conductive layer 19a and the conductive layer 14a. The conductive layer 51b is connected to the conductive layer 14b via the conductive layer 19b. The conductive layer 51b functions as a bit line.

[0303] The memory cells 30 shown in FIG. 43A can be arranged in a matrix on the same layer to form a memory array.

[0304] By providing the conductive layer 51a above the conductive layer 51b, the conductive layer 51a can be arranged to overlap the transistor 10 without interfering with the conductive layer 51b. Therefore, the capacitor 40 provided on the conductive layer 51a can be arranged to overlap the transistor 10. Here, it is preferable that at least a part of the capacitor 40, for example, an overlapping portion of the conductive layer 41, the insulating layer 42, and the conductive layer 43, overlap with the semiconductor layer 11 and the conductive layer 13. With this structure, the memory cell 30 can be provided without significantly increasing the occupied area. This allows the storage capacity per unit area of ​​the memory device to be increased.

[0305] Note that the insulating layer 64 preferably functions as an etching stopper when the conductive layer 51 a is formed. With this structure, even if part of the conductive layer 51 a overlaps with the conductive layer 51 b, the part of the conductive layer 51 a can be prevented from contacting the conductive layer 51 b.

[0306] 43A, the conductive layer 51a is provided in a layer above the conductive layer 51b, but the present invention is not limited to this. For example, the conductive layer 51a and the conductive layer 51b may be formed in the same layer.

[0307] The capacitor 40 includes a conductive layer 41 on the conductive layer 51 a, an insulating layer 42 on the conductive layer 41, and a conductive layer 43 (conductive layer 43_1 and conductive layer 43_2) on the insulating layer 42.

[0308] At least a portion of each of the conductive layer 41, the insulating layer 42, and the conductive layer 43 is disposed inside an opening provided in the insulating layer 66. At least the ends of the conductive layer 41, the insulating layer 42, and the conductive layer 43 are located on the insulating layer 66. The insulating layer 42 is provided so as to cover the end of the conductive layer 41. This allows the conductive layer 41 and the conductive layer 43 to be electrically insulated from each other.

[0309] The deeper the opening provided in the insulating layer 66 (i.e., the thicker the insulating layer 66), the greater the capacitance of the capacitive element 40. Increasing the capacitance per unit area of ​​the capacitive element 40 allows for miniaturization or high integration of the memory device. For example, the depth of the opening (the thickness of the insulating layer 66) can be set to approximately 150 nm or more and 350 nm or less. Forming the capacitive element 40 within this range allows the capacitive element 40 to have sufficient capacitance, and prevents the height of one layer from becoming excessively high in a semiconductor device in which multiple memory cell layers are stacked.

[0310] The sidewalls of the openings may be perpendicular or approximately perpendicular to the upper surface of the substrate 21, or may be tapered. Tapering the sidewalls improves the coverage of the conductive layer 41 and the like provided inside the openings, and reduces defects such as voids.

[0311] The conductive layer 41 has a region that functions as one electrode (lower electrode) of the capacitance element 40. The insulating layer 42 has a region that functions as a dielectric of the capacitance element 40. The conductive layer 43 has a region that functions as the other electrode (upper electrode) of the capacitance element 40. The capacitance element 40 constitutes an MIM (Metal-Insulator-Metal) capacitor.

[0312] The conductive layer 41 and the conductive layer 43 can each be formed using a conductive material that can be used for the conductive layer 13. The conductive layer 41 and the conductive layer 43 are each preferably formed by a film formation method with good coverage, such as an ALD method or a CVD method. For example, the conductive layer 41 can be a titanium nitride film or a tantalum nitride film formed by an ALD method or a CVD method.

[0313] The upper surface of the conductive layer 51a contacts the lower surface of the conductive layer 41. Here, by using a conductive material with good conductivity as the conductive layer 51a, the contact resistance between the conductive layer 41 and the conductive layer 51a can be reduced.

[0314] Alternatively, a titanium nitride film formed by an ALD method or a CVD method can be used as the conductive layer 43_1, and a tungsten film formed by a CVD method can be used as the conductive layer 43_2. Note that if the adhesion of the tungsten film to the insulating layer 42 is sufficiently high, the conductive layer 43 may have a single-layer structure of a tungsten film formed by a CVD method.

[0315] It is preferable to use a high-dielectric-constant (high-k) material (material with a high relative dielectric constant) described above in [Insulating Layer] for the insulating layer 42. By using a high-k material, it is possible to make the insulating layer 42 thick enough to suppress leakage current and to ensure sufficient capacitance of the capacitive element 40. It is preferable to form the insulating layer 42 using a film formation method with good coverage, such as an ALD method or a CVD method.

[0316] The insulating layer 42 may have a laminated structure of a high-k material and a material having a higher dielectric strength than the high-k material. For example, the insulating layer 42 may be an insulator formed by laminating zirconium oxide, aluminum oxide, and zirconium oxide in this order. Alternatively, the insulating layer 42 may be an insulator formed by laminating zirconium oxide, aluminum oxide, zirconium oxide, and aluminum oxide in this order. Alternatively, the insulating layer 42 may be an insulating film formed by laminating hafnium zirconium oxide, aluminum oxide, hafnium zirconium oxide, and aluminum oxide in this order. By laminating an insulator having a relatively high dielectric strength, such as aluminum oxide, the dielectric strength is improved, and electrostatic breakdown of the capacitor element 40 can be suppressed.

[0317] The insulating layer 42 may also be made of a material capable of exhibiting ferroelectricity, as described above in the "Insulating Layer" section. A nonvolatile memory element can be formed using a capacitive element (hereinafter sometimes referred to as a ferroelectric capacitor) that uses a material capable of exhibiting ferroelectricity as a dielectric. A nonvolatile memory element using a ferroelectric capacitor is sometimes called a Ferroelectric Random Access Memory (FeRAM), a ferroelectric memory, or the like. For example, a ferroelectric memory has a transistor and a ferroelectric capacitor, and one of the source and drain of the transistor is electrically connected to one terminal of the ferroelectric capacitor. Therefore, a memory cell that uses a ferroelectric capacitor as the capacitive element 40 functions as a ferroelectric memory.

[0318] 43A, the memory cell 30 is configured such that the capacitance element 40 is provided above the transistor 10, but the present invention is not limited to this. For example, as shown in FIG. 43B, the capacitance element 40 may be provided below the transistor 10.

[0319] 43B , an insulating layer 68 can be provided below the insulating layer 22, an insulating layer 69 can be provided below the insulating layer 68, an insulating layer 70 can be provided below the insulating layer 69, an insulating layer 71 can be provided below the insulating layer 70, an insulating layer 72 can be provided below the insulating layer 71, and an insulating layer 73 can be provided below the insulating layer 72. The insulating layers 69, 70, 71, 72, and 73 can be made of the same insulating material as can be used for the insulating layer 17.

[0320] A conductive layer 53 is provided so as to be embedded in the insulating layer 73. The conductive layer 53 functions as a wiring or an electrode, and a conductive material that can be used for the conductive layer 13 can be applied. A capacitor 40 is provided so as to be embedded in the insulating layers 71 and 72. The capacitor 40 shown in FIG. 43B has the same structure as that shown in FIG. 43A. A conductive layer 52 is provided so as to be embedded in the insulating layers 69 and 70. The conductive layer 52 can be formed using, for example, a dual damascene method. A conductive layer 19c is provided so as to be embedded in the insulating layers 68, 22, 17, 18, 61, and 62. The conductive layer 19c can be formed in the same process as the conductive layers 19a and 19b.

[0321] 43B , the conductive layer 14a is in contact with the conductive layer 19a, the conductive layer 19a is in contact with the conductive layer 51a, the conductive layer 51a is in contact with the conductive layer 19c, the conductive layer 19c is in contact with the conductive layer 52, and the conductive layer 52 is in contact with the conductive layer 43. Thus, the conductive layer 43 which is the upper electrode of the capacitor 40 is electrically connected to the conductive layer 14a which functions as one of the source electrode and drain electrode of the transistor 10 through the conductive layer 52, the conductive layer 19c, the conductive layer 51a, and the conductive layer 19a.

[0322] 43B, the conductive layer 53 is in contact with the conductive layer 41. Here, the conductive layer 41 can function as the wiring PL.

[0323] With the above-described structure, the capacitor 40 can be disposed under and overlapped with the transistor 10. Here, it is preferable that at least a part of the capacitor 40, for example, a portion where the conductive layer 41, the insulating layer 42, and the conductive layer 43 overlap, overlap with the semiconductor layer 11 and the conductive layer 13. With such a structure, the memory cell 30 can be provided without significantly increasing the occupied area. This allows the storage capacity per unit area of ​​the storage device to be increased.

[0324] Alternatively, for example, as shown in FIG. 44A, a part of the transistor 10 and a part of the capacitive element 40 may be provided in the same layer.

[0325] In the memory cell 30 shown in FIG. 44A, an insulating layer 68 can be provided under the insulating layer 22, and an insulating layer 69 can be provided under the insulating layer 68.

[0326] Conductive layers 51a and 51b are provided so as to be embedded in insulating layer 68. Insulating layer 22 has an opening that reaches conductive layer 51a. Conductive layer 14a has a portion located within the opening and in contact with conductive layer 51a. Insulating layer 22 also has an opening that reaches conductive layer 51b. Conductive layer 14b has a portion located within the opening and in contact with conductive layer 51b. With this configuration, there is no need to provide a plug connecting conductive layer 14a and conductive layer 51a, and a plug connecting conductive layer 14b and conductive layer 51b. This makes it possible to reduce the number of steps in the semiconductor device and increase productivity.

[0327] The capacitance element 40 is provided so as to be embedded in the insulating layer 22, the insulating layer 17, the insulating layer 18, the insulating layer 61, and the insulating layer 62. The capacitance element 40 shown in Fig. 44A has the same structure as that in Fig. 43A.

[0328] 44A , a conductive layer 41 that is a lower electrode of the capacitor 40 is electrically connected through a conductive layer 51 a to a conductive layer 14 a that functions as one of a source electrode and a drain electrode of the transistor 10. The conductive layer 43 can function as a wiring PL.

[0329] 43A shows a configuration in which the transistor 10 in any one of FIGS. 2A to 2F is used as the transistor included in the memory cell 30, but the present invention is not limited to this. For example, as shown in FIG. 44B, the transistor shown in FIG. 29B can also be used as the transistor 10 included in the memory cell 30.

[0330] 44B shows a configuration in which a first memory cell including a transistor 10a and a capacitor 40a and a second memory cell including a transistor 10b and a capacitor 40b share one bit line (conductive layer 51b shown in FIG. 44B ). This allows the number of wirings to be reduced. Furthermore, the degree of circuit integration can be increased. One of the source electrode and drain electrode of the transistor 10a is connected to the conductive layer 41 of the capacitor 40a through the conductive layer 19a1 and the conductive layer 51a1, and one of the source electrode and drain electrode of the transistor 10b is connected to the conductive layer 41 of the capacitor 40b through the conductive layer 19a2 and the conductive layer 51a2.

[0331] An example of the layout of a memory cell will be described. Fig. 45A shows a plan view of the memory cell. Note that in Fig. 45A, in order to clarify the layout of the memory cell, components above insulating layer 64 (capacitor element 40a, capacitor element 40b, etc.) and some insulating layers (insulating layer 16, insulating layer 17, insulating layer 18, etc.) are omitted.

[0332] 45A, the semiconductor layer 11 is provided so that its longitudinal direction is inclined in the X direction, the conductive layer 13 is provided so as to extend in the X direction, and the conductive layer 51b is provided so as to extend in the Y direction. In a plan view, the conductive layer 19a1 of the first transistor and the conductive layer 19a2 of the second transistor adjacent to the first transistor in the X direction are arranged in a region surrounded by the conductive layer 13 of the first transistor, the conductive layer 13 of the second transistor, the conductive layer 51b connected to the first transistor, and the conductive layer 51b connected to the second transistor. Furthermore, in a plan view, there is a region surrounded by two conductive layers 13 adjacent in the Y direction and two conductive layers 51b adjacent in the X direction where the conductive layers 19a1 and 19a2 are not arranged. This arrangement reduces the occupied area per memory cell (i.e., a configuration including one transistor 10 and one capacitive element 40) to 6F. ２ (F is the minimum processing dimension) This makes it possible to realize a memory device in which memory cells are arranged at high density.

[0333] 45A illustrates a configuration in which the plurality of conductive layers 19a1 and the plurality of conductive layers 19a2 are linearly arranged along the X direction, but the present invention is not limited to this. For example, the plurality of conductive layers 19a1 and the plurality of conductive layers 19a2 may be arranged in a zigzag pattern along the X direction. For example, in a plan view, the conductive layer 19a1 of the first transistor may be located closer to the conductive layer 51b connected to the first transistor than the conductive layer 51b connected to the second transistor, and the conductive layer 19a2 of the second transistor may be located closer to the conductive layer 51b connected to the second transistor than the conductive layer 51b connected to the first transistor. This increases the distance between the conductive layers 19a1 and 19a2, thereby increasing the area in plan view where the upper electrode and lower electrode of the capacitor element face each other across the dielectric, thereby increasing the capacitance value of the capacitor element.

[0334] 45B is a cross-sectional view taken along dashed line D1-D2 in FIG. 45A. As shown in FIG. 45B, one of the source electrode and the drain electrode of transistor 10a is connected to the conductive layer 41 of the capacitor 40a through a conductive layer 19a1, and one of the source electrode and the drain electrode of transistor 10b is connected to the conductive layer 41 of the capacitor 40b through a conductive layer 19a2. By using a structure in which the conductive layers 51a1 and 51a2 are not provided, the number of steps for manufacturing the memory cell can be reduced, and productivity can be improved.

[0335] FIG. 46 shows a plan view of another example of a memory cell. To clarify the layout of the memory cell, FIG. 46 omits components (e.g., capacitor 40a, capacitor 40b) above insulating layer 64 and some insulating layers (e.g., insulating layer 16, insulating layer 17, insulating layer 18). In a plan view, one of conductive layer 19a1 and conductive layer 19a2 is disposed in a region surrounded by two conductive layers 13 adjacent in the Y direction and two conductive layers 51b adjacent in the X direction. This arrangement allows for a memory device with even higher density memory cells. Furthermore, since one of conductive layer 19a1 and conductive layer 19a2 is disposed in each region surrounded by two conductive layers 13 adjacent in the Y direction and two conductive layers 51b adjacent in the X direction in a plan view, the distance between conductive layer 19a1 and conductive layer 19a2 is increased, thereby increasing the area in plan view where the upper electrode and lower electrode of the capacitor face each other across the dielectric, thereby increasing the capacitance value of the capacitor.

[0336] The memory cells will be described in detail in a later embodiment.

[0337] <Configuration Example 4 of Semiconductor Device> A semiconductor device including the above-described transistor 10 can realize various circuits by combining it with a Si transistor. A configuration including a Si transistor and the transistor 10 will be described below.

[0338] 47 illustrates an example of a structure of a semiconductor device in which a transistor 80, which is a Si transistor, and a transistor 10, which is an OS transistor, are stacked. FIG. 47 illustrates an example of a cross-sectional structure of the transistor 80 and the transistor 10 in the channel length direction.

[0339] 47 includes a functional layer 92 in which a transistor 80 is provided and a functional layer 91 in which a transistor 10 is provided. The functional layer 91 can be provided on the functional layer 92.

[0340] The transistor 80 is provided on a substrate 81 and includes a conductive layer 84 functioning as a gate electrode, an insulating layer 83 functioning as a gate insulating layer, a semiconductor region 82 formed of a part of the substrate 81, a low-resistance region 85a functioning as one of a source region and a drain region, and a low-resistance region 85b functioning as the other of the source region and the drain region. The transistor 80 is also called a fin-type transistor because it utilizes a protruding portion of the semiconductor substrate. The transistor 80 may be either a p-type or an n-type.

[0341] It is preferable to have a wiring layer 94 in which interlayer insulating layers and wiring layers are alternately stacked between the functional layer 92 in which the transistor 80 is provided and the functional layer 91 in which the transistor 10 is provided. Figure 47 shows an example in which the low-resistance region 85b of the transistor 80 is connected to the conductive layer 14a provided in the functional layer 91 via a wiring and a plug.

[0342] 47 illustrates the transistor illustrated in FIG. 2B as an example of the transistor 10. In the example illustrated in FIG. 47, an insulating layer 74 is provided over the transistor 10, and an insulating layer 63 is provided over the insulating layer 74. The insulating layer 74 functions as a protective layer and prevents impurities such as hydrogen from diffusing from the outside of the transistor 10.

[0343] 48 shows an example in which a memory device is further stacked above the transistor 10. The memory device has a plurality of memory cells 340 arranged in a matrix.

[0344] 48 includes a functional layer 92 having a transistor 80, a functional layer 91 having a transistor 10, and a functional layer 93 having a memory cell 340. The functional layer 91 can be provided over the functional layer 92. The functional layer 93 can be provided over the functional layer 91.

[0345] The memory cell 340 has a stacked structure of a capacitor 360 and a transistor 350. The memory cell 340 functions as, for example, a memory cell of a dynamic random access memory (DRAM).

[0346] The capacitor 360 includes a conductive layer 361, a conductive layer 363, and an insulating layer 362 sandwiched between the conductive layers 361 and 363. The conductive layer 361 has a region that functions as one electrode of the capacitor 360. The conductive layer 363 has a region that functions as the other electrode of the capacitor 360. The insulating layer 362 has a region that functions as a dielectric of the capacitor 360. A ferroelectric insulating layer can also be used for the insulating layer 362.

[0347] An insulating layer 371 and a conductive layer 364 embedded in the insulating layer 371 are provided over the insulating layer 65. The conductive layer 364 functions as a wiring. An insulating layer 372 having an opening reaching the conductive layer 364 is provided over the conductive layer 364. In the opening of the insulating layer 372, the conductive layer 361, the insulating layer 362, and the conductive layer 363 are stacked. The conductive layer 361 is provided in contact with the conductive layer 364 in the opening of the insulating layer 372, and the conductive layer 363 is provided to fill the opening. The conductive layer 361 and the insulating layer 362 have a region located over the insulating layer 372 and are provided in common to a plurality of capacitors 360. The conductive layer 363 has a region embedded in the insulating layer 373 located over the insulating layer 362.

[0348] In the transistor 350, the source electrode and the drain electrode are located at different heights, and a current flows in the height direction of the semiconductor layer. In other words, it can be said that the channel length direction has a component in the height direction (vertical direction). Therefore, one embodiment of the present invention can be called a VFET (Vertical Field Effect Transistor), a vertical transistor, a vertical channel transistor, a vertical channel transistor, or the like.

[0349] The transistor 350 includes a semiconductor layer 351, a conductive layer 354, a conductive layer 355, an insulating layer 352, and a conductive layer 353. The conductive layer 354 has a region functioning as one of a source electrode and a drain electrode of the transistor 350. The conductive layer 355 has a region functioning as the other of the source electrode and the drain electrode of the transistor 350. The insulating layer 352 has a region functioning as a gate insulating layer of the transistor 350. The conductive layer 353 has a region functioning as a gate electrode of the transistor 350.

[0350] The semiconductor layer 351 of the transistor 350 is preferably made of a metal oxide (oxide semiconductor) that exhibits semiconductor characteristics. For example, silicon, a typical semiconductor material, needs to be doped with impurities that function as donors or acceptors to form source and drain regions. However, in the vertical transistor of one embodiment of the present invention, it may be difficult to dope impurities into the semiconductor layer with high precision because the source and drain regions are different in height and the channel formation region is located vertically relative to the substrate surface. On the other hand, an oxide semiconductor can form a low-resistance region without doping with such impurities and can provide good connection with the source and drain electrodes. Therefore, a transistor having a three-dimensional structure as in one embodiment of the present invention can be manufactured with high yield.

[0351] The conductive layer 354 is provided in contact with the top surface of the conductive layer 363. An insulating layer 374 is provided over the conductive layer 354, and a conductive layer 355 is provided over the insulating layer 374. The conductive layer 355 and the insulating layer 374 have openings that reach the conductive layer 354. The semiconductor layer 351 has a region in contact with the conductive layer 355, a region in contact with a side surface of the insulating layer 374 in the opening of the insulating layer 374, and a region in contact with the conductive layer 354. The insulating layer 352 is provided to cover the semiconductor layer 351. The conductive layer 353 is provided over the insulating layer 352. The semiconductor layer 351 and the insulating layer 352 have regions located over the insulating layer 374 and are provided in common to a plurality of transistors 350. The conductive layer 353 has a region that is embedded in the insulating layer 375 over the insulating layer 352. In addition, a conductive layer 356 that is in contact with the conductive layer 353 is provided over the insulating layer 375. The conductive layer 356 is connected to the conductive layers 353 of the plurality of transistors 350 arranged in the depth direction.

[0352] An insulating layer 376 can be provided over the conductive layer 356 and the insulating layer 375. An insulating layer 377 can be provided over the insulating layer 376. The insulating layer 376 functions as an interlayer insulating layer, and the insulating layer 377 functions as a protective layer. Note that the stacking order of the insulating layer 376 and the insulating layer 377 may be changed.

[0353] For example, a driver circuit, an arithmetic circuit, a control circuit, or the like can be configured using the transistors 10 and 80, and a memory device having a memory cell 340 can be stacked above the driver circuit, and the memory device can be configured to operate at high speed because the wiring length can be significantly shortened.

[0354] The memory cells 340 may be stacked. For example, two, four, eight, or 16 or more layers may be stacked. The greater the number of stacked memory cells 340, the greater the storage capacity.

[0355] This embodiment mode can be combined with other embodiment modes as appropriate. In addition, in this specification, when a plurality of configuration examples are shown in one embodiment mode, the configuration examples can be combined as appropriate.

[0356] Embodiment 2 In this embodiment, an example of a CMOS circuit configuration using a Si transistor and an OS transistor according to one embodiment of the present invention will be described.

[0357] Si transistors have higher field-effect mobility and faster operation speed than OS transistors. Furthermore, OS transistors have significantly lower off-state current than Si transistors. In particular, OS transistors that use indium oxide for the semiconductor layer in which a channel is formed have significantly lower off-state current and higher field-effect mobility comparable to that of Si transistors. A CMOS circuit with low power consumption and high-speed operation can be realized by using an OS transistor and a Si transistor in combination.

[0358] In this embodiment, examples of circuits using Si transistors and OS transistors will be described, including a NOT circuit, a NOR circuit, and a NAND circuit, which are logic circuits. Also, examples of circuits using Si transistors and OS transistors will be described, including a buffer circuit, a ring oscillator, a delay flip-flop (DFF) circuit, a shift register circuit using a DFF circuit, a selector, and an analog switch.

[0359] [NOT Circuit] Fig. 49A is a circuit diagram showing an example configuration of a NOT circuit (NOT). A NOT circuit is also called an inversion circuit, inverter circuit, etc. Fig. 49B shows the circuit symbol for a NOT circuit. Fig. 49C is a timing chart explaining the operation of the NOT circuit.

[0360] The NOT circuit shown in FIG. 49A includes transistors Tr11 and Tr12. The transistor Tr11 is a Si transistor functioning as a p-channel transistor, and the transistor Tr12 is an OS transistor functioning as an n-channel transistor. A potential H (e.g., a high power supply potential VDD) is supplied to one of the source and the drain of the transistor Tr11. The other of the source and the drain of the transistor Tr11 is connected to one of the source and the drain of the transistor Tr12 and to a terminal Y. A potential L (e.g., a low power supply potential VSS) is supplied to the other of the source and the drain of the transistor Tr12. The gates of the transistors Tr11 and Tr12 are connected to a terminal A.

[0361] In this specification and the like, a high power supply potential VDD (hereinafter simply referred to as "VDD") refers to a power supply potential that is higher than a low power supply potential VSS (hereinafter simply referred to as "VSS"). Also, the low power supply potential VSS refers to a power supply potential that is lower than the high power supply potential VDD.

[0362] The potential H is a potential that turns on an n-channel transistor and turns off a p-channel transistor. The potential L is a potential that turns off an n-channel transistor and turns on a p-channel transistor. Therefore, the potential H is higher than the potential L. The potential H may be equal to VDD, and the potential L may be equal to VSS.

[0363] 49A, terminal A functions as an input terminal, and terminal Y functions as an output terminal. When a potential H is input to terminal A of the NOT circuit, a potential L is output from terminal Y, and when a potential L is input to terminal A, a potential H is output from terminal Y (see FIG. 49C).

[0364] As shown in FIG. 49C , the NOT circuit has a function (also called a "waveform shaping function") of correcting an input signal distorted by wiring resistance, parasitic capacitance, noise, etc., to a signal that is distorted or has reduced distortion, and outputting the corrected signal. The NOT circuit also has a function of amplifying the voltage amplitude of the input signal and outputting the corrected signal. The output of the NOT circuit is supplied to a load such as a capacitance element Cx and a transistor Trx. Since power is supplied to the output of the NOT circuit via transistor Tr11 or transistor Tr12, the ability to drive a load connected to the output can be improved. The NOT circuit has a function (also called a "driving force improvement function") of improving the ability to drive a load.

[0365] [NOR Circuit] Fig. 50A is a circuit diagram showing a configuration example of a two-input, one-output NOR circuit (NOR). Fig. 50B shows a circuit symbol for the NOR circuit. The NOR circuit shown in Fig. 50A includes transistors Tr21, Tr22, Tr23, and Tr24. Si transistors functioning as p-channel transistors are used as the transistors Tr21 and Tr22, and OS transistors functioning as n-channel transistors are used as the transistors Tr23 and Tr24.

[0366] 50A , a potential H is supplied to one of the source and drain of transistor Tr21. The other of the source and drain of transistor Tr21 is connected to one of the source and drain of transistor Tr22. The other of the source and drain of transistor Tr22 is connected to one of the source and drain of transistor Tr23, one of the source and drain of transistor Tr24, and terminal Y. A potential L is supplied to the other of the source and drain of transistor Tr23 and the other of the source and drain of transistor Tr24.

[0367] The gate of the transistor Tr21 is connected to the gate of the transistor Tr23 and the terminal A. The gate of the transistor Tr22 is connected to the gate of the transistor Tr24 and the terminal B.

[0368] 50A and 50B has a function of outputting a potential H from a terminal Y when a potential L is input to both a terminal A and a terminal B. In addition, the NOR circuit has a function of outputting a potential L from a terminal Y when a potential H is input to one or both of the terminals A and B.

[0369] Furthermore, as shown in FIG. 50C, an OR circuit can be realized by connecting the input of a NOT circuit to the output of a NOR circuit.

[0370] [NAND Circuit] Fig. 50D is a circuit diagram showing a configuration example of a two-input, one-output NAND circuit (NAND). Fig. 50E shows a circuit symbol of the NAND circuit. The NAND circuit shown in Fig. 50D includes transistors Tr31, Tr32, Tr33, and Tr34. Si transistors functioning as p-channel transistors are used as the transistors Tr31 and Tr32, and OS transistors functioning as n-channel transistors are used as the transistors Tr33 and Tr34.

[0371] 50D, a potential H is supplied to one of the source and drain of transistor Tr31 and one of the source and drain of transistor Tr32. The other of the source and drain of transistor Tr31 and the other of the source and drain of transistor Tr32 are connected to one of the source and drain of transistor Tr33 and terminal Y. The other of the source and drain of transistor Tr33 is connected to one of the source and drain of transistor Tr34. A potential L is supplied to the other of the source and drain of transistor Tr34.

[0372] The gate of the transistor Tr31 is connected to the gate of the transistor Tr34 and the terminal B. The gate of the transistor Tr32 is connected to the gate of the transistor Tr33 and the terminal A.

[0373] 50D and 50E has a function of outputting a potential L from a terminal Y when a potential H is input to both the terminal A and the terminal B. Also, when a potential L is input to one or both of the terminal A and the terminal B, the NAND circuit has a function of outputting a potential H from the terminal Y.

[0374] Furthermore, as shown in FIG. 50F, an AND circuit can be realized by combining a NAND circuit with a NOT circuit.

[0375] [Buffer Circuit] Figure 51A shows the circuit symbol for a buffer circuit. A buffer circuit (BF) can be realized by connecting an even number of NOT circuits in series. Figure 51B shows an example configuration of a buffer circuit made up of two NOT circuits. Figure 51C is a timing chart explaining the operation of the buffer circuit.

[0376] A buffer circuit does not perform a logical operation, but outputs the same value as the input logical value. Specifically, when a potential H is input, a potential H is output, and when a potential L is input, a potential L is output. Similarly to a NOT circuit, a buffer circuit has a waveform shaping function (see FIG. 51C ) and a driving force improving function. By using a buffer circuit, it is possible to correct a distorted signal and improve the driving force for a load without inverting the signal.

[0377] [Ring Oscillator] A ring oscillator (also called an "oscillating circuit") can be realized by connecting an odd number of NOT circuits in a ring. FIG. 51D shows an example of the configuration of a ring oscillator (RO) made up of NOT circuits. FIG. 51D shows a ring oscillator made up of five NOT circuits. A ring oscillator has the function of generating (oscillating) an AC signal when power is supplied. FIG. 51E is a diagram illustrating the oscillation of a ring oscillator.

[0378] Generally, the first of n NOT circuits (n is an odd number equal to or greater than 3) that make up a ring oscillator is sometimes called the "first stage." The nth circuit is sometimes called the "nth stage." A ring oscillator made up of NOT circuits has a configuration in which the output of each NOT circuit is connected to the input of the NOT circuit in the next stage. The output of the nth NOT circuit is connected to the input of the first NOT circuit.

[0379] Furthermore, in a NOT circuit, a certain delay time occurs before the inverted signal of the input signal is output. Since n is an odd number, the signal output from the first stage is delayed by n stages before being input to the first stage. This causes the ring oscillator to oscillate. That is, an AC signal is supplied to terminal Y shown in FIG. 51C. By using a ring oscillator, for example, it is possible to generate a clock signal within the circuit. Furthermore, the delay time of the NOT circuit can be determined by measuring the oscillation frequency of the ring oscillator.

[0380] [DFF Circuit] Fig. 52A is a circuit diagram showing an example of the configuration of a D flip-flop circuit (DFF). Fig. 52B shows the circuit symbol for the D flip-flop circuit. The DFF has a clock signal input terminal CK, an input terminal D, and an output terminal Q.

[0381] 52A includes transistors Tr41 to Tr49, transistors Tr51 to Tr59, transistor Tr61, transistor Tr62, transistor Tr71, and transistor Tr72. Si transistors functioning as p-channel transistors are used as the transistors Tr41 to Tr49, transistor Tr61, and transistor Tr62, and OS transistors functioning as n-channel transistors are used as the transistors Tr51 to Tr59, transistor Tr71, and transistor Tr72.

[0382] A potential H is supplied to one of the source and drain of transistor Tr41, one of the source and drain of transistor Tr42, one of the source and drain of transistor Tr44, one of the source and drain of transistor Tr46, one of the source and drain of transistor Tr48, one of the source and drain of transistor Tr61, and one of the source and drain of transistor Tr62.

[0383] The other of the source and drain of transistor Tr41 is connected to one of the source and drain of transistor Tr51, the gate of transistor Tr44, the gate of transistor Tr46, the gate of transistor Tr53, and the gate of transistor Tr59. The gate of transistor Tr41 is connected to clock signal input terminal CK, the gate of transistor Tr51, the gate of transistor Tr42, the gate of transistor Tr48, the gate of transistor Tr55, and the gate of transistor Tr57.

[0384] The other of the source and drain of transistor Tr42 is connected to one of the source and drain of transistor Tr43. The other of the source and drain of transistor Tr44 is connected to one of the source and drain of transistor Tr45. The other of the source and drain of transistor Tr43 is connected to the other of the source and drain of transistor Tr45, one of the source and drain of transistor Tr52, one of the source and drain of transistor Tr54, the gate of transistor Tr61, and the gate of transistor Tr71. The gate of transistor Tr43 is connected to the gate of transistor Tr52 and input terminal D.

[0385] The other of the source and drain of transistor Tr52 is connected to one of the source and drain of transistor Tr53. The other of the source and drain of transistor Tr54 is connected to one of the source and drain of transistor Tr55. The gate of transistor Tr45 is connected to the gate of transistor Tr54, the other of the source and drain of transistor Tr61, one of the source and drain of transistor Tr71, the gate of transistor Tr47, and the gate of transistor Tr56. The other of the source and drain of transistor Tr46 is connected to one of the source and drain of transistor Tr47. The other of the source and drain of transistor Tr48 is connected to one of the source and drain of transistor Tr49.

[0386] The other of the source and drain of the transistor Tr47 is connected to one of the source and drain of the transistor Tr56, the other of the source and drain of the transistor Tr49, one of the source and drain of the transistor Tr58, the gate of the transistor Tr62, and the gate of the transistor Tr72. The other of the source and drain of the transistor Tr62 is connected to one of the source and drain of the transistor Tr72, the gate of the transistor Tr49, the gate of the transistor Tr58, and the output terminal Q.

[0387] The other of the source and drain of transistor Tr56 is connected to one of the source and drain of transistor Tr57. The other of the source and drain of transistor Tr58 is connected to one of the source and drain of transistor Tr59. A potential L is supplied to the other of the source and drain of transistor Tr51, the other of the source and drain of transistor Tr53, the other of the source and drain of transistor Tr55, the other of the source and drain of transistor Tr71, the other of the source and drain of transistor Tr57, the other of the source and drain of transistor Tr59, and the other of the source and drain of transistor Tr72.

[0388] 52A and 52B has a function in which information (potential) supplied to input terminal D is written to DFF at the timing when the signal input to clock signal input terminal CK changes from potential L to potential H, and the information is held until the next timing when the signal input to clock signal input terminal CK changes from potential L to potential H. In addition, a signal (potential H or potential L) based on the information held by DFF is always output from output terminal Q.

[0389] FIG. 53A is a block diagram showing an example configuration of a shift register circuit (SR). The SR includes multiple DFFs. In this specification, the first-stage (first) DFF is referred to as "DFF[1]," and the potential (data) output from the output terminal Q of DFF[1] is referred to as "DATA OUT[1]." FIG. 53A shows a block diagram of an SR including four stages (four) of DFFs (DFF[1] to DFF[4]). In FIG. 53A, the data output from the output terminals Q of DFF[1] to DFF[4], respectively, are referred to as DATA OUT[1] to DATA OUT[4].

[0390] 53B is a timing chart illustrating the operation of the SR. The clock signal CLK1 is input to the clock signal input terminal CK of the odd-numbered DFFs. The inverted signal of the clock signal CLK1 is input to the clock signal input terminal CK of the even-numbered DFFs.

[0391] A pulse signal SPL is input to the input terminal D of DFF[1]. DFF[1] holds a signal corresponding to the input signal SPL in synchronization with the clock signal CLK1 and outputs it as data OUT[1]. Note that data OUT[1] has a value corresponding to the data held by DFF[1].

[0392] Furthermore, data OUT[1] is input to input terminal D of DFF[2]. DFF[2] holds a signal corresponding to the input data OUT[1] in synchronization with clock signal CLK1 and outputs it as data OUT[2]. Similarly, data OUT[2] is input to input terminal D of DFF[3], and data OUT[3] is input to input terminal D of DFF[4].

[0393] In this way, the SR has the function of sequentially transferring the input signal SPL to the subsequent DFF in synchronization with the clock signal CLK1. The SR also has the function of sequentially switching the potential of the data OUT output from the multiple DFFs in synchronization with the clock signal CLK1.

[0394] Furthermore, it is preferable to provide an overlapping structure between a Si transistor and an OS transistor. By providing an overlapping structure between a Si transistor and an OS transistor, a circuit with a small occupancy area can be realized. Furthermore, an OS transistor operates stably even in a high-temperature environment and exhibits little fluctuation in characteristics. Therefore, the OS transistor is less susceptible to the heat generated by the Si transistor and can operate stably. Furthermore, by providing an overlapping structure between a Si transistor and an OS transistor, the connection distance between them can be made extremely short. As a result, wiring resistance and parasitic capacitance are reduced, enabling the circuit to operate at high speed. Furthermore, the power consumption of the circuit is reduced.

[0395] [Selector] A selector (also called a "selection circuit") can be realized by using a plurality of transistors. Figures 54A and 54B are circuit diagrams showing configuration examples of a selector (SEL).

[0396] 54A shows an example in which a selector is provided between a power supply PW and a circuit 1001, a circuit 1002, or a circuit 1003. The selector shown in Fig. 54A has a transistor Tr81, a transistor Tr82, and a transistor Tr83. The transistor Tr81, the transistor Tr82, and the transistor Tr83 each function as a switch.

[0397] 54A , one of the source and drain of the transistor Tr81, one of the source and drain of the transistor Tr82, and one of the source and drain of the transistor Tr83 are connected to a power supply PW via a wiring PL. The other of the source and drain of the transistor Tr81 is connected to a circuit 1001. The other of the source and drain of the transistor Tr82 is connected to a circuit 1002. The other of the source and drain of the transistor Tr83 is connected to a circuit 1003.

[0398] That is, the circuit 1001 is connected to the power supply PW via a transistor Tr81, the circuit 1002 is connected to the power supply PW via a transistor Tr82, and the circuit 1003 is connected to the power supply PW via a transistor Tr83. The transistors Tr81 to Tr83 function as power transistors that control the power supply to the circuits 1001 to 1003. OS transistors are suitable as power transistors because they have a higher withstand voltage between the source and drain than Si transistors.

[0399] Furthermore, by providing a selector between the circuit 1001, the circuit 1002, and the circuit 1003 and the power supply PW, power gating can be performed to supply power to circuits that are operating and stop the power supply to circuits that are not operating.

[0400] FIG. 54B shows an example in which selectors are provided between the circuit 1001, the circuit 1002, and the circuit 1003 and the circuit 1100.

[0401] 54B , one of the source and drain of the transistor Tr81, one of the source and drain of the transistor Tr82, and one of the source and drain of the transistor Tr83 are connected to the circuit 1100 through a wiring SL. By using a selector, for example, the supply destination of the output signal of the circuit 1100 can be selected from the circuit 1001, the circuit 1002, and the circuit 1003. Alternatively, it can be selected which of the circuits 1001, 1002, and 1003 the output signal of which is to be supplied to the circuit 1100.

[0402] Furthermore, for example, when a clock signal is supplied from circuit 1100 to circuit 1001, circuit 1002, and circuit 1003, clock gating can be performed to supply a clock signal to a circuit that is operating and stop supplying the clock signal to a circuit that is not operating.

[0403] Furthermore, when transmitting and receiving signals of different polarities between multiple circuits, it is preferable to use analog switches (ASW) as switches provided between the multiple circuits. Fig. 54C is a circuit diagram showing an example of the configuration of an analog switch. The analog switch shown in Fig. 54C has a transistor Tr84 which is a p-channel transistor and a transistor Tr85 which is an n-channel transistor.

[0404] One of the source and drain of transistor Tr84 is connected to one of the source and drain of transistor Tr85 and functions as one of the input terminal and output terminal of the analog switch. The other of the source and drain of transistor Tr84 is connected to the other of the source and drain of transistor Tr85 and functions as the other of the input terminal and output terminal of the analog switch. The gate of transistor Tr84 is connected to terminal A, and the gate of transistor Tr85 is connected to terminal AB.

[0405] 54C shows an example in which one of the input terminal or output terminal of the analog switch is connected to the circuit 1100, and the other of the input terminal or output terminal of the analog switch is connected to the circuit 1001. Furthermore, potentials that are always inverted to each other are supplied to the terminal A and the terminal AB. For example, when the analog switch is turned on, a potential L is supplied to the terminal A, and a potential H is supplied to the terminal AB. Furthermore, when the analog switch is turned off, a potential H is supplied to the terminal A, and a potential L is supplied to the terminal AB.

[0406] By using analog switches as switches, signals with different polarities can be transmitted more reliably. Analog switches can be used in the selectors shown in Figures 54A and 54B.

[0407] This embodiment mode can be combined with other embodiment modes as appropriate. In addition, in this specification, when a plurality of configuration examples are shown in one embodiment mode, the configuration examples can be combined as appropriate.

[0408] Embodiment 3 In this embodiment, a structural example of a logic circuit including a semiconductor device which is one embodiment of the present invention will be described.

[0409] 55A is a circuit diagram illustrating an example of a logic circuit including a semiconductor device of one embodiment of the present invention, which includes a logic circuit RC1, a logic circuit RC2, a transistor SW1, a transistor SW2, and a transistor SW3.

[0410] The logic circuits RC1 and RC2 have Si transistors fabricated using a CMOS (Complementary MOS) process. The logic circuits RC1 and RC2 are basic logic gates such as NOT, NAND, NOR, AND, and OR. Alternatively, the logic circuits RC1 and RC2 may be circuits such as flip-flops, registers, and shift registers that are combinations of these logic gates. Alternatively, the logic circuits RC1 and RC2 may be large-scale arithmetic circuits that are combinations of multiple of the above circuits.

[0411] For example, in the case of a NOT gate, the logic circuit RC1 outputs the inverted logic of the input data SIN input to the input terminal (IN) to the output terminal (OUT). There may be multiple input terminals and output terminals depending on the type of logic gate. In addition, in Figure 55A, the wiring connected to the output terminal of the logic circuit RC1 is referred to as node NodeA.

[0412] In the case of a NOT gate, for example, the logic circuit RC2 outputs, from its output terminal (OUT), the inverted logic of the signal held at node NodeB that is input to its input terminal (IN) as an output signal SOUT. In Figure 55A, the wiring connected to the input terminal of the logic circuit RC2 is referred to as node NodeB.

[0413] The logic circuits RC1 and RC2 are each connected to a wiring line supplied with a high power supply potential VDD. The logic circuit RC1 is connected to a power supply line supplied with a low power supply potential VSS via a transistor SW1. The logic circuit RC2 is connected to a power supply line supplied with a low power supply potential VSS via a transistor SW2. The output terminal of the logic circuit RC1 is connected to the input terminal of the logic circuit RC2 via a transistor SW3.

[0414] The transistors SW1 to SW3 are the transistors described in the above embodiment, each including indium in an oxide semiconductor layer that serves as a channel formation region. The transistors SW1 to SW2 function as power gating switches. The transistor SW3 functions as a switch that controls conduction between the logic circuits RC1 and RC2. The transistors SW1 to SW3 are turned on or off by control signals SPG1 to SPG3, respectively.

[0415] As described above, the transistor, which is one embodiment of a semiconductor device, has extremely high field-effect mobility and extremely low off-state current. Therefore, when the transistors SW1 and SW2 are used as switches for power gating of the logic circuits, power gating can be performed for each logic circuit without impairing high-speed operation of the logic circuits. Furthermore, when the transistor SW3 is used as a switch for controlling conduction between the logic circuits, a potential corresponding to data input / output between the logic circuits can be held.

[0416] In the configuration of Figure 55A, partial power gating can be performed without stopping the output signal by performing power gating for each logic circuit and by maintaining a potential according to the data input and output between the logic circuits.

[0417] Fig. 55B is a timing chart illustrating the power gating operation of the logic circuits RC1 and RC2 shown in Fig. 55A, showing periods P01 to P06 that illustrate the on / off timing of the transistors SW1 to SW3.

[0418] A period P01 is a period for explaining normal operation. In this operation, all of the transistors SW1 to SW3 are turned on. The logic circuits RC1 and RC2 can obtain output data corresponding to the input data SIN.

[0419] Period P02 is a period for cutting off the current path between nodes NodeA and NodeB. During this period, transistor SW3 is switched off. By turning off transistor SW3, the current path between nodes NodeA and NodeB between logic circuits RC1 and RC2 can be cut off. As a result, node NodeB between transistor SW3 and logic circuit RC2 can hold a charge according to the logic of the output terminal of logic circuit RC1.

[0420] Period P03 is a period during which the logic circuit RC1 is power-gated. During this period, the transistor SW1 is switched off. By turning off the transistor SW1, the current path between the power supply lines that provide the power supply potential to the logic circuit RC1 can be cut off. As a result, the logic circuit RC1 is power-gated, and power consumption is reduced. In the logic circuit RC2, a charge corresponding to the signal logic is held at node NodeB, and an output signal SOUT corresponding to that logic can be output.

[0421] FIG. 56A is a circuit diagram schematically illustrating period P03. In FIG. 56A, crosses are drawn over the transistors SW1 and SW3 that are turned off, and the potential VDATA corresponding to the charge held at node NodeB is shown. Also in FIG. 56A, the power gating of logic circuit RC1 is shown with a dashed line. As shown in FIG. 56A, the configuration of FIG. 55A enables fine-grained power gating at the logic circuit level. This configuration allows partial power gating of logic circuit RC1 without stopping the output signal SOUT.

[0422] Although the configuration of Figure 55A is illustrated with one logic circuit RC1, multiple logic circuits RC1 may be used. Figure 56B is a schematic diagram of partial power gating when logic circuits RC1A and RC1B corresponding to the logic circuit RC1 of Figure 55A are included. Figure 56B illustrates transistor SW1A, which controls the power gating of logic circuit RC1A, and transistor SW3A, which is located between logic circuit RC2. Figure 56B also illustrates transistor SW1B, which controls the power gating of logic circuit RC1B, and transistor SW3B, which is located between logic circuit RC2.

[0423] In Figure 56B, crosses are drawn over the transistors SW1A and SW3A that are turned off, and the signal paths between the logic circuits RC1B and RC2 are shown with bold arrows. Also in Figure 56B, the power gating of the logic circuit RC1A is shown with dashed lines. As shown in Figure 56B, it is also possible to use the transistors SW3A and SW3B as switching switches to selectively power gate the logic circuits RC1A and RC1B.

[0424] Period P04 is a period during which the logic circuit RC2 is power-gated. During this period, the transistor SW2 is switched off. By turning off the transistor SW2, the current path between the power supply lines that provide the power supply potential to the logic circuit RC2 can be cut off. As a result, both the logic circuits RC1 and RC2 are power-gated, reducing power consumption.

[0425] Period P05 is a period for opening a current path between node NodeA and node NodeB. During this period, transistor SW3 is turned on. By turning on transistor SW3, a signal path between node NodeA and node NodeB can be opened when logic circuits RC1 and RC2 are operating.

[0426] The period P06, like the period P01, is a period for explaining normal operation. In this operation, all of the transistors SW1 to SW3 are turned on. The logic circuits RC1 and RC2 can obtain output data corresponding to the input data SIN.

[0427] As described above, power gating for each logic circuit can be performed by selectively turning off transistors functioning as switches provided for each logic circuit. This allows for extremely small leakage current between power supply lines without impairing the high-speed operation of the logic circuits. Furthermore, by selectively turning off transistors functioning as switches provided between logic circuits, the current path between the logic circuits can be blocked. As a result, charge can be retained according to the signal logic, signal paths can be switched, and the impact of operational delays caused by power gating can be reduced.

[0428] This embodiment mode can be combined with other embodiment modes as appropriate. In addition, in this specification, when a plurality of configuration examples are shown in one embodiment mode, the configuration examples can be combined as appropriate.

[0429] Embodiment 4 In this embodiment, a semiconductor device 900 according to one embodiment of the present invention will be described. The semiconductor device 900 can function as a memory device.

[0430] Fig. 57 is a block diagram showing a configuration example of a semiconductor device 900. The semiconductor device 900 shown in Fig. 57 has a driver circuit 910 and a memory array 920. The memory array 920 has one or more memory cells 950. Fig. 57 shows an example in which the memory array 920 has a plurality of memory cells 950 arranged in a matrix.

[0431] The transistor described as an example in Embodiment 1 can be applied to the memory cell 950. By using the transistor, the operation speed of the memory device can be improved. Furthermore, miniaturization and high integration of the memory device can be achieved. Furthermore, the capacitance per area of ​​the memory device can be increased.

[0432] The driver circuit 910 includes a PSW 931 (power switch), a PSW 932, and a peripheral circuit 915. The peripheral circuit 915 includes a peripheral circuit 911, a control circuit 912, and a voltage generating circuit 928.

[0433] In the semiconductor device 900, each circuit, signal, and voltage can be appropriately selected or omitted as needed. Alternatively, other circuits or signals may be added. The signals BW, CE, GW, clock signal CLK2, WAKE, ADDR, WDA, PON1, and PON2 are input signals from the outside, and the signal RDA is an output signal to the outside. The signal CLK is a clock signal.

[0434] Furthermore, signals BW, CE, and GW are control signals. Signal CE is a chip enable signal, signal GW is a global write enable signal, and signal BW is a byte write enable signal. Signal ADDR is an address signal. Signal WDA is a write data signal, and signal RDA is a read data signal. Signals PON1 and PON2 are power gating control signals. Note that signals PON1 and PON2 may be generated by the control circuit 912.

[0435] The control circuit 912 is a logic circuit having a function of controlling the overall operation of the semiconductor device 900. For example, the control circuit 912 performs a logical operation on the signals CE, GW, and BW to determine the operation mode (e.g., write operation, read operation) of the semiconductor device 900. Alternatively, the control circuit 912 generates a control signal for the peripheral circuit 911 so that this operation mode is executed.

[0436] The voltage generation circuit 928 has a function of generating a voltage. The signal WAKE has a function of controlling the input of the clock signal CLK2 to the voltage generation circuit 928. For example, when an H-level signal is given as the signal WAKE, the clock signal CLK2 is input to the voltage generation circuit 928, and the voltage generation circuit 928 generates a voltage.

[0437] The peripheral circuit 911 is a circuit for writing and reading data to and from the memory cells 950. The peripheral circuit 911 includes a row decoder 941, a column decoder 942, a row driver 923, a column driver 924, an input circuit 925, an output circuit 926, and a sense amplifier 927.

[0438] The row decoder 941 and the column decoder 942 have the function of decoding the signal ADDR. The row decoder 941 is a circuit for specifying a row to be accessed, and the column decoder 942 is a circuit for specifying a column to be accessed. The row driver 923 has the function of selecting the row specified by the row decoder 941. The column driver 924 has the function of writing data to the memory cells 950, reading data from the memory cells 950, and retaining the read data.

[0439] The input circuit 925 has a function of holding a signal WDA. The data held by the input circuit 925 is output to the column driver 924. The output data of the input circuit 925 is data (Din) to be written to the memory cell 950. The data (Dout) read from the memory cell 950 by the column driver 924 is output to the output circuit 926. The output circuit 926 has a function of holding Dout. In addition, the output circuit 926 has a function of outputting Dout to the outside of the semiconductor device 900. The data output from the output circuit 926 is a signal RDA.

[0440] The PSW 931 has a function of controlling the supply of VDD to the peripheral circuit 915. The PSW 932 has a function of controlling the supply of VHM to the row driver 923. In this embodiment, the high power supply potential of the semiconductor device 900 is VDD, and the low power supply potential is GND (ground potential). Also, VHM is a high power supply potential used to set the word line to a high level, and is higher than VDD. The on / off of the PSW 931 is controlled by a signal PON1, and the on / off of the PSW 932 is controlled by a signal PON2. In FIG. 57, in the peripheral circuit 915, V ＤＤ Although the number of power domains to which power is supplied is set to one, it may be set to a plurality of power domains. In this case, a power switch can be provided for each power domain.

[0441] 58A to 58I, other examples of memory cell configurations that can be applied to the memory cell 950 will be described.

[0442] 58A shows an example of a circuit configuration of a DRAM memory cell. In this specification and the like, a DRAM using an OS transistor is referred to as a DOSRAM (Dynamic Oxide Semiconductor Random Access Memory). A memory cell 951 includes a transistor M1 and a capacitor CA.

[0443] The transistor M1 may have a front gate (sometimes simply referred to as a gate) and a back gate. In this case, the back gate may be connected to a wiring to which a constant potential or a signal is applied, or the front gate and the back gate may be connected to each other.

[0444] A first terminal of the transistor M1 is connected to a first terminal of the capacitance element CA, a second terminal of the transistor M1 is connected to the wiring BIL, and a gate of the transistor M1 is connected to the wiring WOL. The second terminal of the capacitance element CA is connected to the wiring CAL.

[0445] The wiring BIL functions as a bit line, and the wiring WOL functions as a word line. The wiring CAL functions as a wiring for applying a predetermined potential to the second terminal of the capacitance element CA. When writing and reading data, it is preferable to apply a low-level potential (sometimes referred to as a reference potential) to the wiring CAL.

[0446] Data is written and read by applying a high-level potential to the wiring WOL to turn on the transistor M1 and connect the wiring BIL to the first terminal of the capacitor CA.

[0447] Furthermore, the memory cell that can be used for the memory cell 950 is not limited to the memory cell 951, and the circuit configuration can be changed. For example, the memory cell 952 shown in FIG. 58B may be used. The memory cell 952 is an example in which the memory cell 952 does not include a capacitor CA and a wiring CAL. The first terminal of the transistor M1 is in an electrically floating state.

[0448] In the memory cell 952, the potential written through the transistor M1 is held in a capacitance (also referred to as a parasitic capacitance) between the first terminal and the gate, which is indicated by a dashed line. With this configuration, the configuration of the memory cell can be significantly simplified.

[0449] Note that the OS transistor described in Embodiment 1 is preferably used as the transistor M1. For example, the transistor 10 and the capacitor 40 described in Embodiment 1 can be applied to the transistor M1 and the capacitor CA of the memory cell 951, respectively. By using an OS transistor as the transistor M1, the operation speed of the memory device can be improved. Furthermore, the area occupied by the memory cell can be reduced. Furthermore, an OS transistor has a characteristic of extremely low off-state current. By using an OS transistor as the transistor M1, the leakage current of the transistor M1 can be significantly reduced. That is, written data can be held by the transistor M1 for a long time, thereby reducing the frequency of refreshing the memory cell. Alternatively, refreshing the memory cell can be eliminated. Furthermore, because the leakage current is extremely low, multilevel data or analog data can be held in the memory cells 951 and 952.

[0450] Furthermore, as shown in Figure 58C, one wiring BIL can be provided in common for two or more DRAM memory cells. In Figure 58C, a memory cell having a transistor M1 and a capacitor CA1 and a memory cell having a transistor M2 and a capacitor CA2 are connected to one wiring BIL. For example, when Figure 58C corresponds to Figure 44B, the transistor M1 corresponds to the transistor 10a, the capacitor CA1 corresponds to the capacitor 40a, the transistor M2 corresponds to the transistor 10b, and the capacitor CA2 corresponds to the capacitor 40b. The wiring BIL also corresponds to the conductive layer 51b.

[0451] 58D shows an example circuit configuration of a gain cell type memory cell having two transistors and one capacitor. The memory cell 953 includes a transistor M2, a transistor M3, and a capacitor CB. In this specification and the like, a memory device having a gain cell type memory cell in which the transistor M2 is an OS transistor is referred to as a nonvolatile oxide semiconductor RAM (NOSRAM).

[0452] The first terminal of transistor M2 is connected to the first terminal of capacitance element CB, the second terminal of transistor M2 is connected to wiring WBL, and the gate of transistor M2 is connected to wiring WOL. The second terminal of capacitance element CB is connected to wiring CAL. The first terminal of transistor M3 is connected to wiring RBL, the second terminal of transistor M3 is connected to wiring SL, and the gate of transistor M3 is connected to the first terminal of capacitance element CB.

[0453] The wiring WBL functions as a write bit line, the wiring RBL functions as a read bit line, and the wiring WOL functions as a word line. The wiring CAL functions as a wiring for applying a predetermined potential to the second terminal of the capacitance element CB. When writing data, while retaining data, and when reading data, it is preferable to apply a low-level potential (sometimes referred to as a reference potential) to the wiring CAL.

[0454] Data is written by applying a high-level potential to the wiring WOL, turning on the transistor M2, and connecting the wiring WBL to the first terminal of the capacitor CB. Specifically, when the transistor M2 is on, a potential corresponding to the information to be recorded is applied to the wiring WBL, and the potential is written to the first terminal of the capacitor CB and the gate of the transistor M3. Then, a low-level potential is applied to the wiring WOL, turning off the transistor M2, thereby maintaining the potential of the first terminal of the capacitor CB and the potential of the gate of the transistor M3.

[0455] Data is read by applying a predetermined potential to the wiring SL. The current flowing between the source and drain of the transistor M3 and the potential of the first terminal of the transistor M3 are determined by the potential of the gate of the transistor M3 and the potential of the second terminal of the transistor M3. Therefore, the potential held in the first terminal of the capacitor CB (or the gate of the transistor M3) can be read by reading the potential of the wiring RBL connected to the first terminal of the transistor M3. In other words, information written in this memory cell can be read from the potential held in the first terminal of the capacitor CB (or the gate of the transistor M3).

[0456] Alternatively, for example, the wiring WBL and the wiring RBL may be combined into a single wiring BIL. An example circuit configuration of such a memory cell is shown in Figure 58E. The memory cell 954 is configured such that the wiring WBL and the wiring RBL of the memory cell 953 are combined into a single wiring BIL, and the second terminal of the transistor M2 and the first terminal of the transistor M3 are connected to the wiring BIL. In other words, the memory cell 954 is configured to operate as a write bit line and a read bit line using a single wiring BIL.

[0457] 58F is an example in which the capacitor element CB and the wiring CAL in the memory cell 953 are omitted. Also, the memory cell 956 in Fig. 58G is an example in which the capacitor element CB and the wiring CAL in the memory cell 954 are omitted. With such a configuration, the integration degree of the memory cells can be increased.

[0458] Note that it is preferable to use the OS transistor described in Embodiment 1 as at least the transistor M2. For example, the transistor 10 and the transistor 80 described in Embodiment 1 can be used as the transistors M2 and M3 in the memory cells 953 and 954, respectively. Note that the transistor 10 described in Embodiment 1 may also be used as the transistor M3. By using an OS transistor as at least one of the transistors included in the memory cells 953 to 956, the operation speed of the storage device can be improved. Furthermore, the area occupied by the memory cell can be reduced.

[0459] Since the OS transistor has an extremely low off-state current, written data can be held by the transistor M2 for a long time, which reduces the frequency of refreshing the memory cell. Alternatively, the refresh operation of the memory cell can be eliminated. Furthermore, since the leakage current is extremely low, multilevel data or analog data can be held in the memory cell 953, the memory cell 954, the memory cell 955, and the memory cell 956.

[0460] The memory cell 953, the memory cell 954, the memory cell 955, and the memory cell 956, each of which uses an OS transistor as the transistor M2, are one embodiment of an NOSRAM.

[0461] Note that a Si transistor may be used as the transistor M3. The Si transistor can increase the field effect mobility and can also be used as a p-channel transistor, thereby increasing the degree of freedom in circuit design.

[0462] When an OS transistor is used as the transistor M3, the memory cell can be configured using only n-channel transistors.

[0463] 58H shows a three-transistor, one-capacitor gain cell type memory cell 957. The memory cell 957 has transistors M4 to M6 and a capacitative element CC.

[0464] The first terminal of the transistor M4 is connected to the first terminal of the capacitor CC, the second terminal of the transistor M4 is connected to the wiring BIL, and the gate of the transistor M4 is connected to the wiring WOL. The second terminal of the capacitor CC is electrically connected to the first terminal of the transistor M5 and the wiring GNDL. The second terminal of the transistor M5 is connected to the first terminal of the transistor M6, and the gate of the transistor M5 is connected to the first terminal of the capacitor CC. The second terminal of the transistor M6 is connected to the wiring BIL, and the gate of the transistor M6 is connected to the wiring RWL.

[0465] The wiring BIL functions as a bit line, the wiring WOL functions as a write word line, and the wiring RWL functions as a read word line. The wiring GNDL is a wiring that applies a low-level potential.

[0466] Data is written by applying a high-level potential to the wiring WOL, turning on the transistor M4, and connecting the wiring BIL to the first terminal of the capacitor CC. Specifically, when the transistor M4 is turned on, a potential corresponding to the information to be recorded is applied to the wiring BIL, and the potential is written to the first terminal of the capacitor CC and the gate of the transistor M5. Then, a low-level potential is applied to the wiring WOL, turning off the transistor M4, thereby holding the potential of the first terminal of the capacitor CC and the potential of the gate of the transistor M5.

[0467] Data is read by precharging the wiring BIL to a predetermined potential, then electrically floating the wiring BIL, and applying a high-level potential to the wiring RWL. Because the wiring RWL is at a high-level potential, the transistor M6 is turned on, and the wiring BIL and the second terminal of the transistor M5 are electrically connected. At this time, the potential of the wiring BIL is applied to the second terminal of the transistor M5. The potential of the second terminal of the transistor M5 and the potential of the wiring BIL change depending on the potential held in the first terminal of the capacitor CC (or the gate of the transistor M5). By reading the potential of the wiring BIL, the potential held in the first terminal of the capacitor CC (or the gate of the transistor M5) can be read. In other words, information written in this memory cell can be read from the potential held in the first terminal of the capacitor CC (or the gate of the transistor M5).

[0468] Note that at least the transistor M4 is preferably the OS transistor described in Embodiment 1. For example, the transistor 10 described in Embodiment 1 can be used as the transistor M4 of the memory cell 957. By using an OS transistor, the area occupied by the memory cell can be reduced.

[0469] Note that Si transistors may be used as the transistors M5 and M6. As described above, Si transistors may have higher field-effect mobility than OS transistors depending on the crystalline state of silicon used in the semiconductor layer.

[0470] When OS transistors are used as the transistors M5 and M6, the memory cell can be configured using only n-channel transistors.

[0471] [OS-SRAM] FIG. 58I shows an example of an SRAM (Static Random Access Memory) using OS transistors. In this specification and the like, an SRAM using OS transistors is referred to as an OS-SRAM (Oxide Semiconductor-SRAM). Note that a memory cell 958 shown in FIG. 58I is a memory cell of an SRAM capable of backing up data.

[0472] The memory cell 958 includes transistors M7 to M10, transistors MS1 to MS4, and capacitors CD1 and CD2. Note that the transistors MS1 and MS2 are p-channel transistors, and the transistors MS3 and MS4 are n-channel transistors.

[0473] A first terminal of transistor M7 is connected to wiring BIL, and a second terminal of transistor M7 is connected to a first terminal of transistor MS1, a first terminal of transistor MS3, the gate of transistor MS2, the gate of transistor MS4, and a first terminal of transistor M10. The gate of transistor M7 is connected to wiring WOL. A first terminal of transistor M8 is connected to wiring BILB, and a second terminal of transistor M8 is connected to a first terminal of transistor MS2, the first terminal of transistor MS4, the gate of transistor MS1, the gate of transistor MS3, and a first terminal of transistor M9. The gate of transistor M8 is connected to wiring WOL.

[0474] A second terminal of the transistor MS1 is electrically connected to the wiring VDL. A second terminal of the transistor MS2 is electrically connected to the wiring VDL. A second terminal of the transistor MS3 is electrically connected to the wiring GNDL. A second terminal of the transistor MS4 is electrically connected to the wiring GNDL.

[0475] A second terminal of the transistor M9 is connected to a first terminal of the capacitor CD1, and a gate of the transistor M9 is connected to the wiring BRL. A second terminal of the transistor M10 is connected to a first terminal of the capacitor CD2, and a gate of the transistor M10 is connected to the wiring BRL.

[0476] A second terminal of the capacitance element CD1 is connected to the wiring GNDL, and a second terminal of the capacitance element CD2 is connected to the wiring GNDL.

[0477] The wirings BIL and BILB function as bit lines, the wiring WOL functions as a word line, and the wiring BRL is a wiring that controls the conductive state and non-conductive state of the transistors M9 and M10.

[0478] The wiring VDL is a wiring that applies a high-level potential, and the wiring GNDL is a wiring that applies a low-level potential.

[0479] Data is written by applying a high-level potential to the wiring WOL and a high-level potential to the wiring BRL. Specifically, when the transistor M10 is in a conductive state, a potential corresponding to information to be recorded is applied to the wiring BIL, and the potential is written to the second terminal of the transistor M10.

[0480] Since the memory cell 958 includes an inverter loop formed by the transistors MS1 and MS2, an inverted signal of the data signal corresponding to the potential is input to the second terminal of the transistor M8. Because the transistor M8 is conductive, the potential applied to the wiring BIL, i.e., the inverted signal of the signal input to the wiring BIL, is output to the wiring BILB. Because the transistors M9 and M10 are conductive, the potentials of the second terminals of the transistors M7 and M8 are held in the first terminals of the capacitors CD2 and CD1, respectively. After that, a low-level potential is applied to the wiring WOL and a low-level potential is applied to the wiring BRL to turn off the transistors M7 to M10, thereby holding the potentials of the first terminals of the capacitors CD1 and CD2.

[0481] Data is read by precharging the wirings BIL and BILB to a predetermined potential in advance, and then applying a high-level potential to the wiring WOL and a high-level potential to the wiring BRL. The potential of the first terminal of the capacitor CD1 is refreshed by the inverter loop of the memory cell 958 and output to the wiring BILB. The potential of the first terminal of the capacitor CD2 is refreshed by the inverter loop of the memory cell 958 and output to the wiring BIL. The potentials of the wirings BIL and BILB change from the precharged potentials to the potentials of the first terminal of the capacitor CD2 and the first terminal of the capacitor CD1, respectively. Therefore, the potential held in the memory cell can be read from the potential of the wiring BIL or BILB.

[0482] Note that the OS transistors described in Embodiment 1 are preferably used as the transistors M7 to M10. This allows written data to be held by the transistors M7 to M10 for a long time, which reduces the frequency of refreshing the memory cells. Alternatively, the refresh operation of the memory cells can be eliminated. Furthermore, the operating speed of the memory device can be improved. Furthermore, the area occupied by the memory cells can be reduced.

[0483] Note that Si transistors may be used as the transistors MS1 to MS4.

[0484] This embodiment mode can be combined with other embodiment modes as appropriate. In addition, in this specification, when a plurality of configuration examples are shown in one embodiment mode, the configuration examples can be combined as appropriate.

[0485] Embodiment 5 In this embodiment, application examples of a semiconductor device of one embodiment of the present invention will be described with reference to FIGS. 59A to 60E.

[0486] The semiconductor device of one embodiment of the present invention can be used in, for example, electronic components, mainframes, space equipment, data centers (also referred to as DCs), and various electronic devices. By using the semiconductor device of one embodiment of the present invention, low power consumption and high performance can be achieved for the electronic components, mainframes, space equipment, data centers, and various electronic devices.

[0487] Examples of electronic devices include electronic devices with relatively large screens such as television sets, desktop or notebook computers, computer monitors, digital signage, large game machines such as pachinko machines, as well as digital cameras, digital video cameras, digital photo frames, mobile phones, portable game machines, personal digital assistants, and sound playback devices.

[0488] The electronic device of this embodiment may have a sensor (including the function of detecting, detecting, or measuring force, displacement, position, velocity, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical substance, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor, or infrared rays).

[0489] The electronic device of the present embodiment can have various functions, such as a function to display various information (still images, videos, text images, etc.) on a display unit, a touch panel function, a function to display a calendar, date, time, etc., a function to execute various software (programs), a wireless communication function, and a function to read out programs or data recorded on a recording medium.

[0490] [Electronic Component] FIG. 59A shows a perspective view of a substrate (mounting substrate 989) on which an electronic component 980 is mounted. The electronic component 980 shown in FIG. 59A has a semiconductor device 981 inside a mold 984. FIG. 59A omits some details in order to show the interior of the electronic component 980. The electronic component 980 has lands 985 on the outside of the mold 984. The lands 985 are electrically connected to electrode pads 986, and the electrode pads 986 are electrically connected to the semiconductor device 981 via wires 987. The electronic component 980 is mounted on, for example, a printed circuit board 988. A plurality of such electronic components are combined and electrically connected on the printed circuit board 988 to complete the mounting substrate 989.

[0491] The semiconductor device 981 also includes a drive circuit layer 982 and a memory layer 983. The memory layer 983 has a configuration in which multiple memory cell arrays are stacked. The stacked configuration of the drive circuit layer 982 and the memory layer 983 can be a monolithic stacked configuration. In a monolithic stacked configuration, the layers can be connected without using through-electrode technology such as TSV (Through Silicon Via) or bonding technology such as Cu-Cu direct bonding. By monolithically stacking the drive circuit layer 982 and the memory layer 983, for example, a so-called on-chip memory configuration can be achieved in which the memory is formed directly on the processor. The on-chip memory configuration enables the operation of the interface between the processor and the memory to be faster.

[0492] Furthermore, by configuring an on-chip memory, the size of the connection wiring can be reduced compared to technologies that use through electrodes such as TSVs, and the number of connection pins can be increased. Increasing the number of connection pins enables parallel operation, which makes it possible to improve the memory bandwidth (also called memory bandwidth).

[0493] Furthermore, it is preferable that the memory cell arrays included in the memory layer 983 are formed using OS transistors and the memory cell arrays are monolithically stacked. By forming the memory cell arrays in a monolithic stacked configuration, it is possible to improve one or both of the memory bandwidth and the memory access latency. Note that the bandwidth is the amount of data transferred per unit time, and the access latency is the time from access to the start of data exchange. Note that when Si transistors are used for the memory layer 983, it is more difficult to form a monolithic stacked configuration than when OS transistors are used. Therefore, it can be said that OS transistors have a superior structure to Si transistors in a monolithic stacked configuration.

[0494] Alternatively, an OS transistor can be used for the driver circuit layer 982. The OS transistor described in the above embodiment can pass a large current, which enables the semiconductor device 994 to operate at high speed.

[0495] The semiconductor device 981 may also be referred to as a die. In this specification, a die refers to a chip piece obtained during the semiconductor chip manufacturing process by forming a circuit pattern on, for example, a disk-shaped substrate (also called a wafer) and dicing it into cubes. Semiconductor materials that can be used for the die include, for example, silicon (Si), silicon carbide (SiC), or gallium nitride (GaN). For example, a die obtained from a silicon substrate (also called a silicon wafer) may be called a silicon die.

[0496] Although the above example shows the semiconductor device 981 functioning as a memory device, the present invention is not limited to this. For example, the semiconductor device 981 can also function as a processor such as a CPU, a GPU, or a field programmable gate array (FPGA). In this case, an OS transistor is preferably used for the semiconductor device 981. The OS transistor described in the above embodiment can pass a large current. This enables the semiconductor device 981 to operate at high speed.

[0497] 59B shows a perspective view of an electronic component 990. The electronic component 990 is an example of a SiP (System in Package) or an MCM (Multi-Chip Module). The electronic component 990 has an interposer 991 provided on a package substrate 992 (printed circuit board), and a semiconductor device 994 and a plurality of semiconductor devices 981 provided on the interposer 991.

[0498] In the electronic component 990, the semiconductor device 981 is used as a high bandwidth memory (HBM), and the semiconductor device 994 can be used in an integrated circuit such as a CPU, a GPU, or an FPGA.

[0499] In addition, an OS transistor is preferably used for the semiconductor device 994. The OS transistor described in the above embodiment can pass a large current, which enables the semiconductor device 994 to operate at high speed.

[0500] For example, a ceramic substrate, a plastic substrate, or a glass epoxy substrate can be used as the package substrate 992. For example, a silicon interposer or a resin interposer can be used as the interposer 991.

[0501] The interposer 991 has multiple wirings and functions to connect multiple integrated circuits with different terminal pitches. The multiple wirings are provided in a single layer or multiple layers. The interposer 991 also functions to connect the integrated circuits provided on the interposer 991 to electrodes provided on the package substrate 992. For these reasons, the interposer is sometimes called a "rewiring substrate" or "intermediate substrate." In some cases, through electrodes are provided in the interposer 991, and the integrated circuits and the package substrate 992 are connected using the through electrodes. In addition, in a silicon interposer, TSVs can also be used as through electrodes.

[0502] In an HBM, many wirings must be connected to achieve a wide memory bandwidth. Therefore, the interposer on which the HBM is mounted must have fine and high-density wiring. Therefore, it is preferable to use a silicon interposer for the interposer on which the HBM is mounted.

[0503] Furthermore, in SiPs, MCMs, and the like that use silicon interposers, a decrease in reliability due to differences in the coefficient of expansion between the integrated circuit and the interposer is unlikely to occur. Furthermore, because the silicon interposer has a highly flat surface, poor connection between the integrated circuit mounted on the silicon interposer and the silicon interposer is unlikely to occur. In particular, it is preferable to use silicon interposers in 2.5D packages (2.5-dimensional packaging) in which multiple integrated circuits are arranged horizontally on an interposer.

[0504] On the other hand, when connecting multiple integrated circuits with different terminal pitches using a silicon interposer, TSVs, or the like, a space is required, such as the width of the terminal pitch. Therefore, when attempting to reduce the size of the electronic component 990, the width of the terminal pitch becomes an issue, and it may be difficult to provide the many wirings necessary to achieve a wide memory bandwidth. Therefore, as described above, a monolithic stacked structure using OS transistors is preferable. A composite structure may be formed by combining a memory cell array stacked using TSVs with a monolithic stacked memory cell array.

[0505] A heat sink (heat dissipation plate) may be provided over the electronic component 990. When a heat sink is provided, it is preferable to align the height of an integrated circuit provided on the interposer 991. For example, in the electronic component 990 shown in this embodiment, it is preferable to align the height of the semiconductor device 981 and the height of the semiconductor device 994.

[0506] Electrodes 993 may be provided on the bottom of the package substrate 992 in order to mount the electronic component 990 on another substrate. FIG. 59B shows an example in which the electrodes 993 are formed of solder balls. By providing solder balls in a matrix on the bottom of the package substrate 992, BGA (Ball Grid Array) mounting can be achieved. The electrodes 993 may also be formed of conductive pins. By providing conductive pins in a matrix on the bottom of the package substrate 992, PGA (Pin Grid Array) mounting can be achieved.

[0507] The electronic component 990 can be mounted on other substrates using various mounting methods, not limited to BGA and PGA, such as a staggered pin grid array (SPGA), a land grid array (LGA), a quad flat package (QFP), a quad flat J-leaded package (QFJ), and a quad flat non-leaded package (QFN).

[0508] 60A shows a perspective view of a mainframe computer 5600. The mainframe computer 5600 shown in Fig. 60A has a rack 5610 housing a plurality of rack-mounted computers 5620. The mainframe computer 5600 may also be called a supercomputer.

[0509] The computer 5620 can have the configuration shown in the perspective view in Fig. 60B, for example. In Fig. 60B, the computer 5620 has a motherboard 5630, which has a plurality of slots 5631 and a plurality of connection terminals. A PC card 5621 is inserted into the slot 5631. In addition, the PC card 5621 has connection terminals 5623, 5624, and 5625, which are each connected to the motherboard 5630.

[0510] PC card 5621 shown in Figure 60C is an example of a processing board equipped with a CPU, GPU, storage device, etc. PC card 5621 has board 5622. Board 5622 also has connection terminal 5623, connection terminal 5624, connection terminal 5625, semiconductor device 5626, semiconductor device 5627, semiconductor device 5628, and connection terminal 5629. Note that Figure 60C illustrates semiconductor devices other than semiconductor device 5626, semiconductor device 5627, and semiconductor device 5628, but for these semiconductor devices, the following descriptions of semiconductor device 5626, semiconductor device 5627, and semiconductor device 5628 can be referenced.

[0511] The connection terminal 5629 has a shape that allows it to be inserted into a slot 5631 of the motherboard 5630, and the connection terminal 5629 functions as an interface for connecting the PC card 5621 and the motherboard 5630. An example of the standard for the connection terminal 5629 is PCIe.

[0512] The connection terminals 5623, 5624, and 5625 can be, for example, interfaces for supplying power to the PC card 5621, inputting signals, etc. Furthermore, they can be, for example, interfaces for outputting signals calculated by the PC card 5621. Examples of the standards for the connection terminals 5623, 5624, and 5625 include USB (Universal Serial Bus), SATA (Serial ATA), and SCSI (Small Computer System Interface). Furthermore, when a video signal is output from the connection terminals 5623, 5624, and 5625, examples of the standards for each include HDMI (registered trademark).

[0513] The semiconductor device 5626 has a terminal (not shown) for inputting and outputting signals, and the semiconductor device 5626 can be connected to the board 5622 by inserting the terminal into a socket (not shown) provided on the board 5622.

[0514] The semiconductor device 5627 has a plurality of terminals, and the semiconductor device 5627 can be connected to the board 5622 by, for example, reflow soldering the terminals to wiring provided on the board 5622. Examples of the semiconductor device 5627 include an FPGA, a GPU, and a CPU. For example, the electronic component 990 can be used as the semiconductor device 5627.

[0515] The semiconductor device 5628 has a plurality of terminals, and the semiconductor device 5628 can be connected to the board 5622 by, for example, reflow soldering the terminals to wiring provided on the board 5622. Examples of the semiconductor device 5628 include a memory device. For example, the electronic component 990 can be used as the semiconductor device 5628.

[0516] The mainframe computer 5600 can also function as a parallel computer. By using the mainframe computer 5600 as a parallel computer, it is possible to perform large-scale calculations required for learning and inference in artificial intelligence, for example.

[0517] [Space Equipment] The semiconductor device according to one embodiment of the present invention is suitable for space equipment.

[0518] A semiconductor device according to one embodiment of the present invention includes an OS transistor. Compared to a Si transistor, an OS transistor exhibits smaller variations in electrical characteristics due to radiation exposure. That is, an OS transistor has high radiation resistance and is therefore highly reliable and suitable for use in an environment where radiation may be incident. For example, an OS transistor is suitable for use in outer space. Specifically, an OS transistor can be used as a transistor for a semiconductor device provided in a space shuttle, an artificial satellite, or a space probe. Examples of radiation include X-rays and neutrons. Note that outer space refers to an altitude of 100 km or higher, and the outer space described in this specification can include one or more of the thermosphere, the mesosphere, and the stratosphere.

[0519] Fig. 60D shows an artificial satellite 6800 as an example of space equipment. The artificial satellite 6800 has a body 6801, a solar panel 6802, an antenna 6803, a secondary battery 6805, and a control device 6807. Note that Fig. 60D illustrates a planet 6804 in space.

[0520] 60D , a battery management system (also referred to as a BMS) or a battery control circuit may be provided for the secondary battery 6805. The use of an OS transistor in the battery management system or the battery control circuit is preferable because it has low power consumption and high reliability even in space.

[0521] Furthermore, outer space is an environment with radiation levels 100 times higher than on Earth. Examples of radiation include electromagnetic waves (electromagnetic radiation) such as X-rays and gamma rays, and particle radiation such as alpha rays, beta rays, neutron rays, proton rays, heavy ion rays, and meson rays.

[0522] When sunlight is irradiated onto the solar panel 6802, the power required for the operation of the satellite 6800 is generated. However, for example, in a situation where sunlight is not irradiated onto the solar panel or where the amount of sunlight irradiating the solar panel is small, the generated power is small. Therefore, there is a possibility that the power required for the operation of the satellite 6800 will not be generated. In order to operate the satellite 6800 even in a situation where the generated power is small, it is preferable to provide a secondary battery 6805 in the satellite 6800. Note that the solar panel may be called a solar cell module.

[0523] The satellite 6800 can generate a signal. The signal is transmitted via an antenna 6803, and can be received by, for example, a receiver installed on the ground or another satellite. By receiving the signal transmitted by the satellite 6800, the position of the receiver that received the signal can be determined. As described above, the satellite 6800 can constitute a satellite positioning system.

[0524] The control device 6807 has a function of controlling the artificial satellite 6800. The control device 6807 is configured using, for example, one or more selected from a CPU, a GPU, and a storage device. Note that the control device 6807 is preferably a semiconductor device including an OS transistor which is one embodiment of the present invention.

[0525] The artificial satellite 6800 can also be configured to include a sensor. For example, by including a visible light sensor, the artificial satellite 6800 can have the function of detecting sunlight reflected from an object on the ground. Alternatively, by including a thermal infrared sensor, the artificial satellite 6800 can have the function of detecting thermal infrared rays emitted from the earth's surface. As described above, the artificial satellite 6800 can function as, for example, an earth observation satellite.

[0526] Although an artificial satellite is given as an example of space equipment in this embodiment, the invention is not limited thereto. For example, the semiconductor device of one embodiment of the present invention is suitable for space equipment such as a spaceship, a space capsule, and a space probe.

[0527] As described above, OS transistors have excellent advantages over Si transistors, such as the ability to achieve a wide memory bandwidth and high radiation resistance.

[0528] [Data Center] The semiconductor device according to one embodiment of the present invention is suitable for a storage system applied to, for example, a data center. Data centers are required to perform long-term management of data, such as ensuring the immutability of data. Managing long-term data requires larger buildings, such as installing storage and servers for storing huge amounts of data, ensuring a stable power supply for maintaining the data, or ensuring cooling equipment required for maintaining the data.

[0529] By using the semiconductor device of one embodiment of the present invention in a storage system applied to a data center, it is possible to reduce the power required to store data and the size of the semiconductor device that stores data. Therefore, it is possible to reduce the size of the storage system, the size of the power supply for storing data, the scale of cooling equipment, etc. Therefore, it is possible to reduce the space required for the data center.

[0530] Furthermore, the semiconductor device of one embodiment of the present invention has low power consumption, which allows heat generation from the circuit to be reduced. Therefore, adverse effects of the heat generation on the circuit itself, peripheral circuits, and modules can be reduced. Furthermore, by using the semiconductor device of one embodiment of the present invention, a data center that operates stably even in a high-temperature environment can be realized. Therefore, the reliability of the data center can be improved.

[0531] Fig. 60E shows a storage system applicable to a data center. The storage system 7010 shown in Fig. 60E has multiple servers 7001sb as hosts 7001. It also has multiple storage devices 7003md as storage 7003. The host 7001 and storage 7003 are connected via a storage area network 7004 and a storage control circuit 7002.

[0532] The host 7001 corresponds to a computer that accesses data stored in the storage 7003. The hosts 7001 may be connected to each other via a network.

[0533] Although the storage 7003 uses flash memory to reduce the data access speed, i.e., the time required to store and output data, this time is significantly longer than the time required for DRAM, which can be used as cache memory within the storage. In order to solve the problem of the long access speed of the storage 7003, a storage system typically provides cache memory within the storage to reduce the time required to store and output data.

[0534] The cache memory described above is used in the storage control circuit 7002 and the storage 7003. Data exchanged between the host 7001 and the storage 7003 is stored in the cache memory in the storage control circuit 7002 and the storage 7003, and then output to the host 7001 or the storage 7003.

[0535] By using OS transistors as transistors for storing data in the cache memory and holding a potential corresponding to the data, the frequency of refresh operations can be reduced, and power consumption can be reduced.

[0536] Note that power consumption can be reduced by applying the semiconductor device of one embodiment of the present invention to any one or more selected from electronic components, mainframe computers, space equipment, data centers, and electronic devices. Therefore, while energy demand is expected to increase with the improvement in performance or integration of semiconductor devices, the use of the semiconductor device of one embodiment of the present invention can also reduce emissions of greenhouse gases such as carbon dioxide (CO). Furthermore, the semiconductor device of one embodiment of the present invention is effective as a countermeasure against global warming due to its low power consumption.

[0537] This embodiment mode can be combined with other embodiment modes as appropriate. In addition, in this specification, when a plurality of configuration examples are shown in one embodiment mode, the configuration examples can be combined as appropriate.

[0538] 10: transistor, 10A: transistor, 10a: transistor, 10Aa: transistor, 10Ab: transistor, 10b: transistor, 11: semiconductor layer, 11a: semiconductor layer, 11b: semiconductor layer, 11F: semiconductor film, 11i: region, 12: insulating layer, 12a: insulating layer, 12b: insulating layer, 12F: insulating film, 13: conductive layer, 13_1: conductive layer, 13_2: conductive layer, 13a: conductive layer, 13b: conductive layer, 13F: conductive film, 14a: conductive layer, 14b: conductive layer, 14c: conductive layer, 14f: conductive layer, 14F: conductive film, 15: insulating layer, 15a: insulating layer, 15b: Insulating layer, 15f: insulating layer, 15F: insulating film, 16: insulating layer, 17: insulating layer, 18: insulating layer, 19a: conductive layer, 19b: conductive layer, 19c: conductive layer, 21: substrate, 22: insulating layer, 26: recess, 27: opening, 28: opening, 30: memory cell, 31: sacrificial layer, 32: sacrificial layer, 33: sacrificial layer, 34: insulating layer, 34_1: insulating layer, 34_2: insulating layer, 36: resist, 40: capacitive element, 40a: capacitive element, 40b: capacitive element, 41: conductive layer, 42: insulating layer, 43: conductive layer, 43_1: conductive layer, 43_2: conductive layer, 51a: conductive layer, 51b: conductive layer, 52: conductive layer , 53: Conductive layer, 61: Insulating layer, 62: Insulating layer, 63: Insulating layer, 64: Insulating layer, 65: Insulating layer, 66: Insulating layer, 67: Insulating layer, 68: Insulating layer, 69: Insulating layer, 70: Insulating layer, 71: Insulating layer, 72: Insulating layer, 73: Insulating layer, 74: Insulating layer, 80: Transistor, 81: Substrate, 82: Semiconductor region, 83: Insulating layer, 84: Conductive layer, 85a: Low resistance region, 85b: Low resistance region, 91: Functional layer, 92: Functional layer, 93: Functional layer, 94: Wiring layer, 340: Memory cell, 350: Transistor, 351: Semiconductor layer, 352: Insulating layer, 353: Conductive layer, 354: Conductive layer, 3 55: conductive layer, 356: conductive layer, 360: capacitance element, 361: conductive layer, 362: insulating layer, 363: conductive layer, 364: conductive layer, 371: insulating layer, 372: insulating layer, 373: insulating layer, 374: insulating layer, 375: insulating layer, 376: insulating layer, 377: insulating layer, 900: semiconductor device, 910: driver circuit, 911: peripheral circuit, 912: control circuit, 915: peripheral circuit, 920: memory array, 923: row driver, 924: column driver, 925: input circuit, 926: output circuit, 927: sense amplifier, 928: voltage generation circuit, 931: PSW, 932: PSW,941: row decoder, 942: column decoder, 950: memory cell, 951: memory cell, 952: memory cell, 953: memory cell, 954: memory cell, 955: memory cell, 956: memory cell, 957: memory cell, 958: memory cell, 980: electronic component, 981: semiconductor device, 982: drive circuit layer, 983: memory layer, 984: mold, 985: land, 986: electrode pad, 987: wire, 988: printed circuit board, 989: mounting board, 990: electronic component, 991: interposer, 992: package board, 993: electrode, 994: semiconductor device, 1001: circuit, 1002: circuit, 1003: circuit, 1100: circuit, 5600: mainframe computer, 5610: rack, 5620: computer, 5621: PC card, 5622: board, 5623: connection terminal, 5624: connection terminal, 5625: connection terminal, 5626: semiconductor device, 5627: semiconductor device, 5628: semiconductor device, 5629: connection terminal, 5630: motherboard, 5631: slot, 6800: artificial satellite, 6801: aircraft, 6802: solar panel, 6803: antenna, 6804: planet, 6805: secondary battery, 6807: control device, 7001: host, 7001sb: server, 7002: storage control circuit, 7003: storage, 7003md: storage device, 7004: storage area network, 7010: storage system,

Claims

a first insulating layer; a semiconductor layer covering a side surface of the first insulating layer; a first conductive layer in contact with a part of a side surface of the semiconductor layer; a second conductive layer provided apart from the first conductive layer and in contact with another part of the side surface of the semiconductor layer; a second insulating layer covering the first insulating layer and a portion of the semiconductor layer; a third conductive layer on the second insulating layer; and The third conductive layer covers the first insulating layer and a portion of the semiconductor layer via the second insulating layer. 　 In claim 1, The semiconductor device, wherein the height of the semiconductor layer is 5 nm or more and 200 nm or less. 　 In claim 1, a first conductive layer and a second conductive layer, each of which does not contact an upper surface of the semiconductor layer; 　 In claim 1, The third conductive layer does not overlap with either the first conductive layer or the second conductive layer. 　 In claim 1, a third insulating layer; the third insulating layer has an opening; At least a portion of each of the first insulating layer, the semiconductor layer, the first conductive layer, the second conductive layer, the second insulating layer, and the third conductive layer is located within the opening. 　 In claim 1, a fourth insulating layer; the first insulating layer and the semiconductor layer are provided on the fourth insulating layer; the fourth insulating layer has a recess surrounding the first insulating layer and the semiconductor layer; the first conductive layer and the second conductive layer are each provided to fill a part of the recess; The second insulating layer is provided so as to fill another part of the recess. 　 In claim 6, A semiconductor device, wherein a lower surface of the third conductive layer at a position overlapping the recess is located lower than a lower surface of the semiconductor layer. 　 In any one of claims 1 to 7, The semiconductor device, wherein the semiconductor layer contains indium and oxygen. 　 In any one of claims 1 to 7, The semiconductor device, wherein the first insulating layer contains hafnium and oxygen. 　 In any one of claims 1 to 7, The semiconductor device, wherein the first conductive layer and the second conductive layer each contain indium, tin, and oxygen. 　 forming a first insulating layer; forming a first sacrificial layer covering a side surface of the first insulating layer; forming a second sacrificial layer covering a side surface of the first sacrificial layer; forming a second insulating layer covering a side surface of the second sacrificial layer; removing the second sacrificial layer to form an opening in the second insulating layer; forming a first conductive layer to fill the opening; removing a portion of the first conductive layer to form a second conductive layer and a third conductive layer spaced apart from each other; forming a third insulating layer so as to cover the first insulating layer and a portion of the first sacrificial layer; forming a fourth conductive layer on the third insulating layer; removing the first sacrificial layer; forming a semiconductor layer in a portion where the first sacrificial layer was located. 　 In claim 11, The method for manufacturing a semiconductor device includes forming the semiconductor layer by atomic layer deposition. 　 In claim 11, The method for manufacturing a semiconductor device further comprises forming the semiconductor layer to have a height of 5 nm to 200 nm. 　 In claim 11, a fourth conductive layer formed at a position where the fourth conductive layer does not overlap with the second conductive layer or the third conductive layer; 　 In claim 11, The method for manufacturing a semiconductor device, wherein the second sacrificial layer has a material different from that of the first sacrificial layer. 　 In any one of claims 11 to 15, The method for manufacturing a semiconductor device, wherein the semiconductor layer contains indium and oxygen. 　 In any one of claims 11 to 15, The method for manufacturing a semiconductor device, wherein the first insulating layer contains hafnium and oxygen. 　 In any one of claims 11 to 15, The method for manufacturing a semiconductor device, wherein the first conductive layer contains indium, tin, and oxygen.

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