Semiconductor memory device

Abstract

According to the present invention, a nonvolatile memory cell using a Complementary FET (CFET) comprises a program transistor (TP) that has a gate connected to a first word line (WLP), and a switch transistor (TS) that is provided between the program transistor (TP) and a bit line (BL) and has a gate connected to a second word line (WLR). The memory cell further comprises dummy transistors (TD1, TD2) that are provided below the program transistor (TP) and the switch transistor (TS), and have different conductivity types from the program transistor (TP) and the switch transistor (TS). The program transistor (TP) and the dummy transistor (TD1) have either a source or a drain connected to each other.

Description

semiconductor memory device

[0001] The present disclosure relates to a semiconductor memory device using a CFET (Complementary FET) device, and more particularly to a layout structure of a nonvolatile memory cell using a CFET.

[0002] Semiconductor memory devices with nonvolatile memory cells are used in many applications. One type of nonvolatile memory cell is the OTP (One Time Programmable) memory cell, which is characterized by storing and reading out the states "1" and "0" in the memory by, for example, destroying an insulating film.

[0003] Furthermore, transistors, which are the basic components of LSIs, have achieved increased integration density, reduced operating voltages, and improved operating speeds through the reduction of gate length (scaling). However, in recent years, excessive scaling has led to problems with off-state current and the resulting significant increase in power consumption. To solve this problem, three-dimensional transistors, which change the transistor structure from the conventional planar type to a three-dimensional type, have been actively researched.

[0004] Patent Document 1 discloses a layout structure of an OTP memory using a CFET.

[0005] International Publication No. 2020 / 262248

[0006] In Patent Document 1, bit lines and power supply lines are provided separately in a buried wiring layer and an upper wiring layer, thereby increasing the wiring width of the wiring provided in the upper wiring layer. However, since the wiring in the buried wiring layer cannot be provided overlapping with the transistor (nanosheet), the wiring width cannot be increased, resulting in increased wiring resistance. Therefore, when the wiring in the buried wiring layer is a bit line, the operating speed decreases. Furthermore, when the wiring in the buried wiring layer is a power supply line, the power supply voltage drops significantly when the OTP memory is used as a mask ROM, resulting in a decrease in operating speed.

[0007] Furthermore, in Patent Document 1, the upper and lower transistors of the CFET that constitutes the OTP memory have the same conductivity type (N-type). On the other hand, the upper and lower transistors of the CFET that constitutes the logic cell have different conductivity types. Therefore, for the semiconductor memory device, different manufacturing methods must be used for the OTP memory region and the logic cell region, which poses a problem of increased manufacturing costs.

[0008] The present disclosure aims to provide a layout structure for an OTP memory using a CFET that can suppress an increase in manufacturing costs and a decrease in operating speed.

[0009] In a first aspect of the present disclosure, a semiconductor memory device including non-volatile memory cells includes first and second word lines extending in a first direction and a bit line extending in a second direction perpendicular to the first direction, and the memory cells each include a first program transistor of a first conductivity type, a first program transistor between the first program transistor and the bit line and a gate connected to the second word line, a first switch transistor of the first conductivity type, a first dummy transistor of a second conductivity type provided below the first program transistor and overlapping with the first program transistor in a planar view, and a second dummy transistor of the second conductivity type provided below the first switch transistor and overlapping with the first switch transistor in a planar view, and either a source or a drain of the first program transistor and the first dummy transistor are connected to each other.

[0010] According to this aspect, in the semiconductor memory device, the nonvolatile memory cell includes a program transistor having a gate connected to a first word line, and a switch transistor disposed between the program transistor and a bit line and having a gate connected to a second word line. That is, the memory cell is an OTP memory cell. The memory cell further includes a dummy transistor disposed below the program transistor and the switch transistor and having a conductivity type different from that of the program transistor and the switch transistor. The program transistor and the dummy transistor have either their source or drain connected to each other. That is, the memory cell is configured using a CFET, and the upper program transistor and switch transistor have a conductivity type different from that of the lower dummy transistor. Therefore, the same manufacturing method can be used for the OTP memory region and the logic cell region of the semiconductor memory device, thereby suppressing increases in manufacturing costs.

[0011] In a second aspect of the present disclosure, a semiconductor memory device including nonvolatile memory cells includes first and second word lines extending in a first direction, a bit line extending in a second direction perpendicular to the first direction, and a power supply wiring extending in the second direction, and the memory cells include first and second program transistors of a first conductivity type connected in parallel and having gates connected to the first word line, and first and second switch transistors of the first conductivity type provided between the first and second program transistors and the bit lines, connected in parallel, and having gates connected to the second word line, and the second program transistors The bit line and the power supply wiring are formed in a first wiring layer on the back side of the first and second program transistors and the first and second switch transistors, and overlap the first and second program transistors and the first and second switch transistors in plan view.

[0012] According to this aspect, in the semiconductor memory device, a nonvolatile memory cell includes first and second program transistors connected in parallel, with gates connected to a first word line, and first and second switch transistors arranged between the first and second program transistors and a bit line, connected in parallel, with gates connected to a second word line. That is, the memory cell is an OTP memory cell. The second program transistor is arranged below the first program transistor, and the second switch transistor is arranged below the first switch transistor. That is, the memory cell is configured using a CFET. Either the bit line or the power supply wiring is formed in a wiring layer on the back side of the first and second program transistors and the first and second switch transistors, and overlaps the first and second program transistors and the first and second switch transistors in a planar view. This allows the bit line or the power supply wiring to have a larger wiring width, thereby reducing wiring resistance. Therefore, when the wiring in the back wiring layer is a bit line, operating speed is improved. Furthermore, if the wiring on the back wiring layer is a power supply wiring, a drop in the power supply voltage when the OTP memory is diverted as a mask ROM is suppressed, thereby improving the operating speed.

[0013] According to the present disclosure, it is possible to provide a layout structure for an OTP memory using a CFET that can suppress an increase in manufacturing costs and a decrease in operating speed.

[0014] 3 and 4 are cross-sectional views of the layout structures of FIGS. 3 and 4; plan views showing another example of the layout structure of the lower part of the memory cell according to the first embodiment; (a) and (b) are plan views showing an example of the layout structure of the inverter cell using CFET; (a) and (b) are circuit diagrams of a mask ROM cell converted from an OTP memory cell; 1A and 1B are circuit diagrams of a memory cell in a semiconductor memory device according to a third embodiment, where (a) is an OTP memory and (b) is a mask ROM diverted from an OTP memory;

[0015] Hereinafter, embodiments will be described with reference to the drawings.

[0016] In this specification, "VDD" and "VSS" refer to the power supply voltage or the power supply itself. Furthermore, in this specification, expressions such as "same wiring width" that mean the same width, etc., are assumed to include the range of manufacturing variations.

[0017] In this specification, the source and drain regions of a transistor are referred to as the "nodes" of the transistor, as appropriate. For example, one node of a transistor refers to the source or drain of the transistor, and both nodes of a transistor refer to the source and drain of the transistor.

[0018] 1 and 2 are diagrams showing an example of the configuration of a semiconductor memory device including nonvolatile memory cells according to a first embodiment, with FIG. 1 being a configuration diagram of a memory cell array and FIGS. 2(a) and 2(b) being circuit diagrams of the memory cells. As shown in FIG. 1, each memory cell 1 (MC1 to MC8) is connected to a corresponding first word line WLP (denoted as WLPi (i is an integer) where appropriate), second word line WLR (denoted as WLRi (i is an integer) where appropriate), and bit line BL (denoted as BLi (i is an integer) where appropriate). In addition to the memory cell array, the semiconductor memory device also includes peripheral circuits such as a write circuit and a read circuit, but these are not shown here. In addition, in FIG. 1, for the sake of simplicity, the memory cell array is shown to consist of (4×2) memory cells 1, but the number of memory cells 1 is not limited to this in the X direction (in this embodiment, the direction in which the first and second word lines WLP, WLR extend) and the Y direction (in this embodiment, the direction in which the bit line BL extends).

[0019] In this embodiment, the memory cell 1 is a gate oxide breakdown type OTP (One Time Programmable) memory cell. The circuit diagrams in Figures 2(a) and 2(b) have the same basic configuration, but differ in the pattern of conversion to a mask ROM, as will be described later.

[0020] As shown in FIGS. 2A and 2B, memory cell 1 includes N-conductivity type (abbreviated as "N-type" where appropriate) transistors TP and TS connected in series. Transistor TP is a program element, and its gate is connected to a first word line WLP. The program element stores a value of "1" or "0" depending on the destruction or non-destruction state of its gate oxide film. Transistor TS is a switch element, and its gate is connected to a second word line WLR. The switch element controls access to the program element from bit line BL. Here, the switch element and program element are configured, for example, by transistors having gate oxide thicknesses comparable to those of so-called core transistors in the internal circuitry of a semiconductor integrated circuit.

[0021] In addition, the memory cell 1 includes dummy transistors TD1 and TD2 of P conductivity type (abbreviated as "P type" where appropriate) connected in series. The gate of the dummy transistor TD1 is connected to a first word line WLP. The gate of the dummy transistor TD2 is connected to a second word line WLR. In FIG. 2(a), the nodes of the transistor TP and the dummy transistor TD1 on the opposite side of the bit line BL are connected to each other. In FIG. 2(b), the nodes of the transistor TP and the dummy transistor TD1 on the side of the bit line BL are connected to each other.

[0022] Here, a dummy transistor refers to a transistor that does not contribute to the operation of a memory cell.

[0023] The write operation of the memory cell 1 is performed as follows: A high voltage VPP, which serves as the write voltage, is applied to the desired first word line WLP. The high voltage VPP is a voltage greater than the breakdown voltage of the gate oxide film of the program element, e.g., 3V. Then, a voltage VPR is applied to the second word line WLR. The voltage VPR is a voltage lower than the breakdown voltage of the gate oxide film of the switch element, and the voltage (VPP-VPR) is also lower than the breakdown voltage of the gate oxide film of the switch element, e.g., 1V. Then, 0V is applied to the bit line BL connected to the memory cell 1 whose gate oxide film is to be destroyed, and the voltage VPR is applied to the bit line BL connected to the memory cell 1 whose gate oxide film is not to be destroyed. As a result, the switch element of the memory cell 3 whose bit line BL is applied with 0V becomes conductive, and the gate oxide film of the program element is destroyed by the application of the high voltage VPP.

[0024] The read operation of the memory cell 1 is performed as follows. The bit line BL is precharged to, for example, 0 V. A voltage VRR lower than the high voltage VPP is applied to the desired first and second word lines WLP and WLR. The voltage VRR is a voltage that does not destroy the gate oxide film of the program element, for example, 1 V. If the gate oxide film of the program element is destroyed, current flows from the first word line WLP to the bit line BL via the gate of the program element, and the potential of the bit line BL rises. On the other hand, if the gate oxide film of the program element is not destroyed, the potential of the bit line BL does not change. This potential difference allows the state of the memory cell 1, i.e., the value "0" or "1," to be read.

[0025] (Layout Structure) Figures 3 and 4 are plan views showing examples of the layout structure of a memory cell according to the first embodiment. Figure 3 shows the lower part, i.e., a portion including a P-type nanosheet FET (lower transistor) formed on the side closer to the substrate, and the BM0 wiring layer, which is the wiring layer on the back side thereof. Figure 4 shows the upper part, i.e., a portion including an N-type nanosheet FET (upper transistor) formed on the side farther from the substrate, and the M1 wiring layer, which is the wiring layer on the front side thereof. Figure 5 is a cross-sectional view of the memory cell in the vertical direction in a plan view, showing the cross section taken along line Y1-Y1' in Figures 3 and 4.

[0026] Here, the front side of the nanosheet FET refers to the side on which local wiring, metal wiring, etc. connected to the nanosheet FET are laminated, and the back side of the nanosheet FET refers to the side opposite to the side on which local wiring, metal wiring, etc. connected to the nanosheet FET are laminated.

[0027] In the following description, in plan views such as Figure 3, the horizontal direction of the drawing is the X direction (corresponding to the first direction), the vertical direction of the drawing is the Y direction (corresponding to the second direction), and the direction perpendicular to the substrate surface is the Z direction (corresponding to the depth direction). Note that the X direction is the direction in which the gate wiring and word lines extend, and the Y direction is the direction in which the nanowires and bit lines extend.

[0028] 3 and 4 correspond to a layout for (4×2) bits. Dashed lines indicate the frame of a memory cell for one bit. That is, FIGS. 3 and 4 show a configuration in which four memory cells are arranged in the X direction and two in the Y direction. In the Y direction, the memory cells are arranged inverted in the Y direction in every other column. In FIGS. 3 and 4, the two memory cells from the left in the top row of the drawings correspond to memory cells MC1 and MC2 in the circuit diagram of FIG. 1, and the two memory cells from the left in the bottom row of the drawings correspond to memory cells MC5 and MC6 in the circuit diagram of FIG. 1. Hereinafter, the structure of the memory cells will be mainly explained using memory cells MC1 and MC5 as an example.

[0029] Each memory cell has the circuit configuration shown in Fig. 2(a). The lower P-type nanosheet FET serves as dummy transistors TD1 and TD2, and the upper N-type nanosheet FET serves as a program transistor TP and a switch transistor TS.

[0030] 3, power supply wirings 11, 12, 13, and 14 are provided in the BM0 wiring layer, extending in parallel in the Y direction. The power supply wirings 11, 12, 13, and 14 supply VDD.

[0031] An active region 2P1 constituting the channel, source, and drain of the P-type nanosheet FET is formed above the power supply wiring 11. The active region 2P1 overlaps the power supply wiring 11 in plan view. The active region 2P1 includes nanosheets 21a, 21b, 21c, and 21d that become the channel of the P-type nanosheet FET, and portions 22a, 22b, 22c, 22d, and 22e that become the source or drain of the P-type nanosheet FET.

[0032] Local wirings 41a, 41b, 41c, 41d, and 41e are formed extending in the X direction. The local wirings 41a, 41b, 41c, 41d, and 41e are in contact with the portions 22a, 22b, 22c, 22d, and 22e in the active region 2P1, respectively.

[0033] 4, bit lines 61, 62, 63, and 64 are formed in the M1 wiring layer, extending in parallel in the Y direction. The bit lines 61, 62, 63, and 64 correspond to the bit lines BL0, BL1, BL2, and BL3, respectively. The bit lines 61, 62, 63, and 64 overlap the power supply lines 11, 12, 13, and 14, respectively, in a plan view.

[0034] An active region 2N1 constituting the channel, source, and drain of the N-type nanosheet FET is formed below the bit line 61. The active region 2N1 overlaps with the bit line 61 in a plan view. The active region 2N1 includes nanosheets 23a, 23b, 23c, and 23d that become the channel of the N-type nanosheet FET, and portions 24a, 24b, 24c, 24d, and 24e that become the source or drain of the N-type nanosheet FET.

[0035] Local wirings 42a, 42b, 42c, 42d, and 42e are formed extending in the X direction. The local wirings 42a, 42b, 42c, 42d, and 42e are in contact with the portions 24a, 24b, 24c, 24d, and 24e in the active region 2N1, respectively.

[0036] In the memory cell MC1, the nanosheet 21a forms the channel of the dummy transistor TD1, and the nanosheet 21b forms the channel of the dummy transistor TD2. In the memory cell MC1, the nanosheet 23a forms the channel of the program transistor TP, and the nanosheet 23b forms the channel portion of the switch transistor TS.

[0037] In the memory cell MC5, the nanosheet 21d forms the channel of the dummy transistor TD1, and the nanosheet 21c forms the channel of the dummy transistor TD2. In the memory cell MC5, the nanosheet 23d forms the channel of the program transistor TP, and the nanosheet 23c forms the channel of the switch transistor TS.

[0038] The gate wirings 31, 32, 33, and 34 extend in parallel in the X direction and in the Z direction from bottom to top. The gate wiring 31 surrounds the outer peripheries of the nanosheets 21a and 23a in the X and Z directions via a gate insulating film (not shown). The gate wiring 32 surrounds the outer peripheries of the nanosheets 21b and 23b in the X and Z directions via a gate insulating film (not shown). The gate wiring 33 surrounds the outer peripheries of the nanosheets 21c and 23c in the X and Z directions via a gate insulating film (not shown). The gate wiring 34 surrounds the outer peripheries of the nanosheets 21d and 23d in the X and Z directions via a gate insulating film (not shown). The gate wirings 31, 32, 33, and 34 correspond to word lines WLP0, WLR0, WLR1, and WLP1, respectively.

[0039] The local wirings 41a and 41e are connected to the active region 2N1 through vias. The local wiring 42c is connected to the bit line 61 through a via.

[0040] Fig. 6 shows the layout structure of the lower part when each memory cell has the circuit configuration of Fig. 2(b). The layout structure of the upper part is the same as Fig. 4. In Fig. 6, local wirings 41b and 41d are connected to the active region 2N1 through vias. The rest of the configuration is the same as Fig. 3.

[0041] In this embodiment, a P-type nanosheet FET is formed in the lower part, and an N-type nanosheet FET is formed in the upper part. Only the upper N-type nanosheet FET is used as the transistors TP and TS of the OTP memory cell. The lower P-type nanosheet FET becomes dummy transistors TD1 and TD2.

[0042] 7A and 7B show examples of the layout structure of an inverter cell using a CFET. The lower transistor shown in Fig. 7A is a P-type, and the upper transistor shown in Fig. 7B is an N-type. The inverter cell is an example of a logic cell.

[0043] 7, a power supply wiring 611 extending in the X direction is formed in the BM0 wiring layer. The power supply wiring 611 supplies VDD. A power supply wiring 612 extending in the X direction is formed in the M1 wiring layer. The power supply wiring 612 supplies VSS.

[0044] An active region 6P1 that constitutes the channel, source, and drain of the P-type nanosheet FET is formed at the bottom. The active region 6P1 includes a nanosheet 621 that serves as the channel of the P-type nanosheet FET and portions 622 and 623 that serve as nodes of the P-type nanosheet FET. An active region 6N1 that constitutes the channel, source, and drain of the N-type nanosheet FET is formed at the top. The active region 6N1 includes a nanosheet 624 that serves as the channel of the N-type nanosheet FET and portions 625 and 626 that serve as nodes of the N-type nanosheet FET. The active regions 6P1 and 6N1 overlap with the power supply wiring 611 and 612 in a planar view.

[0045] The gate wiring 631 extends in the Y direction and also extends in the Z direction from bottom to top. The gate wiring 631 surrounds the outer peripheries of the nanosheets 621 and 624 in the Y and Z directions via a gate insulating film (not shown).

[0046] The local wirings 651a and 651b extend in the Y direction and are connected to portions 622 and 623 of the active region 6P1, respectively. The local wirings 652a and 652b extend in the Y direction and are connected to portions 625 and 626 of the active region 6N1, respectively.

[0047] A portion 622 of the active region 6P1 is connected to the power supply wiring 611 through a via. A portion 625 of the active region 6N1 is connected to the power supply wiring 612 through a via and a local wiring 652a. The local wiring 651b and the local wiring 652b are connected to each other through a via.

[0048] An M1 wiring 661 serving as the input of the inverter is connected to the gate wiring 631. An M1 wiring 662 serving as the output of the inverter is connected to a local wiring 652b through a via.

[0049] Therefore, in this embodiment, the conductivity types of the upper and lower transistors are the same in the OTP memory cell and the logic cell, so there is no need to use different manufacturing methods for the OTP region and the logic cell region, which makes it possible to suppress increases in manufacturing costs.

[0050] (Conversion to Mask ROM) The OTP memory of FIG. 2 can be easily converted to a mask ROM cell. FIG. 8(a) shows the OTP memory of FIG. 2(a) converted to a mask ROM, and FIG. 8(b) is a circuit diagram of the OTP memory of FIG. 2(b) converted to a mask ROM. In the mask ROM cell shown in FIG. 8, the stored value is determined by whether or not the point where the nodes of the transistor TP and the dummy transistor TD1 are connected to each other is connected to the power supply VDD (point "D" in FIG. 8). The presence or absence of the connection is achieved, for example, by the presence or absence of a contact.

[0051] Data is read from the mask ROM cell shown in Figure 8 as follows: The bit line BL is precharged to a low level, and in this state, the word lines WLP and WLR are both set to a high level. When the node of the transistor TP is connected to the power supply VDD, the bit line BL changes to a high level. On the other hand, when the node of the transistor TP is not connected to the power supply VDD, the bit line BL remains at a low level. The state of the mask ROM cell, i.e., the value "0" or "1", is read out depending on the potential difference of the bit line BL.

[0052] FIG. 9 is a plan view showing an example of the layout structure of a mask ROM cell converted from an OTP memory cell, showing the configuration of the lower part. FIG. 9 corresponds to the circuit configuration of FIG. 8(a). The configuration of the upper part is the same as that of FIG. 4. In FIG. 9, the configuration other than the contacts that define the storage value is the same as that of FIG. 3. In each figure showing a mask ROM, the contacts that define the storage value are marked with the letter "D."

[0053] The presence or absence of contacts 51 and 52 determines the storage value of the mask ROM cell.

[0054] When formed, the contact 51 connects the portion 22a of the active region 2P1 to the power supply wiring 11. The portion 22a serves as the node of the lower dummy transistor TD1, and is connected to the portion 24a of the active region 2N1 through the local wiring 41a and a via. The portion 24a serves as the source of the upper transistor TP. In other words, the presence or absence of the contact 51 determines whether the source of the upper transistor TP is connected to VDD.

[0055] When formed, the contact 52 connects the portion 22e of the active region 2P1 to the power supply wiring 11. The portion 22e serves as the node of the lower dummy transistor TD1, and is connected to the portion 24e of the active region 2N1 through the local wiring 41e and a via. The portion 24e serves as the source of the upper transistor TP. In other words, the presence or absence of the contact 52 determines whether the source of the upper transistor TP is connected to VDD.

[0056] FIG. 10 is a plan view showing an example of the layout structure of a mask ROM cell converted from an OTP memory cell, showing the configuration of the lower part. FIG. 10 corresponds to the circuit configuration of FIG. 8(b). The configuration of the upper part is the same as that of FIG. 4. In FIG. 10, the configuration other than the contact that defines the storage value is the same as that of FIG. 3.

[0057] The presence or absence of contacts 53 and 54 determines the storage value of the mask ROM cell.

[0058] When formed, the contact 53 connects the portion 22b of the active region 2P1 to the power supply wiring 11. The portion 22b serves as the node of the lower dummy transistor TD1, and is connected to the portion 24b of the active region 2N1 through the local wiring 41b and a via. The portion 24b serves as the drain of the upper transistor TP. In other words, the presence or absence of the contact 53 determines whether the drain of the upper transistor TP is connected to VDD.

[0059] When formed, the contact 54 connects the portion 22d of the active region 2P1 to the power supply wiring 11. The portion 22d serves as the node of the lower dummy transistor TD1, and is connected to the portion 24d of the active region 2N1 through the local wiring 41d and a via. The portion 24d serves as the drain of the upper transistor TP. In other words, the presence or absence of the contact 54 determines whether the drain of the upper transistor TP is connected to VDD.

[0060] 9 and 10, the power supply wiring 11 overlaps with the active regions 2N1 and 2P1 in plan view. This allows the wiring width of the power supply wiring to be increased. This reduces the wiring resistance of the power supply wiring, suppressing power supply voltage drops and improving the operating speed of the mask ROM.

[0061] Furthermore, in the manufacturing process of a semiconductor memory device, the formation of wiring in the back wiring layer is performed after the formation of wiring in the surface wiring layer. Therefore, in this embodiment, the contacts 51, 52, 53, and 54 for setting the memory value of the memory cell can be formed in a later process. This shortens the manufacturing time for changing the memory value of the memory cell.

[0062] That is, in the method for manufacturing a semiconductor memory device according to the present disclosure, for example, a step of forming word lines, bit lines, and a plurality of nanosheet FETs on a semiconductor substrate is performed, and after this step, contacts are formed on the back side of the plurality of nanosheet FETs to connect the sources of the nanosheet FETs to power wiring according to the data to be stored, and then power wiring is formed on the wiring layer on the back side.

[0063] In the OTP memory cell according to this embodiment, power supply wirings 11, 12, 13, and 14 for supplying VDD are provided to facilitate conversion to a mask ROM cell. However, if conversion to a mask ROM cell is not taken into consideration, the power supply wirings for supplying VDD may be omitted.

[0064] In addition, in this embodiment, the power supply wirings 11, 12, 13, and 14 are formed for each bit string, but for example, the power supply wirings may be formed integrally for a plurality of bit strings.

[0065] In the above-mentioned example of conversion to a mask ROM, the storage value is determined by the presence or absence of contact between the lower active region and the power supply wiring of the BM0 wiring layer. Alternatively, for example, in an OTP memory, the lower active region and the power supply wiring of the BM0 wiring layer may be connected in advance, and the storage value may be determined by the presence or absence of connection between the nodes of the upper and lower transistors.

[0066] 11A and 11B are circuit diagrams of memory cells in a semiconductor memory device according to a second embodiment, where (a) is an OTP memory and (b) is a mask ROM converted from an OTP memory. The configuration of the memory cell array in this embodiment is the same as that of the memory cell array according to the first embodiment shown in FIG.

[0067] 11 , in this embodiment, the program element and the switch element each include two transistors. That is, the program element includes N-type transistors TP1 and TP2 connected in parallel, and the switch element includes N-type transistors TS1 and TS2 connected in parallel. The gates of transistors TP1 and TP2 are connected to a first word line WLP, and the gates of transistors TS1 and TS2 are connected to a second word line WLR.

[0068] The program element having two transistors TP1 and TP2 offers the following advantages. Even if one of the transistors is not fully written, i.e., the gate oxide film is not fully destroyed, the other transistor can change the potential of the bit line BL, allowing the stored data to be read correctly. Furthermore, the drive capability of the transistors is greater than that of the first embodiment, allowing for faster read operations.

[0069] Additionally, the OTP memory cell includes series-connected P-type dummy transistors TD11 and TD12 and series-connected P-type dummy transistors TD21 and TD22. The gates of the dummy transistors TD11 and TD21 are connected to a first word line WLP. The gates of the dummy transistors TD12 and TD22 are connected to a second word line WLR. The transistor TP1 and the dummy transistor TD11 are connected at nodes opposite to the bit line BL, and the transistor TP2 and the dummy transistor TD21 are connected at nodes opposite to the bit line BL.

[0070] 12 and 13 are plan views showing an example of the layout structure of an OTP memory cell according to the second embodiment, with FIG. 12 showing the lower part and FIG. 13 showing the upper part.

[0071] The layout structures in Figures 12 and 13 are basically the same as those in Figures 3 and 4. However, two memory cells aligned in the Y direction in Figures 3 and 4 are combined into a single memory cell. For example, memory cells MC1 and MC5 in Figures 3 and 4 are combined into a single memory cell MC21 in Figures 12 and 13. In Figures 12 and 13, word lines WLP0 and WLP1 in Figures 3 and 4 are replaced by word line WLP0 to which a common signal is supplied, and word lines WLR0 and WLR1 in Figures 3 and 4 are replaced by word line WLR0 to which a common signal is supplied.

[0072] Each memory cell has the circuit configuration shown in Fig. 11(a) , in which the lower P-type nanosheet serves as dummy transistors TD11, TD12, TD21, and TD22, and the upper N-type nanosheet serves as program transistors TP1 and TP2 and switch transistors TS1 and TS2.

[0073] The following description of the memory cell structure will be made mainly using memory cell MC21 as an example. Note that detailed description of configurations that can be easily inferred from the layout structures of FIGS. 3 and 4 may be omitted.

[0074] 12, power supply wirings 111, 112, 113, and 114 extending in the Y direction are formed in the BM0 wiring layer. The power supply wirings 111, 112, 113, and 114 supply VDD.

[0075] An active region 2P2 constituting the channel, source, and drain of the P-type nanosheet FET is formed above the power supply wiring 111. The active region 2P2 overlaps with the power supply wiring 111 in a planar view. The active region 2P2 includes nanosheets 121a, 121b, 121c, and 121d that become the channel of the P-type nanosheet FET, and portions 122a, 122b, 122c, 122d, and 122e that become the source or drain of the P-type nanosheet FET.

[0076] Local interconnections 141a, 141b, 141c, 141d, and 141e are formed extending in the X direction. The local interconnections 141a, 141b, 141c, 141d, and 141e are in contact with the portions 122a, 122b, 122c, 122d, and 122e in the active region 2P2, respectively.

[0077] 13, bit lines 161, 162, 163, and 164 are formed in the M1 wiring layer, extending in parallel in the Y direction. The bit lines 161, 162, 163, and 164 correspond to the bit lines BL0, BL1, BL2, and BL3, respectively. The bit lines 161, 162, 163, and 164 overlap the power supply lines 111, 112, 113, and 114, respectively, in a plan view.

[0078] An active region 2N2 constituting the channel, source, and drain of the N-type nanosheet FET is formed below the bit line 161. The active region 2N2 overlaps with the bit line 161 in a plan view. The active region 2N2 includes nanosheets 123a, 123b, 123c, and 123d that become the channel of the N-type nanosheet FET, and portions 124a, 124b, 124c, 124d, and 124e that become the source or drain of the N-type nanosheet FET.

[0079] Local interconnections 142a, 142b, 142c, 142d, and 142e are formed extending in the X direction. The local interconnections 142a, 142b, 142c, 142d, and 142e are in contact with the portions 124a, 124b, 124c, 124d, and 124e in the active region 2N2, respectively.

[0080] In memory cell MC21, nanosheet 121a forms the channel of dummy transistor TD11, nanosheet 121b forms the channel of dummy transistor TD12, nanosheet 121c forms the channel of dummy transistor TD22, and nanosheet 121d forms the channel of dummy transistor TD21. Also in memory cell MC21, nanosheet 123a forms the channel of program transistor TP1, nanosheet 123b forms the channel of switch transistor TS1, nanosheet 123c forms the channel of switch transistor TS2, and nanosheet 123d forms the channel of program transistor TP2.

[0081] The gate wirings 131, 132, 133, and 134 extend in parallel in the X direction and in the Z direction from bottom to top. The gate wiring 131 surrounds the outer peripheries of the nanosheets 121a and 123a in the X and Z directions via a gate insulating film (not shown). The gate wiring 132 surrounds the outer peripheries of the nanosheets 121b and 123b in the X and Z directions via a gate insulating film (not shown). The gate wiring 133 surrounds the outer peripheries of the nanosheets 121c and 123c in the X and Z directions via a gate insulating film (not shown). The gate wiring 134 surrounds the outer peripheries of the nanosheets 121d and 123d in the X and Z directions via a gate insulating film (not shown). The gate wirings 131, 132, 133, and 134 correspond to word lines WLP0, WLR0, WLR0, and WLP0, respectively.

[0082] The local wirings 141a and 141e are connected to the active region 2N2 through vias. The local wiring 142c is connected to the bit line 161 through a via.

[0083] (Repurposed into Mask ROM) Figure 14 is a plan view showing an example of the layout structure of a Mask ROM cell diverted from an OTP memory cell, showing the configuration of the lower part. The configuration of the upper part is the same as that of Figure 13. In Figure 14, the configuration other than the contacts that define the storage value is the same as that of Figure 12. The configuration of each memory cell corresponds to the circuit configuration of Figure 11(b).

[0084] The presence or absence of contacts 151 and 152 determines the storage value of the mask ROM cell.

[0085] When formed, the contact 151 connects the portion 122a of the active region 2P2 to the power supply wiring 111. The portion 122a serves as the node of the lower dummy transistor TD11, and is connected to the portion 124a of the active region 2N2 via the local wiring 141a and a via. The portion 124a serves as the source of the upper transistor TP1. In other words, the presence or absence of the contact 151 determines whether the source of the upper transistor TP1 is connected to VDD.

[0086] When formed, the contact 152 connects the portion 122e of the active region 2P2 to the power supply wiring 111. The portion 122e serves as the node of the lower dummy transistor TD21, and is connected to the portion 124e of the active region 2N2 via the local wiring 141e and a via. The portion 124e serves as the source of the upper transistor TP2. In other words, the presence or absence of the contact 152 determines whether the source of the upper transistor TP2 is connected to VDD.

[0087] 2B, the transistor TP1 and the dummy transistor TD11 may be connected at their nodes on the bit line BL side, and the transistor TP2 and the dummy transistor TD21 may be connected at their nodes on the bit line BL side. The layout structure of this configuration can be achieved by changing the positions of the contacts in FIG. 12 to the positions of the local wirings 141b and 141d, similar to FIG. 6.

[0088] According to this embodiment, the conductivity types of the upper and lower transistors are the same in the OTP memory cell and the logic cell, so there is no need to use different manufacturing methods for the OTP region and the logic cell region, which can prevent an increase in manufacturing costs.

[0089] Furthermore, the power supply wiring 111 overlaps with the active regions 2N2 and 2P2 in plan view, which allows the wiring width to be increased. This reduces the wiring resistance, so when the OTP memory is used as a mask ROM, the power supply voltage drop is suppressed and the operating speed can be improved.

[0090] Furthermore, in the manufacturing process of a semiconductor memory device, the formation of wiring in the back wiring layer is performed after the formation of wiring in the surface wiring layer. Therefore, in this embodiment, the contacts 151 and 152 for setting the memory value of the memory cell can be formed in a later process. This shortens the manufacturing time for changing the memory value of the memory cell.

[0091] In the OTP memory cell according to this embodiment, power supply wirings 111, 112, 113, and 114 for supplying VDD are provided to facilitate conversion to a mask ROM cell. However, if conversion to a mask ROM cell is not taken into consideration, the power supply wirings for supplying VDD may be omitted.

[0092] Furthermore, in this embodiment, the power supply wirings 111, 112, 113, and 114 are formed for each bit string, but for example, the power supply wirings may be formed integrally for a plurality of bit strings.

[0093] 15A and 15B are circuit diagrams of memory cells in a semiconductor memory device according to a third embodiment, where (a) is an OTP memory and (b) is a mask ROM converted from an OTP memory. The configuration of the memory cell array in this embodiment is the same as that of the memory cell array according to the first embodiment shown in FIG.

[0094] 15, in this embodiment, as in the second embodiment, the switch element and program element each comprise two transistors. That is, the switch element comprises N-type transistors TP1 and TP2 connected in parallel, and the program element comprises N-type transistors TS1 and TS2 connected in parallel. The gates of transistors TP1 and TP2 are connected to a first word line WLP, and the gates of transistors TS1 and TS2 are connected to a second word line WLR. However, in this embodiment, the memory cell does not comprise a dummy transistor.

[0095] 16 and 17 are plan views showing an example of the layout structure of the OTP memory cell according to the third embodiment, with FIG. 16 showing the lower part and FIG. 17 showing the upper part. The layout structures in FIG. 16 and FIG. 17 are similar to those in FIG. 3 and FIG. 4. However, in both the lower part and the upper part, an N-type nanosheet FET is formed.

[0096] 16, power supply wirings 211, 212, 213, and 214 are formed in the BM0 wiring layer so as to extend in parallel in the Y direction. The power supply wirings 211, 212, 213, and 214 supply VDD.

[0097] An active region 2N3 constituting the channel, source, and drain of the N-type nanosheet FET is formed above the power supply wiring 211. The active region 2N3 overlaps with the power supply wiring 211 in a planar view. The active region 2N3 includes nanosheets 221a, 221b, 221c, and 221d that become the channel of the N-type nanosheet FET, and portions 222a, 222b, 222c, 222d, and 222e that become the source or drain of the N-type nanosheet FET.

[0098] Local interconnections 241a, 241b, 241c, 241d, and 241e are formed extending in the X direction. The local interconnections 241a, 241b, 241c, 241d, and 241e are in contact with portions 222a, 222b, 222c, 222d, and 222e in the active region 2N3, respectively.

[0099] 17, bit lines 261, 262, 263, and 264 are formed in the M1 wiring layer, extending in parallel in the Y direction. The bit lines 261, 262, 263, and 264 correspond to the bit lines BL0, BL1, BL2, and BL3, respectively. The bit lines 261, 262, 263, and 264 overlap the power supply lines 211, 212, 213, and 214, respectively, in a plan view.

[0100] An active region 2N4 that constitutes the channel, source, and drain of the N-type nanosheet FET is formed below the bit line 261. The active region 2N4 overlaps with the bit line 261 in a plan view. The active region 2N4 includes nanosheets 223a, 223b, 223c, and 223d that become the channel of the N-type nanosheet FET, and portions 224a, 224b, 224c, 224d, and 224e that become the source or drain of the N-type nanosheet FET.

[0101] Local interconnections 242a, 242b, 242c, 242d, and 242e are formed extending in the X direction. The local interconnections 242a, 242b, 242c, 242d, and 242e are in contact with portions 224a, 224b, 224c, 224d, and 224e in the active region 2N4, respectively.

[0102] In the memory cell MC1, the nanosheet 221a forms the channel of the program transistor TP1, and the nanosheet 221b forms the channel of the switch transistor TS1. In the memory cell MC1, the nanosheet 223a forms the channel of the program transistor TP2, and the nanosheet 223b forms the channel of the switch transistor TS2.

[0103] In the memory cell MC5, the nanosheet 221d forms the channel of the program transistor TP1, and the nanosheet 221c forms the channel of the switch transistor TS1. In the memory cell MC5, the nanosheet 223d forms the channel of the program transistor TP2, and the nanosheet 223c forms the channel of the switch transistor TS2.

[0104] The gate wirings 231, 232, 233, and 234 extend in parallel in the X direction and in the Z direction from bottom to top. The gate wiring 231 surrounds the outer peripheries of the nanosheets 221a and 223a in the X and Z directions via a gate insulating film (not shown). The gate wiring 232 surrounds the outer peripheries of the nanosheets 221b and 223b in the X and Z directions via a gate insulating film (not shown). The gate wiring 233 surrounds the outer peripheries of the nanosheets 221c and 223c in the X and Z directions via a gate insulating film (not shown). The gate wiring 234 surrounds the outer peripheries of the nanosheets 221d and 223d in the X and Z directions via a gate insulating film (not shown). The gate wirings 231, 232, 233, and 234 correspond to word lines WLP0, WLR0, WLR1, and WLP1, respectively.

[0105] The local wirings 241a, 241b, 241c, 241d, and 241e are connected to the active region 2N4 through vias. The local wiring 242c is connected to the bit line 261 through a via.

[0106] (Repurposed into Mask ROM) Fig. 18 is a plan view showing an example of the layout structure of a Mask ROM cell diverted from an OTP memory cell, showing the configuration of the lower part. Fig. 18 corresponds to the circuit configuration of Fig. 15(b). The configuration of the upper part is the same as Fig. 17. In Fig. 18, the configuration other than the contact that defines the storage value is the same as Fig. 16.

[0107] The presence or absence of contacts 251 and 252 determines the storage value of the mask ROM cell.

[0108] When contact 251 is formed, it connects portion 222a of active region 2N3 to power supply wiring 211. Portion 222a serves as the source of lower program transistor TP1, and is connected to portion 224a of active region 2N4 via local wiring 241a and a via. Portion 224a serves as the source of upper program transistor TP2. In other words, the presence or absence of contact 251 determines whether the sources of program transistors TP1 and TP2 are connected to VDD.

[0109] When formed, contact 252 connects portion 222e of active region 2N3 to power supply wiring 211. Portion 222e serves as the source of lower program transistor TP1, and is connected to portion 224e of active region 2N4 via local wiring 241e and a via. Portion 224e serves as the source of upper program transistor TP2. In other words, the presence or absence of contact 252 determines whether the sources of program transistors TP1 and TP2 are connected to VDD.

[0110] 18, the power supply wiring 211 overlaps with the active regions 2N3 and 2N4 in plan view. This allows the wiring width of the power supply wiring to be increased. This reduces the wiring resistance of the power supply wiring, suppressing power supply voltage drops and improving the operating speed of the mask ROM.

[0111] Furthermore, in the manufacturing process of a semiconductor memory device, the formation of wiring in the back wiring layer is performed after the formation of wiring in the surface wiring layer. Therefore, in this embodiment, the contacts 251 and 252 for setting the memory value of the memory cell can be formed in a later process. This shortens the manufacturing time for changing the memory value of the memory cell.

[0112] In the OTP memory according to this embodiment, power supply wiring 211, 212, 213, and 214 for supplying VDD are provided to facilitate conversion to a mask ROM. However, if conversion to a mask ROM cell is not taken into consideration, the power supply wiring for supplying VDD may be omitted.

[0113] Furthermore, in this embodiment, the power supply wirings 211, 212, 213, and 214 are formed for each bit string, but for example, the power supply wirings may be formed integrally for a plurality of bit strings.

[0114] In this embodiment, contacts for defining the storage value of the mask ROM cell may be provided in the portions 222b and 222d of the active region 2N3, similar to FIG.

[0115] (Modification) Figures 19 and 20 are plan views showing the layout structure of an OTP memory according to a modification of the third embodiment, with Figure 19 showing the bottom and Figure 20 showing the top. This modification corresponds to the third embodiment in which the wiring layers of the bit lines and VDD power supply wiring are swapped. That is, in this modification, the bit lines are arranged in the BM0 wiring layer, and the VDD power supply wiring is arranged in the M1 wiring layer. N-type nanosheet FETs are formed in both the bottom and top. Note that detailed descriptions of the configurations common to Figures 16 and 17 may be omitted here.

[0116] 19, bit lines 215, 216, 217, and 218 extending in parallel in the Y direction are formed in the BM0 wiring layer. The bit lines 215, 216, 217, and 218 correspond to bit lines BL0, BL1, BL2, and BL3, respectively.

[0117] 20, power supply wirings 265, 266, 267, and 268 are formed in the M1 wiring layer, extending in parallel in the Y direction. The power supply wirings 265, 266, 267, and 268 supply VDD. The power supply wirings 265, 266, 267, and 268 overlap with the bit lines 215, 216, 217, and 218, respectively, in a plan view.

[0118] The active region 2N3 overlaps, in plan view, with the bit line 215 and the power supply wiring 265. A portion 222c of the active region 2N3 is connected to the bit line 215 through a via.

[0119] (Repurposed into Mask ROM) Fig. 21 is a plan view showing an example of the layout structure of a mask ROM diverted from an OTP memory, showing the configuration of the upper part. Fig. 21 corresponds to the circuit configuration of Fig. 15(b). The configuration of the lower part is the same as Fig. 19. In Fig. 21, the configuration other than the contacts that define the stored value is the same as Fig. 20.

[0120] The presence or absence of contacts 253 and 254 determines the storage value of the mask ROM cell.

[0121] When contact 253 is formed, it connects local wiring 242a, which is connected to portion 224a of active region 2N4, with power supply wiring 265. Portion 224a serves as the source of upper program transistor TP2, and is connected to portion 222a of active region 2N3 via local wiring 241a and a via. Portion 222a serves as the source of lower program transistor TP1. In other words, the presence or absence of contact 253 determines whether the sources of program transistors TP1 and TP2 are connected to VDD.

[0122] When contact 254 is formed, it connects local interconnect 242e, which is connected to portion 224e of active region 2N4, with power supply interconnect 265. Portion 224e serves as the source of upper program transistor TP2, and is connected to portion 222e of active region 2N3 via local interconnect 241e and a via. Portion 222e serves as the source of lower program transistor TP1. In other words, the presence or absence of contact 254 determines whether the sources of program transistors TP1 and TP2 are connected to VDD.

[0123] 21, the power supply wiring 265 overlaps with the active regions 2N3 and 2N4 in plan view. This allows the wiring width of the power supply wiring to be increased. This reduces the wiring resistance of the power supply wiring, suppressing power supply voltage drops and improving the operating speed of the mask ROM.

[0124] In the OTP memory cell according to this modification, power supply wirings 265, 266, 267, and 268 for supplying VDD are provided to facilitate conversion to a mask ROM cell. However, if conversion to a mask ROM cell is not taken into consideration, the power supply wirings for supplying VDD may be omitted.

[0125] Furthermore, in this modification, the power supply wirings 265, 266, 267, and 268 are formed for each bit string, but for example, the power supply wirings may be formed integrally for a plurality of bit strings.

[0126] In this modification, contacts for defining the storage values ​​of the mask ROM cells may be provided in the local wirings 242b and 242d connected to the portions 224b and 224d of the active region 2N4.

[0127] (Other Examples) In each of the above-described embodiments, the number and cross-sectional shape of the nanosheets in the nanosheet FET are not limited to those shown here. That is, some or all of the nanosheets may have a single sheet structure, or two or more sheets. Furthermore, the cross-sectional shape of the nanosheets may be rectangular, square, circular, elliptical, etc.

[0128] In each of the above-described embodiments, the transistor is a nanosheet FET, but the present invention is not limited to this.

[0129] The present disclosure can suppress increases in manufacturing costs and decreases in operating speed for OTP memories using CFETs, and is therefore useful for reducing the cost and improving the performance of semiconductor chips, for example.

[0130] 1 Memory cell 2P1, 2P2, 2N1, 2N2, 2N3, 2N4 Active area 11, 12, 13, 14 Power supply wiring 21a, 21b, 21c, 21d, 23a, 23b, 23c, 23d Nanosheet 31, 32, 33, 34 Gate wiring (word line) 51, 52, 53, 54 Contact 61, 62, 63, 64 Bit line 111, 112, 113, 114 Power supply wiring 121a, 121b, 121c, 121d, 123a, 123b, 123c, 123d Nanosheet 131, 132, 133, 134 Gate wiring (word line) 151, 152 Contact 161, 162, 163, 164 Bit line 211, 222, 213, 214 Power supply wiring 215, 216, 217, 218 Bit lines 221a, 221b, 221c, 221d, 223a, 223b, 223c, 223d Nanosheets 231, 232, 233, 234 Gate wiring (word line) 251, 252, 253, 254 Contacts 261, 262, 263, 264 Bit lines 265, 266, 267, 268 Power supply wiring MC1 to MC8, MC21 Memory cells WLP, WLR Word lines BL Bit lines TP, TP1, TP2 Program transistors TS, TS1, TS2 Switch transistors TD1, TD2, TD11, TD12, TD21, TD22 Dummy transistors

Claims

1. A semiconductor memory device having non-volatile memory cells, comprising: first and second word lines extending in a first direction; and a bit line extending in a second direction perpendicular to the first direction, wherein the memory cells comprise: a first program transistor of a first conductivity type, the gate of which is connected to the first word line; a first switch transistor of the first conductivity type, which is provided between the first program transistor and the bit line and the gate of which is connected to the second word line; a first dummy transistor of a second conductivity type, which is provided below the first program transistor and overlaps with the first program transistor in a planar view; and a second dummy transistor of the second conductivity type, which is provided below the first switch transistor and overlaps with the first switch transistor in a planar view, wherein either the source or the drain of the first program transistor and the first dummy transistor are connected to each other.

2. A semiconductor memory device according to claim 1, further comprising power supply wiring extending in the second direction, wherein the bit line is formed in a wiring layer on the front side of the first program transistor, the first switch transistor, and the first and second dummy transistors, and the power supply wiring is formed in a wiring layer on the back side of the first program transistor, the first switch transistor, and the first and second dummy transistors.

3. A semiconductor memory device according to claim 2, wherein the power supply wiring and the bit line overlap the first program transistor, the first switch transistor, and the first and second dummy transistors in a plan view.

4. A semiconductor memory device according to claim 1, comprising third and fourth word lines extending in the first direction, the first and fourth word lines being supplied with a common first word line signal, and the second and third word lines being supplied with a common second word line signal, and the memory cells comprising: a second program transistor of the first conductivity type having a gate connected to the fourth word line; a second switch transistor of the first conductivity type provided between the second program transistor and the bit line and having a gate connected to the third word line; a third dummy transistor of the second conductivity type provided below the second program transistor and overlapping with the second program transistor in a planar view; and a fourth dummy transistor of the second conductivity type provided below the second switch transistor and overlapping with the second switch transistor in a planar view, and the second program transistor and the third dummy transistor having either a source or a drain connected to each other.

5. A semiconductor memory device according to claim 4, further comprising power supply wiring extending in the second direction, wherein the bit lines are formed in a wiring layer on the front side of the first and second program transistors, the first and second switch transistors, and the first to fourth dummy transistors, and the power supply wiring is formed in a wiring layer on the back side of the first and second program transistors, the first and second switch transistors, and the first to fourth dummy transistors.

6. A semiconductor memory device according to claim 5, wherein the power supply wiring and the bit line overlap the first and second program transistors, the first and second switch transistors, and the first to fourth dummy transistors in a plan view.

7. A semiconductor memory device having nonvolatile memory cells, comprising: first and second word lines extending in a first direction; a bit line extending in a second direction perpendicular to the first direction; and a power supply wiring extending in the second direction, wherein the memory cells comprise: first and second program transistors of a first conductivity type connected in parallel and having gates connected to the first word line; and first and second switch transistors of the first conductivity type provided between the first and second program transistors and the bit lines, connected in parallel, and having gates connected to the second word line, wherein the second program transistor is provided below the first program transistor and overlaps with the first program transistor in a planar view; and the second switch transistor is provided below the first switch transistor and overlaps with the first switch transistor in a planar view. a semiconductor memory device in which either the bit line or the power supply wiring is formed in a first wiring layer on the back side of the first and second program transistors and the first and second switch transistors, and overlaps with the first and second program transistors and the first and second switch transistors in a planar view; 8. A semiconductor memory device according to claim 7, wherein the bit lines are formed in a wiring layer on the surface side of the first and second program transistors and the first and second switch transistors, and the power supply wiring is formed in the first wiring layer.

9. A semiconductor memory device according to claim 7, wherein the bit lines are formed in the first wiring layer, and the power supply wiring is formed in a wiring layer on the surface side of the first and second program transistors and the first and second switch transistors.

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