Semiconductor device

Abstract

[Problem] To provide a semiconductor device which is capable of maintaining a normal transistor operation even when the thickness of stacked semiconductor substrates is reduced. [Solution] A semiconductor device according to an embodiment comprises: a first semiconductor substrate; a second semiconductor substrate which is stacked on the first semiconductor substrate and has a first surface and a second surface opposite to the first surface, the second semiconductor substrate facing the first semiconductor substrate on one of the first and second surfaces; a third semiconductor substrate which is stacked on the second semiconductor substrate and faces the second semiconductor substrate on the other of the first and second surfaces; a first diffusion layer of a first conductivity-type impurity, the first diffusion layer being provided in the second semiconductor substrate from the first surface to the second surface; a transistor which is provided in the first diffusion layer on the first surface side; a first electrode which is provided in the first diffusion layer on the second surface side and is electrically connected to the first diffusion layer; and a supply wiring line which is provided on the first or third semiconductor substrate and is electrically connected to the first electrode so as to supply a reference voltage or a power supply voltage to the first electrode.

Description

Semiconductor Devices

[0001] The present disclosure relates to semiconductor devices.

[0002] A semiconductor device such as a light-emitting device or an imaging device may have a structure in which three or more semiconductor substrates are stacked. In this case, the intermediate substrates sandwiched between the upper and lower substrates must be thinned to form through-electrodes.

[0003] JP 2020-088380 A JP 2023-120413 A JP 2022-092536 A JP 11-102910 A

[0004] However, thinning the intermediate substrate increases the resistance of the well diffusion layer provided in the intermediate substrate, which increases the likelihood of the snapback or latch-up phenomenon occurring in the transistor provided in the well diffusion layer.

[0005] The present technology has been made in view of such problems, and provides a semiconductor device that can maintain normal operation of transistors even when the thickness of stacked semiconductor substrates is reduced.

[0006] A semiconductor device according to one aspect of the present disclosure includes: a first semiconductor substrate; a second semiconductor substrate stacked on the first semiconductor substrate, having a first surface and a second surface opposite the first surface, and facing the first semiconductor substrate at one of the first and second surfaces; a third semiconductor substrate stacked on the second semiconductor substrate and facing the second semiconductor substrate at the other of the first and second surfaces; a first diffusion layer of a first conductivity type impurity provided in the second semiconductor substrate from the first surface to the second surface; a transistor provided in the first diffusion layer on the first surface side; a first electrode provided in the first diffusion layer on the second surface side and electrically connected to the first diffusion layer; and a supply wiring provided on the first or third semiconductor substrate, electrically connected to the first electrode, and configured to supply a reference voltage or a power supply voltage to the first electrode.

[0007] The first electrode extends from the second surface toward the first surface to the middle of the first diffusion layer.

[0008] The first electrode includes a first silicide layer in contact with the first diffusion layer.

[0009] The semiconductor device further includes a first insulating film provided on a sidewall of a trench or hole provided in the first diffusion layer, and the first electrode includes a first conductive portion provided inside the first insulating film within the trench or hole, and a first silicide layer provided at an end of the first conductive portion on the first surface side and in contact with the first diffusion layer.

[0010] The semiconductor device further includes a through electrode that penetrates the second semiconductor substrate between the first surface and the second surface.

[0011] The semiconductor device further includes an element isolation portion provided on the first surface side of the second semiconductor substrate, and a polysilicon layer provided on or within the element isolation portion, and the through electrode penetrates the second semiconductor substrate and contacts the polysilicon layer.

[0012] The semiconductor device further includes a second insulating film provided on the inner wall of a through hole that penetrates the second semiconductor substrate between the first surface and the second surface, and the through electrode includes a second conductive portion provided inside the second insulating film within the through hole, and a second silicide layer provided at the end of the second conductive portion on the first surface side and in contact with the polysilicon layer.

[0013] The first electrode is disposed directly under the gate or channel of the transistor.

[0014] The first electrode is shorter than the through electrode in the stacking direction of the first to third semiconductor substrates.

[0015] The through electrode has approximately the same length as the first electrode in the stacking direction of the first to third semiconductor substrates.

[0016] The polysilicon layer is provided from the first surface toward the second surface up to the middle of the element isolation portion, and the through electrode penetrates the second semiconductor substrate and contacts the polysilicon layer.

[0017] The first diffusion layer is a well diffusion layer of P-type impurities.

[0018] The first semiconductor substrate faces the second semiconductor substrate at a first surface, and the third semiconductor substrate faces the second semiconductor substrate at a second surface.

[0019] The first semiconductor substrate faces the second semiconductor substrate at the second surface, and the third semiconductor substrate faces the second semiconductor substrate at the first surface.

[0020] In the stacking direction of the first to third semiconductor substrates, the length of the first electrode is approximately half the length of the first diffusion layer, and the diameter of the first electrode in a direction approximately perpendicular to the stacking direction is smaller than the diameter of the through electrode in a direction approximately perpendicular to the stacking direction.

[0021] The aspect ratio of the first electrode is approximately equal to the aspect ratio of the through electrode.

[0022] The semiconductor device further includes an element isolation portion provided on the first surface side of the second semiconductor substrate and a first wiring above the element isolation portion, and the through electrode penetrates the second semiconductor substrate and the element isolation portion and contacts the first wiring.

[0023] The first semiconductor substrate includes a plurality of pixels including photodiodes, and the second and third semiconductor substrates include CMOS circuitry.

[0024] The first conductive portion includes any one of tungsten, copper, and aluminum.

[0025] The first silicide layer contains any of Ti, Zr, Hf, V, Cr, Ta, Co, Fe, Ni, Mo, Pt, W, and Nb.

[0026] 1 is a cross-sectional view showing an example of the configuration of a semiconductor device according to a first embodiment; 2 is a cross-sectional view showing an example of the configuration of a semiconductor device according to a second embodiment; 3 is a cross-sectional view showing an example of the configuration of a semiconductor device according to a third embodiment; 4 is a cross-sectional view showing an example of the configuration of a semiconductor device according to a fourth embodiment; 5 is a cross-sectional view showing an example of the configuration of a semiconductor device according to a fifth embodiment; 6 is a cross-sectional view showing an example of the configuration of a semiconductor device according to a sixth embodiment;

[0027] Hereinafter, specific embodiments to which the present technology is applied will be described in detail with reference to the drawings. The drawings are schematic or conceptual, and the proportions of each part are not necessarily the same as those in reality. In the specification and drawings, elements similar to those described above with reference to the previous drawings are designated by the same reference numerals, and detailed descriptions thereof will be omitted as appropriate.

[0028] 1 is a cross-sectional view showing an example of the configuration of a semiconductor device according to a first embodiment. The semiconductor device 1 of this embodiment may be, for example, an imaging device such as a CMOS (Complementary Metal Oxide Semiconductor) Image Sensor (CIS) or a ToF (Time of Flight) sensor, or a light-emitting device. In the following description, the semiconductor device 1 will be described as a CIS, as an example.

[0029] The semiconductor device 1 includes semiconductor chips CH1, CH2, and CH3 stacked in the Z direction. While the semiconductor chips CH3, CH2, and CH1 are stacked in this order in Fig. 1, the order may be CH1, CH2, and CH3. However, the semiconductor chip CH2 is sandwiched between the semiconductor chip CH1 and the semiconductor chip CH3.

[0030] (Semiconductor Chip CH1) The semiconductor chip CH1 includes a semiconductor substrate SUB1, an element isolation part STI1, a photodiode PD, a color filter CF, a lens LNS, a transistor Tr1, a contact CNT1, a wiring WRG1, and an interlayer insulating film ILD1.

[0031] The semiconductor substrate SUB1 is, for example, a silicon substrate. The semiconductor substrate SUB1 has a front surface F1_1 and a back surface F1_2 opposite to the front surface F1_1.

[0032] The photodiode PD is provided in the semiconductor substrate SUB1, photoelectrically converts light incident from the back surface F1_2, and accumulates electric charges (pixel signals) according to the intensity of the light. That is, the semiconductor device 1 is a back-illuminated CIS.

[0033] The element isolation portions STI1 are provided between the photodiodes PD of the respective pixels, and electrically or optically isolate the photodiodes PD of the respective pixels. The element isolation portions STI1 are made of an insulating material such as a silicon oxide film.

[0034] The color filter CF is provided on the rear surface F1_2 side. The color filter CF transmits light of a specific wavelength of incident light and blocks light of other wavelengths. The color filter CF is made of a colored material such as resin.

[0035] The lens LNS is provided on the rear surface F1_2 side. The lens LNS focuses incident light onto each pixel. The lens LNS is made of a transparent material such as resin.

[0036] The plurality of transistors Tr1 are provided on the front surface F1_1 side of the semiconductor substrate SUB1. The transistors Tr1 constitute a pixel circuit that amplifies a pixel signal from the photodiode PD. The transistors Tr1 are electrically connected to the wiring WRG1 via the contacts CNT1.

[0037] The wiring WRG1 constitutes a multilayer wiring layer provided in the interlayer dielectric film ILD1. The wiring WRG1 is made of a metal such as tungsten, copper, or aluminum. A part of the wiring WRG1 is exposed on the surface of the interlayer dielectric film ILD1 and is directly bonded to a part of the wiring WRG2 of the semiconductor chip CH2.

[0038] (Semiconductor Chip CH2) The semiconductor chip CH2 includes a semiconductor substrate SUB2, an element isolation part STI2, a transistor Tr2, a contact CNT2, a wiring WRG2, an interlayer insulating film ILD2, a first electrode 30, a through electrode 31, and a polysilicon layer Gsti.

[0039] The semiconductor substrate SUB2 is, for example, a silicon substrate. The semiconductor substrate SUB2 has a front surface F1_1 and a back surface F1_2 opposite to the front surface F1_1. The front surface F2_1 of the semiconductor substrate SUB2 faces the semiconductor substrate SUB1 and is stacked on the semiconductor substrate SUB1. That is, the semiconductor substrates SUB1 and SUB2 face each other at their front surfaces F1_1 and F2_1.

[0040] The semiconductor substrate SUB2 is provided with a P-type well diffusion layer 50P containing a P-type impurity (e.g., boron) and an N-type well diffusion layer 50N containing an N-type impurity (e.g., phosphorus, arsenic). Since the semiconductor substrate SUB2 is thinned, the well diffusion layers 50P, 50N are provided throughout the semiconductor substrate SUB2 from the front surface F2_1 to the back surface F2_2 (the entire semiconductor substrate SUB2 in the Z direction).

[0041] The element isolation portion STI2 is provided on the surface F2_1 side of the semiconductor substrate SUB2. The element isolation portion STI2 is provided between the well diffusion layer 50P and the well diffusion layer 50N, or within the well diffusion layers 50P and 50N. The element isolation portion STI2 electrically isolates the well diffusion layer 50P from the well diffusion layer 50N. The element isolation portion STI2 is made of an insulating material such as a silicon oxide film, for example.

[0042] A plurality of transistors Tr2 are provided on the surface F2_1 side of the semiconductor substrate SUB2. The transistors Tr2 have a gate electrode G, a source S, and a drain D. The gate electrode G is made of, for example, doped polysilicon. The transistors Tr2 provided in the P-type well diffusion layer 50P are N-channel transistors and have a source S and a drain D made of an N-type impurity diffusion layer. The transistors Tr2 provided in the N-type well diffusion layer 50N are P-channel transistors and have a source S and a drain D made of a P-type impurity diffusion layer. In this way, the semiconductor chip CH2 is configured as a CMOS circuit including N-channel transistors and P-channel transistors.

[0043] The transistor Tr2 constitutes an ADC (Analog-to-Digital Converter) that performs AD (Analog-to-Digital) conversion on pixel signals from the semiconductor substrate SUB1, or a logic circuit that processes digital signals, etc. The transistor Tr2 is electrically connected to the wiring WRG2 via a contact CNT2.

[0044] The wiring WRG2 constitutes a multilayer wiring layer provided in the interlayer insulating film ILD2. The wiring WRG2 is made of a metal such as tungsten, copper, or aluminum. A part of the wiring WRG2 is exposed on the surface of the interlayer insulating film ILD2 and is directly bonded to a part of the wiring WRG1 of the semiconductor chip CH1.

[0045] The plurality of first electrodes 30 are provided in well diffusion layers 50P and 50N on the rear surface F2_2 side of the semiconductor substrate SUB2. The first electrodes 30 are electrically connected to the well diffusion layers 50P and 50N, respectively. The first electrodes 30 provided in the well diffusion layer 50P and the first electrodes 30 provided in the well diffusion layer 50N are electrically isolated from each other.

[0046] The first electrode 30 extends in the Z direction from the back surface F2_2 toward the front surface F2_1 to partway through the well diffusion layers 50P, 50N. Therefore, the first electrode 30 is shorter in the Z direction (stacking direction of CH1 to CH3) than the through electrode 31. The first electrode 30 may be provided in a trench extending in the Y direction (or X direction) in a plan view seen from the Z direction. When the first electrode 30 is provided in a trench, the first electrode 30 is formed in a plate shape. Alternatively, the first electrode 30 may be provided in a hole that is substantially circular or substantially elliptical in a plan view seen from the Z direction. When the first electrode 30 is provided in a hole, the first electrode 30 is formed in a columnar shape.

[0047] The first electrode 30 includes a metal portion 10 and a silicide layer 20 .

[0048] The metal portion 10 serving as the first conductive portion is the main body of the first electrode 30 extending from the rear surface F2_2 toward the front surface F2_1. The metal portion 10 is provided inside the sidewall insulating film 40 in the trench or hole. The metal portion 10 includes, for example, any one of tungsten, copper, and aluminum.

[0049] The silicide layer 20 is provided at the end of the metal portion 10 on the surface F2_1 side, and is in contact with the well diffusion layer 50P or 50N. The silicide layer 20 is provided to connect the metal portion 10 and the well diffusion layer 50P, 50N with low resistance. The silicide layer 20 is, for example, a compound of silicon and any of Ti, Zr, Hf, V, Cr, Ta, Co, Fe, Ni, Mo, Pt, W, and Nb. The silicide layer 20 is preferably made of a metal material that can be silicided at a lower temperature than the metal portion 10.

[0050] The first electrode 30 is disposed directly below the gate electrode G or channel region of the transistor Tr2 (on the back surface F2_2 side). The multiple first electrodes 30 are electrically connected in common to each of the well diffusion layers 50P and 50N. For example, in the well diffusion layer 50P, the multiple first electrodes 30 are electrically connected by wiring 35. In the well diffusion layer 50P, the multiple first electrodes 30 and the wiring 35 transmit, for example, a ground voltage Vss, and apply the ground voltage Vss to the well diffusion layer 50P. Meanwhile, in the well diffusion layer 50N, the multiple first electrodes 30 are also electrically connected by wiring 35. In the well diffusion layer 50N, the multiple first electrodes 30 and the wiring 35 transmit, for example, a power supply voltage Vdd, and apply the power supply voltage Vdd to the well diffusion layer 50N.

[0051] In this way, by directly connecting the first electrode 30 to the well diffusion layers 50P, 50N on the back surface F2_2 and applying a voltage, it is possible to reduce the resistance of the well diffusion layers 50P, 50N from the channel region of the transistor Tr2 to the first electrode 30. In addition, the first electrode 30 is disposed directly below the transistor Tr2 and is in low-resistance contact with the well diffusion layers 50P, 50N via the silicide layer 20. This makes it possible to suppress a voltage rise in the well diffusion layers 50P, 50N due to substrate current. As a result, it is possible to suppress the snapback phenomenon or latch-up phenomenon of the transistor Tr2.

[0052] The sidewall insulating film 40 is provided on the sidewall of a trench or hole formed in the well diffusion layers 50P, 50N. The sidewall insulating film 40 is provided between the well diffusion layers 50P, 50N and the metal portion 10. The sidewall insulating film 40 is provided to suppress diffusion of the metal material of the metal portion 10 into the well diffusion layers 50P, 50N.

[0053] The through electrode 31 penetrates the semiconductor substrate SUB2 between the back surface F2_2 and the front surface F2_1. The through electrode 31 is provided in the region of the element isolation part STI2 and also penetrates the element isolation part STI2 in the Z direction. The through electrode 31 penetrates the semiconductor substrate SUB2 and the element isolation part STI2 and comes into contact with the polysilicon layer Gsti.

[0054] The through electrode 31 includes a metal portion 11 and a silicide layer 21 .

[0055] The metal portion 11 serving as the second conductive portion is the main body of the second electrode 31 provided in a through-hole penetrating the semiconductor substrate SUB2 between the back surface F2_2 and the front surface F2_1. The metal portion 11 is provided inside the hole and on the inside of the sidewall insulating film 41. The metal portion 11 includes, for example, any one of tungsten, copper, and aluminum.

[0056] The silicide layer 21 as the second silicide layer is provided at the end of the metal portion 11 on the surface F2_1 side and is in contact with the polysilicon layer Gsti. The silicide layer 21 is provided to connect the metal portion 11 and the polysilicon layer Gsti with low resistance. The silicide layer 21 is a compound of silicon and any of Ti, Zr, Hf, V, Cr, Ta, Co, Fe, Ni, Mo, Pt, W, and Nb, for example.

[0057] The through electrode 31 is disposed directly below the polysilicon layer Gsti (on the back surface F2_2 side). The through electrode 31 is electrically connected to the first electrode 30 in common for each of the well diffusion layers 50P and 50N. For example, in the well diffusion layer 50P, the through electrode 31 is electrically connected to the first electrode 30 by a wiring 35. In the well diffusion layer 50P, the through electrode 31 supplies, for example, a reference voltage (ground voltage) Vss to a logic circuit such as an ADC. Meanwhile, in the well diffusion layer 50N, the through electrode 31 is also electrically connected to the first electrode 30 by a wiring 35. In the well diffusion layer 50N, the through electrode 31 supplies, for example, a power supply voltage Vdd to a logic circuit such as an ADC.

[0058] The polysilicon layer Gsti is provided on the element isolation part STI2, in the element isolation part STI2, or on the silicide layer 21. The polysilicon layer Gsti can be formed of the same material in the same process as the gate electrode of the transistor Tr2. The polysilicon layer Gsti functions as an etching stopper for the through hole when the through electrode 31 is formed. The polysilicon layer Gsti is provided to react with a metal material to form the silicide layer 21.

[0059] The sidewall insulating film 41 is provided on the sidewall of the through hole formed in the well diffusion layers 50P, 50N. The sidewall insulating film 41 is provided between the well diffusion layers 50P, 50N or the element isolation part STI2 and the metal part 11. The sidewall insulating film 41 is provided to suppress the diffusion of the metal material of the metal part 11 into the well diffusion layers 50P, 50N.

[0060] (Semiconductor Chip CH3) The semiconductor chip CH3 includes a semiconductor substrate SUB3, an element isolation part STI3, a transistor Tr3, a contact CNT3, a wire WRG3, and an interlayer insulating film ILD3.

[0061] The semiconductor substrate SUB3 is, for example, a silicon substrate. The semiconductor substrate SUB3 has a front surface F3_1 and a back surface F3_2 opposite to the front surface F3_1. The front surface F3_1 of the semiconductor substrate SUB3 faces the back surface F2_2 of the semiconductor substrate SUB2, and is stacked on the semiconductor substrate SUB2. That is, the back surfaces F2_2 and the front surface F3_1 of the semiconductor substrates SUB2 and SUB3 face each other, respectively.

[0062] The element isolation portion STI3 is provided on the front surface F3_1 side of the semiconductor substrate SUB3. The element isolation portion STI3 is provided between the well diffusion layer 51P and the well diffusion layer 51N, or within the well diffusion layers 51P and 51N. The element isolation portion STI3 electrically isolates the well diffusion layer 51P from the well diffusion layer 51N. The element isolation portion STI3 is made of an insulating material such as a silicon oxide film.

[0063] The plurality of transistors Tr3 are provided on the surface F3_1 side of the semiconductor substrate SUB3. The transistors Tr3 provided in the P-type well diffusion layer 51P are N-channel transistors. The transistors Tr3 provided in the N-type well diffusion layer 51N are P-channel transistors. In this way, the semiconductor chip CH3 is configured as a CMOS circuit including N-type transistors and P-type transistors.

[0064] The transistor Tr3 constitutes a signal processing circuit that processes a digital signal from the semiconductor substrate SUB2. The transistor Tr3 is electrically connected to the wiring WRG3 via a contact CNT3.

[0065] The wiring WRG3 as a supply wiring constitutes a multilayer wiring layer provided in the interlayer insulating film ILD3. The wiring WRG3 is made of a metal such as tungsten, copper, or aluminum. A part of the wiring WRG3 is exposed on the surface of the interlayer insulating film ILD3 and is directly bonded to a part of the wiring WRG2 of the semiconductor chip CH2 or to the wiring 35. For example, the semiconductor chips CH2 and CH3 are electrically connected to the wirings WRG2, WRG3, and 35 by so-called Cu-Cu junctions.

[0066] The wiring WRG3 is electrically connected to the first electrode 30 via the wiring 35, and supplies the reference voltage Vss or the power supply voltage Vdd to the first electrode 30. The wiring WRG3 is also electrically connected to the through electrode 31 via the wiring 35, and supplies the reference voltage Vss or the power supply voltage Vdd to the through electrode 31.

[0067] As described above, the semiconductor device 1 according to this embodiment is a CIS having a stacked structure of semiconductor chips CH1 to CH3. Note that the semiconductor device 1 may have a stacked structure of four or more chips. The semiconductor chip CH2 located between the semiconductor chip CH1 and the semiconductor chip CH3 is thinned to reduce electrical resistance and reduce the thickness of the entire device.

[0068] If the first electrode 30 and the wiring 35 were not provided and well contacts (not shown) of the well diffusion layers 50P and 50N were provided on the surface F2_1 side, the well contacts would be farther away from the channel region of the transistor Tr2. In this case, the resistance of the well diffusion layer from the channel region of the transistor Tr2 to the well contacts would make snapback or latch-up more likely to occur. While it is conceivable to arrange the well contacts in multiple locations to prevent such problems, this would increase the layout area and go against the trend toward miniaturization of the semiconductor device 1.

[0069] In contrast, in the semiconductor device 1 according to this embodiment, the first electrode 30 and the wiring 35 are directly connected to the well diffusion layers 50P, 50N on the back surface F2_2 of the semiconductor substrate SUB2 to apply a voltage. The first electrode 30 is disposed directly below the transistor Tr2 and protrudes toward the channel region of the transistor Tr2. Furthermore, the first electrode 30 is connected to the well diffusion layers 50P, 50N with low resistance via the silicide layer 20 at its tip. As a result, when the semiconductor substrate SUB2 is thinned, the first electrode 30 and the wiring 35 are brought even closer to the channel region of the transistor Tr2, efficiently eliminating hot carriers or substrate currents generated near the channel region. As a result, the rise in the electrode potential of the well diffusion layers 50P, 50N can be suppressed, thereby suppressing the snapback or latch-up phenomenon of the transistor Tr2.

[0070] Second Embodiment FIG. 2 is a cross-sectional view showing an example of the configuration of a semiconductor device according to a second embodiment.

[0071] In the second embodiment, the through electrode 31 has approximately the same length in the Z direction as the first electrode 30. Meanwhile, the polysilicon layer Gsti extends from the front surface F2_1 toward the back surface F2_2 of the semiconductor substrate SUB2 to the middle of the element isolation portion STI2. The polysilicon layer Gsti is provided thicker (deeper) than the gate electrode G of the transistor Tr2. Therefore, the through electrode 31 can penetrate the semiconductor substrate SUB2 and come into contact with the polysilicon layer Gsti. This allows a silicide layer 21 to be formed at the tip of the metal portion 11. The through electrode 31 is connected to the polysilicon layer Gsti via the silicide layer 21 and electrically connected to one of the contacts CNT2 via the polysilicon layer Gsti. Therefore, the through electrode 31 of the second embodiment can function in the same manner as that of the first embodiment.

[0072] Since the through electrode 31 has approximately the same length as the first electrode 30 in the Z direction, the through electrode 31 can be formed simultaneously with the first electrode 30 in the same process. This leads to a shortening of the manufacturing process. Furthermore, the aspect ratio of the through electrode 31 is reduced, making its formation easier. On the other hand, since the polysilicon layer Gsti is thicker than the gate electrode G, it is necessary to deeply etch the element isolation part STI2 before depositing the polysilicon. The polysilicon deposition process may be common to the polysilicon layer Gsti and the gate electrode G.

[0073] Other configurations of the second embodiment may be the same as those of the first embodiment, and therefore the second embodiment can achieve the same effects as the first embodiment.

[0074] Third Embodiment FIG. 3 is a cross-sectional view showing an example of the configuration of a semiconductor device according to a third embodiment.

[0075] In the third embodiment, the first electrode 30 is provided only in the P-type well diffusion layer 50 P, and is not provided in the N-type well diffusion layer 50 N. The other configurations of the third embodiment may be similar to those of the first embodiment.

[0076] The snapback or latch-up phenomenon of the transistor Tr2 is likely to occur mainly in the N-channel transistor Tr2 in the P-type well diffusion layer 50P. Therefore, even if the first electrode 30 is provided only in the N-channel transistor Tr2 in the P-type well diffusion layer 50P, the effect of this embodiment can be sufficiently obtained.

[0077] The third embodiment may be combined with the second embodiment, thereby making it possible to obtain the same effects as those of the second embodiment.

[0078] Fourth Embodiment FIG. 4 is a cross-sectional view showing an example of the configuration of a semiconductor device according to a fourth embodiment.

[0079] In the fourth embodiment, the upside down in the Z direction of the semiconductor chip CH2 is reversed from that of the third embodiment. Therefore, the semiconductor substrate SUB1 faces the semiconductor substrate SUB2 at the back surface F2_2 of the semiconductor substrate SUB2. The semiconductor substrate SUB3 faces the semiconductor substrate SUB2 at the front surface F2_1 of the semiconductor substrate SUB2. Therefore, the wiring 35 and the first electrode 30 of the semiconductor substrate SUB2 are provided on the semiconductor chip CH1 side and are joined to a part of the wiring WRG1 of the semiconductor chip CH1. Therefore, the wiring 35 and the first electrode 30 are supplied with the reference voltage (ground voltage) Vss from the semiconductor chip CH1.

[0080] Other configurations of the fourth embodiment may be similar to those of the third embodiment. Therefore, the fourth embodiment can achieve the same effects as the third embodiment. Furthermore, the fourth embodiment may be combined with the first or second embodiment. In this case, the fourth embodiment can achieve the same effects as the first or second embodiment.

[0081] In the fourth embodiment and other embodiments, even if the semiconductor chip CH3 is inverted upside down in the Z direction, the effects of this embodiment can be obtained as long as the semiconductor chip CH2 can be supplied with the reference voltage (ground voltage) Vss and the power supply voltage Vdd. Furthermore, the semiconductor chip CH1 may be a front-illuminated CIS.

[0082] Fifth Embodiment FIG. 5 is a cross-sectional view showing an example of the configuration of a semiconductor device according to a fifth embodiment.

[0083] In the fifth embodiment, the length (height) H30 of the first electrode 30 in the Z direction is approximately half the length (height) Hwell of the well diffusion layers 50P, 50N. The length H30 of the first electrode 30 is, for example, 0.5 μm to 5 μm. The length Hwell of the well diffusion layers 50P, 50N is, for example, 1 μm to 10 μm. The diameter of the first electrode 30 in the X or Y direction is smaller than the diameter of the through electrode 31. The aspect ratio of the first electrode 30 is preferably approximately equal to the aspect ratio of the through electrode 31. This allows the first electrode 30 and the through electrode 31, although they have different sizes, to be formed simultaneously in the same process. This shortens the manufacturing process of the semiconductor device 1.

[0084] Other configurations of the fifth embodiment may be the same as those of the first embodiment. Therefore, the fifth embodiment can achieve the same effects as the first embodiment. Furthermore, the fifth embodiment may be combined with any of the second to fourth embodiments. In this case, the fifth embodiment can achieve the same effects as any of the second to fourth embodiments.

[0085] Sixth Embodiment FIG. 6 is a cross-sectional view showing an example of the configuration of a semiconductor device according to a sixth embodiment.

[0086] In the sixth embodiment, the through electrode 31 extends from the wiring 35 through the well diffusion layer 50P or 50N, the element isolation portion STI2, and the interlayer insulating film ILD2 to a portion of the wiring WRG2 provided above the element isolation portion STI2. The polysilicon layer Gsti is not provided, and the wiring WRG2 is made of a metal (e.g., tungsten, copper, or aluminum). Therefore, the silicide layer 21 is not formed at the tip of the metal portion 11. That is, the through electrode 31 is made of the metal portion 11 that directly connects the wiring 35 to the wiring WRG2. A sidewall insulating film 41 is provided around the through electrode 31.

[0087] In the sixth embodiment, it is not necessary to form the polysilicon layer Gsti on the element isolation part STI 2. Therefore, the degree of freedom in the layout of the through electrode 31 is increased.

[0088] Other configurations of the sixth embodiment may be the same as those of the first embodiment. Therefore, the sixth embodiment can achieve the same effects as the first embodiment. The sixth embodiment may also be combined with the third or fourth embodiment. In this case, the sixth embodiment can achieve the same effects as the third or fourth embodiment.

[0089] (Application Example to a Mobile Body) The technology according to the present disclosure (the present technology) can be applied to various products. For example, the technology according to the present disclosure may be realized as a device mounted on any type of mobile body, such as an automobile, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, personal mobility, an airplane, a drone, a ship, or a robot.

[0090] FIG. 7 is a block diagram showing a schematic configuration example of a vehicle control system, which is an example of a mobile object control system to which the technology according to the present disclosure can be applied.

[0091] The vehicle control system 12000 includes a plurality of electronic control units connected via a communication network 12001. In the example shown in Fig. 7, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an outside-vehicle information detection unit 12030, an inside-vehicle information detection unit 12040, and an integrated control unit 12050. Also shown in the figure are a microcomputer 12051, an audio / video output unit 12052, and an in-vehicle network I / F (Interface) 12053 as functional components of the integrated control unit 12050.

[0092] The drivetrain control unit 12010 controls the operation of devices related to the drivetrain of the vehicle in accordance with various programs. For example, the drivetrain control unit 12010 functions as a control device for a drive force generating device for generating a drive force of the vehicle, such as an internal combustion engine or a drive motor, a drive force transmission mechanism for transmitting the drive force to the wheels, a steering mechanism for adjusting the steering angle of the vehicle, and a braking device for generating a braking force of the vehicle.

[0093] The body system control unit 12020 controls the operation of various devices equipped in the vehicle body according to various programs. For example, the body system control unit 12020 functions as a control device for a keyless entry system, a smart key system, a power window device, or various lamps such as headlamps, backup lamps, brake lamps, turn signals, and fog lamps. In this case, radio waves transmitted from a portable device that serves as a key or signals from various switches can be input to the body system control unit 12020. The body system control unit 12020 receives these radio waves or signals and controls the vehicle's door lock device, power window device, lamps, etc.

[0094] The outside-vehicle information detection unit 12030 detects information outside the vehicle equipped with the vehicle control system 12000. For example, an imaging unit 12031 is connected to the outside-vehicle information detection unit 12030. The outside-vehicle information detection unit 12030 causes the imaging unit 12031 to capture images outside the vehicle and receives the captured images. The outside-vehicle information detection unit 12030 may perform object detection processing or distance detection processing for people, cars, obstacles, signs, characters on the road surface, etc. based on the received images.

[0095] The imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal corresponding to the amount of light received. The imaging unit 12031 can output the electrical signal as an image or as distance measurement information. The light received by the imaging unit 12031 may be visible light or invisible light such as infrared light.

[0096] The in-vehicle information detection unit 12040 detects information inside the vehicle. For example, a driver state detection unit 12041 that detects the state of the driver is connected to the in-vehicle information detection unit 12040. The driver state detection unit 12041 includes, for example, a camera that captures an image of the driver, and the in-vehicle information detection unit 12040 may calculate the degree of fatigue or concentration of the driver based on the detection information input from the driver state detection unit 12041, or may determine whether the driver is dozing off.

[0097] The microcomputer 12051 can calculate control target values ​​for the driving force generating device, steering mechanism, or braking device based on the information inside and outside the vehicle acquired by the outside-vehicle information detection unit 12030 or the inside-vehicle information detection unit 12040, and output control commands to the drive system control unit 12010. For example, the microcomputer 12051 can perform cooperative control aimed at realizing the functions of an ADAS (Advanced Driver Assistance System), including vehicle collision avoidance or impact mitigation, following driving based on the distance between vehicles, maintaining vehicle speed, vehicle collision warning, vehicle lane departure warning, etc.

[0098] In addition, the microcomputer 12051 can perform cooperative control for the purpose of autonomous driving, which allows the vehicle to travel autonomously without relying on driver operation, by controlling the driving force generating device, steering mechanism, braking device, etc. based on information about the surroundings of the vehicle obtained by the outside vehicle information detection unit 12030 or the inside vehicle information detection unit 12040.

[0099] Furthermore, the microcomputer 12051 can output a control command to the body system control unit 12020 based on the information outside the vehicle acquired by the outside information detection unit 12030. For example, the microcomputer 12051 can control the headlamps according to the position of a preceding vehicle or an oncoming vehicle detected by the outside information detection unit 12030, and perform cooperative control aimed at preventing glare, such as switching from high beams to low beams.

[0100] The audio / video output unit 12052 transmits at least one of audio and video output signals to an output device capable of visually or audibly notifying the passengers of the vehicle or the outside of the vehicle of information. In the example of Fig. 7, the output devices are exemplified by an audio speaker 12061, a display unit 12062, and an instrument panel 12063. The display unit 12062 may include, for example, at least one of an on-board display and a head-up display.

[0101] FIG. 8 is a diagram showing an example of the installation position of the imaging unit 12031.

[0102] In FIG. 8, the imaging unit 12031 includes imaging units 12101, 12102, 12103, 12104, and 12105.

[0103] The imaging units 12101, 12102, 12103, 12104, and 12105 are provided, for example, at positions such as the front nose, side mirrors, rear bumper, back door, and the top of the windshield inside the vehicle cabin of the vehicle 12100. The imaging unit 12101 provided on the front nose and the imaging unit 12105 provided on the top of the windshield inside the vehicle cabin mainly acquire images of the front of the vehicle 12100. The imaging units 12102 and 12103 provided on the side mirrors mainly acquire images of the sides of the vehicle 12100. The imaging unit 12104 provided on the rear bumper or back door mainly acquires images of the rear of the vehicle 12100. The imaging unit 12105 provided on the top of the windshield inside the vehicle cabin is mainly used to detect preceding vehicles, pedestrians, obstacles, traffic lights, traffic signs, lanes, etc.

[0104] 8 shows an example of the imaging ranges of the imaging units 12101 to 12104. Imaging range 12111 indicates the imaging range of the imaging unit 12101 provided on the front nose, imaging ranges 12112 and 12113 indicate the imaging ranges of the imaging units 12102 and 12103 provided on the side mirrors, respectively, and imaging range 12114 indicates the imaging range of the imaging unit 12104 provided on the rear bumper or back door. For example, by overlaying the image data captured by the imaging units 12101 to 12104, an overhead image of the vehicle 12100 viewed from above can be obtained.

[0105] At least one of the image capturing units 12101 to 12104 may have a function of acquiring distance information. For example, at least one of the image capturing units 12101 to 12104 may be a stereo camera made up of multiple image capturing elements, or may be an image capturing element having pixels for phase difference detection.

[0106] For example, based on the distance information obtained from the imaging units 12101 to 12104, the microcomputer 12051 can calculate the distance to each three-dimensional object within the imaging ranges 12111 to 12114 and the change in this distance over time (relative speed with respect to the vehicle 12100), thereby extracting as a preceding vehicle, in particular, the three-dimensional object that is the closest three-dimensional object on the path of the vehicle 12100 and traveling in approximately the same direction as the vehicle 12100 at a predetermined speed (e.g., 0 km / h or higher). Furthermore, the microcomputer 12051 can set a vehicle-to-vehicle distance to be maintained in advance in front of the preceding vehicle, and perform automatic braking control (including follow-up stop control), automatic acceleration control (including follow-up start control), etc. In this way, cooperative control can be performed for the purpose of autonomous driving, which allows the vehicle to travel autonomously without relying on driver operation.

[0107] For example, the microcomputer 12051 classifies and extracts three-dimensional object data regarding three-dimensional objects into two-wheeled vehicles, ordinary vehicles, large vehicles, pedestrians, utility poles, and other three-dimensional objects based on distance information obtained from the imaging units 12101 to 12104, and can use the data for automatic obstacle avoidance. For example, the microcomputer 12051 distinguishes obstacles around the vehicle 12100 into obstacles that are visible to the driver of the vehicle 12100 and obstacles that are difficult to see. The microcomputer 12051 then determines a collision risk that indicates the risk of collision with each obstacle, and when the collision risk is equal to or greater than a set value and a collision is possible, the microcomputer 12051 can provide driving assistance for collision avoidance by outputting an alarm to the driver via the audio speaker 12061 or the display unit 12062, or by performing forced deceleration or avoidance steering via the drive system control unit 12010.

[0108] At least one of the image capturing units 12101 to 12104 may be an infrared camera that detects infrared rays. For example, the microcomputer 12051 can recognize a pedestrian by determining whether a pedestrian is present in the images captured by the image capturing units 12101 to 12104. Such pedestrian recognition is performed, for example, by extracting feature points from the images captured by the image capturing units 12101 to 12104 as infrared cameras and performing pattern matching on a series of feature points that indicate the outline of an object to determine whether the object is a pedestrian. When the microcomputer 12051 determines that a pedestrian is present in the images captured by the image capturing units 12101 to 12104 and recognizes the pedestrian, the audio / image output unit 12052 controls the display unit 12062 to superimpose a rectangular outline on the recognized pedestrian for emphasis. The audio / image output unit 12052 may also control the display unit 12062 to display an icon or the like indicating the pedestrian at a desired position.

[0109] The above describes an example of a vehicle control system to which the technology according to the present disclosure can be applied. The technology according to the present disclosure can be applied to, for example, the image capturing unit 12031 of the above-described configuration.

[0110] (Application Example to Endoscopic Surgery System) The technology according to the present disclosure (the present technology) can be applied to various products. For example, the technology according to the present disclosure may be applied to an endoscopic surgery system.

[0111] FIG. 9 is a diagram showing an example of a schematic configuration of an endoscopic surgery system to which the technology according to the present disclosure (the present technology) can be applied.

[0112] 9 shows an operator (doctor) 11131 performing surgery on a patient 11132 on a patient bed 11133 using an endoscopic surgery system 11000. As shown in the figure, the endoscopic surgery system 11000 is composed of an endoscope 11100, other surgical tools 11110 such as an insufflation tube 11111 and an energy treatment tool 11112, a support arm device 11120 that supports the endoscope 11100, and a cart 11200 on which various devices for endoscopic surgery are mounted.

[0113] The endoscope 11100 is composed of a lens barrel 11101, a region of a predetermined length from the tip of which is inserted into a body cavity of a patient 11132, and a camera head 11102 connected to the base end of the lens barrel 11101. In the example shown, the endoscope 11100 is configured as a so-called rigid scope having a rigid lens barrel 11101, but the endoscope 11100 may also be configured as a so-called flexible scope having a flexible lens barrel.

[0114] An opening into which an objective lens is fitted is provided at the tip of the lens barrel 11101. A light source device 11203 is connected to the endoscope 11100, and light generated by the light source device 11203 is guided to the tip of the lens barrel by a light guide extending inside the lens barrel 11101, and is irradiated via the objective lens toward an object to be observed inside the body cavity of the patient 11132. The endoscope 11100 may be a direct-viewing endoscope, an oblique-viewing endoscope, or a side-viewing endoscope.

[0115] An optical system and an image sensor are provided inside the camera head 11102, and light reflected from the object of observation (observation light) is collected onto the image sensor by the optical system. The observation light is photoelectrically converted by the image sensor to generate an electrical signal corresponding to the observation light, i.e., an image signal corresponding to the observed image. The image signal is sent to a camera control unit (CCU) 11201 as RAW data.

[0116] The CCU 11201 is configured with a CPU (Central Processing Unit), a GPU (Graphics Processing Unit), etc., and comprehensively controls the operations of the endoscope 11100 and the display device 11202. Furthermore, the CCU 11201 receives an image signal from the camera head 11102 and performs various types of image processing on the image signal, such as development processing (demosaic processing), to display an image based on the image signal.

[0117] Under the control of the CCU 11201, the display device 11202 displays an image based on an image signal that has been subjected to image processing by the CCU 11201.

[0118] The light source device 11203 is composed of a light source such as an LED (light emitting diode), and supplies irradiation light to the endoscope 11100 when photographing the surgical area, etc.

[0119] The input device 11204 is an input interface for the endoscopic surgery system 11000. A user can input various information and instructions to the endoscopic surgery system 11000 via the input device 11204. For example, the user inputs an instruction to change the imaging conditions (type of irradiation light, magnification, focal length, etc.) of the endoscope 11100.

[0120] The treatment tool control device 11205 controls the driving of the energy treatment tool 11112 for cauterizing tissue, incising, sealing blood vessels, etc. The insufflation device 11206 inflates the body cavity of the patient 11132 through the insufflation tube 11111 in order to ensure a clear field of view for the endoscope 11100 and a working space for the surgeon. The recorder 11207 is a device capable of recording various types of information related to the surgery. The printer 11208 is a device capable of printing various types of information related to the surgery in various formats such as text, images, or graphs.

[0121] The light source device 11203, which supplies illumination light to the endoscope 11100 when photographing the surgical site, can be configured from a white light source, such as an LED, a laser light source, or a combination of these. When the white light source is configured from a combination of RGB laser light sources, the output intensity and output timing of each color (each wavelength) can be controlled with high precision, allowing the light source device 11203 to adjust the white balance of the captured image. In this case, it is also possible to time-share images corresponding to each RGB by irradiating the object of observation with laser light from each RGB laser light source and controlling the drive of the image sensor of the camera head 11102 in synchronization with the irradiation timing. According to this method, color images can be obtained without providing a color filter to the image sensor.

[0122] Furthermore, the light source device 11203 may be controlled to change the intensity of light it outputs at predetermined time intervals. By controlling the driving of the image sensor of the camera head 11102 in synchronization with the timing of the change in light intensity to acquire images in a time-division manner and combining the images, it is possible to generate an image with a high dynamic range that is free from so-called blocked-up shadows and blown-out highlights.

[0123] The light source device 11203 may also be configured to supply light in a predetermined wavelength band corresponding to special light observation. Special light observation, for example, utilizes the wavelength dependence of light absorption in body tissues to irradiate light with a narrower band than the light irradiated during normal observation (i.e., white light), thereby capturing high-contrast images of specific tissues, such as blood vessels on the surface of mucous membranes, known as narrow-band imaging. Alternatively, special light observation may involve fluorescence observation, in which images are obtained using fluorescence generated by irradiating excitation light. Fluorescence observation may involve irradiating excitation light onto body tissues and observing the fluorescence from the tissue (autofluorescence observation), or by locally injecting a reagent such as indocyanine green (ICG) into the body tissue and irradiating the tissue with excitation light corresponding to the fluorescent wavelength of the reagent to obtain a fluorescent image. The light source device 11203 may be configured to supply narrow-band light and / or excitation light corresponding to such special light observation.

[0124] FIG. 10 is a block diagram showing an example of the functional configuration of the camera head 11102 and the CCU 11201 shown in FIG.

[0125] The camera head 11102 has a lens unit 11401, an imaging unit 11402, a drive unit 11403, a communication unit 11404, and a camera head control unit 11405. The CCU 11201 has a communication unit 11411, an image processing unit 11412, and a control unit 11413. The camera head 11102 and the CCU 11201 are connected to each other via a transmission cable 11400 so that they can communicate with each other.

[0126] The lens unit 11401 is an optical system provided at the connection portion with the lens barrel 11101. Observation light taken in from the tip of the lens barrel 11101 is guided to the camera head 11102 and enters the lens unit 11401. The lens unit 11401 is composed of a combination of multiple lenses including a zoom lens and a focus lens.

[0127] The imaging unit 11402 may include one imaging element (a so-called single-chip type) or multiple imaging elements (a so-called multi-chip type). When the imaging unit 11402 is configured as a multi-chip type, for example, each imaging element may generate an image signal corresponding to each of RGB, and a color image may be obtained by combining these signals. Alternatively, the imaging unit 11402 may be configured to have a pair of imaging elements for acquiring image signals for the right eye and the left eye corresponding to a 3D (dimensional) display. The 3D display allows the surgeon 11131 to more accurately grasp the depth of the biological tissue at the surgical site. Note that when the imaging unit 11402 is configured as a multi-chip type, multiple lens units 11401 may be provided corresponding to each imaging element.

[0128] Furthermore, the imaging unit 11402 does not necessarily have to be provided in the camera head 11102. For example, the imaging unit 11402 may be provided inside the lens barrel 11101, immediately after the objective lens.

[0129] The driving unit 11403 is configured by an actuator, and moves the zoom lens and focus lens of the lens unit 11401 by a predetermined distance along the optical axis under the control of the camera head control unit 11405. This allows the magnification and focus of the image captured by the imaging unit 11402 to be adjusted appropriately.

[0130] The communication unit 11404 is configured by a communication device for transmitting and receiving various types of information to and from the CCU 11201. The communication unit 11404 transmits the image signal obtained from the imaging unit 11402 to the CCU 11201 via the transmission cable 11400 as RAW data.

[0131] Furthermore, the communication unit 11404 receives a control signal for controlling the driving of the camera head 11102 from the CCU 11201 and supplies the control signal to the camera head control unit 11405. The control signal includes information on the imaging conditions, such as information specifying the frame rate of the captured image, information specifying the exposure value at the time of imaging, and / or information specifying the magnification and focus of the captured image.

[0132] The image capturing conditions such as the frame rate, exposure value, magnification, and focus may be appropriately specified by the user, or may be automatically set by the control unit 11413 of the CCU 11201 based on the acquired image signal. In the latter case, the endoscope 11100 is equipped with so-called AE (Auto Exposure) function, AF (Auto Focus) function, and AWB (Auto White Balance) function.

[0133] The camera head control unit 11405 controls the driving of the camera head 11102 based on a control signal received from the CCU 11201 via the communication unit 11404 .

[0134] The communication unit 11411 is configured by a communication device for transmitting and receiving various information to and from the camera head 11102. The communication unit 11411 receives an image signal transmitted from the camera head 11102 via the transmission cable 11400.

[0135] Furthermore, the communication unit 11411 transmits to the camera head 11102 a control signal for controlling the driving of the camera head 11102. The image signal and the control signal can be transmitted by electrical communication, optical communication, or the like.

[0136] The image processing unit 11412 performs various image processing operations on the image signal, which is RAW data transmitted from the camera head 11102 .

[0137] The control unit 11413 performs various controls related to the imaging of the surgical site, etc. by the endoscope 11100 and the display of the captured image obtained by imaging the surgical site, etc. For example, the control unit 11413 generates a control signal for controlling the driving of the camera head 11102.

[0138] Furthermore, the control unit 11413 displays the captured image showing the surgical site, etc., on the display device 11202 based on the image signal subjected to image processing by the image processing unit 11412. At this time, the control unit 11413 may recognize various objects in the captured image using various image recognition technologies. For example, the control unit 11413 can recognize surgical tools such as forceps, specific biological parts, bleeding, mist generated when using the energy treatment tool 11112, etc., by detecting the shape and color of the edges of objects included in the captured image. When displaying the captured image on the display device 11202, the control unit 11413 may use the recognition results to superimpose various surgical support information on the image of the surgical site. By superimposing the surgical support information and presenting it to the surgeon 11131, the burden on the surgeon 11131 can be reduced and the surgeon 11131 can proceed with the surgery reliably.

[0139] The transmission cable 11400 connecting the camera head 11102 and the CCU 11201 is an electrical signal cable for electrical signal communication, an optical fiber for optical communication, or a composite cable of these.

[0140] In the illustrated example, communication is performed wired using a transmission cable 11400, but communication between the camera head 11102 and the CCU 11201 may also be performed wirelessly.

[0141] The above describes an example of an endoscopic surgery system to which the technology according to the present disclosure can be applied. The technology according to the present disclosure can be applied to, for example, the endoscope 11100, the imaging unit 11402 of the camera head 11102, the image processing unit 11412 of the CCU 11201, and the like, among the above-described components.

[0142] Although an endoscopic surgery system has been described as an example here, the technology according to the present disclosure may also be applied to other systems, such as a microsurgery system.

[0143] The present technology can be configured as follows.

[0144] (1) A semiconductor device comprising: a first semiconductor substrate; a second semiconductor substrate laminated on the first semiconductor substrate, having a first surface and a second surface opposite to the first surface, and facing the first semiconductor substrate at one of the first and second surfaces; a third semiconductor substrate laminated on the second semiconductor substrate, facing the second semiconductor substrate at the other of the first and second surfaces; a first diffusion layer of a first conductivity type impurity provided in the second semiconductor substrate from the first surface to the second surface; a transistor provided in the first diffusion layer on the first surface side; a first electrode provided in the first diffusion layer on the second surface side and electrically connected to the first diffusion layer; and a supply wiring provided on the first or third semiconductor substrate, electrically connected to the first electrode, and supplying a reference voltage or a power supply voltage to the first electrode.

[0145] (2) The semiconductor device according to (1), wherein the first electrode extends from the second surface toward the first surface to a point partway along the first diffusion layer.

[0146] (3) The semiconductor device according to (1) or (2), wherein the first electrode includes a first silicide layer in contact with the first diffusion layer.

[0147] (4) The semiconductor device according to (2), further comprising a first insulating film provided on a sidewall of a trench or hole provided in the first diffusion layer, wherein the first electrode includes a first conductive portion provided inside the first insulating film in the trench or hole, and a first silicide layer provided at an end of the first conductive portion on the first surface side and in contact with the first diffusion layer.

[0148] (5) The semiconductor device according to any one of (1) to (4), further comprising a through electrode that penetrates the second semiconductor substrate between the first surface and the second surface.

[0149] (6) The semiconductor device according to (5), further comprising: an element isolation portion provided on the first surface side of the second semiconductor substrate; and a polysilicon layer provided on or within the element isolation portion, wherein the through electrode penetrates the second semiconductor substrate and contacts the polysilicon layer.

[0150] (7) The semiconductor device according to (6), further comprising a second insulating film provided on an inner wall of a through hole penetrating the second semiconductor substrate between the first surface and the second surface, wherein the through electrode includes a second conductive portion provided inside the second insulating film within the through hole, and a second silicide layer provided at an end of the second conductive portion on the first surface side and in contact with the polysilicon layer.

[0151] (8) The semiconductor device according to any one of (1) to (7), wherein the first electrode is disposed directly below a gate or a channel of the transistor.

[0152] (9) The semiconductor device according to any one of (5) to (7), wherein the first electrode is shorter than the through electrode in the stacking direction of the first to third semiconductor substrates.

[0153] (10) The semiconductor device according to any one of (5) to (7), wherein the through electrode has substantially the same length as the first electrode in the stacking direction of the first to third semiconductor substrates.

[0154] (11) The semiconductor device according to (6) or (7), wherein the polysilicon layer is provided from the first surface toward the second surface up to the middle of the element isolation portion, and the through electrode penetrates the second semiconductor substrate and contacts the polysilicon layer.

[0155] (12) The semiconductor device according to any one of (1) to (11), wherein the first diffusion layer is a well diffusion layer of a P-type impurity.

[0156] (13) The semiconductor device according to any one of (1) to (12), wherein the first semiconductor substrate faces the second semiconductor substrate at a first surface, and the third semiconductor substrate faces the second semiconductor substrate at a second surface.

[0157] (14) The semiconductor device according to any one of (1) to (12), wherein the first semiconductor substrate faces the second semiconductor substrate at the second surface, and the third semiconductor substrate faces the second semiconductor substrate at the first surface.

[0158] (15) The semiconductor device according to (5), wherein the length of the first electrode in the stacking direction of the first to third semiconductor substrates is approximately half the length of the first diffusion layer, and the diameter of the first electrode in a direction approximately perpendicular to the stacking direction is smaller than the diameter of the through electrode in a direction approximately perpendicular to the stacking direction.

[0159] (16) The semiconductor device according to (15), wherein the aspect ratio of the first electrode is approximately equal to the aspect ratio of the through electrode.

[0160] (17) The semiconductor device according to (5), further comprising: an element isolation portion provided on the first surface side of the second semiconductor substrate; and a first wiring above the element isolation portion, wherein the through electrode penetrates the second semiconductor substrate and the element isolation portion and contacts the first wiring.

[0161] (18) The semiconductor device according to any one of (1) to (17), wherein the first semiconductor substrate includes a plurality of pixels including photodiodes, and the second and third semiconductor substrates include CMOS circuits.

[0162] (19) The semiconductor device according to (4), wherein the first conductive portion includes any one of tungsten, copper, and aluminum.

[0163] (20) The semiconductor device according to (3), wherein the first silicide layer contains any one of Ti, Zr, Hf, V, Cr, Ta, Co, Fe, Ni, Mo, Pt, W, and Nb.

[0164] The present disclosure is not limited to the above-described embodiments, and various modifications are possible within the scope of the gist of the present disclosure. Furthermore, the effects described in this specification are merely examples and are not intended to be limiting, and other effects may also be obtained.

[0165] 1 semiconductor device CH1 to CH3 semiconductor chip SUB1 to SUB3 semiconductor substrate STI1 to STI3 element isolation portion PD photodiode CF color filter LNS lens Tr1 to Tr3 transistor CNT1 to CNT3 contact WRG1 to WRG3 wiring ILD1 to ILD3 interlayer insulating film 10, 11 metal portion 20, 21 silicide layer 30 first electrode 31 through electrode 40, 41 sidewall insulating film Gsti polysilicon layer 50P, 50N well diffusion layer

Claims

1. A semiconductor device comprising: a first semiconductor substrate; a second semiconductor substrate laminated on the first semiconductor substrate, having a first surface and a second surface opposite to the first surface, and facing the first semiconductor substrate at one of the first and second surfaces; a third semiconductor substrate laminated on the second semiconductor substrate and facing the second semiconductor substrate at the other of the first and second surfaces; a first diffusion layer of a first conductivity type impurity provided in the second semiconductor substrate from the first surface to the second surface; a transistor provided in the first diffusion layer on the first surface side; a first electrode provided in the first diffusion layer on the second surface side and electrically connected to the first diffusion layer; and supply wiring provided on the first or third semiconductor substrate, electrically connected to the first electrode, and supplying a reference voltage or a power supply voltage to the first electrode.

2. The semiconductor device according to claim 1, wherein said first electrode extends from said second surface toward said first surface to a point partway along said first diffusion layer.

3. The semiconductor device according to claim 1, wherein said first electrode includes a first silicide layer in contact with said first diffusion layer.

4. The semiconductor device according to claim 2, further comprising a first insulating film provided on a sidewall within a trench or hole provided in the first diffusion layer, wherein the first electrode includes a first conductive portion provided inside the first insulating film within the trench or hole, and a first silicide layer provided at an end of the first conductive portion on the first surface side and in contact with the first diffusion layer.

5. The semiconductor device according to claim 1, further comprising a through electrode that penetrates said second semiconductor substrate between said first surface and said second surface.

6. The semiconductor device according to claim 5, further comprising: an element isolation portion provided on the first surface (F2_1) side of the second semiconductor substrate; and a polysilicon layer provided on or within the element isolation portion, wherein the through electrode penetrates the second semiconductor substrate and contacts the polysilicon layer.

7. The semiconductor device according to claim 6, further comprising a second insulating film provided on an inner wall of a through hole penetrating said second semiconductor substrate between said first surface and said second surface, wherein said through electrode includes a second conductive portion provided inside said second insulating film within said through hole, and a second silicide layer provided at an end of said second conductive portion on said first surface side and in contact with said polysilicon layer.

8. The semiconductor device according to claim 1, wherein the first electrode is disposed directly below the gate or channel of the transistor.

9. The semiconductor device according to claim 5, wherein the first electrode is shorter than the through electrode in the stacking direction of the first to third semiconductor substrates.

10. The semiconductor device according to claim 5, wherein said through electrode has substantially the same length as said first electrode in the stacking direction of said first to third semiconductor substrates.

11. The semiconductor device according to claim 6, wherein the polysilicon layer is provided from the first surface toward the second surface up to the middle of the element isolation portion, and the through electrode penetrates the second semiconductor substrate and contacts the polysilicon layer.

12. The semiconductor device according to claim 1, wherein said first diffusion layer is a well diffusion layer of P-type impurities.

13. The semiconductor device according to claim 1, wherein the first surface of the first semiconductor substrate faces the second semiconductor substrate, and the second surface of the third semiconductor substrate faces the second semiconductor substrate.

14. The semiconductor device according to claim 1, wherein the first semiconductor substrate faces the second semiconductor substrate at the second surface, and the third semiconductor substrate faces the second semiconductor substrate at the first surface.

15. The semiconductor device according to claim 5, wherein the length of the first electrode in the stacking direction of the first to third semiconductor substrates is approximately half the length of the first diffusion layer, and the diameter of the first electrode in a direction approximately perpendicular to the stacking direction is smaller than the diameter of the through electrode in a direction approximately perpendicular to the stacking direction.

16. The semiconductor device according to claim 15, wherein the aspect ratio of said first electrode is approximately equal to the aspect ratio of said through-electrode.

17. The semiconductor device according to claim 5, further comprising: an element isolation portion provided on the first surface side of the second semiconductor substrate; and a first wiring above the element isolation portion, wherein the through electrode penetrates the second semiconductor substrate and the element isolation portion and contacts the first wiring.

18. The semiconductor device according to claim 1, wherein the first semiconductor substrate includes a plurality of pixels including photodiodes, and the second and third semiconductor substrates include CMOS circuits.

19. The semiconductor device according to claim 4, wherein the first conductive portion contains any one of tungsten, copper, and aluminum.

20. The semiconductor device according to claim 3, wherein the first silicide layer contains any of Ti, Zr, Hf, V, Cr, Ta, Co, Fe, Ni, Mo, Pt, W, and Nb.

Images