Semiconductor device

Abstract

A purpose of the invention is to provide a technology for reducing power consumption.　A semiconductor device according to the present invention comprises a memory cell having a first transistor, a second transistor, and a third transistor. The gate, a first terminal, and a second terminal of the first transistor are respectively connected to a first word line, a first bit line, and a first terminal of the second transistor. The gate and a second terminal of the second transistor are respectively connected to a second word line and the gate of the third transistor. A first terminal and a second terminal of the third transistor are respectively connected to the first terminal and a second bit line of the second transistor. A node where the second terminal of the second transistor and the gate of the third transistor are connected is a storage node for retaining data.

Description

Semiconductor Devices

[0001] The present disclosure relates to a semiconductor device and is applicable to, for example, a semiconductor device having a gain cell type memory.

[0002] On-chip memories embedded on the same chip as logic circuits such as processors use static random access memories (SRAMs) because of their compatibility with logic CMOS (Complementary Metal-Oxide-Semiconductor) transistors in their manufacturing processes. Dynamic random access memories (DRAMs) using gain cells have been proposed as an alternative to SRAMs (see, for example, Non-Patent Documents 1 and 2).

[0003] International Publication No. 2013 / 105460

[0004] KC Chun et al., IEEE J. Solid-State Circuits 46, pp. 1495-1505, 2011R. Giterman et al., IEEE TCAS I, pp. 1245-1256, 2018

[0005] For example, if the data retention time at the storage node of a memory cell is short, the frequency of refresh increases, resulting in increased power consumption.

[0006] An object of the present disclosure is to provide a technology for reducing power consumption. Other objects and novel features will become apparent from the description of this specification and the accompanying drawings.

[0007] A representative aspect of the present disclosure can be briefly outlined as follows: A semiconductor device includes a memory cell having a first transistor, a second transistor, and a third transistor. The gate, first terminal, and second terminal of the first transistor are connected to a first word line, a first bit line, and a first terminal of the second transistor, respectively. The gate and second terminal of the second transistor are connected to a second word line and a gate of the third transistor, respectively. The first terminal and second terminal of the third transistor are connected to a first terminal of the second transistor and a second bit line, respectively. A node where the second terminal of the second transistor and the gate of the third transistor are connected is a storage node that holds data.

[0008] According to the present disclosure, power consumption can be reduced.

[0009] FIG. 1 is a circuit diagram showing an example of the configuration of a memory cell in an embodiment. FIG. 2 is a diagram showing, in tabular form, an example of drive biases for word lines and bit lines in the retention operation, read operation, and write operation of the memory cell shown in FIG. 1. FIG. 3 is a circuit block diagram showing an example of the configuration of a memory device using the memory cell shown in FIG. 1. FIG. 4(a) is a logic circuit diagram showing an example of the configuration of the clock control circuit shown in FIG. 3. FIG. 4(b) is a logic circuit diagram showing an example of the configuration of the access control circuit shown in FIG. 3. FIG. 5 is a circuit block diagram showing a modified example of the memory device shown in FIG. 3. FIG. 6 is a logic circuit diagram showing an example of the configuration of the access control circuit shown in FIG. 5. FIG. 7 is a timing diagram illustrating a refresh operation of the memory device shown in FIG. 3. FIG. 8 is a timing diagram illustrating a refresh operation of the memory device shown in FIG. 5. FIG. 9 is a circuit diagram showing the configuration of a memory cell in Comparative Example 1. FIG. 10 is a diagram showing, in tabular form, drive biases for word lines and bit lines in the retention operation, read operation, and write operation of the memory cell shown in FIG. 9. FIG. 11 is a circuit diagram showing the configuration of a memory cell in Comparative Example 2. FIG. 12 is a diagram showing, in tabular form, drive biases for word lines and bit lines in the retention operation, read operation, and write operation of the memory cell shown in FIG. 11. FIG. 13 is a diagram illustrating the leakage current of a memory cell. FIG. 14 is a diagram illustrating read disturbance of a memory cell. FIG. 15 is a diagram illustrating the transition of the potential of the storage node of a memory cell in Comparative Example 1, Comparative Example 2, and an embodiment. FIG. 16 is a diagram illustrating a comparison of the data retention time of a memory cell in Comparative Example 1, Comparative Example 2, and an embodiment. FIG. 17 is a diagram illustrating an example of the cell layout of a memory cell in Comparative Example 1, Comparative Example 2, and an embodiment. FIG. 18 is a diagram illustrating a comparison of the cell area of ​​a memory cell in Comparative Example 1, Comparative Example 2, and an embodiment. FIG. 19 is a circuit diagram illustrating the configuration of a memory cell in another aspect. FIG. 20 is a diagram illustrating, in tabular form, an example of the drive biases of the word lines and bit lines in the retention operation, read operation, and write operation of the memory cell shown in FIG. 19. FIG. 21 is a circuit block diagram illustrating an example of the configuration of a memory device driven with the drive biases shown in FIG. 20. FIG. 22 is a diagram illustrating the operation of a memory cell in another aspect.

[0010] The following description of the embodiments will be made with reference to the accompanying drawings. However, for clarity of explanation, the following description and drawings have been omitted and simplified as appropriate. Furthermore, the same components are designated by the same reference numerals, and repeated explanations may be omitted.

[0011] In addition, several representative modified examples and other aspects of the embodiments will be exemplified. In the description of the modified examples and other aspects described below, the same reference numerals as in the embodiments will be used for parts having the same configurations and functions as those described in the embodiments described below. Furthermore, the description of such parts may be appropriately cited within the scope of technical inconsistency. Furthermore, parts of the embodiments, and all or part of multiple modified examples and other aspects may be appropriately applied in a composite manner within the scope of technical inconsistency.

[0012] [Embodiment] <Memory Cell> An example of the configuration of a memory cell in the embodiment will be described with reference to Fig. 1. Fig. 1 is a circuit diagram showing an example of the configuration of a memory cell in the embodiment.

[0013] The memory cell 11 is a 3T type gain cell composed of three transistors. The memory cell 11 has a node ND as a first node, a storage node Q as a second node, and transistors M as first to third transistors. １ , M ２ , FBT and a transistor M １ , M ２ , FBT are, for example, p-channel MOS (p-type MOS, pMOS) transistors. The memory cell 11 may be referred to as a "P3T-MC."

[0014] A MOS transistor has three terminals called a gate, a source, and a drain. Of the two input / output terminals that function as a source or a drain, one becomes a source and the other a drain depending on the polarity of the transistor (channel conductivity type) and the level of the potential applied to each terminal. Therefore, in this specification, the terms source and drain are used interchangeably. Also, in this specification, the two input / output terminals mentioned above may be referred to as a first terminal and a second terminal.

[0015] Transistor M １ In the transistor M, the gate is connected to a word line WL as a first word line, and one of the source and the drain (first terminal) is connected to a write bit line WBL as a first bit line. １ The transistor M ２ , the gate is connected to a write word line WWL as a second word line, and one of the source and drain (first terminal) is connected to a transistor M １ The write word line WWL is connected to the other of the source and drain (second terminal) of the transistor M ２ In the transistor FBT, the gate is connected to the transistor M ２ and one of the source and drain (first terminal) of the transistor M １ and transistor M ２ The other of the source and drain (second terminal) is connected to a read bit line RBL as a second bit line. ２ The connection point between the transistor FBT and the memory cell 11 is the storage node Q of the memory cell 11. The node can be a terminal, a wiring, an electrode, a conductive layer, a conductor, an impurity region, or the like depending on the circuit configuration, device structure, and the like.

[0016] In this specification, the phrase "A is connected to B" includes not only cases where A is directly connected to B, but also cases where A is electrically connected to B. A and B are, for example, devices, elements, circuits, wiring, electrodes, terminals, conductive films, and other objects. Note that "electrically connected" also includes cases where objects are connected via something that enables the exchange of electrical signals between them (electrical elements). Electrical elements include, for example, electrodes and wiring. Furthermore, even when the phrase "connect" or "connected" is used in this specification, in actual circuits, there may be no physical connection and only an extending wiring. For example, in a MOS transistor circuit, a single wiring may also serve as the gate of the MOS transistor.

[0017] <Operation of Memory Cell> Retention, read, and write operations are performed in the memory cell 11. The drive levels of the word lines (word line WL and write word line WWL) and bit lines (write bit line WBL and read bit line RBL) in each operation will be explained using Figure 2. Figure 2 is a table showing an example of the drive biases of the word lines and bit lines in the retention, read, and write operations of the memory cell shown in Figure 1.

[0018] (Retention Operation) In the retention operation, the word line WL and the write word line WWL are driven to "H", and the write bit line WBL and the read bit line RBL are driven to "L". １ , M ２ is turned off, and the storage node Q maintains the potential it holds. Here, "H" is a high-level potential, and "L" is a low-level potential. "H" is also called a high level, and for example, V ＤＤ "L" is also called low level, for example, V ＳＳ is.

[0019] (Read Operation) In a read operation, the word line WL of the selected memory cell 11 is driven to "L", the write word line WWL and write bit line WBL are driven to "H", and the read bit line RBL is "FL:L". "FL:L" is a low level floating state, which is a state that is made floating after pre-discharge.

[0020] When the storage node Q is "L" (data is "0"), the transistor FBT is in an ON state. Also, since the word line WL is driven to "L", the transistor M １ is in the on state. １Since the transistor FBT is on, a current (I) flows from the write bit line WBL to the read bit line RBL, as shown by the solid arrow in FIG. 1. This charges the read bit line RBL, causing the potential of the read bit line RBL to rise from "FL:L". When the storage node Q is "H" (data "1"), the transistor FBT is off, so no current flows from the write bit line WBL to the read bit line RBL. As a result, the potential of the read bit line RBL changes very little and remains at "FL:L".

[0021] The word line WL, the write word line WWL, and the write bit line WBL of the unselected memory cell 11 are driven to "H", and the read bit line RBL is "FL:L". １ , M ２ is in the OFF state, the storage node Q maintains the potential it holds.

[0022] (Write Operation) In a write operation, the word line WL of the selected memory cell 11 is driven to "L", the write word line WWL is driven to "L-", the write bit line WBL is driven to "H / L", and the read bit line RBL is driven to "L". Here, "H / L" is "H" or "L". "L-" is V ＳＳ "L-" is called the low level (VOL) of overdrive.

[0023] Transistor M １ and transistor M ２ is turned on, the potential input to the write bit line WBL is written to the memory node Q. When the write bit line WBL is at "H", "H" (data "1") is written to the memory node Q. When the write bit line WBL is at "L", "L" (data "0") is written to the memory node Q.

[0024] The word line WL and the write word line WWL of the unselected memory cell 11 are driven to "H", the write bit line WBL is driven to "H / L", and the read bit line RBL is driven to "L". １ , M ２is in the OFF state, the storage node Q maintains the potential it holds.

[0025] The drive biases of the word lines and bit lines in each operation of the memory cell 11 can be other than those shown in Fig. 2. For example, the bit lines may be driven with a drive bias so that the direction of the current in the read operation is opposite to that in Fig. 2.

[0026] <Memory Device> The configuration of a memory device using the memory cell 11 shown in Fig. 1 will be described with reference to Fig. 3. Fig. 3 is a circuit block diagram showing an example of the configuration of a memory device using the memory cell shown in Fig. 1. Fig. 3 shows a part of the memory cell array and essential parts of its peripheral circuits.

[0027] The memory device 1 includes a memory cell array 10, a row circuit 20, an input / output circuit 30, and a control circuit 40. The row circuit 20, the input / output circuit 30, and the control circuit 40 constitute peripheral circuits.

[0028] The storage device 1 is externally connected to ＤＤ , V ＳＳ , a clock signal (CLK), an address signal (ADDR), an enable signal (EN), a write enable signal (WE), an access signal (AC), and data (DIN) are input to the memory device 1. A refresh signal (RFR) and data (DOUT) are output to the outside from the memory device 1. The memory device 1 is a pseudo SRAM mounted on the same semiconductor chip (semiconductor device) as a logic circuit such as a processor, for example, on a microprocessor or SoC (System-on-Chip).

[0029] (Memory Array) The memory cell array 10 includes a plurality of memory cells (MC) 11 arranged in a matrix. The write bit lines WBL and read bit lines RBL extend in the column direction of the memory cell array 10 and are shared by the plurality of memory cells 11 arranged in the column direction. The word lines WL and write word lines WWL extend in the row direction of the memory cell array 10 and are shared by the plurality of memory cells 11 arranged in the row direction.

[0030] FIG. 3 shows a memory cell array 10 with X+1 rows (X is a positive integer). X+1 memory cells 11[0] to 11[X] are provided in each column of the memory cell array 10. X+1 word lines WL[0] to WL[X] and X+1 write word lines WWL[0] to WWLB[X] are provided corresponding to each row of the memory cell array 10. Note that FIG. 3 shows only one column of the memory cell array 10. When the number of columns is Y+1 (Y is a positive integer), Y+1 write bit lines WBL and Y+1 read bit lines RBL are provided corresponding to each column of the memory cell array 10.

[0031] (Row Circuit) The row circuit 20 has the function of selecting the word line WL and write word line WWL of the row specified by ADDR. The row circuit 20 includes a multiplexer (MUX) 21 as a selection circuit, a flip-flop circuit (FF) 22 as a holding circuit, a word decoder (W_DEC) 23, and write word line drivers 24[0] to 24[X]. When there is no need to distinguish between the write word line drivers 24[0] to 24[X], they will be collectively referred to as write word line drivers 24.

[0032] The multiplexer 21 selects either an ADDR input from the outside or a refresh address signal (R_ADDR) input from a refresh control circuit (R_CTRL) 4D (described later), and outputs an address signal (XAD).

[0033] The flip-flop circuit 22 temporarily holds the XAD output from the multiplexer 21. The flip-flop circuit 22 captures the XAD in synchronization with the rising edge of the CLK, for example.

[0034] The word decoder 23 selects a word line WL by decoding the address signal (S_XAD) output from the flip-flop circuit 22. The word decoder 23 includes a word line driver (first drive circuit) that drives the potential of the word line WL to "H" or "L" based on the selection state.

[0035] The write word line driver 24, which serves as a second drive circuit, selects the write word line WWL during writing. The write word line driver 24 drives the potential of the write word line WWL to "H" or "L-" based on the selected state. The potential (VOL) of "L-" is V ＳＳ Since the potential is lower than ＳＳ is at ground potential, the write word line driver 24 overdrives it to a negative potential. The write word line driver 24 is configured, for example, by a logical sum circuit (OR circuit).

[0036] (Input / Output Circuit) The input / output circuit (column circuit) 30 has the function of writing data to the write bit lines WBL of a column designated by an externally input address signal and reading data from the read bit lines RBL. The input / output circuit 30 includes a sense amplifier (SA) 31 as a read circuit, a multiplexer (MUX) 32, a write driver (WR_DR) 33 as a write circuit (third drive circuit), a precharge circuit 34p, predischarge circuits 35d and 36d, a switch circuit 37, and a predischarge circuit 38d.

[0037] During a read operation, the sense amplifier 31 amplifies and outputs data read from each memory cell 11 via the read bit line RBL. The sense amplifier 31 compares the potential of the read bit line RBL with a reference potential (Vref) as a predetermined potential, and outputs a potential based on the comparison result, for example.

[0038] The multiplexer 32 selects either the data (DO) or DIN to be read during refresh and outputs it to the write driver 33 as write data (DI).

[0039] During writing, the write driver 33 supplies write data via the write bit line WBL to each memory cell 11. The write driver 33 drives the potential of the write bit line WBL to "H" or "L" based on the potential of DI.

[0040] The precharge circuit 34p as a first charge circuit is a circuit that charges the potential of the write bit line WBL to "H." The precharge circuit 34p is composed of, for example, a pMOS transistor. The gate of this pMOS transistor is connected to a wiring that supplies a precharge control signal (BLP), and the source is connected to V ＤＤ The drain is connected to a power supply line that supplies the potential of the write bit line WBL.

[0041] The pre-discharge circuit 35d as a second charge circuit is a circuit that discharges the potential of the write bit line WBL to "L." The pre-discharge circuit 35d is configured, for example, with an n-channel MOS (n-type MOS, nMOS) transistor. The gate of this nMOS transistor is connected to a wiring that supplies a pre-discharge control signal (BLD), and the source is connected to V ＳＳ The drain is connected to a power supply line that supplies the potential of the write bit line WBL.

[0042] The pre-discharge circuit 36d as a third charge circuit is a circuit that pre-discharges the potential of the read bit line RBL to "L." The pre-discharge circuit 36d is configured, for example, with an nMOS transistor. The gate of this nMOS transistor is connected to a wiring that supplies BLP, and the source is connected to V ＳＳ The drain is connected to a power supply line that supplies a potential of 0 V, and the drain is connected to a read bit line RBL.

[0043] The switch circuit 37 is configured, for example, by an nMOS transistor, one of whose source or drain is connected to the read bit line RBL, the other of whose source or drain is connected to the sense amplifier 31, and the gate is connected to a read operation signal (RO) described later. The pre-discharge circuit 38d is configured, for example, by an nMOS transistor, the gate of which is connected to a line that supplies BLP, and the source of which is connected to V ＳＳ The drain is connected to a power supply line that supplies a potential of 0 V, and the drain is connected to a read bit line RBL.

[0044] (Control Circuit) The control circuit 40 has the function of controlling the overall operation of the memory device 1. The control circuit 40 includes logical negation circuits (inverter circuits) 4A and 4B, a timer circuit (TMR) 4C, a refresh control circuit (R_CTRL) 4D, a clock control circuit (CLK_CTRL) 4F, and an access control circuit (A_CTRL) 4G.

[0045] The timer circuit 4C counts CLK and, when it is time for a refresh operation, sets RFR to "H." When RFR goes to "H," the refresh control circuit 4D generates a refresh address selection signal (RAS), R-ADDR, a refresh read signal (RFR_RE), a refresh write signal (RFR_WE), and a reset signal (RST) to control the refresh operation.

[0046] The clock control circuit 4F controls the supply of CLK to the row circuit 20, the refresh control circuit 4D, the access control circuit 4G, etc. based on EN and RFR. The access control circuit (A_CTRL) 4G generates a write access signal (WA), a write operation signal (WO), and a read operation signal (RO) based on AC, WE, RFR, RFR-RE, and RFR-WE, and controls reading from and writing to the memory cell array 10.

[0047] An example of the clock control circuit 4F and the access control circuit 4G will be described with reference to Figures 4(a) and 4(b). Figure 4(a) is a logic circuit diagram showing an example of the configuration of the clock control circuit shown in Figure 3. Figure 4(b) is a logic circuit diagram showing an example of the configuration of the access control circuit shown in Figure 3.

[0048] The clock control circuit 4F includes, for example, a logical sum circuit (OR circuit) 41 and a logical product circuit (AND circuit) 42. The OR circuit 41 and the AND circuit 42 control the supply of CLK to the memory device 1 except for the timer circuit 4C. When EN or RFR is "H", CLK is supplied to the row circuit 20, the refresh control circuit 4D, etc. When both EN and RFR are "L", CLK is not supplied. CLK is always supplied to the timer circuit 4C. Here, the output signal of the AND circuit 42 is referred to as CE. The flip-flop circuit 22, the word decoder 23, and the refresh control circuit 4D operate in synchronization with CE (CLK).

[0049] The access control circuit 4G includes, for example, OR circuits 48 and 49, AND circuits 44, 46 and 47, and inverter circuits 43 and 45. The inverter circuit 43 and the AND circuit 44 control the supply of AC into the memory device 1. When CE is "H" and RFR is "L", AC is supplied to the AND circuits 46 and 47. When CE is "L" or RFR is "H", AC is not supplied to the AND circuits 46 and 47. Here, the output signal of the AND circuit 44 is designated as AE.

[0050] The inverter circuit 45 and AND circuits 46, 47 determine whether the external access is a read access or a write access. When AE is "H" and WE is "L", the read access signal (RA) becomes "H" and WA becomes "L". When AE is "H" and WE is "H", WA becomes "H" and RA becomes "L". When CLK is "L", CE becomes "L" and AE becomes "L", so that both RA and WA become "L". When WA is "H", the multiplexer 32 selects and outputs DIN. When WA is "L", the multiplexer 32 selects and outputs DO.

[0051] The OR circuit 48 and the inverter circuit 4A control the read operation. When RA or RFR_RE is "H", RO becomes "H" and a read operation is performed on the memory cell 11. Since RO is "H", the inverter circuit 4A sets BLP to "L", causing the pre-discharge circuit 36d to float the read bit line RBL and activate the sense amplifier 31. Also, since BLP is "L", the pre-charge circuit 34p charges the write bit line WBL to "H". Note that the read operation from the memory cell 11 is performed when CLK is "H".

[0052] The OR circuits 48 and 49 and the inverter circuit 4A control the write operation. When WA or RFR_WE is "H", WO becomes "H" and a write operation is performed on the memory cell 11. When WO is "H", the write driver 33 is activated. In addition, the OR circuit 48 sets BLP to "H", causing the write bit line WBL to float and the read bit line RBL to "L". Note that the write operation on the memory cell 11 is performed when CLK is "H".

[0053] An example of the operation of the memory device 1 shown in Figure 3 will be described. The memory device 1 performs data retention, read, write, and refresh operations. The memory device 1 cannot be accessed (read or write) from the outside until the refresh operation of all memory cells is completed. Here, the clock control circuit 4F is the example shown in Figure 4(a), and the access control circuit 4G is the example shown in Figure 4(b).

[0054] (Data Retention) When EN is set to "L" and RFR is "L", the memory device 1 performs the above-described retention operation of the memory cell 11. In this case, CE becomes "L", so AE, RA, WA, RO, and WO become "L", and BLP and BLD become "H". Since BLP and BLD become "H", the write bit line WBL becomes "L", and the read bit line RBL becomes "L".

[0055] Furthermore, since CE is "L", the word decoder 23 is in an inactive state, and all the word lines WL are "H". Furthermore, since WO is "L", the output NW of the inverter circuit 4E is "H", the output of the write word line driver 24, which is a logical sum circuit (NOR circuit), is "H", and all the write word lines WWL are "H".

[0056] These operations result in the same drive bias states as those of the word line WL, write word line WWL, write bit line WBL, and read bit line RBL in the hold operation of FIG.

[0057] (Read) When EN and AC are set to "H" and WE is set to "L", if RFR is "L", the memory device 1 performs a read operation. When CLK becomes "L", RO becomes "L", so BLP becomes "H", and the read bit line RBL becomes "L". When CLK becomes "H", CE, AE, RA, and RO become "H", and WA, WO, BLP, and BLD become "L". Since BLP and BLD are "L", the write bit line WBL becomes "H", and the read bit line RBL becomes floating.

[0058] At the rising edge of CLK, ADDR is taken into the flip-flop circuit 22 and decoded by the word decoder 23, causing the selected word line WL to go low. Also, since WO goes low, NW goes high, and all write word lines WWL go high.

[0059] These operations result in the same drive bias states as those of the word line WL, write word line WWL, write bit line WBL, and read bit line RBL in the read operation of FIG.

[0060] When RO is "H", the sense amplifier 31 determines whether the data read from the memory cell 11 is 0 or 1 based on the magnitude relationship between the potential of the read bit line RBL and Vref. In the example of the memory cell 11 shown in FIG. 1, if the potential of the read bit line RBL is greater than Vref, the sense amplifier 31 outputs data "0", and if the potential of the read bit line RBL is equal to or less than Vref, the sense amplifier 31 outputs data "1". When CLK goes "L" and RO goes "L", the sense amplifier 31 is disconnected from the read bit line RBL but retains the data read from the memory cell 11. In other words, the outputs of DOUT and DO are maintained while CLK is "L".

[0061] (Write) When EN and AC are set to "H" and WE is set to "H", if RFR is "L", the memory device 1 performs a write operation. When CLK becomes "H", CE, AE, WA, WO, and BLP become "H", and RA, RO, and BLD become "L". Since BLP becomes "H", the read bit line RBL becomes "L".

[0062] When CE becomes "H", ADDR is taken into the flip-flop circuit 22 and decoded by the word decoder 23, and the selected word line WL becomes "L". Also, since WO becomes "H", NW becomes "L", and the write word line WWL of the selected cell becomes "L-".

[0063] Since BLP goes "H" and BLD goes "L", the write bit line WBL is not charged by the precharge circuit 34p and is not discharged by the predischarge circuit 35d. Since WA is "H", the multiplexer 32 selects DIN and outputs it to the write driver 33 as DI. Since WO is "H", the write driver 33 takes in DI and drives the write bit line WBL to a potential based on the potential of DI. When CLK goes "L" and WO goes "L", the write driver 33 is disconnected from the output of the multiplexer 32 but retains the captured data. In other words, data output is maintained while CLK is "L".

[0064] These operations result in the same drive bias states as those of the word line WL, write word line WWL, write bit line WBL, and read bit line RBL in the write operation of FIG.

[0065] (Refresh) The refresh operation will be described with reference to Fig. 3 and Fig. 7. Fig. 7 is a timing diagram illustrating the refresh operation of the memory device shown in Fig. 3. The refresh operation is roughly divided into reading and rewriting. In the configuration of the memory device 1, reading and rewriting are each performed in one clock cycle.

[0066] [Start of refresh operation (S1)] The timer circuit 4C sets RFR to "H" in synchronization with the falling edge of CLK when a certain fixed time (predetermined time) has elapsed since the previous refresh operation. RFR is also output to the outside, and when RFR is "H", it cannot be accessed from the outside. When RFR becomes "H", CE becomes "H" if CLK is "H", and CE becomes "L" if CLK is "L". When RFR becomes "H", AE becomes "L", AC and WE are invalid, and RA and WA become "L". When RFR becomes "H", the refresh control circuit 4D controls the refresh operation.

[0067] [Read Preparation (S2)] When CLK is "L" (CE is "L"), the refresh control circuit 4D sets RFR_RE and RFR_WE to "L". Since RA and WA are "L", RO and WO become "L". As a result, BLP becomes "H", and the pre-discharge circuit 36d pre-discharges the read bit line RBL.

[0068] [Read (S3)] When CLK is "H" (CE is "H"), the refresh control circuit 4D sets RFR_RE to "H". This causes RO to go to "H" and BLP to go to "L". Since BLP goes to "L", the precharge circuit 34p sets the write bit line WBL to "H" and the predischarge circuit 36d sets the read bit line RBL to a floating state.

[0069] [Read (S4)] Since CLK is "H" (CE is "H"), the refresh control circuit 4D outputs R_ADDR. At this time, RAS is "H", so the multiplexer 21 selects R_ADDR and outputs it as XAD to the flip-flop circuit 22. The flip-flop circuit 22 takes in XAD and outputs it as S_XAD to the word decoder 23. The word decoder 23 decodes S_XAD and sets the word line WL of the selected cell to "L" and the word lines WL of the unselected cells to "H". Since WO is "L", NW goes to "H", and all write word lines WWL go to "H". The potential of the read bit line RBL changes depending on the state of the storage node Q, and this change in potential of the read bit line RBL is read by the sense amplifier 31.

[0070] [Preparing for rewrite (S5)] When CLK goes to "L" (CE is "L"), the refresh control circuit 4D sets RFR-RE to "L". At this time, RFR-WE remains at "L". WA is also at "L". Since RFR-RE goes to "L", RO goes to "L", and the sense amplifier 31 latches and holds the read data. Since WA is "L", the multiplexer 32 selects DO and outputs it as DI. All word lines WL are set to "H".

[0071] [Preparation for rewrite (S6)] Since CLK becomes "L" (CE becomes "L"), BLD becomes "H". Since RO becomes "L", BLP becomes "H". As a result, the write bit line WBL and read bit line RBL are pre-discharged and become "L".

[0072] [Rewrite (S7)] When CLK goes to "H" (CE goes to "H"), the refresh control circuit 4D sets RFR-WE to "H". When CLK goes to "H" (CE goes to "H"), BLD goes to "L", so the write bit line WBL goes to a floating state. Since RFR-WE goes to "H", WO goes to "H", and DI is taken in by the write driver 33. Here, DI is the data held by the sense amplifier 31 in S5. The write driver 33 sets the write bit line WBL to the same state as the data read out in S5.

[0073] [Rewrite (S8)] When CLK goes high (CE goes high), the refresh control circuit 4D outputs the same address as R_ADDR output in S4. The word decoder 23 sets the word line WL of the cell selected in S4 to low, and sets the word lines WL of unselected cells to high. Since WO is high, NW goes low, and the write word line WWL of the selected cell goes low. This causes the data taken into the write driver 33 in S7 to be rewritten to the memory cell 11.

[0074] The address count of the refresh control circuit 4D is advanced, and the operations of S2 to S8 are repeated until all addresses are counted.

[0075] (Modifications) Modifications of the configuration of the memory device in the embodiment will be described with reference to Fig. 5, Fig. 6, and Fig. 8. Fig. 5 is a circuit block diagram showing a modification of the memory device shown in Fig. 3. Fig. 6 is a logic circuit diagram showing an example of the configuration of the access control circuit shown in Fig. 5. Fig. 8 is a timing chart explaining the refresh operation of the memory device shown in Fig. 5.

[0076] The memory device 1 in the embodiment does not accept AC from the outside until the refresh operation of all memory cells is completed, whereas the memory device 1A in this modification accepts AC during the refresh operation.

[0077] The memory cell array 10, row circuit 20, and input / output circuit 30 of the memory device 1A have the same configuration as the respective circuits of the memory device 1. A control circuit 40_A in this modification is partially different from the control circuit 40 in the embodiment. The following description will focus on these differences.

[0078] The control circuit 40_A includes inverter circuits 4A and 4B, a timer circuit 4C, a refresh control circuit (R_CTRL) 4D_A, a clock control circuit 4F, and an access control circuit 4G_A. The access control circuit 4G_A does not include the inverter circuit 43, but is otherwise configured similarly to the access control circuit 4G. However, ACE is input to an AND circuit 44_A.

[0079] AC is input to the refresh control circuit 4D_A. An access permission signal (ACE) from the refresh control circuit 4D_A is input to the access control circuit 4G_A instead of RFR. A wait signal (WAI) is output from the refresh control circuit 4D_A. RFR is not output to the outside of the memory device 1A, but WAI is output. Furthermore, RFR remains at "H" until the refresh operation of all memory cells is completed. Note that the operation of the memory device 1 of this modified example at S1 to S8 shown in FIG. 8 is the same as the operation of S1 to S8 of the memory device 1 shown in FIG. 3.

[0080] When there is an access (AC is set to "H") during a refresh operation (when RFR is in the "H" state), the refresh control circuit 4D_A sets WAI to "H" and ACE to "L" until the operation of the memory cell undergoing the refresh operation is completed. Since ACE becomes "L", AE becomes "L" and AC is disabled. This puts the access on hold. As soon as the refresh operation (operation of S8) is completed, the refresh control circuit 4D_A sets WAI to "L" and ACE to "H" to suspend the refresh operation. Since ACE becomes "H", it becomes possible to input AC and to accept access.

[0081] After the access is completed, the refresh control circuit 4D_A continues the remaining refresh operations from the next address. When the refresh operation is completed, the timer circuit 4C is initialized by RST and RFR is set to "L".

[0082] <Effects of the Embodiment> The effects of the present embodiment will be explained by comparing with a memory cell of a technique (comparative example) that the present inventors have investigated prior to the present disclosure.

[0083] (Comparative Example 1) Fig. 9 is a circuit diagram showing the configuration of a memory cell in Comparative Example 1. Fig. 10 is a diagram showing, in tabular form, the drive biases of the word line and bit line in the retention operation, read operation, and write operation of the memory cell shown in Fig. 9. The memory cell shown in Fig. 9 has the same configuration as the memory cell disclosed in Non-Patent Document 1. The drive biases in each operation shown in Fig. 10 are the same as those disclosed in Non-Patent Document 1, except for the drive bias of the read bit line in the data retention and write modes.

[0084] The memory cell 13 in the comparative example 1 is a 3T type gain cell composed of three transistors. １ , M ２ , M ３ The transistor M １ , M ２ , M ３ are pMOS transistors. The memory cell 13 may be referred to as a "3T-MC."

[0085] Transistor M １ In the transistor M, the gate is connected to the write word line WWL, and either the source or the drain is connected to the write bit line WBL. ２ In this case, the gate of the transistor M １ The source is connected to the other of the source or drain of V ＤＤ The transistor M ３ , the gate is connected to the read word line RWL, and the source is connected to the transistor M ２ The drain of the transistor M is connected to the read bit line RBL.１ and transistor M ２ The connection point of these becomes the storage node Q of the memory cell 13.

[0086] In the holding operation, the read word line RWL, the write word line WWL, and the read bit line RBL are driven to "H", and the write bit line WBL is driven to "L". １ , M ３ is turned off, and the storage node Q maintains the written potential.

[0087] In a read operation, the read word line RWL and the write bit line WBL are driven to "L", the write word line WWL is driven to "H", and the read bit line RBL is "FL:L". When the storage node Q is "L", the transistor M ２ and transistor M ３ is turned on, and as shown by the solid arrow in FIG. ＤＤ A current flows from the power supply wiring that supplies the potential of the read bit line RBL to the read bit line RBL. As a result, the potential of the read bit line RBL rises from "FL:L". When the storage node Q is "H", the transistor M ２ is in the off state, so V ＤＤ Therefore, the potential of the read bit line RBL hardly changes and remains at "FL:L".

[0088] In a write operation, the read word line RWL and the read bit line RBL are driven to "H", the write word line WWL is driven to "L-", and the write bit line WBL is driven to "H" or "L". １ is turned on, the potential input to the write bit line WBL is written to the storage node Q. When the write bit line WBL is at "H", "H" is written to the storage node Q. When the write bit line WBL is at "L", "L" is written to the storage node Q.

[0089] (Comparative Example 2) Fig. 11 is a circuit diagram showing the configuration of a memory cell in Comparative Example 2. Fig. 12 is a diagram showing, in tabular form, the drive biases of the word line and bit line in the retention operation, read operation, and write operation of the memory cell shown in Fig. 11. The memory cell shown in Fig. 11 has a configuration in which the nMOS memory cell disclosed in Non-Patent Document 2 has been changed to a pMOS.

[0090] The memory cell 14 in the comparative example 2 is a 4T type gain cell composed of four transistors. １ , M ２ , M ３ , FBT. １ , M ２ , M ３ , FBT are pMOS transistors. The memory cell 14 may be referred to as a "4T-MC."

[0091] Transistor M １ In the transistor M, the gate is connected to the write word line WWL, and either the source or the drain is connected to the write bit line WBL. ２ , the gate is connected to the write word line WWL, and one of the source and drain is connected to the transistor M １ The transistor M ３ In this case, the gate of the transistor M ２ The gate of the transistor FBT is connected to the other of the source or drain of the transistor M, one of the source or drain is connected to the read bit line RBL, and the other of the source or drain is connected to the read word line RWL. ２ The source is connected to the other of the source or drain of the transistor M １ and the drain is connected to the other of the source or drain of V ＳＳ The transistor M ２ and transistor M ３ The connection point of these becomes the storage node Q of the memory cell 14.

[0092] In the holding operation, the write word line WWL is driven to "H", and the read word line RWL, write bit line WBL, and read bit line RBL are driven to "L". １ , M ２ is turned off, and the storage node Q maintains the written potential.

[0093] In a read operation, the read word line RWL and the write word line WWL are driven to "H", the write bit line WBL is driven to "L", and the read bit line RBL is "FL:L". When the storage node Q is "L", the transistor M ３ is turned on, and a current flows from the read word line RWL to the read bit line RBL as shown by the solid arrow in FIG. 11. This causes the potential of the read bit line RBL to rise from "FL:L". When the storage node Q is "H", the transistor M ３ is in the OFF state, no current flows from the read word line RWL to the read bit line RBL. As a result, the potential of the read bit line RBL hardly changes and remains at "FL:L".

[0094] In a write operation, the read word line RWL and the read bit line RBL are driven to "L", the write word line WWL is driven to "L-", and the write bit line WBL is driven to "H" or "L". １ , M ２ is turned on, the potential input to the write bit line WBL is written to the storage node Q. When the write bit line WBL is at "H", "H" is written to the storage node Q. When the write bit line WBL is at "L", "L" is written to the storage node Q.

[0095] The 3T-MC in Comparative Example 1 has a large leakage current and a short data retention time. The reason for this will be explained using Figure 13. Figure 13 is a diagram for explaining the leakage current of a memory cell.

[0096] In the 3T-MC, for example, when the storage node Q of an unselected memory cell is at "L" and "H" is applied to the write bit line WBL, as shown by the solid arrow, the transistor M１ Subthreshold leakage current (I Ｌ ) causes charge to flow into the storage node Q. When the storage node Q of an unselected memory cell is at "H" and "L" is applied to the write bit line WBL, charge is discharged from the storage node Q by a subthreshold leakage current as shown by the dashed arrow in FIG. 13. This makes the data retention time very short. Note that the transistor M １ When the transistor is a pMOS, charge inflow occurs more easily than charge discharge. Subthreshold leakage current is also called subthreshold current.

[0097] The 4T-MC in Comparative Example 2 has a smaller leakage current and a longer data retention time than the 3T-MC. This will be explained with reference to FIG. １ , M ２ When the transistor is a pMOS, the inflow of charges is more likely to occur than the discharge of charges, as in the case of 3T-MC. Therefore, the case of the inflow of charges will be explained below.

[0098] In the 4T-MC, for example, when the storage node Q of an unselected memory cell is at "L" and "H" is applied to the write bit line WBL, as shown by the solid arrow, the transistor M １ When the storage node Q is at "L", the gate of the transistor FBT is at "L", so that the potential from the node ND is V ＳＳ As a result, the charge flowing into the node ND decreases. Since the potential difference between the node ND and the storage node Q does not increase, the transistor M ２ It is possible to suppress the inflow of charges due to the subthreshold leakage current in the transistor M ２ , M ３ There is an inflow of charges due to gate leakage current and junction leakage current from the gate electrode. However, the gate leakage current and junction leakage current are smaller than the subthreshold leakage current. This allows the data retention time of 4T-MC to be longer than that of 3T-MC.

[0099] The P3T-MC in the embodiment also has a smaller leakage current and a longer data retention time than the 3T-MC. This will be explained with reference to FIG. １ , M ２ When the transistor is a pMOS, the inflow of charges is more likely to occur than the discharge of charges, as in the case of 3T-MC. Therefore, the case of the inflow of charges will be explained below.

[0100] In the P3T-MC, for example, when the storage node Q of an unselected memory cell is at "L" and "H" is applied to the write bit line WBL, as shown by the solid arrow, the transistor M １ When the storage node Q is at "L", the gate of the transistor FBT is at "L", so a current flows from the node ND to the read bit line RBL. As a result, the charge flowing into the node ND decreases. Since the potential difference between the node ND and the storage node Q does not increase, the potential difference between the node ND and the storage node Q does not increase. ２ It is possible to suppress the inflow of charges due to the subthreshold leakage current in the transistor M ２ , M ３ There is an inflow of charges due to gate leakage current and junction leakage current from the gate electrode. However, the gate leakage current and junction leakage current are smaller than the subthreshold leakage current. This allows the data retention time of P3T-MC to be longer than that of 3T-MC and equivalent to that of 4T-MC.

[0101] Since 4T-MC does not have a gate-controlled selector transistor, read disturbance and increased power consumption can occur. This will be explained using Figure 14. Figure 14 is a diagram for explaining read disturbance of a memory cell.

[0102] In the 4T-MC, for example, assume that "L" is stored in the storage node Q[0] of the memory cell 14[0] in the 0th row and the storage node Q[1] of the memory cell 14[1] in the 1st row. In this case, when reading the memory cell 14[0] in the 0th row, as shown by the solid arrow in FIG. ３ In other words, when reading "L", a current flows from the selected cell to the unselected cell storing "L". The potential ΔV of the read bit line RBL is ３ This depends on the threshold voltage of the memory cell and the number of cells storing "L" (voltage division ratio), and there is a possibility of read disturbance, and power consumption increases.

[0103] Since P3T-MC has a gate-controlled selector transistor, the read disturbance and increased power consumption that occur in 4T-MC do not occur. This will be explained with reference to FIG.

[0104] In P3T-MC, for example, assume that "L" is stored in the storage node Q[0] of the memory cell 11[0] in the 0th row and the storage node Q[1] of the memory cell 11[1] in the 1st row. In this case, when reading the memory cell 11[0] in the 0th row, the gate-controlled selector transistor M １ Therefore, no current flows through the transistor FBT of the memory cell 11[1] in the first row, and power consumption does not increase.

[0105] The data retention times of memory cells in Comparative Example 1, Comparative Example 2, and the embodiment will be described with reference to Fig. 15 and Fig. 16. Fig. 15 is a diagram showing the transition of potential at the storage node of memory cells in Comparative Example 1, Comparative Example 2, and the embodiment. Fig. 16 is a diagram showing a comparison of the data retention times of memory cells in Comparative Example 1, Comparative Example 2, and the embodiment.

[0106] In all of the 3T-MC, 4T-MC, and P3T-MC, all transistors are pMOS high threshold (LSTP: Low Standby Power) devices, configured with the minimum size (L = 60 nm, W = 140 nm). The data retention time (DRT) is defined as the time when VQH - VQL = 100 mV. The horizontal axis of Figure 15 is the time (NT) normalized by the average value of the 3T-MC of Comparative Example 1, and the vertical axis is the time when V ＤＤ = 1.2V, V ＳＳ = 0V. The DRT varies, but only the central value is shown. The vertical axis of the graph shown in Figure 16 is the normalized average DRT (NA_DRT). This DRT is evaluated using the mean value (μ) of the distribution obtained from the Monte Carlo simulation and is normalized by the mean value of the DRT of 3T-MC.

[0107] In any of 3T-MC, 4T-MC, and P3T-MC, when the potential of the storage node Q is "H" and the potential of the write bit line WBL is "L", charge tends to flow out. When the potential of the storage node Q is "L", and the potential of the write bit line WBL is "H", charge tends to flow in. In Figure 15, the former case is shown by a dashed line, and the latter case is shown by a solid line, showing the transition of the potential at the storage node.

[0108] As shown in Figure 15, in all of 3T-MC, 4T-MC, and P3T-MC, the inflow of charge to storage node Q is greater than the outflow. As shown in Figure 16, the DRT of P3T-MC is almost the same as that of 4T-MC, and is about 10 times that of 3T-MC. The DRT of P3T-MC is about a few ms.

[0109] The cell area will be described with reference to FIGS. 17 and 18. FIG. 17 is a diagram showing examples of cell layouts of memory cells in Comparative Example 1, Comparative Example 2, and the embodiment. FIG. 18 is a diagram showing a comparison of the cell areas of memory cells in Comparative Example 1, Comparative Example 2, and the embodiment. The vertical axis of the graph shown in FIG. 18 is cell area (CA).

[0110] Using the 60 nm CMOS logic design rule, the cell layouts of 3T-MC, 4T-MC, and P3T-MC were created. The cell layout of P3T-MC is explained below. The diffusion layer is represented by a dashed line, the gate electrode layer by a solid line, the metal layer by a dashed line, and the contact by a square with an x.

[0111] The diffusion layer of the transistor FBT extends in the Y1-Y2 direction, and the gate electrode layer extends in the X1-X2 direction. １ The transistor M is disposed on the Y1 side of the diffusion layer of the transistor M. ２ The diffusion layer of the transistor M １ and is disposed on the X1 direction side of the diffusion layer of the transistor FBT. When the gate electrode layer and the diffusion layer are connected to a metal layer, they are connected via contacts.

[0112] Transistor M １ The gate electrode layer of the transistor M is connected to the metal layer that forms the word line WL. １ The diffusion layer of the first terminal is connected to a metal layer that constitutes the write bit line WBL.

[0113] Transistor M ２ The gate electrode layer of the transistor M is connected to a metal layer that forms the write word line WWL. ２ The diffusion layer of the first terminal of the transistor M １ The node ND is connected to the diffusion layer of the second terminal of the first transistor via a metal layer. The node ND is, for example, the metal layer.

[0114] The gate electrode layer of the transistor FBT is ２ The memory node Q is, for example, the metal layer. The diffusion layer of the first terminal of the transistor FBT is connected to the diffusion layer of the second terminal of the transistor M. １ The diffusion layer of the second terminal of the transistor FBT is directly connected to the metal layer that forms the read bit line RBL.

[0115] The cell size of 3T-MC is 0.58 μm×0.99 μm, the cell size of 4T-MC is 1.02 μm×0.97 μm, and the cell size of P3T-MC is 0.68 μm×0.96 μm.

[0116] As shown in Figure 18, the cell area of ​​4T-MC is only 24% less than that of 6T-SRAM. The cell area of ​​P3T-MC can be reduced by 34% from that of 4T-MC and 50% from that of 6T-SRAM, making it comparable to the cell area of ​​3T-MC. Here, 6T-SRAM is an SRAM consisting of six transistors.

[0117] This embodiment has at least one of the following effects.

[0118] (a) P3T-MC can maintain data retention times comparable to those of 4T-MC, and can achieve longer data retention times than 3T-MC. This allows memories using P3T-MC to have longer refresh intervals and consume less current than memories using 3T-MC.

[0119] (b) P3T-MC can suppress the read disturbance that occurs in 4T-MC, which allows a memory using P3T-MC to consume less current than a memory using 4T-MC.

[0120] (c) The cell area of ​​P3T-MC can be made smaller than that of 4T-MC, so that a memory using P3T-MC can have a smaller area than a memory using 4T-MC.

[0121] [Another Aspect] <Memory Cell> An example of the configuration of a memory cell in another aspect will be described with reference to Fig. 19. Fig. 19 is a circuit diagram showing an example of the configuration of a memory cell in another aspect.

[0122] The memory cell 11n is a 3T type gain cell composed of three transistors. The memory cell 11n has a storage node Q, a node ND, and a transistor M. １ , M ２ , FBT and a transistor M １, M ２ , FBT are, for example, nMOS transistors.

[0123] Transistor M １ In the transistor M, the gate is connected to the word line WL, and one of the source and the drain (first terminal) is connected to the write bit line WBL. ２ , the gate is connected to the write word line WWL, and one of the source and drain (first terminal) is connected to the transistor M １ In the transistor FBT, the gate is connected to the other of the source and drain (second terminal) of the transistor M ２ and one of the source and drain (first terminal) of the transistor M １ and transistor M ２ The other of the source and drain (second terminal) is connected to the read bit line RBL. ２ The connection point between the transistor FBT and the memory cell 11n becomes the storage node Q of the memory cell 11n.

[0124] <Operation of Memory Cell> FIG. 20 is a diagram showing, in a table format, an example of the drive biases of the word lines and bit lines in the holding operation, read operation, and write operation of the memory cell shown in FIG.

[0125] (Retention Operation) In the retention operation, the word line WL and the write word line WWL are driven to "L", and the write bit line WBL and the read bit line RBL are driven to "H". １ , M ２ is turned off, and the storage node Q maintains the potential it holds.

[0126] (Read Operation) In the case of a read operation, the word line WL of the selected memory cell 11n is driven to "H", the write word line WWL and write bit line WBL are driven to "L", and the read bit line RBL is "FL:H". "FL:H" is called a high level floating, and is a state in which the memory cell is floating after being precharged.

[0127] When the storage node Q is at "H", the transistor FBT is in an ON state. Also, since the word line WL is driven to "H", the transistor M １ is in the on state. １ 19. As a result, the read bit line RBL is discharged, and the potential of the read bit line RBL drops from "H". When the storage node Q is "L", the transistor FBT is in the off state, so no current flows from the read bit line RBL to the write bit line WBL. As a result, the potential of the read bit line RBL hardly changes, and remains "FL:H".

[0128] The word line WL, write word line WWL, and write bit line WBL of the unselected memory cell 11n are driven to "L", and the read bit line RBL is "FL:H". １ , M ２ is in the OFF state, the storage node Q maintains the potential it holds.

[0129] (Write Operation) In the write operation, the word line WL of the selected memory cell 11n is driven to "H", the write word line WWL is driven to "H+", the write bit line WBL is driven to "H" or "L", and the read bit line RBL is driven to "H". "H+" is V ＤＤ "H+" is called the overdrive high level (VOH).

[0130] Transistor M １ and transistor M ２ is turned on, the potential input to the write bit line WBL is written to the storage node Q. When the write bit line WBL is at "H", "H" is written to the storage node Q. When the write bit line WBL is at "L", "L" is written to the storage node Q.

[0131] The word line WL and write word line WWL of the unselected memory cell 11n are driven to "L", the write bit line WBL is driven to "H" or "L", and the read bit line RBL is driven to "H". １ , M ２ is in the OFF state, the storage node Q maintains the potential it holds.

[0132] A memory device 2 that drives the memory cell shown in Fig. 19 with the drive bias shown in Fig. 20 will be described with reference to Fig. 21. Fig. 21 is a circuit block diagram showing an example of the configuration of a memory device that drives with the drive bias shown in Fig. 20.

[0133] 3, the memory device 2 changes the precharge circuit 34p connected to the write bit line WBL to a predischarge circuit 34d, and the predischarge circuit 35d to a precharge circuit 35p. Also, the predischarge circuit 36d connected to the read bit line RBL is changed to a precharge circuit 36p. The precharge circuit 35p as the second charge circuit is composed of, for example, a pMOS transistor. The gate of this pMOS transistor is connected to a wiring that supplies BLD, and the source is connected to V ＤＤ The drain is connected to a power supply line that supplies the potential of the write bit line WBL.

[0134] Also, the switch circuit 37 is changed to a switch circuit 37n. The pre-discharge circuit 38d is changed to a pre-charge circuit 38p. The switch circuit 37n is made up of, for example, a pMOS transistor, one of the source or the drain of which is connected to the read bit line RBL, the other of which is connected to the sense amplifier 31, and the gate of which is connected to a line that supplies an inverted signal of RO. The pre-charge circuit 38p is made up of, for example, a pMOS transistor, the gate of which is connected to a line that supplies RO, and the source of which is connected to V ＤＤ The drain is connected to a power supply line that supplies a potential of 0 V, and the drain is connected to a read bit line RBL.

[0135] In addition, the memory device 2 changes the word line driver of the word decoder 23 in the memory device 1 to a word decoder 23n that inverts the polarity, changes the write word line driver 24 of an OR circuit to a write word line driver 24n of an AND circuit, and deletes the inverter circuits 4A and 4B. In addition, the memory device 2 changes to a sense amplifier 31n that reverses the 0 / 1 determination of the sense amplifier 31.

[0136] Other configurations of the memory device 2 are the same as those of the memory device 1. Note that the memory device 2 can accept AC during a refresh operation by using the control circuit 40_A of the memory device 1A.

[0137] Note that the drive biases of the word line and bit line in each operation of the memory cell 11n shown in Fig. 19 can be other than those shown in Fig. 20. For example, the bit line may be driven biased so that the direction of the current in the read operation is opposite to that in Fig. 20.

[0138] The operation of the other embodiment will be described with reference to Fig. 22. Fig. 22 is a diagram for explaining the operation of the memory cell of the other embodiment.

[0139] As shown in MC of FIG. 22, the memory cell 11n includes a transistor M １ , M ２ , FBT are composed of nMOS transistors. １ , M ２ In the memory cell 11n, for example, when the storage node Q of the unselected memory cell is at "H" and "L" is applied to the write bit line WBL, the transistor M １ When the storage node Q is at "H", the gate of the transistor FBT is at "H", so that charge flows from the read bit line RBL to the node ND. As a result, the charge flowing out from the node ND decreases. Since the potential difference between the node ND and the storage node Q does not increase, the potential difference between the node ND and the storage node Q does not increase, so that the potential difference between the node ND and the transistor M ２In other aspects, the memory cell has the same effects as the embodiment.

[0140] 22, in a memory cell array made up of memory cells 11n, for example, assume that "H" is stored in the storage node Q[0] of 11n[0] in the 0th row and the storage node Q[1] of 11n[1] in the 1st row. In this case, when reading out 11n[0] in the 0th row, the gate-controlled selector transistor M １ Therefore, no current flows through the transistor FBT of 11n[1] in the first row. Therefore, the memory cell in the other aspects has the same effect as the embodiment.

[0141] The disclosure made by the present inventors has been specifically described above based on embodiments and modified examples, but the present disclosure is not limited to the above-described embodiments and modified examples and can be modified in various ways.

[0142] 11...Memory cell M １ ...Transistor (first transistor) M ２ . . transistor (second transistor) FBT . . . transistor (third transistor) Q . . . storage node RBL . . . read bit line (second bit line) WBL . . . write bit line (first bit line) WL . . . word line (first word line) WWL . . . write word line (second word line)

Claims

1. A semiconductor device comprising: a memory cell having a first transistor, a second transistor, and a third transistor; a first word line, a second word line, a first bit line, and a second bit line; wherein the gate, first terminal, and second terminal of the first transistor are connected to the first word line, the first bit line, and the first terminal of the second transistor, respectively; the gate and second terminal of the second transistor are connected to the second word line and the gate of the third transistor, respectively; the first terminal and second terminal of the third transistor are connected to the first terminal of the second transistor and the second bit line, respectively; the first transistor, the second transistor, and the third transistor have the same conductivity type; a node connecting the second terminal of the second transistor and the gate of the third transistor is a storage node that stores data; and the first word line controls the on / off of the first transistor, the second word line controls the on / off of the second transistor, and data is written to, stored in, or read from the memory cell by controlling at least one of the first bit line and the second bit line to a predetermined potential.

2. A semiconductor device according to claim 1, wherein, when data in the memory cell is to be retained, the first word line turns off the first transistor, the second word line turns off the second transistor, and the first bit line and the second bit line are set to a predetermined potential.

3. A semiconductor device according to claim 1, wherein when data is read from the memory cell, the first word line turns on the first transistor, the second word line turns off the second transistor, the first bit line is set to a predetermined potential, and the second bit line is made floating.

4. A semiconductor device according to claim 1, wherein when data is written to the memory cell, the first word line turns on the first transistor, the second word line turns on the second transistor, the first bit line is set to a potential corresponding to the data to be written, and the second bit line is set to a predetermined potential.

5. The semiconductor device of claim 1, further comprising peripheral circuits including: a first drive circuit for driving the first word line to a high level potential and a low level potential; a second drive circuit for driving the second word line to a high level potential and a potential lower than the low level potential; a third drive circuit for driving the first bit line to a high level potential and a low level potential; and a read circuit for comparing the potential of the second bit line with a predetermined potential and outputting a potential based on the comparison result.

6. A semiconductor device according to claim 5, wherein the peripheral circuit further comprises: a first charge circuit that charges the first bit line to a high level potential; a second charge circuit that discharges the first bit line to a low level potential; and a third charge circuit that discharges the second bit line to a low level potential.

7. The semiconductor device of claim 1, further comprising peripheral circuits including: a first drive circuit for driving the first word line to a high level potential and a low level potential; a second drive circuit for driving the second word line to a high level potential and a low level potential higher than the high level potential; a third drive circuit for driving the first bit line to a high level potential and a low level potential; and a read circuit for comparing the potential of the second bit line with a predetermined potential and outputting a potential based on the comparison result.

8. A semiconductor device according to claim 7, wherein the peripheral circuit further comprises: a first charge circuit that discharges the first bit line to a low level potential; a second charge circuit that charges the first bit line to a high level potential; and a third charge circuit that charges the second bit line to a high level potential.

9. A semiconductor device according to any one of claims 1 to 8, further comprising a control circuit including a refresh control circuit, wherein the control circuit is configured to, when an activated access signal is input from the outside during a refresh, output a wait signal to the outside until the operation of the memory cell undergoing the refresh operation is completed, enable access as soon as the refresh operation is completed, and perform the remaining refresh after the access is completed.

10. A memory cell comprising: a first word line, a second word line, a first bit line, a second bit line, and a memory cell, wherein the memory cell comprises: a first transistor having a gate, a first terminal, and a second terminal, the gate and the first terminal being connected to the first word line and the first bit line, respectively; a first node connected to the second terminal of the first transistor; a second transistor having a gate, a first terminal, and a second terminal, the gate and the first terminal being connected to the second word line and the first node, respectively; a second node connected to the second terminal of the second transistor and holding data; and a third transistor having a gate, a first terminal, and a second terminal, the gate and the first terminal being connected to the second node, the first node, and the second bit line, respectively; A semiconductor device configured such that the first word line controls the on / off of the first transistor, the second word line controls the on / off of the second transistor, and at least one of the first bit line and the second bit line is controlled to a predetermined potential, thereby writing, retaining, or reading data from the memory cell.

11. A memory cell comprising: a first word line, a second word line, a first bit line, a second bit line, and a memory cell, wherein the memory cell comprises: a first transistor having a gate, a first terminal, and a second terminal, the gate and the first terminal being connected to the first word line and the first bit line, respectively; a first node connected to the second terminal of the first transistor; a second transistor having a gate, a first terminal, and a second terminal, the gate and the first terminal being connected to the second word line and the first node, respectively; a second node connected to the second terminal of the second transistor and holding data; and a third transistor having a gate, a first terminal, and a second terminal, the gate and the first terminal being connected to the second node, the first node, and the second bit line, respectively; the first transistor, the second transistor, and the third transistor having the same conductivity type; and the first transistor, the second transistor, and the third transistor being configured as nMOS, A semiconductor device configured such that, when the first word line turns off the first transistor, the second word line turns off the second transistor, the first bit line is at a low potential, the second bit line is at a high potential, and the second node is holding a high potential, when charge flows out of the first node due to a subthreshold current of the first transistor, charge flows into the first node from the second bit line by turning on the third transistor.

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