Semiconductor device and electronic apparatus

Abstract

Provided is a semiconductor device including a first transistor and a second transistor connected in series by sharing a source / drain, the first transistor having a first gate electrode provided on a first surface of a first semiconductor substrate, the second transistor having a second gate electrode provided on a second surface of the first semiconductor substrate facing the first surface, and the first gate electrode and the second gate electrode at least partially overlapping when viewed from above the first semiconductor substrate.

Description

Semiconductor devices and electronic devices

[0001] The present disclosure relates to a semiconductor device and an electronic device.

[0002] In recent years, attempts have been made to further miniaturize and integrate imaging devices (photodetection devices), which are a type of semiconductor device. One such attempt is an imaging device with a stacked structure. An example of such a device is the imaging device disclosed in Patent Document 1 listed below. The technology disclosed in Patent Document 1 achieves miniaturization of the imaging device by stacking and bonding a first layer provided with imaging elements (photodetection elements) and a second layer provided with a readout circuit including a plurality of pixel transistors that read pixel signals from each imaging element.

[0003] International Publication No. 2017 / 138197

[0004] However, in the efforts to further miniaturize and integrate imaging devices, there has been little in-depth research into technologies for improving various characteristics, such as the noise characteristics of transistors and the photoelectric conversion efficiency of imaging devices.

[0005] Therefore, the present disclosure proposes a technique that enables semiconductor devices (photodetectors, imaging devices) to be miniaturized and integrated, while further improving various characteristics.

[0006] According to the present disclosure, there is provided a semiconductor device including a first transistor and a second transistor connected in series by sharing a source / drain, the first transistor having a first gate electrode provided on a first surface of a first semiconductor substrate, the second transistor having a second gate electrode provided on a second surface of the first semiconductor substrate opposite to the first surface, and when viewed from above the first semiconductor substrate, the first gate electrode and the second gate electrode at least partially overlap each other.

[0007] Furthermore, according to the present disclosure, there is provided an electronic device equipped with a semiconductor device, the semiconductor device including a first transistor and a second transistor connected in series by sharing a source / drain, the first transistor having a first gate electrode provided on a first surface of a first semiconductor substrate, the second transistor having a second gate electrode provided on a second surface of the first semiconductor substrate opposite to the first surface, and when viewed from above the first semiconductor substrate, the first gate electrode and the second gate electrode at least partially overlap each other.

[0008] 4A . A plan view showing an example of a planar configuration of an imaging device 1 according to an embodiment of the present disclosure. An equivalent circuit diagram of a pixel 12 and a readout circuit 22. A plan view showing an example of a planar configuration of a readout circuit 22a according to a comparative example. A cross-sectional view when a part of the readout circuit 22a is cut along line A-A' and line B-B' shown in FIG. 3A. A cross-sectional view showing an example of a cross-sectional configuration of a main part of the readout circuit 22 according to the first embodiment of the present disclosure. A cross-sectional view when a main part of the readout circuit 22 is cut along line C-C' shown in FIG. 4A. A plan view showing an example of a planar configuration of a main part of the readout circuit 22 according to the first embodiment of the present disclosure. A cross-sectional view showing an example of a cross-sectional configuration of a main part of the readout circuit 22 according to Modification 1 of the first embodiment of the present disclosure. A plan view showing an example of a planar configuration of a main part of the readout circuit 22 according to Modification 1 of the first embodiment of the present disclosure. A plan view showing an example of a planar configuration of a main part of the readout circuit 22 according to Modification 2 of the first embodiment of the present disclosure. A cross-sectional view showing an example of a cross-sectional configuration of a main part of the readout circuit 22 according to Modification 2 of the first embodiment of the present disclosure. FIG. 1 is a cross-sectional view (part 1) showing an example cross-sectional configuration of a main part of a readout circuit 22 according to a second embodiment of the present disclosure. FIG. 2 is a cross-sectional view (part 2) showing an example cross-sectional configuration of a main part of a readout circuit 22 according to a second embodiment of the present disclosure. FIG. 1 is a cross-sectional view (part 1) showing an example cross-sectional configuration of a main part of a readout circuit 22 according to a fourth embodiment of the present disclosure. FIG. 2 is a cross-sectional view (part 2) showing an example cross-sectional configuration of a main part of a readout circuit 22 according to a fourth embodiment of the present disclosure. FIG. 3 is a cross-sectional view (part 3) showing an example cross-sectional configuration of a main part of a readout circuit 22 according to a fourth embodiment of the present disclosure. FIG. 1 is a cross-sectional view showing an example cross-sectional configuration of a main part of a readout circuit 22 according to a modification of the fourth embodiment of the present disclosure. FIG. 2 is a plan view showing an example planar configuration of a main part of a readout circuit 22 according to a fifth embodiment of the present disclosure. FIG. 3 is a cross-sectional view showing an example cross-sectional configuration of a main part of a readout circuit 22 according to a fifth embodiment of the present disclosure. FIG. 4 is a cross-sectional view showing an example cross-sectional configuration of a main part of a readout circuit 22 according to a first modification of the fifth embodiment of the present disclosure. 10A and 10B are plan and cross-sectional views showing an example of a planar configuration of a main part of a readout circuit 22 according to a second modification of the fifth embodiment of the present disclosure;12B is a plan view showing an example of a planar configuration of a main part of a readout circuit 22 according to a sixth embodiment of the present disclosure. FIG. 12C is a cross-sectional view when cutting a main part of the readout circuit 22 along line DD' shown in FIG. 12A. FIG. 12D is a cross-sectional view showing an example of a cross-sectional configuration of a main part of a readout circuit 22 according to a modified example of the sixth embodiment of the present disclosure. FIG. 12E is a cross-sectional view (part 1) showing an example of a cross-sectional configuration of an imaging device 1 according to a seventh embodiment of the present disclosure. FIG. 12F is a cross-sectional view (part 2) showing an example of a cross-sectional configuration of an imaging device 1 according to a seventh embodiment of the present disclosure. FIG. 12G is a cross-sectional view (part 1) showing an example of a manufacturing method of an imaging device 1 according to an eighth embodiment of the present disclosure. FIG. 12H is a cross-sectional view (part 2) showing an example of a manufacturing method of an imaging device 1 according to an eighth embodiment of the present disclosure. FIG. 12H is a cross-sectional view (part 3) showing an example of a manufacturing method of an imaging device 1 according to an eighth embodiment of the present disclosure. FIG. 12I is a block diagram showing an example of a schematic functional configuration of a smartphone. FIG. 12J is a diagram showing an example of a schematic configuration of an endoscopic surgery system. FIG. 12I is a block diagram showing an example of a functional configuration of a camera head and a CCU. FIG. 12I is a block diagram showing an example of a schematic configuration of a vehicle control system. FIG. 12I is an explanatory diagram showing an example of installation positions of an outside vehicle information detection unit and an imaging unit.

[0009] Preferred embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. In this specification and the drawings, components having substantially the same functional configurations are designated by the same reference numerals, and redundant description will be omitted. Furthermore, in this specification and the drawings, multiple components having substantially the same or similar functional configurations may be distinguished by adding different letters after the same reference numeral. However, when there is no particular need to distinguish between multiple components having substantially the same or similar functional configurations, only the same reference numerals will be used.

[0010] The drawings referred to in the following description are for explaining and facilitating understanding of one embodiment of the present disclosure, and for the sake of clarity, the shapes, dimensions, ratios, etc. shown in the drawings may differ from the actual ones. Furthermore, the design of the devices shown in the drawings can be modified as appropriate, taking into consideration the following description and known technologies.

[0011] In the following description of circuits (electrical connections), unless otherwise specified, "electrically connected" means connecting multiple elements so that electricity (signals) is conducted between them. In addition, in the following description, "electrically connected" includes not only cases where multiple elements are directly and electrically connected, but also cases where elements are indirectly and electrically connected via other elements.

[0012] In the following description, "sharing" means that different elements (such as transistors) share one other element (such as a diffusion region).

[0013] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the drawings. The description will be made in the following order: 1. Schematic configuration of an imaging device 2. Background 3. First embodiment 3.1 Detailed configuration 3.2 Modified example 4. Second embodiment 5. Third embodiment 6. Fourth embodiment 6.1 Detailed configuration 6.2 Modified example 7. Fifth embodiment 7.1 Detailed configuration 7.2 Modified example 8. Sixth embodiment 8.1 Detailed configuration 8.2 Modified example 9. Seventh embodiment 10. Eighth embodiment 11. Summary 12. Application examples 12.1 Application example to a smartphone 12.2 Application example to an endoscopic surgery system 12.3 Application example to a mobile object 13. Supplementary information

[0014] <<1. Schematic Configuration of Imaging Device>> A schematic configuration of an imaging device 1 according to an embodiment of the present disclosure will be described as an example of a semiconductor device with reference to FIG. 1 . FIG. 1 is a plan view showing an example of the planar configuration of the imaging device 1 according to an embodiment of the present disclosure. The imaging device 1 has three substrates (a first substrate 10, a second substrate 20, and a third substrate 30). The imaging device 1 has a three-dimensional structure formed by bonding together the three substrates (the first substrate 10, the second substrate 20, and the third substrate 30). The first substrate 10, the second substrate 20, and the third substrate 30 are stacked in this order.

[0015] The first substrate 10 has a semiconductor substrate 11 on which a plurality of pixels 12 perform photoelectric conversion. The semiconductor substrate 11 corresponds to a specific example of a "second semiconductor substrate" in the present disclosure. The plurality of pixels 12 are arranged in a matrix within a pixel region 13 of the first substrate 10. The second substrate 20 has a semiconductor substrate 21 on which a readout circuit 22 outputs pixel signals based on electric charges output from the pixels 12. The semiconductor substrate 21 corresponds to a specific example of a "first semiconductor substrate" in the present disclosure. The second substrate 20 has a plurality of pixel drive lines 23 extending in the row direction and a plurality of vertical signal lines 24 extending in the column direction. The third substrate 30 has a semiconductor substrate 31 on which a logic circuit 32 processes pixel signals. The logic circuit 32 includes, for example, a vertical drive circuit 33, a column signal processing circuit 34, a horizontal drive circuit 35, and a system control circuit 36. The logic circuit 32 (specifically, the horizontal drive circuit 35) outputs an output voltage Vout for each pixel 12 to the outside.

[0016] The vertical drive circuit 33, for example, sequentially selects a plurality of pixels 12 row by row. The column signal processing circuit 34, for example, performs analog-to-digital (AD) conversion processing and correlated double sampling (CDS) processing on pixel signals output from each pixel 12 in the row selected by the vertical drive circuit 33. The column signal processing circuit 34 extracts the signal level of the pixel signal by performing CDS processing, for example, and holds pixel data corresponding to the amount of light received by each pixel 12. The horizontal drive circuit 35, for example, sequentially outputs the pixel data held in the column signal processing circuit 34 to the outside. The system control circuit 36, for example, controls the driving of each block (the vertical drive circuit 33, the column signal processing circuit 34, and the horizontal drive circuit 35) in the logic circuit 32.

[0017] Note that, in the embodiment of the present disclosure, the imaging device 1 is not limited to being composed of the first to third substrates 10, 20, and 30. For example, in the embodiment of the present disclosure, the pixels 12, the readout circuit 22, and the logic circuit 32 may be provided on one substrate, or the pixels 12, the readout circuit 22, and the logic circuit 32 may be provided on each of two substrates. Furthermore, the pixels 12, the readout circuit 22, and the logic circuit 32 may be provided across multiple substrates. Furthermore, these substrates or other substrates may be equipped with memory or circuits having AI (artificial intelligence) functions. In addition, other substrates may be stacked on the first to third substrates 10, 20, and 30. Furthermore, the substrate of the pixel 12 may be provided with elements that detect not only visible light but also light of other wavelengths.

[0018] Fig. 2 is an equivalent circuit diagram of an example of a pixel 12 and a readout circuit 22. The pixel 12 shown in Fig. 2 is provided on, for example, a first substrate 10. The pixel 12 further includes a photoelectric conversion unit (photodiode: PD) 101, a transfer transistor (TG) 102 electrically connected to the photoelectric conversion unit 101, and a floating diffusion (FD) (charge accumulation unit) 103 that temporarily accumulates charges output from the photoelectric conversion unit 101 via the transfer transistor 102.

[0019] The photoelectric conversion unit 101 is formed of, for example, a PN junction photodiode, and performs photoelectric conversion to generate charges corresponding to the amount of light received. The cathode of the photoelectric conversion unit 101 is electrically connected to the source of the transfer transistor 102, and the anode of the photoelectric conversion unit 101 is electrically connected to a reference potential line (e.g., ground (GND)). The drain of the transfer transistor 102 is electrically connected to the floating diffusion 103, and the gate of the transfer transistor 102 is electrically connected to the pixel drive line 23. When the transfer transistor 102 is turned on, the transfer transistor 102 transfers the charges generated in the photoelectric conversion unit 101 to the floating diffusion 103. The floating diffusion 103 accumulates the charges transferred from the photoelectric conversion unit 101 and converts the accumulated charges into an electrical signal, for example, a voltage signal, and outputs the electrical signal. The transfer transistor 102 is, for example, a complementary metal oxide semiconductor (CMOS) transistor.

[0020] The readout circuit 22 is provided on, for example, the second substrate 20. The readout circuit 22 further includes, for example, a reset transistor (RST) 201, an amplification transistor (AMP) 202, a selection transistor (SEL) 203, and a conversion efficiency switching transistor (FDG) 204. Hereinafter, these transistors are collectively referred to as "pixel transistors." The selection transistor 203 and the conversion efficiency switching transistor 204 may be omitted as necessary. The source of the reset transistor 201 (the input terminal of the readout circuit 22) is electrically connected to the floating diffusion 103, and the drain of the reset transistor 201 is electrically connected to the power supply line VDD and the drain of the amplification transistor 202. The gate of the reset transistor 201 is electrically connected to the pixel drive line 23 (see FIG. 1 ). The source of the amplification transistor 202 is electrically connected to the drain of the selection transistor 203, and the gate of the amplification transistor 202 is electrically connected to the source of the reset transistor 201 and the floating diffusion 103. The source of the selection transistor 203 (the output terminal of the readout circuit 22) is electrically connected to the vertical signal line 24, and the gate of the selection transistor 203 is electrically connected to the pixel drive line 23 (see FIG. 1 ). Furthermore, the drain of the conversion efficiency switching transistor 204 is electrically connected to the floating diffusion 103, and the source of the conversion efficiency switching transistor 204 is electrically connected to an additional capacitance section (Sub-FD) (additional charge storage section) 205.

[0021] The reset transistor 201 resets the potential of the floating diffusion 103 to a predetermined potential. When the reset transistor 201 is turned on, the potential of the floating diffusion 103 is reset to the potential of the power supply line VDD. The selection transistor 203 controls the output timing of a voltage signal (pixel signal) from the readout circuit 22. The amplification transistor 202 generates (converts into) a voltage signal according to the level of charge accumulated in the floating diffusion 103. When the selection transistor 203 is turned on, the amplification transistor 202 amplifies the potential of the floating diffusion 103 and outputs a voltage according to the amplified potential to the column signal processing circuit 34 via the vertical signal line 24.

[0022] The conversion efficiency switching transistor 204 is used to switch the conversion efficiency. Generally, when shooting in a dark place, the amount of charge generated in the photoelectric conversion unit 101 decreases. In such a case, when converting charge into a voltage signal based on Q=CV, if the capacitance C of the floating diffusion 103 is large, the voltage V after conversion to voltage will be small. On the other hand, when shooting in a bright place, the amount of charge generated in the photoelectric conversion unit 101 increases. In this case, because the amount of charge is large, unless the capacitance C of the floating diffusion 103 is large, the floating diffusion 103 cannot absorb all of the charge generated in the photoelectric conversion unit 101. Furthermore, in this case, it is preferable to increase the capacitance C of the floating diffusion 103 so that the voltage V after conversion does not become too large.

[0023] When the conversion efficiency switching transistor 204 is turned on, the gate capacitance and additional capacitance 205 corresponding to the conversion efficiency switching transistor 204 are added to the floating diffusion 103, thereby increasing the capacitance C that can store charge. On the other hand, when the conversion efficiency switching transistor 204 is turned off, the gate capacitance and additional capacitance 205 corresponding to the conversion efficiency switching transistor 204 are disconnected from the floating diffusion 103, thereby decreasing the capacitance C that can store charge. In this way, by switching the conversion efficiency switching transistor 204 on and off in accordance with the brightness at the time of shooting, the capacitance C that can store charge can be made variable, and the sensitivity (conversion efficiency) of the voltage signal V with respect to the amount of change in charge generated in the photoelectric conversion unit 101 can be switched.

[0024] The reset transistor 201, the amplification transistor 202, the selection transistor 203, and the conversion efficiency switching transistor 204 are, for example, CMOS transistors.

[0025] In the present disclosure, the configuration of the imaging device 1 is not limited to the configuration shown in FIGS.

[0026] <<2. Background>> Next, with reference to FIGS. 3A and 3B , the background that led the inventors to create the embodiments of the present disclosure will be described. FIG. 3A is a plan view showing an example of the planar configuration of a readout circuit 22a according to a comparative example, and FIG. 3B is a cross-sectional view of a portion of the readout circuit 22a cut along line A-A' and line B-B' shown in FIG. 3A. In particular, the upper part of FIG. 3B shows a cross-sectional view of a portion of the readout circuit 22a cut along line A-A' shown in FIG. 3A, and the lower part of FIG. 3B shows a cross-sectional view of a portion of the readout circuit 22a cut along line B-B' shown in FIG. 3A. Note that the comparative example here refers to the configuration of the readout circuit 22a that the inventors studied before creating the embodiments of the present disclosure.

[0027] 3A, in the comparative example, pixel transistors (AMP, SEL, RST, FDG) 201a, 202a, 203a, and 204a of the readout circuit 22a have gate electrodes provided on the semiconductor substrate 21 and source / drain regions provided to sandwich the gate electrodes. That is, in the comparative example, the pixel transistors are transistors having a planar structure.

[0028] 3B, which is a cross-sectional view of a conversion efficiency switching transistor 204a, shows an example of the channel width W and channel length L of such a planar transistor. For example, the conversion efficiency switching transistor (FDG) 204a has a gate electrode 344 provided on the semiconductor substrate 21 via a gate insulating film 40, and source / drain regions 342a and 346a provided to sandwich a channel region 345a below the gate electrode 344. The conversion efficiency switching transistor 204a is also isolated from other transistors by an insulating layer 44 embedded in a trench provided in the semiconductor substrate 21. The channel width W corresponds to the width of the channel region 345a that can occur in the semiconductor substrate 21 below the gate electrode 344, and the channel length L corresponds to the length of the channel region 345a between the source / drain regions 342a and 346a.

[0029] As described above, further miniaturization and integration of the imaging device 1 are required. Therefore, for example, if the planar-type conversion efficiency switching transistor 204a in the comparative example described above is miniaturized to achieve integration, the width W and length L of the channel region 345a will naturally be shortened. Therefore, shortening the channel width W and channel length L will deteriorate the noise (random noise) characteristics of the conversion efficiency switching transistor 204a. Furthermore, miniaturization of the imaging device 1 reduces the overall layout area of ​​the readout circuit 22a, which causes the wiring of the readout circuit 22a to become densely packed, making it easier for parasitic capacitance to be generated in the wiring. If such parasitic capacitance is electrically connected to, for example, the floating diffusion 103, it will result in a decrease in the conversion efficiency of the imaging device 1. In other words, as the imaging device 1 becomes further miniaturized and integrated, there will be limits to the improvement of various characteristics of the imaging device 1, and these characteristics may even be deteriorated.

[0030] In view of this situation, the present inventors have come up with an embodiment of the present disclosure that enables further improvements in various characteristics while miniaturizing and integrating the imaging device 1. Details of the embodiment of the present disclosure created by the present inventors will be described below in order.

[0031] <<3. First Embodiment>> <3.1 Detailed Configuration> First, a detailed configuration of a readout circuit 22 according to a first embodiment of the present disclosure will be described with reference to Figures 4A to 4C. Figure 4A is a cross-sectional view showing an example cross-sectional configuration of a main part of the readout circuit 22 according to this embodiment, and Figure 4B is a cross-sectional view of the main part of the readout circuit 22 taken along line CC' shown in Figure 4A. Furthermore, Figure 4C is a plan view showing an example planar configuration of a main part of the readout circuit 22 according to this embodiment, in which the upper part shows a plan view of the upper surface 21a of the semiconductor substrate 21, and the lower part shows a plan view of the lower surface 21b of the semiconductor substrate 21.

[0032] 4A , in this embodiment, an amplification transistor (AMP) (first transistor) 202 included in a readout circuit 22 is provided on an upper surface (first surface) 21a of a semiconductor substrate (first semiconductor substrate) 21 having impurities (first impurities) of, for example, p-type conductivity (first conductivity type). Also, a selection transistor (SEL) (second transistor) 203 included in the readout circuit 22 is provided on a lower surface (second surface) 21b of the semiconductor substrate 21. Also, the amplification transistor 202 and the selection transistor 203 are connected in series by sharing source / drain regions, as described with reference to FIG. 2 .

[0033] In detail, the amplification transistor 202 has a gate electrode (first gate electrode) 324 made of, for example, a metal material, a silicon material, or the like, provided on the upper surface 21 a of the semiconductor substrate 21, and a source / drain region (first source / drain region) 322 containing, for example, an n-type conductivity type (second conductivity type) impurity (second impurity) provided on the upper surface 21 a side adjacent to the gate electrode 324. Furthermore, the amplification transistor 202 has a source / drain region (first shared source / drain region) 328, which is a diffusion region containing, for example, an n-type conductivity type impurity, provided at a predetermined depth (first depth) from the upper surface 21 a in the semiconductor substrate 21.

[0034] 4A , the gate electrode 324 of the amplification transistor 202 has a vertical gate (first vertical gate) 324a made of, for example, a metal material, a silicon material, or the like, which extends through the semiconductor substrate 21 from the upper surface 21a toward the bottom in the film thickness direction of the semiconductor substrate 21. The lower surface of the gate electrode 324 and the surface of the vertical gate 324a are in contact with the semiconductor substrate 21 via a gate insulating film (first gate insulating film) 40. Furthermore, the lower surface of the vertical gate 324a located on the opposite side to the gate electrode 324 is in contact with a source / drain region 328 via the gate insulating film 40.

[0035] In this embodiment, the channel region (first channel region) 325 of the amplifier transistor 202 may be located between the source / drain region 322 and the source / drain region 328, beneath the gate electrode 324, and within the semiconductor substrate 21 around the vertical gate 324a. Therefore, in this embodiment, the length (channel length L) of the channel region 325 of the amplifier transistor corresponds to the distance between the source / drain region 322 and the source / drain region 328. Also, as shown in FIG. 4B , the width (channel width W) of the channel region 325 of the amplifier transistor 202 is the sum of the lengths of the four sides of the cross section of the vertical gate 324a in a plane perpendicular to the channel length L (the sum of the lengths of the four sides is shown as the perimeter P in FIG. 4B ). Note that, as shown in FIG. 4B , the cross section of the vertical gate 324a is not limited to being rectangular, and may be, for example, polygonal, circular, elliptical, or the like.

[0036] The select transistor 203 also has a gate electrode (second gate electrode) 334 provided on the lower surface 21b of the semiconductor substrate 21, and a source / drain region (second source / drain region) 332 containing, for example, an n-type conductivity impurity, provided on the lower surface 21b side adjacent to the gate electrode 334. The select transistor 203 also has the above-mentioned source / drain region 328. That is, the amplifying transistor 202 and the select transistor 203 are connected in series by sharing the source / drain region 328, which is a region in the semiconductor substrate 21 sandwiched between the gate electrodes 324 and 334 in the film thickness direction of the semiconductor substrate 21.

[0037] 4A , the gate electrode 334 of the select transistor 203 has a vertical gate (second vertical gate) 334a extending upward through the semiconductor substrate 21 from the lower surface 21b along the film thickness direction of the semiconductor substrate 21. The upper surface of the gate electrode 334 and the surface of the vertical gate 334a are in contact with the semiconductor substrate 21 via a gate insulating film (second gate insulating film) 40. Furthermore, the upper surface of the vertical gate 334a located on the opposite side of the gate electrode 334 is in contact with the source / drain region 328 via the gate insulating film 40. In this embodiment, the length of the vertical gate 334a of the select transistor 203 may be the same as or different from the length of the vertical gate 324a of the amplifier transistor 202. Note that, like the vertical gate 324a, the cross section of the vertical gate 334a is not limited to being rectangular, and may be, for example, polygonal, circular, elliptical, or the like.

[0038] In this embodiment, the channel region (second channel region) 335 of the select transistor 203 may be formed between the source / drain region 332 and the source / drain region 328, on the gate electrode 334, and in the semiconductor substrate 21 around the vertical gate 334a. Therefore, in this embodiment, the length (channel length L) of the channel region 335 of the select transistor corresponds to the distance between the source / drain region 332 and the source / drain region 328. Furthermore, the width (channel width W) of the channel region 335 of the select transistor 203 is the sum of the lengths of the four sides of the cross section of the vertical gate 334a in a plane perpendicular to the channel length L, similar to the amplifying transistor 202.

[0039] In this embodiment, the source / drain region 328 is sandwiched between the channel region 325 of the amplifier transistor 202 and the channel region 335 of the select transistor 203 in the film thickness direction of the semiconductor substrate 21 .

[0040] 4A and 4C , the amplification transistor 202 and the selection transistor 203 are disposed opposite each other. For example, in this embodiment, when viewed from above or below the semiconductor substrate 21, the gate electrode 324 of the amplification transistor 202 and the gate electrode 334 of the selection transistor 203 overlap. Note that in this embodiment, it is sufficient that at least a portion of the gate electrode 324 of the amplification transistor 202 and at least a portion of the gate electrode 334 of the selection transistor 203 overlap. Furthermore, as shown in FIG. 4A , the center of the gate electrode 324 and the center of the gate electrode 334 are located on the same axis 450; in other words, the centers of the gate electrodes 324 and 334 are aligned.

[0041] 4A, the gate electrodes 324, 334 and the source / drain regions 322, 332 are electrically connected to signal lines, power supply lines, other elements, etc. via contacts 48 made of, for example, a metal material, a silicon material, etc. Also, on the lower surface 21b of the semiconductor substrate 21, a silicon oxide (SiO ２ ) or the like may be provided.

[0042] As described above, in this embodiment, the amplifier transistor 202 and the select transistor 203 are provided on either side of the semiconductor substrate 21 from the upper surface 21a and the lower surface 21b. Furthermore, in this embodiment, the amplifier transistor 202 and the select transistor 203 share a source / drain region 328 provided at a predetermined depth from the upper surface 21a of the semiconductor substrate 21, thereby connecting these transistors in series. Therefore, in this embodiment, two transistors are provided on both the upper surface 21a and the lower surface 21b of the semiconductor substrate 21, thereby narrowing the layout area while increasing the area occupied by each transistor. As a result, this embodiment prevents the width W and length L of the channel regions 325, 335 of each transistor from becoming shorter. Furthermore, this embodiment allows the width W and length L to be increased, thereby not only avoiding deterioration in noise (random noise) characteristics but also achieving further improvement.

[0043] In addition, according to this embodiment, it is possible to reduce the routing of wiring for connecting the amplification transistor 202 and the selection transistor 203 on the plane of the semiconductor substrate 21. Therefore, according to this embodiment, it is possible to prevent the wiring from being crowded together and suppress the generation of parasitic capacitance in the wiring. As a result, according to this embodiment, it is possible to avoid a decrease in the conversion efficiency of the imaging device 1.

[0044] That is, according to this embodiment, the imaging device 1 can be made smaller and more integrated, while still achieving further improvements in various characteristics.

[0045] The configuration of this embodiment is not limited to the configuration examples shown in FIGS. 4A to 4C.

[0046] 3.2 Modifications (Modification 1) In this embodiment, the amplifying transistor 202 and the selection transistor 203 are not limited to being disposed so as to sandwich the semiconductor substrate 21 from the upper surface 21a and the lower surface 21b. For example, the conversion efficiency switching transistor (FDG) 204 and the reset transistor (RST) 201 of the readout circuit 22 may be disposed so as to sandwich the semiconductor substrate 21 from the upper surface 21a and the lower surface 21b. Therefore, such a modification 1 will be described with reference to FIGS. 5A and 5B. FIG. 5A is a cross-sectional view showing an example of the cross-sectional configuration of a main part of the readout circuit 22 according to Modification 1. FIG. 5B is a plan view showing an example of the planar configuration of a main part of the readout circuit 22 according to Modification 1. In detail, the upper part shows a plan view of the upper surface 21a side of the semiconductor substrate 21, and the lower part shows a plan view of the lower surface 21b side of the semiconductor substrate 21.

[0047] 5A , for example, a conversion efficiency switching transistor (FDG) (first / third transistor) 204 included in the readout circuit 22 is provided on the upper surface 21a side of the semiconductor substrate 21. Furthermore, a reset transistor (RST) (second / fourth transistor) 201 included in the readout circuit 22 is provided on the lower surface 21b side of the semiconductor substrate 21. The conversion efficiency switching transistor 204 and the reset transistor 201 are connected in series by sharing the source / drain regions, as described with reference to FIG.

[0048] In detail, the conversion efficiency switching transistor 204 has a gate electrode (first / third gate electrode) 344 provided on the upper surface 21a of the semiconductor substrate 21, and source / drain regions (first source / drain regions) 342, 346 provided on the upper surface 21a side adjacent to the gate electrode 344. Furthermore, the conversion efficiency switching transistor 204 has a source / drain region (first / second shared source / drain region) 348 which is a diffusion region provided in the semiconductor substrate 21 at a position at a predetermined depth (second depth) from the upper surface 21a.

[0049] 5A , the gate electrode 344 of the conversion efficiency switching transistor 204 has a vertical gate (first vertical gate) 344a that extends through the semiconductor substrate 21 from the upper surface 21a downward along the film thickness direction of the semiconductor substrate 21. The lower surface of the gate electrode 344 and the surface of the vertical gate 344a are in contact with the semiconductor substrate 21 via a gate insulating film (first gate insulating film) 40. Furthermore, the lower surface of the vertical gate 344a located on the opposite side to the gate electrode 344 is in contact with a source / drain region 348 via the gate insulating film 40.

[0050] In this first modification, the channel region (first channel region) 345 of the conversion efficiency switching transistor 204 is between the source / drain regions 342, 346 and the source / drain region 328, and can be generated in the semiconductor substrate 21 below the gate electrode 344 and around the vertical gate 344a. Therefore, in this first modification, the length (channel length L) of the channel region 345 of the conversion efficiency switching transistor 204 corresponds to the distance between the source / drain regions 342, 346 and the source / drain region 348. Furthermore, the width (channel width W) of the channel region 345 of the conversion efficiency switching transistor 204 is the sum of the lengths of the four sides of the cross section of the vertical gate 344a in a plane perpendicular to the channel length L, similar to the amplifying transistor 202 of the first embodiment described above. Note that the cross section of the main part of the readout circuit 22 cut along line CC' shown in FIG. 5A corresponds to FIG. 4B. Furthermore, the cross section of the vertical gate 344a is not limited to being rectangular, but may be, for example, polygonal, circular, oval, or the like.

[0051] The reset transistor 201 also has a gate electrode (second / fourth gate electrode) 314 provided on the lower surface 21b of the semiconductor substrate 21, and a source / drain region (second source / drain region) 312 provided on the lower surface 21b side adjacent to the gate electrode 314. The reset transistor 201 also has the above-mentioned source / drain region 348. That is, the conversion efficiency switching transistor 204 and the reset transistor 201 are connected in series by sharing the source / drain region 348, which is a region in the semiconductor substrate 21 sandwiched between the gate electrode 344 and the gate electrode 314 in the film thickness direction of the semiconductor substrate 21.

[0052] 5A , the gate electrode 314 of the reset transistor 201 has a vertical gate (second vertical gate) 314a extending upward through the semiconductor substrate 21 from the lower surface 21b along the film thickness direction of the semiconductor substrate 21. The upper surface of the gate electrode 314 and the surface of the vertical gate 314a are in contact with the semiconductor substrate 21 via a gate insulating film (second gate insulating film) 40. Furthermore, the upper surface of the vertical gate 314a located on the opposite side of the gate electrode 314 is in contact with the source / drain region 348 via the gate insulating film 40. Also in this first modification, the length of the vertical gate 314a of the reset transistor 201 may be the same as or different from the length of the vertical gate 344a of the conversion efficiency switching transistor 204. Note that, like the vertical gate 344a, the cross section of the vertical gate 314a is not limited to being rectangular and may be, for example, polygonal, circular, oval, or the like.

[0053] In the present modified example 1, the channel region (second channel region) 315 of the reset transistor 201 is between the source / drain region 312 and the source / drain region 348, and can be generated on the gate electrode 314 and in the semiconductor substrate 21 around the vertical gate 314a. Therefore, in the present modified example 1, the length (channel length L) of the channel region 315 of the reset transistor 201 corresponds to the distance between the source / drain region 312 and the source / drain region 348. Furthermore, the width (channel width W) of the channel region 315 of the reset transistor 201 is the sum of the lengths of the four sides of the cross section of the vertical gate 314a in a plane perpendicular to the channel length L, similar to the conversion efficiency switching transistor 204 of the present modified example 1.

[0054] In addition, in the present first modification, the source / drain region 348 is sandwiched between the channel region 345 of the conversion efficiency switching transistor 204 and the channel region 315 of the reset transistor 201 in the film thickness direction of the semiconductor substrate 21 .

[0055] 5A and 5B , in this first modification, the conversion efficiency switching transistor 204 and the reset transistor 201 are provided to face each other. In this first modification, for example, when viewed from above or below the semiconductor substrate 21, the gate electrode 344 of the conversion efficiency switching transistor 204 and the gate electrode 314 of the reset transistor 201 overlap. Note that in this first modification, it is sufficient that at least a portion of the gate electrode 344 of the conversion efficiency switching transistor 204 and at least a portion of the gate electrode 314 of the reset transistor 201 overlap. Furthermore, as shown in FIG. 4A , the center of the gate electrode 344 and the center of the gate electrode 314 are located on the same axis 450; in other words, the positions of the centers of the gate electrodes 344 and 314 are the same.

[0056] 5A , the gate electrodes 314, 344 and the source / drain regions 342, 346, 312 are electrically connected to signal lines, power supply lines, other elements, etc. via contacts 48. An insulating layer 46 may be provided on the lower surface 21 b of the semiconductor substrate 21.

[0057] As described above, in this first modification, the conversion efficiency switching transistor 204 and the reset transistor 201 are provided on either side of the semiconductor substrate 21 from the upper surface 21a and the lower surface 21b. Furthermore, in this first modification, the conversion efficiency switching transistor 204 and the reset transistor 201 share the source / drain region 348 provided at a predetermined depth from the upper surface 21a of the semiconductor substrate 21, thereby connecting these transistors in series. Therefore, in this embodiment, two transistors are provided on both the upper surface 21a and the lower surface 21b of the semiconductor substrate 21, thereby narrowing the layout area while increasing the area occupied by each transistor. As a result, this embodiment prevents the width W and length L of the channel regions 345, 315 of each transistor from becoming shorter. Furthermore, in this first modification, the width W and length L can be increased, thereby not only avoiding deterioration in noise (random noise) characteristics but also achieving further improvement.

[0058] In addition, according to the present modification 1, it is possible to reduce the routing of wiring for connecting the conversion efficiency switching transistor 204 and the reset transistor 201 on the plane of the semiconductor substrate 21, thereby preventing the wiring from being crowded together and suppressing the generation of parasitic capacitance in the wiring. As a result, according to the present modification 1, it is possible to avoid a decrease in the conversion efficiency of the imaging device 1.

[0059] It should be noted that this modification is not limited to application to the conversion efficiency switching transistor 204 and the reset transistor 201, and may be applied to transistors having other functions.

[0060] (Modification 2) Furthermore, the first embodiment and Modification 1 described above may be combined. An example of such a combination will be described as Modification 2 with reference to FIGS. 6A and 6B . FIG. 6A is a cross-sectional view showing an example cross-sectional configuration of a main part of the readout circuit 22 according to Modification 2. FIG. 6B is a plan view showing an example plan configuration of a main part of the readout circuit 22 according to Modification 2. In detail, the upper part shows a plan view of the upper surface 21 a of the semiconductor substrate 21, and the lower part shows a plan view of the lower surface 21 b of the semiconductor substrate 21. Note that, for ease of understanding, FIG. 6B omits the illustration of source / drain regions 322, 332, 342, 346, and 312 provided on the upper surface 21 a and lower surface 21 b of the semiconductor substrate 21.

[0061] 6A and 6B , in the present modification 2, for example, an amplification transistor (AMP) 202 and a conversion efficiency switching transistor (FDG) 204 included in the readout circuit 22 are provided on the upper surface 21a side of the semiconductor substrate 21. In addition, a selection transistor (SEL) 203 and a reset transistor (RST) 201 included in the readout circuit 22 are provided on the lower surface 21b side of the semiconductor substrate 21.

[0062] As described above, in Modification 2, the amplifier transistor 202, the conversion efficiency switching transistor 204, the select transistor 203, and the reset transistor 201 are provided on the upper and lower surfaces 21a and 21b of the semiconductor substrate 21, sandwiching them. Furthermore, in Modification 2, these transistors are connected in series by sharing the source / drain regions 328 and 348, which are provided at a predetermined depth from the upper surface 21a of the semiconductor substrate 21. Therefore, in Modification 2, four transistors are provided on both the upper and lower surfaces 21a and 21b of the semiconductor substrate 21, thereby narrowing the layout area while increasing the area occupied by each transistor. As a result, Modification 2 prevents the widths W and lengths L of the channel regions 315, 325, 335, and 345 of each transistor from becoming shorter. Furthermore, Modification 2 allows the widths W and lengths L to be increased, thereby not only avoiding deterioration in noise (random noise) characteristics but also achieving further improvement.

[0063] In addition, according to the present modification 2, it is possible to reduce the routing of wiring for connecting each transistor on the plane of the semiconductor substrate 21, thereby preventing the wiring from being crowded together and suppressing the generation of parasitic capacitance in the wiring. As a result, according to the present modification 2, it is possible to avoid a decrease in the conversion efficiency of the imaging device 1.

[0064] <<4. Second Embodiment>> Furthermore, in the first embodiment of the present disclosure described above, the lengths of the vertical gates of the two transistors sandwiching the semiconductor substrate 21 are the same. However, in the present disclosure, it is preferable to adjust the length of the vertical gate according to the characteristics required of each transistor. By adjusting the length of the vertical gate, the channel length L of the transistor can be adjusted. More specifically, it is preferable to increase the width W and length L of the channel region 325 of the amplifier transistor (AMP) 202, which is required to have better noise characteristics than other transistors. From this perspective, the vertical gate 324a of the amplifier transistor 202 may be increased.

[0065] 7A and 7B, a second embodiment of the present disclosure, which is capable of adjusting the length of the vertical gate, will be described. Figures 7A and 7B are cross-sectional views showing an example of the cross-sectional configuration of a main part of a readout circuit 22 according to this embodiment.

[0066] 7A , for example, the length of the vertical gate 324a of the amplifier transistor 202 may be longer than the length of the vertical gate 334a of the select transistor 202. In this way, by lengthening the vertical gate 324a of the amplifier transistor 202, the length L of the channel region 325 may be increased, thereby further suppressing noise of the amplifier transistor 202.

[0067] In this embodiment, for example, as shown in Fig. 7B , the gate electrode 334 of the selection transistor 203 does not have a vertical gate 334a in order to make the length of the vertical gate 324a of the amplification transistor 202 longer. That is, in the example shown in Fig. 7B , the selection transistor 203 is a transistor having a planar structure.

[0068] 7A and 7B. This embodiment is not limited to the configuration example shown in FIG. 7A and FIG. 7B. This embodiment is not limited to the configuration in which the amplification transistor 202 and the selection transistor 203 are provided so as to sandwich the semiconductor substrate 21 from the upper surface 21a and the lower surface 21b. This embodiment may also be configured such that the conversion efficiency switching transistor (FDG) 204 and the reset transistor (RST) 201 of the readout circuit 22 sandwich the semiconductor substrate 21 from the upper surface 21a and the lower surface 21b. This embodiment may also be applied to transistors having other functions.

[0069] Furthermore, in this embodiment, as long as two transistors are provided on either side of the semiconductor substrate 21 from the upper surface 21a and the lower surface 21b, the two transistors may have a planar structure. In this case, since the two transistors are provided on the upper surface 21a and the lower surface 21b of the semiconductor substrate 21, the layout area can be narrowed while the area occupied by each transistor can be widened. As a result, this embodiment prevents the width W and length L of the channel regions 345 and 315 of each transistor from becoming short. Furthermore, according to the first modification, the width W and length L can be extended, thereby not only avoiding deterioration of noise (random noise) characteristics but also achieving further improvement. In addition, this embodiment reduces the routing of wiring connecting the two transistors on the plane of the semiconductor substrate 21, thereby preventing wiring from becoming congested and suppressing the generation of parasitic capacitance in the wiring.

[0070] <<5. Third Embodiment>> Next, a third embodiment of the present disclosure will be described with reference to FIG. 4A . This embodiment enables a transistor to have a higher breakdown voltage. In this embodiment, for example, the impurity concentration of the source / drain region 328 in the semiconductor substrate 21 is made lower than that of the source / drain regions 322, 332 present on the upper surface 21 a and lower surface 21 b sides of the semiconductor substrate 21. By doing so, the electric field generated in the channel regions 325, 335 in the semiconductor substrate 21 is alleviated, thereby improving the breakdown voltage of the amplifier transistor 202 and the select transistor 203.

[0071] In this embodiment, the functions of the two transistors are not limited as long as they are disposed so as to sandwich the semiconductor substrate 21 from the upper surface 21 a and the lower surface 21 b. That is, the configuration of this embodiment is not limited to the example configuration shown in FIG.

[0072] <<6. Fourth Embodiment>> <6.1 Detailed Configuration> In the embodiments of the present disclosure described so far, the centers of the gate electrodes of two transistors arranged to sandwich the semiconductor substrate 21 from the upper surface 21a and the lower surface 21b are located on the same axis 450. However, the present disclosure is not limited to this configuration, and the centers of the gate electrodes of each transistor may be located on different axes. In this embodiment, doing so allows the length of the vertical gate of each transistor to be freely adjusted and improves the degree of freedom in routing wiring. Therefore, with reference to FIGS. 8A to 8C , such a fourth embodiment of the present disclosure will be described. FIGS. 8A to 8C are cross-sectional views showing examples of the cross-sectional configuration of a main part of the readout circuit 22 according to this embodiment. Note that, for clarity, the source / drain regions 322 and 332 provided on the upper surface 21a and lower surface 21b of the semiconductor substrate 21 are omitted from these figures.

[0073] 8A , in this embodiment, an amplifier transistor (AMP) 202 is provided on the upper surface 21a of the semiconductor substrate 21, and a selector transistor (SEL) 203 is provided on the lower surface 21b. The amplifier transistor 202 has a gate electrode 324 provided on the upper surface 21a of the semiconductor substrate 21 and a source / drain region 322 (not shown in FIG. 8A ) provided adjacent to the gate electrode 324 on the upper surface 21a side. The amplifier transistor 202 also has a source / drain region 328 provided at a predetermined depth from the upper surface 21a in the semiconductor substrate 21. The gate electrode 324 of the amplifier transistor 202 also has a vertical gate 324a extending downward through the semiconductor substrate 21 from the upper surface 21a in the film thickness direction of the semiconductor substrate 21.

[0074] The select transistor 203 also has a gate electrode 334 provided on the lower surface 21b of the semiconductor substrate 21, and a source / drain region 332 (not shown in FIG. 8A ) provided on the lower surface 21b side adjacent to the gate electrode 334. The select transistor 203 also has the above-mentioned source / drain region 328. The gate electrode 334 of the select transistor 203 has a vertical gate 334a that extends upward through the semiconductor substrate 21 from the lower surface 21b along the film thickness direction of the semiconductor substrate 21.

[0075] 8A , an axis 451 passing through the centers of the gate electrode 324 and vertical gate 324 a of the amplification transistor 202 does not overlap with an axis 452 passing through the centers of the gate electrode 334 and vertical gate 334 a of the selection transistor 203. That is, in this embodiment, when viewed from above or below the semiconductor substrate 21, the center of the gate electrode 324 of the amplification transistor 202 does not coincide with the center of the gate electrode 334 of the selection transistor 203.

[0076] As described above, in this embodiment, the amplifier transistor 202 and the select transistor 203 are provided on either side of the semiconductor substrate 21 from the upper surface 21a and the lower surface 21b. In this embodiment, the amplifier transistor 202 and the select transistor 203 share a source / drain region 328 provided at a predetermined depth from the upper surface 21a of the semiconductor substrate 21, thereby connecting these transistors in series. Therefore, in this embodiment, two transistors are provided on both the upper surface 21a and the lower surface 21b of the semiconductor substrate 21, thereby narrowing the layout area while increasing the area occupied by each transistor. As a result, this embodiment prevents the width W and length L of the channel regions 325, 335 of each transistor from becoming shorter. Furthermore, this embodiment allows the width W and length L to be increased, thereby not only avoiding deterioration in noise (random noise) characteristics but also achieving further improvement.

[0077] In addition, according to this embodiment, it is possible to reduce the routing of wiring for connecting the amplification transistor 202 and the selection transistor 203 on the plane of the semiconductor substrate 21. Therefore, according to this embodiment, it is possible to prevent the wiring from being crowded together and to suppress the generation of parasitic capacitance in the wiring.

[0078] Furthermore, according to this embodiment, by positioning the centers of the gate electrodes 324, 334 of the two transistors on different axes, it is possible to freely adjust the lengths of the vertical gates 324a, 334a of each transistor and improve the degree of freedom in routing the wiring.

[0079] 8B and 8C , similarly to the second embodiment, the lengths of the vertical gates 324 a and 334 a may also be adjusted in this embodiment. Specifically, as shown in FIG. 8B , the length of the vertical gate 324 a of the amplifier transistor 202 may be made longer than the length of the vertical gate 334 a of the select transistor 203. In this way, by lengthening the vertical gate 324 a of the amplifier transistor 202, the length L of the channel region 325 may be increased, thereby further suppressing noise in the amplifier transistor 202.

[0080] Also, as shown in FIG. 8C, the selection transistor 203 may be a transistor having a planar structure, thereby making the vertical gate 324a of the amplification transistor 202 longer.

[0081] 8A to 8C. In this embodiment, the configuration is not limited to the configuration examples shown in FIGS. 8A to 8C. In this embodiment, the configuration is not limited to the configuration in which the amplification transistor 202 and the selection transistor 203 are provided so as to sandwich the semiconductor substrate 21 from the upper surface 21a and the lower surface 21b. In this embodiment, for example, the conversion efficiency switching transistor (FDG) 204 and the reset transistor (RST) 201 of the readout circuit 22 may be provided so as to sandwich the semiconductor substrate 21 from the upper surface 21a and the lower surface 21b. Furthermore, this embodiment may be applied to transistors having other functions.

[0082] 8D is a cross-sectional view showing an example of a cross-sectional configuration of a main part of the readout circuit 22 according to a modified example, and an STI (Shallow Trench Isolation) 50 for isolating the amplification transistor 202 and the selection transistor 203 may be provided between them. The STI 50 is formed by a trench that penetrates a part of or the entire semiconductor substrate 21 in the film thickness direction and a silicon dioxide (SiO ２ ) or other insulating film (insulating layer). In this modification, providing such an STI 50 separates the two transistors, reduces the electric field generated between the two transistors, and suppresses leakage between the transistors. In this modification, an axis 451 passing through the centers of the gate electrode 324 and vertical gate 324 a of the amplification transistor 202 and an axis 452 passing through the centers of the gate electrode 334 and vertical gate 334 a of the selection transistor 203 do not overlap, which makes it easy to form the STI 50 between the two transistors.

[0083] In this modification, the source / drain region 328 is provided below the STI 50 so as to be in contact with the STI 50. Furthermore, in this modification, the source / drain region 328 is sandwiched between the channel region 325 of the amplification transistor 202 and the channel region 335 of the selection transistor 203 in the direction parallel to the surface of the semiconductor substrate 21.

[0084] As described above, in this modification, by providing the STI 50 between two transistors to separate them, the electric field generated between the two transistors can be alleviated, and leakage between the transistors and the like can be suppressed.

[0085] It should be noted that the configuration of this modified example is not limited to the example configuration shown in Fig. 8D. For example, in this modified example, the conversion efficiency switching transistor (FDG) 204 and the reset transistor (RST) 201 may be provided so as to sandwich the semiconductor substrate 21 from the upper surface 21a and the lower surface 21b. Furthermore, this modified example may be applied to transistors having other functions.

[0086] <<7. Fifth Embodiment>> <7.1 Detailed Configuration> Next, a fifth embodiment of the present disclosure will be described, which is an embodiment in which an element isolation structure is applied to four transistors such as in Modification 2 of the first embodiment. Here, the fifth embodiment will be described with reference to FIGS. 9A and 9B . FIG. 9A is a plan view showing an example of the planar configuration of a main part of a readout circuit 22 according to this embodiment, and FIG. 9B is a cross-sectional view showing an example of the cross-sectional configuration of a main part of the readout circuit 22 according to this embodiment. Note that, for ease of understanding, FIG. 9B omits illustration of source / drain regions 322, 332, 342, 346, and 312 provided on the upper surface 21 a side and the lower surface 21 b side of the semiconductor substrate 21.

[0087] 9A and 9B , in this embodiment, an STI 60 is provided between a transistor pair (first element pair) consisting of an amplifier transistor 202 and a select transistor 203 and a transistor pair (second element pair) consisting of a conversion efficiency switching transistor 204 and a reset transistor 201, to separate them. The STI 60 is made of a trench that penetrates the semiconductor substrate 21 from the upper surface 21 a along the film thickness direction to a predetermined depth (third depth), and an insulating film such as silicon oxide embedded in the trench. In this embodiment, by providing such an STI 60, leakage between the transistor pair consisting of the amplifier transistor 202 and the select transistor 203 and the transistor pair consisting of the conversion efficiency switching transistor 204 and the reset transistor 201 can be reduced, and an electric field that may be generated between these transistor pairs can be alleviated.

[0088] In this embodiment, the STI 60 is not limited to having a trench that penetrates the semiconductor substrate 21 from the upper surface 21 a to a predetermined depth in the film thickness direction. In this embodiment, for example, the STI 60 may have a trench (third trench) that penetrates the semiconductor substrate 21 from the lower surface 21 b to a predetermined depth (fourth depth) in the film thickness direction.

[0089] 9A and 9B. For example, this embodiment may be applied to transistors having other functions. Furthermore, in this embodiment, an STI 60 may be provided to surround a transistor pair consisting of the amplification transistor 202 and the selection transistor 203 and / or a transistor pair consisting of the conversion efficiency switching transistor 204 and the reset transistor 201.

[0090] 7.2 Modifications (Modification 1) Next, Modification 1 of this embodiment will be described with reference to Fig. 10A and Fig. 10B. Fig. 10A is a plan view showing an example of the planar configuration of a main part of the readout circuit 22 according to Modification 1 of this embodiment, and Fig. 10B is a cross-sectional view showing an example of the cross-sectional configuration of a main part of the readout circuit 22 according to Modification 1 of this embodiment. Note that, for ease of understanding, Fig. 10B omits the illustration of source / drain regions 322, 332, 342, 346, and 312 provided on the upper surface 21a and lower surface 21b of the semiconductor substrate 21.

[0091] 10A and 10B , in this first modification, a full trench isolation (FTI) 62 may be provided between a transistor pair consisting of an amplification transistor 202 and a selection transistor 203 and a transistor pair consisting of a conversion efficiency switching transistor 204 and a reset transistor 201 to separate them. The FTI 62 is made of a trench that penetrates the semiconductor substrate 21 from the upper surface 21 a to the lower surface 21 b along the film thickness direction, and an insulating film such as silicon oxide embedded in the trench. In this first modification, by providing such an FTI 62, leakage between the transistor pair consisting of the amplification transistor 202 and the selection transistor 203 and the transistor pair consisting of the conversion efficiency switching transistor 204 and the reset transistor 201 can be further reduced, and an electric field that may be generated between these transistor pairs can be alleviated.

[0092] 10A and 10B. For example, Modification 1 may be applied to transistors having other functions. Furthermore, in Modification 1, an FTI 62 may be provided to surround a transistor pair consisting of the amplification transistor 202 and the selection transistor 203 and / or a transistor pair consisting of the conversion efficiency switching transistor 204 and the reset transistor 201.

[0093] (Variation 2) Next, Variation 2 of this embodiment will be described with reference to Figures 11A and 11B. Figure 11A is a plan view showing an example of the planar configuration of a main part of the readout circuit 22 according to Variation 2 of this embodiment, and Figure 11B is a cross-sectional view showing an example of the cross-sectional configuration of a main part of the readout circuit 22 according to Variation 2 of this embodiment. Note that, for ease of understanding, Figure 11B omits the illustration of source / drain regions 322, 332, 342, 346, and 312 provided on the upper surface 21a and lower surface 21b of the semiconductor substrate 21.

[0094] 11A and 11B , in Modification 2, a diffusion region 64 may be provided between a transistor pair consisting of an amplification transistor 202 and a selection transistor 203 and a transistor pair consisting of a conversion efficiency switching transistor 204 and a reset transistor 201 to separate them. The diffusion region 64 is, for example, a diffusion region formed by diffusing impurities of a first conductivity type (e.g., p-type) in the semiconductor substrate 21. Furthermore, it is preferable that the diffusion region 64 have a higher impurity concentration than the semiconductor substrate 21. In Modification 2, by providing such a diffusion region 64, leakage between the transistor pair consisting of the amplification transistor 202 and the selection transistor 203 and the transistor pair consisting of the conversion efficiency switching transistor 204 and the reset transistor 201 can be further reduced, and an electric field that may occur between these transistor pairs can be alleviated.

[0095] 11A and 11B . For example, Modification 2 may be applied to transistors having other functions. Furthermore, in Modification 2, for example, the element isolation portion separating the transistor pair consisting of the amplifier transistor 202 and the select transistor 203 from the transistor pair consisting of the conversion efficiency switching transistor 204 and the reset transistor 201 may be formed by combining the STI 60 or the FTI 62 with the diffusion region 64. Furthermore, in Modification 2, for example, the diffusion region 64 may be provided so as to surround the transistor pair consisting of the amplifier transistor 202 and the select transistor 203 and / or the transistor pair consisting of the conversion efficiency switching transistor 204 and the reset transistor 201.

[0096] 8. Sixth Embodiment 8.1 Detailed Configuration Next, a sixth embodiment of the present disclosure will be described with reference to Fig. 12A and Fig. 12B. Fig. 12A is a plan view showing an example of the planar configuration of a main part of a readout circuit 22 according to this embodiment, and Fig. 12B is a cross-sectional view of the main part of the readout circuit 22 taken along line DD' shown in Fig. 12A.

[0097] In this embodiment, the FTI 62 used in the first modification of the fifth embodiment described above is utilized to allow, for example, a power supply voltage (VDD) applied to the lower surface 21b of the semiconductor substrate 21 to also be applied to the upper surface 21a. Specifically, in this embodiment, as shown in FIGS. 12A and 12B , a through electrode 70 is provided that penetrates the center of the FTI 62. The through electrode 70 is electrically connected to the upper surface of the source / drain 322 region provided on the upper surface 21a via, for example, wiring 72 provided on the upper surface 21a. Therefore, the through electrode 70 can apply the power supply voltage applied to the lower surface 21b to the source / drain 322 region on the upper surface 21a via the wiring 72.

[0098] As described above, in this embodiment, by using the through electrodes 70 in the FTI 62, it is possible to reduce the routing of wiring for applying voltages and the like to these transistors on the plane of the semiconductor substrate 21. Therefore, according to this embodiment, it is possible to avoid the wirings from being crowded together, and to suppress the occurrence of parasitic capacitance in the wirings.

[0099] In this embodiment, the through electrode 70 is not limited to being connected to the power supply line (VDD) and may be connected to wiring having another potential, etc. Furthermore, the through electrode 70 may be provided so as to apply a voltage applied to the upper surface 21 a of the semiconductor substrate 21 to the lower surface 21 b, for example.

[0100] 12A and 12B. In this embodiment, for example, a through electrode 70 may be provided in the STI 60. Furthermore, this embodiment is not limited to being applied to the amplification transistor 202 and the selection transistor 203. For example, this embodiment may be applied to the conversion efficiency switching transistor (FDG) 204 and the reset transistor (RST) 201, and may also be applied to transistors having other functions.

[0101] 8.2 Modifications Next, a modification of this embodiment will be described with reference to Fig. 13. Fig. 13 is a cross-sectional view showing an example of the cross-sectional configuration of a main part of a read circuit 22 according to a modification of this embodiment, and corresponds in detail to the cross-sectional view of Fig. 12B.

[0102] In this modification, like the above-described embodiment, the FTI 62 has a through electrode 70. However, the through electrode 70 is electrically connected to the side surface of the source / drain 322 region provided on the upper surface 21a side of the semiconductor substrate 21 via an electrode 72a provided so as to be embedded in the semiconductor substrate 21, rather than via a wiring 72 provided on the upper surface 21a of the semiconductor substrate 21 (side contact). In this modification, this configuration makes it possible to suppress the occurrence of parasitic capacitance.

[0103] It should be noted that the configuration of this modified example is not limited to the configuration example shown in Fig. 13. Furthermore, this modified example is not limited to being applied to the amplification transistor 202 and the selection transistor 203. For example, this modified example may be applied to the conversion efficiency switching transistor (FDG) 204 and the reset transistor (RST) 201, and may also be applied to transistors having other functions.

[0104] 9. Seventh Embodiment Next, a seventh embodiment of the present disclosure will be described with reference to Fig. 14A and Fig. 14B. Fig. 14A and Fig. 14B are cross-sectional views showing an example of the cross-sectional configuration of an imaging device 1 according to this embodiment.

[0105] As described above, the second substrate 20 including the semiconductor substrate 21 described above may be stacked on a first substrate 10 including a semiconductor substrate (second semiconductor substrate) 11, as shown in Fig. 1. Furthermore, the second substrate 20 including the semiconductor substrate 21 may be stacked on a third substrate 30 including a semiconductor substrate 31, as shown in Fig. 1.

[0106] In detail, the first substrate 10 has, on a semiconductor substrate 11, a photoelectric conversion unit 101 included in the pixel 12, and a floating diffusion (FD) (charge storage unit) 103 that temporarily stores the charge output from the photoelectric conversion unit 101. Furthermore, the floating diffusion (FD) (charge storage unit) 103 is electrically connected to an amplification transistor (AMP) 202, a reset transistor (RST) 201, etc., which are provided on the semiconductor substrate 21.

[0107] The third substrate 30 has a logic circuit 32 that processes pixel signals from the readout circuit 22. The logic circuit 32 can process pixel signals read out by the readout circuit 22, for example.

[0108] 14A, the upper surface (front surface) 21a of the semiconductor substrate 21 may be provided to face the front surface 11b located on the opposite side to the light incident surface (back surface) 11a of the semiconductor substrate 11. Alternatively, more specifically, as shown in FIG. 14B, the lower surface (back surface) 21b of the semiconductor substrate 21 may be provided to face the front surface 11b located on the opposite side to the light incident surface 11a of the semiconductor substrate 11.

[0109] The substrates 10, 20, and 30 may be physically joined and electrically connected by facing and joining electrodes (e.g., electrodes made of copper (Cu)) provided on their outermost surfaces. Furthermore, the substrate 20 may include a through electrode that penetrates the semiconductor substrate 21 included therein.

[0110] The configuration of this embodiment is not limited to the configuration examples shown in FIGS. 14A and 14B.

[0111] 10. Eighth Embodiment Next, an example of a method for manufacturing the image pickup device 1 according to this embodiment will be described with reference to Fig. 15A to Fig. 15C. Fig. 15A to Fig. 15C are cross-sectional views showing an example of a method for manufacturing the image pickup device 1 according to this embodiment.

[0112] First, as shown in the upper part of FIG. 15A , a trench 400 is formed in a semiconductor substrate 21 made of, for example, silicon. Next, as shown in the second part from the top of FIG. 15A , impurities are implanted into the bottom surface of the trench 400 and adjacent regions to form source / drain regions 322, 328 and a channel region 325. Next, as shown in the third part from the top of FIG. 15A , a gate insulating film 40 is formed on the upper surface of the semiconductor substrate 21. Furthermore, as shown in the lower part of FIG. 15A , gate electrodes 324, 344 are formed so as to fill the trench 400. In this manner, the amplifying transistor 202 and the conversion efficiency switching transistor 204 are formed.

[0113] Next, as shown in the upper part of Fig. 15B , a wiring layer 402 is formed on the semiconductor substrate 21. Next, as shown in the second part from the top of Fig. 15B , the semiconductor substrate 21 is inverted and bonded to a first substrate 10 including a semiconductor substrate 11. Next, as shown in the third part from the top of Fig. 15B , an STI 60 is formed on the upper surface side of the semiconductor substrate 21 in the drawing. Furthermore, as shown in the lower part of Fig. 15B , a reset transistor 201 and a selection transistor 203 are formed between the STI 60 in the same procedure as the above-described amplification transistor 202 and conversion efficiency switching transistor 204.

[0114] Next, as shown in the upper part of Fig. 15C, a wiring layer 404 is formed on the semiconductor substrate 21. Next, as shown in the second part from the top of Fig. 15C, the semiconductor substrate 21 is inverted and bonded to a third substrate 30 including a semiconductor substrate 31. Next, as shown in the lower part of Fig. 15C, a color filter 410 and an on-chip lens 412 are formed.

[0115] It should be noted that the method for manufacturing the imaging device 1 according to this embodiment is not limited to the example shown in FIGS. 15A to 15C.

[0116] Furthermore, in this embodiment, it is possible to manufacture the semiconductor device by using the method, apparatus, and conditions that are used in the manufacture of general semiconductor devices, i.e., it is possible to use the existing semiconductor device manufacturing process in this embodiment.

[0117] Examples of the above-mentioned method include a PVD (Physical Vapor Deposition) method, a CVD (Chemical Vapor Deposition) method, and an ALD (Atomic Layer Deposition) method. Examples of PVD methods include vacuum deposition, EB (electron beam) deposition, various sputtering methods (magnetron sputtering, RF (radio frequency)-DC (direct current) combined bias sputtering, ECR (electron cyclotron resonance) sputtering, facing target sputtering, high frequency sputtering, etc.), ion plating, laser ablation, molecular beam epitaxy (MBE), and laser transfer. Examples of CVD methods include plasma CVD, thermal CVD, metal organic (MO) CVD, and photo CVD. Other methods include electroplating, electroless plating, spin coating, dipping, casting, microcontact printing, drop casting, various printing methods such as screen printing, inkjet printing, offset printing, gravure printing, and flexographic printing, stamping, spraying, and various coating methods such as air doctor coater, blade coater, rod coater, knife coater, squeeze coater, reverse roll coater, transfer roll coater, gravure coater, kiss coater, cast coater, spray coater, slit orifice coater, and calendar coater. Furthermore, patterning methods include chemical etching such as shadow mask, laser transfer, and photolithography, and physical etching using ultraviolet light or laser. Additionally, planarization techniques include CMP (Chemical Mechanical Polishing), laser planarization, and reflow.

[0118] <<11. Summary>> As described above, in each embodiment of the present disclosure, two transistors are provided on either side of the semiconductor substrate 21 from the upper surface 21a and the lower surface 21b. Furthermore, in this embodiment, the two transistors are connected in series by sharing a source / drain region provided at a predetermined depth from the upper surface 21a of the semiconductor substrate 21. Therefore, in this embodiment, two transistors are provided on both the upper surface 21a and the lower surface 21b of the semiconductor substrate 21, which allows the layout area to be narrowed while the area occupied by each transistor to be widened. As a result, this embodiment prevents the width W and length L of the channel region 345a of each transistor from becoming short. Therefore, this embodiment allows the width W and length L to be longer, which not only prevents deterioration of the noise (random noise) characteristics of the transistor but also allows further improvement.

[0119] In addition, according to this embodiment, it is possible to reduce the amount of wiring required to connect two transistors on the plane of the semiconductor substrate 21, thereby preventing the wiring from becoming congested and suppressing the generation of parasitic capacitance in the wiring. As a result, according to this embodiment, it is possible to avoid a decrease in the conversion efficiency of the imaging device 1.

[0120] That is, according to this embodiment, the imaging device 1 can be made smaller and more integrated, while still achieving further improvements in various characteristics.

[0121] In the above-described embodiment of the present disclosure, the photoelectric conversion unit 101 is described in which the first conductivity type is p-type, the second conductivity type is n-type, and electrons are used as signal charges, but the embodiment of the present disclosure is not limited to this example. For example, the present embodiment can also be applied to a photoelectric conversion unit 101 in which the first conductivity type is n-type, the second conductivity type is p-type, and holes are used as signal charges.

[0122] Furthermore, the imaging device 1 according to the embodiment of the present disclosure is not limited to an imaging device that detects the distribution of incident light intensity of visible light and captures an image. For example, the present embodiment can be applied to various photodetection devices, such as an imaging device that captures an image of the distribution of incident light intensity of infrared rays, X-rays, particles, etc., or a distance measuring device that measures distance based on light reflection. In addition, the technology of the present disclosure may be applied to other semiconductor devices.

[0123] <<12. Application Examples>> <12.1 Application Examples to Smartphones> The technology according to the present disclosure may also be applied to electronic devices such as cameras and smartphones. Therefore, a configuration example of a smartphone 900 as an electronic device to which the present technology is applied will be described with reference to Fig. 16. Fig. 16 is a block diagram showing an example of a schematic functional configuration of a smartphone 900 to which the technology according to the present disclosure (the present technology) can be applied.

[0124] 16 , the smartphone 900 includes a CPU (Central Processing Unit) 901, a ROM (Read Only Memory) 902, and a RAM (Random Access Memory) 903. The smartphone 900 also includes a storage device 904, a communication module 905, and a sensor module 907. The smartphone 900 also includes an imaging device 1, a display device 910, a speaker 911, a microphone 912, an input device 913, and a bus 914. The smartphone 900 may also include a processing circuit such as a DSP (Digital Signal Processor) instead of or in addition to the CPU 901.

[0125] The CPU 901 functions as an arithmetic processing unit and control device, and controls all or part of the operations within the smartphone 900 in accordance with various programs recorded in the ROM 902, RAM 903, storage device 904, etc. The ROM 902 stores programs and calculation parameters used by the CPU 901. The RAM 903 temporarily stores programs used in the execution of the CPU 901 and parameters that change as appropriate during the execution. The CPU 901, ROM 902, and RAM 903 are interconnected by a bus 914. The storage device 904 is a data storage device configured as an example of a storage unit of the smartphone 900. The storage device 904 is configured, for example, by a magnetic storage device such as an HDD (hard disk drive), a semiconductor storage device, an optical storage device, etc. This storage device 904 stores programs executed by the CPU 901, various data, and various data acquired from outside.

[0126] The communication module 905 is a communication interface configured with, for example, a communication device for connecting to the communication network 906. The communication module 905 may be, for example, a communication card for a wired or wireless local area network (LAN), Bluetooth (registered trademark), or wireless USB (WUSB). The communication module 905 may also be a router for optical communication, a router for asymmetric digital subscriber line (ADSL), or a modem for various communications. The communication module 905 transmits and receives signals between the Internet and other communication devices using a predetermined protocol such as TCP (Transmission Control Protocol) / IP (Internet Protocol). The communication network 906 connected to the communication module 905 is a wired or wireless network, such as the Internet, a home LAN, infrared communication, or satellite communication.

[0127] The sensor module 907 includes various sensors such as a motion sensor (e.g., an acceleration sensor, a gyro sensor, a geomagnetic sensor, etc.), a biometric information sensor (e.g., a pulse sensor, a blood pressure sensor, a fingerprint sensor, etc.), or a position sensor (e.g., a GNSS (Global Navigation Satellite System) receiver, etc.).

[0128] The imaging device 1 is provided on the surface of the smartphone 900 and can capture an image of an object located on the front or back side of the smartphone 900. Specifically, the imaging device 1 is configured to employ the technology of the present disclosure (the present technology). That is, the imaging device 1 may include an imaging element (not shown) and a signal processing circuit (not shown) that performs imaging signal processing on a signal photoelectrically converted by the imaging element. Furthermore, the imaging device 1 may further include an optical system mechanism (not shown) including an imaging lens, a zoom lens, a focus lens, and the like, and a drive system mechanism (not shown) that controls the operation of the optical system mechanism. The imaging element collects incident light from an object as an optical image, and the signal processing circuit photoelectrically converts the formed optical image on a pixel-by-pixel basis, reads out the signal from each pixel as an imaging signal, and performs image processing to obtain a captured image.

[0129] The display device 910 is provided on the surface of the smartphone 900 and can be, for example, a display device such as an LCD (Liquid Crystal Display) or an organic EL (Electro Luminescence) display. The display device 910 can display an operation screen, captured images acquired by the imaging device 1 described above, and the like.

[0130] The speaker 911 can output, for example, telephone call audio and audio accompanying the video content displayed by the display device 910 described above to the user.

[0131] The microphone 912 can collect, for example, the user's call voice, voice including commands to activate functions of the smartphone 900, and voice from the surrounding environment of the smartphone 900.

[0132] The input device 913 is a device operated by a user, such as a button, a keyboard, a touch panel, or a mouse. The input device 913 includes an input control circuit that generates an input signal based on information input by the user and outputs the signal to the CPU 901. By operating the input device 913, the user can input various data to the smartphone 900 and instruct processing operations.

[0133] The above describes an example configuration of the smartphone 900. Each of the above components may be configured using general-purpose components, or may be configured using hardware specialized for the function of each component. Such a configuration may be changed as appropriate depending on the technical level at the time of implementation.

[0134] Furthermore, by applying the technology according to the present disclosure, a small imaging device (photodetector) 1 can be obtained, which can be applied to a camera attached to a part of a user's body, etc. Similarly, the technology according to the present disclosure can also be applied to a camera mounted on an HMD (Head Mounted Display) that provides a virtual reality experience by superimposing and displaying virtual items on a real space image.

[0135] 12.2 Application Example to Endoscopic Surgery System The technology according to the present disclosure (the present technology) may be applied to, for example, an endoscopic surgery system.

[0136] FIG. 17 is a diagram showing an example of a schematic configuration of an endoscopic surgery system to which the technology according to the present disclosure (the present technology) can be applied.

[0137] 17 shows an operator (doctor) 11131 performing surgery on a patient 11132 on a patient bed 11133 using an endoscopic surgery system 11000. As shown in the figure, the endoscopic surgery system 11000 is composed of an endoscope 11100, other surgical tools 11110 such as an insufflation tube 11111 and an energy treatment tool 11112, a support arm device 11120 that supports the endoscope 11100, and a cart 11200 on which various devices for endoscopic surgery are mounted.

[0138] The endoscope 11100 is composed of a lens barrel 11101, a region of a predetermined length from the tip of which is inserted into a body cavity of a patient 11132, and a camera head 11102 connected to the base end of the lens barrel 11101. In the example shown, the endoscope 11100 is configured as a so-called rigid scope having a rigid lens barrel 11101, but the endoscope 11100 may also be configured as a so-called flexible scope having a flexible lens barrel.

[0139] An opening into which an objective lens is fitted is provided at the tip of the lens barrel 11101. A light source device 11203 is connected to the endoscope 11100, and light generated by the light source device 11203 is guided to the tip of the lens barrel by a light guide extending inside the lens barrel 11101, and is irradiated via the objective lens toward an object to be observed inside the body cavity of the patient 11132. The endoscope 11100 may be a direct-viewing endoscope, an oblique-viewing endoscope, or a side-viewing endoscope.

[0140] An optical system and an image sensor are provided inside the camera head 11102, and light reflected from the object of observation (observation light) is collected by the optical system onto the image sensor. The observation light is photoelectrically converted by the image sensor to generate an electrical signal corresponding to the observation light, i.e., an image signal corresponding to the observed image. The image signal is sent to a camera control unit (CCU) 11201 as RAW data.

[0141] The CCU 11201 is configured with a CPU (Central Processing Unit), a GPU (Graphics Processing Unit), etc., and comprehensively controls the operations of the endoscope 11100 and the display device 11202. Furthermore, the CCU 11201 receives an image signal from the camera head 11102 and performs various types of image processing on the image signal, such as development processing (demosaic processing), to display an image based on the image signal.

[0142] Under the control of the CCU 11201, the display device 11202 displays an image based on an image signal that has been subjected to image processing by the CCU 11201.

[0143] The light source device 11203 is composed of a light source such as an LED (Light Emitting Diode), and supplies the endoscope 11100 with irradiation light when photographing the surgical site, etc.

[0144] The input device 11204 is an input interface for the endoscopic surgery system 11000. A user can input various information and instructions to the endoscopic surgery system 11000 via the input device 11204. For example, the user inputs an instruction to change the imaging conditions (type of irradiation light, magnification, focal length, etc.) of the endoscope 11100.

[0145] The treatment tool control device 11205 controls the driving of the energy treatment tool 11112 for cauterizing tissue, incising, sealing blood vessels, etc. The insufflation device 11206 inflates the body cavity of the patient 11132 through the insufflation tube 11111 in order to ensure a clear field of view for the endoscope 11100 and a working space for the surgeon. The recorder 11207 is a device capable of recording various types of information related to the surgery. The printer 11208 is a device capable of printing various types of information related to the surgery in various formats such as text, images, or graphs.

[0146] The light source device 11203, which supplies illumination light to the endoscope 11100 when photographing the surgical site, can be configured from a white light source, such as an LED, a laser light source, or a combination of these. When the white light source is configured from a combination of RGB laser light sources, the output intensity and output timing of each color (each wavelength) can be controlled with high precision, allowing the light source device 11203 to adjust the white balance of the captured image. In this case, it is also possible to time-share images corresponding to each RGB by irradiating the object of observation with laser light from each RGB laser light source and controlling the drive of the image sensor of the camera head 11102 in synchronization with the irradiation timing. According to this method, color images can be obtained without providing a color filter to the image sensor.

[0147] Furthermore, the light source device 11203 may be controlled to change the intensity of light it outputs at predetermined time intervals. By controlling the driving of the image sensor of the camera head 11102 in synchronization with the timing of the change in light intensity to acquire images in a time-division manner and combining the images, it is possible to generate an image with a high dynamic range that is free from so-called blocked-up shadows and blown-out highlights.

[0148] The light source device 11203 may also be configured to supply light in a predetermined wavelength band corresponding to special light observation. Special light observation, for example, utilizes the wavelength dependence of light absorption in body tissues to irradiate a specific tissue, such as blood vessels on the surface of the mucosa, with light in a narrower band than the light irradiated during normal observation (i.e., white light), thereby performing so-called narrow band imaging. Alternatively, special light observation may be performed using fluorescence observation, in which images are obtained using fluorescence generated by irradiating excitation light. Fluorescence observation may involve irradiating excitation light onto body tissue and observing the fluorescence from the tissue (autofluorescence observation), or by locally injecting a reagent such as indocyanine green (ICG) into the body tissue and irradiating the tissue with excitation light corresponding to the fluorescent wavelength of the reagent to obtain a fluorescent image. The light source device 11203 may be configured to supply narrow band light and / or excitation light corresponding to such special light observation.

[0149] FIG. 18 is a block diagram showing an example of the functional configuration of the camera head 11102 and the CCU 11201 shown in FIG.

[0150] The camera head 11102 has a lens unit 11401, an imaging unit 11402, a drive unit 11403, a communication unit 11404, and a camera head control unit 11405. The CCU 11201 has a communication unit 11411, an image processing unit 11412, and a control unit 11413. The camera head 11102 and the CCU 11201 are connected to each other via a transmission cable 11400 so that they can communicate with each other.

[0151] The lens unit 11401 is an optical system provided at the connection portion with the lens barrel 11101. Observation light taken in from the tip of the lens barrel 11101 is guided to the camera head 11102 and enters the lens unit 11401. The lens unit 11401 is composed of a combination of multiple lenses including a zoom lens and a focus lens.

[0152] The imaging unit 11402 may include one imaging element (a so-called single-chip type) or multiple imaging elements (a so-called multi-chip type). When the imaging unit 11402 is configured as a multi-chip type, for example, each imaging element may generate an image signal corresponding to each of RGB, and a color image may be obtained by combining these signals. Alternatively, the imaging unit 11402 may be configured to have a pair of imaging elements for acquiring image signals for the right eye and the left eye corresponding to 3D (dimensional) display. The 3D display allows the surgeon 11131 to more accurately grasp the depth of the biological tissue at the surgical site. Note that when the imaging unit 11402 is configured as a multi-chip type, multiple lens units 11401 may be provided corresponding to each imaging element.

[0153] Furthermore, the imaging unit 11402 does not necessarily have to be provided in the camera head 11102. For example, the imaging unit 11402 may be provided inside the lens barrel 11101, immediately after the objective lens.

[0154] The driving unit 11403 is configured by an actuator, and moves the zoom lens and focus lens of the lens unit 11401 by a predetermined distance along the optical axis under the control of the camera head control unit 11405. This allows the magnification and focus of the image captured by the imaging unit 11402 to be adjusted appropriately.

[0155] The communication unit 11404 is configured by a communication device for transmitting and receiving various types of information to and from the CCU 11201. The communication unit 11404 transmits the image signal obtained from the imaging unit 11402 to the CCU 11201 via the transmission cable 11400 as RAW data.

[0156] Furthermore, the communication unit 11404 receives a control signal for controlling the driving of the camera head 11102 from the CCU 11201 and supplies the control signal to the camera head control unit 11405. The control signal includes information on the imaging conditions, such as information specifying the frame rate of the captured image, information specifying the exposure value at the time of imaging, and / or information specifying the magnification and focus of the captured image.

[0157] The image capturing conditions such as the frame rate, exposure value, magnification, and focus may be appropriately specified by the user, or may be automatically set by the control unit 11413 of the CCU 11201 based on the acquired image signal. In the latter case, the endoscope 11100 is equipped with a so-called AE (Auto Exposure) function, AF (Auto Focus) function, and AWB (Auto White Balance) function.

[0158] The camera head control unit 11405 controls the driving of the camera head 11102 based on a control signal received from the CCU 11201 via the communication unit 11404 .

[0159] The communication unit 11411 is configured by a communication device for transmitting and receiving various information to and from the camera head 11102. The communication unit 11411 receives an image signal transmitted from the camera head 11102 via the transmission cable 11400.

[0160] Furthermore, the communication unit 11411 transmits to the camera head 11102 a control signal for controlling the driving of the camera head 11102. The image signal and the control signal can be transmitted by electrical communication, optical communication, or the like.

[0161] The image processing unit 11412 performs various image processing operations on the image signal, which is RAW data transmitted from the camera head 11102 .

[0162] The control unit 11413 performs various controls related to the imaging of the surgical site, etc. by the endoscope 11100 and the display of the captured image obtained by imaging the surgical site, etc. For example, the control unit 11413 generates a control signal for controlling the driving of the camera head 11102.

[0163] Furthermore, the control unit 11413 displays the captured image showing the surgical site, etc., on the display device 11202 based on the image signal subjected to image processing by the image processing unit 11412. At this time, the control unit 11413 may recognize various objects in the captured image using various image recognition technologies. For example, the control unit 11413 can recognize surgical tools such as forceps, specific biological parts, bleeding, mist generated when using the energy treatment tool 11112, etc., by detecting the shape and color of the edges of objects included in the captured image. When displaying the captured image on the display device 11202, the control unit 11413 may use the recognition results to superimpose various surgical support information on the image of the surgical site. By superimposing the surgical support information and presenting it to the surgeon 11131, the burden on the surgeon 11131 can be reduced and the surgeon 11131 can proceed with the surgery reliably.

[0164] The transmission cable 11400 connecting the camera head 11102 and the CCU 11201 is an electrical signal cable for electrical signal communication, an optical fiber for optical communication, or a composite cable of these.

[0165] In the illustrated example, communication is performed wired using a transmission cable 11400, but communication between the camera head 11102 and the CCU 11201 may also be performed wirelessly.

[0166] The above describes an example of an endoscopic surgery system to which the technology disclosed herein can be applied. The technology disclosed herein can be applied to, for example, the endoscope 11100, the camera head 11102 (the imaging unit 11402), the CCU 11201 (the image processing unit 11412), etc., among the components described above. By applying the technology disclosed herein to these components, the device can be further miniaturized.

[0167] Although an endoscopic surgery system has been described as an example here, the technology according to the present disclosure may also be applied to other systems, such as a microsurgery system.

[0168] 12.3 Application Examples to Mobile Bodies The technology according to the present disclosure (the present technology) may be realized as a device mounted on any type of mobile body, such as an automobile, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, personal mobility, an airplane, a drone, a ship, or a robot.

[0169] FIG. 19 is a block diagram showing a schematic configuration example of a vehicle control system, which is an example of a mobile object control system to which the technology according to the present disclosure can be applied.

[0170] The vehicle control system 12000 includes a plurality of electronic control units connected via a communication network 12001. In the example shown in Fig. 19, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an outside-vehicle information detection unit 12030, an inside-vehicle information detection unit 12040, and an integrated control unit 12050. Also shown as functional components of the integrated control unit 12050 are a microcomputer 12051, an audio / video output unit 12052, and an in-vehicle network I / F (Interface) 12053.

[0171] The drivetrain control unit 12010 controls the operation of devices related to the drivetrain of the vehicle in accordance with various programs. For example, the drivetrain control unit 12010 functions as a control device for a drive force generating device for generating a drive force of the vehicle, such as an internal combustion engine or a drive motor, a drive force transmission mechanism for transmitting the drive force to the wheels, a steering mechanism for adjusting the steering angle of the vehicle, and a braking device for generating a braking force of the vehicle.

[0172] The body system control unit 12020 controls the operation of various devices equipped in the vehicle body according to various programs. For example, the body system control unit 12020 functions as a control device for a keyless entry system, a smart key system, a power window device, or various lamps such as headlamps, backup lamps, brake lamps, turn signals, and fog lamps. In this case, radio waves transmitted from a portable device that serves as a key or signals from various switches can be input to the body system control unit 12020. The body system control unit 12020 receives these radio waves or signals and controls the vehicle's door lock device, power window device, lamps, etc.

[0173] The outside-vehicle information detection unit 12030 detects information outside the vehicle equipped with the vehicle control system 12000. For example, an imaging unit 12031 is connected to the outside-vehicle information detection unit 12030. The outside-vehicle information detection unit 12030 causes the imaging unit 12031 to capture images outside the vehicle and receives the captured images. The outside-vehicle information detection unit 12030 may perform object detection processing or distance detection processing for people, cars, obstacles, signs, characters on the road surface, etc. based on the received images.

[0174] The imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal corresponding to the amount of light received. The imaging unit 12031 can output the electrical signal as an image or as distance measurement information. The light received by the imaging unit 12031 may be visible light or invisible light such as infrared light.

[0175] The in-vehicle information detection unit 12040 detects information inside the vehicle. For example, a driver state detection unit 12041 that detects the state of the driver is connected to the in-vehicle information detection unit 12040. The driver state detection unit 12041 includes, for example, a camera that captures an image of the driver, and the in-vehicle information detection unit 12040 may calculate the degree of fatigue or concentration of the driver based on the detection information input from the driver state detection unit 12041, or may determine whether the driver is dozing off.

[0176] The microcomputer 12051 can calculate control target values ​​for the driving force generating device, steering mechanism, or braking device based on the information inside and outside the vehicle acquired by the outside-vehicle information detection unit 12030 or the inside-vehicle information detection unit 12040, and output control commands to the drive system control unit 12010. For example, the microcomputer 12051 can perform cooperative control aimed at realizing the functions of an ADAS (Advanced Driver Assistance System), including vehicle collision avoidance or impact mitigation, following driving based on the inter-vehicle distance, vehicle speed maintenance driving, vehicle collision warning, vehicle lane departure warning, etc.

[0177] In addition, the microcomputer 12051 can perform cooperative control for the purpose of autonomous driving, which allows the vehicle to travel autonomously without relying on driver operation, by controlling the driving force generating device, steering mechanism, braking device, etc. based on information about the surroundings of the vehicle obtained by the outside vehicle information detection unit 12030 or the inside vehicle information detection unit 12040.

[0178] Furthermore, the microcomputer 12051 can output a control command to the body system control unit 12020 based on the information outside the vehicle acquired by the outside information detection unit 12030. For example, the microcomputer 12051 can control the headlamps according to the position of a preceding vehicle or an oncoming vehicle detected by the outside information detection unit 12030, and perform cooperative control aimed at preventing glare, such as switching from high beams to low beams.

[0179] The audio / video output unit 12052 transmits at least one of audio and video output signals to an output device capable of visually or audibly notifying the passengers of the vehicle or the outside of the vehicle of information. In the example of Fig. 19, the output devices are exemplified by an audio speaker 12061, a display unit 12062, and an instrument panel 12063. The display unit 12062 may include, for example, at least one of an on-board display and a head-up display.

[0180] FIG. 20 is a diagram showing an example of the installation position of the imaging unit 12031.

[0181] In FIG. 20, the imaging unit 12031 includes imaging units 12101, 12102, 12103, 12104, and 12105.

[0182] The imaging units 12101, 12102, 12103, 12104, and 12105 are provided, for example, at positions such as the front nose, side mirrors, rear bumper, back door, and the top of the windshield inside the vehicle cabin of the vehicle 12100. The imaging unit 12101 provided on the front nose and the imaging unit 12105 provided on the top of the windshield inside the vehicle cabin mainly acquire images of the front of the vehicle 12100. The imaging units 12102 and 12103 provided on the side mirrors mainly acquire images of the sides of the vehicle 12100. The imaging unit 12104 provided on the rear bumper or back door mainly acquires images of the rear of the vehicle 12100. The imaging unit 12105 provided on the top of the windshield inside the vehicle cabin is mainly used to detect preceding vehicles, pedestrians, obstacles, traffic lights, traffic signs, lanes, etc.

[0183] 20 shows an example of the imaging ranges of the imaging units 12101 to 12104. Imaging range 12111 indicates the imaging range of the imaging unit 12101 provided on the front nose, imaging ranges 12112 and 12113 indicate the imaging ranges of the imaging units 12102 and 12103 provided on the side mirrors, respectively, and imaging range 12114 indicates the imaging range of the imaging unit 12104 provided on the rear bumper or back door. For example, by overlaying the image data captured by the imaging units 12101 to 12104, an overhead image of the vehicle 12100 viewed from above can be obtained.

[0184] At least one of the image capturing units 12101 to 12104 may have a function of acquiring distance information. For example, at least one of the image capturing units 12101 to 12104 may be a stereo camera made up of multiple image capturing elements, or may be an image capturing element having pixels for phase difference detection.

[0185] For example, based on the distance information obtained from the imaging units 12101 to 12104, the microcomputer 12051 can calculate the distance to each three-dimensional object within the imaging ranges 12111 to 12114 and the change in this distance over time (relative speed with respect to the vehicle 12100), thereby extracting as a preceding vehicle, in particular, the three-dimensional object that is the closest three-dimensional object on the path of the vehicle 12100 and traveling in approximately the same direction as the vehicle 12100 at a predetermined speed (e.g., 0 km / h or higher). Furthermore, the microcomputer 12051 can set a vehicle-to-vehicle distance to be maintained in advance in front of the preceding vehicle, and perform automatic braking control (including follow-up stop control), automatic acceleration control (including follow-up start control), etc. In this way, cooperative control can be performed for the purpose of autonomous driving, which allows the vehicle to travel autonomously without relying on driver operation.

[0186] For example, the microcomputer 12051 classifies and extracts three-dimensional object data regarding three-dimensional objects into two-wheeled vehicles, ordinary vehicles, large vehicles, pedestrians, utility poles, and other three-dimensional objects based on distance information obtained from the imaging units 12101 to 12104, and can use the data for automatic obstacle avoidance. For example, the microcomputer 12051 distinguishes obstacles around the vehicle 12100 into obstacles that are visible to the driver of the vehicle 12100 and obstacles that are difficult to see. The microcomputer 12051 then determines a collision risk that indicates the risk of collision with each obstacle, and when the collision risk is equal to or greater than a set value and a collision is possible, the microcomputer 12051 can provide driving assistance for collision avoidance by outputting an alarm to the driver via the audio speaker 12061 or the display unit 12062, or by performing forced deceleration or avoidance steering via the drive system control unit 12010.

[0187] At least one of the image capturing units 12101 to 12104 may be an infrared camera that detects infrared rays. For example, the microcomputer 12051 can recognize a pedestrian by determining whether a pedestrian is present in the images captured by the image capturing units 12101 to 12104. Such pedestrian recognition is performed, for example, by extracting feature points from the images captured by the image capturing units 12101 to 12104 as infrared cameras and performing pattern matching on a series of feature points that indicate the outline of an object to determine whether the object is a pedestrian. When the microcomputer 12051 determines that a pedestrian is present in the images captured by the image capturing units 12101 to 12104 and recognizes the pedestrian, the audio / image output unit 12052 controls the display unit 12062 to superimpose a rectangular outline on the recognized pedestrian for emphasis. The audio / image output unit 12052 may also control the display unit 12062 to display an icon or the like indicating the pedestrian at a desired position.

[0188] The above describes an example of a vehicle control system to which the technology according to the present disclosure can be applied. The technology according to the present disclosure can be applied to, for example, the image capturing unit 12031, etc., among the components described above. By applying the technology according to the present disclosure to the image capturing unit 12031, etc., the device can be made even more compact.

[0189] <<13. Supplementary Information>> Although preferred embodiments of the present disclosure have been described in detail above with reference to the accompanying drawings, the technical scope of the present disclosure is not limited to such examples. It is clear that a person skilled in the art of the present disclosure can conceive of various modified or altered examples within the scope of the technical idea described in the claims, and it is understood that these also naturally fall within the technical scope of the present disclosure.

[0190] Furthermore, the effects described herein are merely descriptive or exemplary and are not limiting. In other words, the technology according to the present disclosure may achieve other effects that will be apparent to those skilled in the art from the description of this specification, in addition to or in place of the above-described effects.

[0191] The present technology can also be configured as follows. (1) A semiconductor device including a first transistor and a second transistor connected in series by sharing a source / drain, wherein the first transistor has a first gate electrode provided on a first surface of a first semiconductor substrate, and the second transistor has a second gate electrode provided on a second surface of the first semiconductor substrate opposite to the first surface, and when viewed from above the first semiconductor substrate, the first gate electrode and the second gate electrode at least partially overlap. (2) The semiconductor device according to (1), wherein a first shared source / drain region shared by the first and second transistors is a region in the first semiconductor substrate located between the first gate electrode and the second gate electrode in a film thickness direction of the first semiconductor substrate. (3) The semiconductor device according to (2), wherein the first shared source / drain region is a diffusion region containing an impurity provided in the first semiconductor substrate at a first depth from the first surface. (4) The semiconductor device according to (2) or (3), wherein the first shared source / drain region is sandwiched between a first channel region of the first transistor located in the first semiconductor substrate below the first gate electrode and a second channel region of the second transistor located in the first semiconductor substrate below the second gate electrode. (5) The semiconductor device according to (4), wherein the first shared source / drain region is sandwiched between the first channel region and the second channel region in a thickness direction of the first semiconductor substrate. (6) The semiconductor device according to (4), wherein the first shared source / drain region is sandwiched between the first channel region and the second channel region in a direction parallel to the first surface of the first semiconductor substrate. (7) The semiconductor device according to any one of (2) to (4), wherein the first gate electrode has a first vertical gate extending through the first semiconductor substrate from the first surface along a thickness direction of the first semiconductor substrate.(8) The semiconductor device according to (7) above, wherein a surface of the first vertical gate located opposite the first gate electrode is in contact with at least a portion of the first shared source / drain region via a first gate insulating film. (9) The semiconductor device according to (7) or (8) above, wherein the second gate electrode has a second vertical gate extending through the first semiconductor substrate from the second surface along a film thickness direction of the first semiconductor substrate. (10) The semiconductor device according to (9) above, wherein a surface of the second vertical gate located opposite the second gate electrode is in contact with at least a portion of the first shared source / drain region via a second gate insulating film. (11) The semiconductor device according to (9) or (10) above, wherein the length of the first vertical gate is the same as the length of the second vertical gate. (12) The semiconductor device according to (9) or (10) above, wherein the length of the first vertical gate is different from the length of the second vertical gate. (13) The semiconductor device according to any one of (1) to (4) above, wherein a center of the first gate electrode and a center of the second gate electrode coincide with each other when viewed from above the first semiconductor substrate. (14) The semiconductor device according to any one of (1) to (4) above, wherein a center of the first gate electrode and a center of the second gate electrode do not coincide with each other when viewed from above the first semiconductor substrate. (15) The semiconductor device according to any one of (2) to (12) above, wherein the first transistor further has a first source / drain region adjacent to the first gate electrode and provided on the first surface side of the first semiconductor substrate, and the second transistor further has a second source / drain region adjacent to the second gate electrode and provided on the second surface side of the first semiconductor substrate. (16) The semiconductor device according to (15), wherein the first semiconductor substrate contains a first impurity having a first conductivity type, and the first and second source / drain regions and the first shared source / drain region contain a second impurity having a second conductivity type opposite to the first conductivity type. (17) The semiconductor device according to (16), wherein the first shared source / drain region has a lower concentration of the second impurity than the first and second source / drain regions.(18) The semiconductor device according to (16) or (17), including a third transistor and a fourth transistor connected in series by sharing a source / drain, the third transistor having a third gate electrode provided on the first surface of the first semiconductor substrate, the fourth transistor having a fourth gate electrode provided on the second surface of the first semiconductor substrate, and the third and fourth transistors sharing a second shared source / drain region provided in the first semiconductor substrate at a second depth from the first surface. (19) The semiconductor device according to (18), wherein a first element pair consisting of the first transistor and the second transistor and a second element pair consisting of the third transistor and the fourth transistor are separated by a trench or a diffusion region provided in the first semiconductor substrate. (20) The semiconductor device according to any one of (1) to (17), further comprising a photoelectric conversion unit that converts incident light into charges, and a charge accumulation unit that accumulates the charges generated in the photoelectric conversion unit, wherein the photoelectric conversion unit and the charge accumulation unit are electrically connected to the first and second transistors. (21) The semiconductor device according to (20), wherein one of the first transistor and the second transistor is an amplification transistor electrically connected to the charge accumulation unit and that converts charges from the charge accumulation unit into a pixel signal, and the other of the first transistor and the second transistor is a selection transistor electrically connected to the amplification transistor and that selects the pixel signal to be output. (22) The semiconductor device according to (20), wherein one of the first transistor and the second transistor is a switching transistor electrically connected to the charge accumulation unit and that switches connection of the charge accumulation unit to an additional charge accumulation unit, and the other of the first transistor and the second transistor is a reset transistor electrically connected to the charge accumulation unit and that resets the charge accumulation unit. (23) The semiconductor device according to (20), further comprising: a second semiconductor substrate stacked on the first semiconductor substrate and including the photoelectric conversion portion.(24) An electronic device equipped with a semiconductor device, the semiconductor device including: a first transistor and a second transistor connected in series by sharing a source / drain; the first transistor having a first gate electrode provided on a first surface of a first semiconductor substrate; the second transistor having a second gate electrode provided on a second surface of the first semiconductor substrate opposite to the first surface; and when viewed from above the first semiconductor substrate, the first gate electrode and the second gate electrode at least partially overlap each other.

[0192] REFERENCE SIGNS LIST 1 Imaging device 10, 20, 30 Substrate 11, 21, 31 Semiconductor substrate 11a Light incident surface 11b Surface 12 Pixel 13 Pixel region 21a Upper surface 21b Lower surface 22, 22a Readout circuit 23 Pixel drive line 24 Vertical signal line 32 Logic circuit 33 Vertical drive circuit 34 Column signal processing circuit 35 Horizontal drive circuit 36 ​​System control circuit 40 Gate insulating film 44, 46 Insulating layer 48 Contact 50, 60 STI 62 FTI 64 Diffusion region 70 Through electrode 72 Wiring 72a Electrode 101 Photoelectric conversion section 102 Transfer transistor 103 Floating diffusion 201, 201a Reset transistor 202, 202a Amplification transistor 203, 203a Selection transistor 204, 204a Conversion efficiency switching transistor 205 Additional capacitance section 312, 322, 328, 332, 342, 342a, 346, 346a, 348 Source / drain region 314, 324, 334, 344 Gate electrode 314a, 324a, 334a, 344a Vertical gate 315, 325, 335, 345, 345a Channel region 400 Trench 402, 404 Wiring layer 410 Color filter 412 On-chip lens 450, 451, 452 Axis

Claims

1. A semiconductor device comprising: a first transistor and a second transistor connected in series by sharing a source / drain; the first transistor having a first gate electrode provided on a first surface of a first semiconductor substrate; and the second transistor having a second gate electrode provided on a second surface of the first semiconductor substrate opposite to the first surface; and when viewed from above the first semiconductor substrate, the first gate electrode and the second gate electrode at least partially overlap.

2. The semiconductor device according to claim 1, wherein the first shared source / drain region shared by the first and second transistors is a region in the first semiconductor substrate located between the first gate electrode and the second gate electrode in the film thickness direction of the first semiconductor substrate.

3. The semiconductor device according to claim 2, wherein the first shared source / drain region is a diffusion region containing an impurity and provided in the first semiconductor substrate at a first depth from the first surface.

4. The semiconductor device of claim 2, wherein the first shared source / drain region is sandwiched between a first channel region of the first transistor located in the first semiconductor substrate under the first gate electrode and a second channel region of the second transistor located in the first semiconductor substrate under the second gate electrode.

5. The semiconductor device according to claim 2, wherein said first gate electrode has a first vertical gate extending through said first semiconductor substrate from said first surface along a film thickness direction of said first semiconductor substrate.

6. The semiconductor device according to claim 5, wherein said second gate electrode has a second vertical gate extending through said first semiconductor substrate from said second surface along the film thickness direction of said first semiconductor substrate.

7. The semiconductor device according to claim 6, wherein the length of said first vertical gate is the same as the length of said second vertical gate.

8. The semiconductor device according to claim 6, wherein the length of said first vertical gate is different from the length of said second vertical gate.

9. The semiconductor device according to claim 1, wherein the center of said first gate electrode and the center of said second gate electrode coincide with each other when viewed from above said first semiconductor substrate.

10. The semiconductor device according to claim 1, wherein the center of said first gate electrode and the center of said second gate electrode do not coincide when viewed from above said first semiconductor substrate.

11. The semiconductor device according to claim 2, wherein the first transistor further has a first source / drain region provided adjacent to the first gate electrode on the first surface side of the first semiconductor substrate, and the second transistor further has a second source / drain region provided adjacent to the second gate electrode on the second surface side of the first semiconductor substrate.

12. The semiconductor device according to claim 11, wherein the first semiconductor substrate contains a first impurity having a first conductivity type, and the first and second source / drain regions and the first shared source / drain region contain a second impurity having a second conductivity type opposite to the first conductivity type.

13. The semiconductor device according to claim 12, wherein the first shared source / drain region has a lower concentration of the second impurity than the first and second source / drain regions.

14. The semiconductor device according to claim 12, comprising a third transistor and a fourth transistor connected in series by sharing a source / drain, the third transistor having a third gate electrode provided on the first surface of the first semiconductor substrate, the fourth transistor having a fourth gate electrode provided on the second surface of the first semiconductor substrate, and the third and fourth transistors sharing a second shared source / drain region provided in the first semiconductor substrate at a second depth from the first surface.

15. The semiconductor device according to claim 14, wherein a first element pair consisting of the first transistor and the second transistor and a second element pair consisting of the third transistor and the fourth transistor are separated by a trench or a diffusion region provided in the first semiconductor substrate.

16. The semiconductor device according to claim 1, further comprising a photoelectric conversion unit that converts incident light into electric charges, and a charge accumulation unit that accumulates the electric charges generated in the photoelectric conversion unit, wherein the photoelectric conversion unit and the charge accumulation unit are electrically connected to the first and second transistors.

17. The semiconductor device according to claim 16, wherein one of the first transistor and the second transistor is an amplifying transistor electrically connected to the charge storage section and converts charges from the charge storage section into a pixel signal, and the other of the first transistor and the second transistor is a selecting transistor electrically connected to the amplifying transistor and selects the pixel signal to be output.

18. The semiconductor device according to claim 16, wherein one of the first transistor and the second transistor is a switching transistor electrically connected to the charge storage section and switching the connection of the charge storage section to the additional charge storage section, and the other of the first transistor and the second transistor is a reset transistor electrically connected to the charge storage section and resetting the charge storage section.

19. The semiconductor device according to claim 16, further comprising a second semiconductor substrate stacked on the first semiconductor substrate and including the photoelectric conversion section.

20. An electronic device equipped with a semiconductor device, the semiconductor device including: a first transistor and a second transistor connected in series by sharing a source / drain; the first transistor having a first gate electrode provided on a first surface of a first semiconductor substrate; the second transistor having a second gate electrode provided on a second surface of the first semiconductor substrate opposite to the first surface; and when viewed from above the first semiconductor substrate, the first gate electrode and the second gate electrode at least partially overlap.

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