Wiring board and mounting structure

Abstract

A wiring board according to the present disclosure includes: a core layer including a core insulation layer and a core conductor layer; and a build-up layer located on at least one surface of the core layer. The build-up layer includes a first build-up insulation layer, a build-up conductor layer located on the first build-up insulation layer, and a second build-up insulation layer covering the first build-up insulation layer and the build-up conductor layer. The first build-up insulation layer contains an inorganic insulating filler in a proportion of 75% or more by mass. The build-up conductor layer includes at least two wiring conductors located adjacent and parallel to each other in a plan view. The at least two wiring conductors have, on the surface thereof covered by the second build-up insulation layer, first surfaces that are located facing each other and second surfaces that are located on the opposite side to the first build-up insulation layer. The first arithmetic average roughness of the first surface is smaller than the second arithmetic average roughness of the second surface.

Description

Wiring board and mounting structure

[0001] The present invention relates to a wiring board and a mounting structure using the same.

[0002] Conventionally, in wiring boards, the main surface and side surfaces of wiring conductors are subjected to a roughening treatment to form minute irregularities (for example, see Patent Document 1). When minute irregularities are formed on the main surface and side surfaces of the wiring conductors, the adhesive strength between the wiring conductors and the insulating layer is improved.

[0003] JP 2012-109476 A

[0004] The wiring board according to the present disclosure includes a core layer including a core insulating layer and a core conductor layer, and a buildup layer located on at least one surface of the core layer. The buildup layer includes a first buildup insulating layer, a buildup conductor layer located on the first buildup insulating layer, and a second buildup insulating layer covering the first buildup insulating layer and the buildup conductor layer. The first buildup insulating layer contains an inorganic insulating filler at a ratio of 75% by mass or more. The buildup conductor layer includes at least two wiring conductors located adjacent to each other and parallel to each other in a planar view. The at least two wiring conductors have first surfaces located opposite each other on the surface covered by the second buildup insulating layer, and second surfaces located opposite the first buildup insulating layer. The first arithmetic mean roughness of the first surface is smaller than the second arithmetic mean roughness of the second surface.

[0005] A mounting structure according to the present disclosure includes the above-described wiring board and an electronic component mounted on the wiring board.

[0006] 1 is an explanatory diagram for explaining a mounting structure in which an electronic component is mounted on a wiring board according to an embodiment of the present disclosure, an enlarged explanatory diagram for explaining one embodiment of a region X shown in FIG. 1, and another enlarged explanatory diagram for explaining another embodiment of the region X shown in FIG.

[0007] When the main and side surfaces of the wiring conductor are uneven, as in conventional wiring boards, the adhesive strength between the wiring conductor and the insulating layer is improved, as described in the Background Art section. However, the skin effect causes deterioration of electrical characteristics. Therefore, there is a demand for wiring boards that have excellent electrical characteristics while ensuring adhesiveness of the wiring conductor.

[0008] The wiring board according to the present disclosure has a configuration as described in the section on means for solving the problems, and thus has excellent electrical properties while ensuring adhesion of the wiring conductors.

[0009] A wiring board according to an embodiment of the present disclosure will be described with reference to Figures 1 to 3. Figure 1 is an explanatory diagram illustrating a mounting structure 10 in which an electronic component 6 is mounted on a wiring board 1 according to an embodiment of the present disclosure. As shown in Figure 1, the wiring board 1 according to the embodiment includes a core layer including a core insulating layer 20 and a core conductor layer 30, a buildup layer including a buildup insulating layer 21 and a buildup conductor layer 31, and a solder resist 4.

[0010] The core insulating layer 20 is an insulating layer located approximately in the center in the thickness direction of the wiring board 1. The core insulating layer 20 is not particularly limited as long as it is made of an insulating material. Examples of insulating materials include resins such as epoxy resin, bismaleimide-triazine resin, polyimide resin, and polyphenylene ether resin. These resins may be used alone or in combination of two or more. The thickness of the core insulating layer 20 is not particularly limited and may be, for example, 40 μm or more and 2 mm or less.

[0011] Core conductor layers 30 are located on both sides of the core insulating layer 20. The core conductor layer 30 is not particularly limited as long as it is made of a conductive material. Examples of conductive materials include metals such as copper. The thickness of the core conductor layer 30 is not limited and may be, for example, 10 μm or more and 40 μm or less. Although the core conductor layers 30 are located on both sides of the core insulating layer 20 in FIG. 1 , they may be located on at least one side of the core insulating layer 20.

[0012] As shown in FIG. 1 , a through-hole conductor 30a is located in the core insulating layer 20 to electrically connect the top and bottom surfaces of the core insulating layer 20. The through-hole conductor 30a is located in a through-hole that penetrates from the top surface to the bottom surface of the core insulating layer 20. The through-hole conductor 30a is not particularly limited as long as it is made of a conductive material. Examples of conductive materials include metals such as copper. The through-hole conductor 30a is connected to the core conductor layers 30 formed on both surfaces of the core insulating layer 20. The through-hole conductor 30a may be located only on the inner wall surface of the through-hole, or may fill the through-hole. The through-hole conductor 30a may be made of the same metal as the core conductor layer 30, or a different metal.

[0013] As shown in Fig. 1, buildup layers including buildup insulating layers 21 and buildup conductor layers 31 are located on both sides of a core layer including a core insulating layer 20 and a core conductor layer 30. Although the buildup layers are located on both sides of the core layer in Fig. 1, it is sufficient that the buildup layers are located on at least one side of the core layer.

[0014] The build-up insulating layer 21 is not particularly limited as long as it is made of an insulating material. Examples of insulating materials include resins such as epoxy resin, bismaleimide-triazine resin, polyimide resin, and polyphenylene ether resin. These resins may be used alone or in combination of two or more. The thickness of the build-up insulating layer 21 is not particularly limited and may be, for example, 20 μm or more and 70 μm or less.

[0015] The build-up insulating layers 21 may be made of the same resin or different resins. The build-up insulating layers 21 and the core insulating layer 20 may be made of the same resin or different resins. The build-up insulating layers 21 may have the same thickness or different thicknesses.

[0016] The build-up conductor layer 31 is located on the surface of the build-up insulating layer 21. The build-up conductor layer 31 is not particularly limited as long as it is made of a conductive material. Examples of conductive materials include metals such as copper. The thickness of the build-up conductor layer 31 is not limited and may be, for example, 10 μm or more and 25 μm or less.

[0017] The build-up conductor layers 31 may be made of the same metal or different metals. The build-up conductor layers 31 and the core conductor layers 30 may be made of the same metal or different metals. Furthermore, the build-up conductor layers 31 may have the same thickness or different thicknesses.

[0018] Via-hole conductors 31a are located in the build-up insulating layer 21 to electrically connect the upper and lower surfaces of the build-up insulating layer 21. The via-hole conductors 31a are located in via holes that penetrate the upper and lower surfaces of the build-up insulating layer 21. The via-hole conductors 31a are not particularly limited as long as they are made of a conductive material. Examples of conductive materials include metals such as copper. The via-hole conductors 31a are connected to the build-up conductor layers 31 located on the upper and lower surfaces of the build-up insulating layer 21. The via-hole conductors 31a may fill the via holes or may be located only on the inner surfaces of the via holes. The via-hole conductors 31a may be made of the same metal as the build-up conductor layers 31, or may be made of a different metal.

[0019] At least one of the core insulating layer 20 and the build-up insulating layer 21 may contain a reinforcing material. Examples of the reinforcing material include insulating fabric materials such as glass fiber, glass nonwoven fabric, aramid nonwoven fabric, aramid fiber, and polyester fiber. Only one type of reinforcing material may be used, or two or more types may be used in combination.

[0020] 1, a solder resist 4 may be positioned on the surface of the build-up layer. The solder resist 4 is made of a resin, such as an acrylic-modified epoxy resin. The solder resist 4 has openings for electrically connecting the build-up conductor layer 31 and the electrodes of the electronic components 6 via solder 5. Examples of the electronic components 6 include semiconductor integrated circuit elements and optoelectronic elements.

[0021] The buildup layer has a structure in which at least two buildup insulating layers 21 and at least two buildup conductor layers 31 are alternately stacked. In the wiring board 1, when focusing on two adjacent buildup insulating layers 21, the buildup insulating layer 21 on which the buildup conductor layer 31 is located is defined as the "first buildup insulating layer 211." The buildup insulating layer 21 covering the first buildup insulating layer 211 and the buildup conductor layer 31 is defined as the "second buildup insulating layer 212." In other words, when focusing on two adjacent buildup insulating layers 21, the one closer to the core insulating layer 20 is defined as the "first buildup insulating layer 211," and the one farther from the core insulating layer 20 is defined as the "second buildup insulating layer 212."

[0022] As shown in Figure 2, the first buildup insulating layer 211 contains inorganic insulating filler 22. Figure 2 is an enlarged explanatory view for explaining one embodiment of region X shown in Figure 1. The inorganic insulating filler 22 is contained in the first buildup insulating layer 211 at a ratio of 75 mass% or more. Specifically, the inorganic insulating filler 22 is contained at a ratio of 75 mass% or more relative to the total mass of the material (resin) constituting the first buildup insulating layer 211 and the inorganic insulating filler 22. When the inorganic insulating filler 22 is contained at a ratio of 75 mass% or more, the thermal expansion coefficient of the first buildup insulating layer 211 can be sufficiently reduced.

[0023] The inorganic insulating filler 22 is not limited, and examples thereof include silica, barium sulfate, talc, clay, glass, calcium carbonate, and titanium oxide. The average particle size of the inorganic insulating filler 22 is not limited, and may be, for example, 0.1 μm or more and 1.0 μm or less. Only one type of inorganic insulating filler 22 may be used, or two or more types may be used in combination. The inorganic insulating filler 22 may also be contained in the core insulating layer 20.

[0024] As shown in FIG. 2 , the build-up conductor layer 31 includes at least two wiring conductors 32 positioned adjacent to each other in parallel in a plan view. Hereinafter, when describing the physical properties of the wiring conductors 32, the "at least two wiring conductors 32" may be simply referred to as "wiring conductors 32." While FIG. 2 shows two wiring conductors 32, the number of wiring conductors 32 is not limited as long as there are at least two. In FIG. 3 , four wiring conductors 32 are positioned on the first build-up insulating layer 211. FIG. 3 is an enlarged explanatory view illustrating another embodiment of region X shown in FIG. 1 . The at least two wiring conductors 32 may be, for example, differential signal wiring.

[0025] The wiring conductor 32 is not particularly limited as long as it is made of a conductive material. Examples of conductive materials include metals such as copper. The thickness of the wiring conductor 32 is not limited and may be, for example, 10 μm or more and 25 μm or less. The wiring conductor 32 is part of the build-up conductor layer 31 and may be made of the same material as the build-up conductor layer 31, and may have approximately the same thickness. The wiring conductor 32 may have a wiring width of, for example, 3 μm or more and 100 μm or less. The wiring gap between the wiring conductors 32 may be, for example, 3 μm or more and 20 μm or less.

[0026] The wiring conductor 32 has a first surface 321, a second surface 322, and a third surface 323 on the surface covered with the second buildup insulating layer 212 (the surface in contact with the second buildup insulating layer 212). As shown in Figures 2 and 3, the first surface 321 of the surfaces of the wiring conductor 32 corresponds to the surfaces of at least two wiring conductors 32 positioned opposite to each other. The second surface 322 of the surfaces of the wiring conductor 32 corresponds to the surface positioned opposite to the first buildup insulating layer 211. The third surface 323 of the surfaces of the wiring conductor 32 corresponds to the surface positioned opposite to the first surface 321 of the outermost wiring conductor 32, i.e., the wiring conductor 32 positioned at both ends of the at least two wiring conductors 32.

[0027] In the wiring board 1 according to one embodiment, the first arithmetic mean roughness Ra1 of the first surface 321 is smaller than the second arithmetic mean roughness Ra2 of the second surface 322. When at least two wiring conductors 32 are located, such as in differential signal wiring, the wiring conductors 32 are electromagnetically coupled to each other. Therefore, the surface roughness of the opposing side surfaces significantly affects the electrical characteristics.

[0028] In at least two wiring conductors 32, when the first arithmetic mean roughness Ra1 of the first surfaces 321 facing each other is smaller than the second arithmetic mean roughness Ra2 of the second surfaces 322 not facing each other, the influence of transmission loss due to the skin effect on the first surfaces 321 is reduced. As a result, electrical characteristics are improved compared to when the first arithmetic mean roughness Ra1 is large. On the other hand, the second arithmetic mean roughness Ra2 of the second surfaces 322 can be made relatively large, and the anchor effect improves adhesion between the second build-up insulating layer 212 and the wiring conductors 32.

[0029] Furthermore, even when the gap between the wiring conductors 32 is narrow, if the arithmetic mean roughness Ra1 of the opposing first surfaces 321 is smaller than the second arithmetic mean roughness Ra2 of the non-opposing second surfaces 322, resin easily flows in when laminating the second buildup insulating layer 212. As a result, the first buildup insulating layer 211 and the second buildup insulating layer 212 are easily adhered to each other without any gaps, reducing problems such as delamination.

[0030] The first arithmetic mean roughness Ra1 of the first surface 321 is not limited as long as it is smaller than the second arithmetic mean roughness Ra2 of the second surface 322. The first arithmetic mean roughness Ra1 may be, for example, 300 nm or less. When the first arithmetic mean roughness Ra1 is 300 nm or less, the influence of transmission loss due to the skin effect is further reduced, and electrical characteristics are further improved. The second arithmetic mean roughness Ra2 may be, for example, 200 nm or more and 500 nm or less. The difference between the first arithmetic mean roughness Ra1 and the second arithmetic mean roughness Ra2 may be, for example, 50 nm or more and 200 nm or less. When processing is performed to make the first arithmetic mean roughness Ra1 smaller, the second arithmetic mean roughness Ra2 is also formed to be relatively small.

[0031] The third arithmetic mean roughness Ra3 of the third surface 323 is not limited, and may be, for example, greater than the first arithmetic mean roughness Ra1. When the third arithmetic mean roughness Ra3 is greater than the first arithmetic mean roughness Ra1, the anchor effect further improves the adhesion between the second build-up insulating layer 212 and the wiring conductor 32. The third arithmetic mean roughness Ra3 may be, for example, 200 nm or more and 500 nm or less. The difference between the first arithmetic mean roughness Ra1 and the third arithmetic mean roughness Ra3 may be, for example, 50 nm or more and 200 nm or less.

[0032] The second arithmetic mean roughness Ra2 and the third arithmetic mean roughness Ra3 may be substantially the same. The second arithmetic mean roughness Ra2 and the third arithmetic mean roughness Ra3 being substantially the same means that the following formula (I) is satisfied: 0.95Ra2≦Ra3≦1.05Ra2 (I)

[0033] When the second arithmetic mean roughness Ra2 and the third arithmetic mean roughness Ra3 are substantially the same, that is, when the second arithmetic mean roughness Ra2 and the third arithmetic mean roughness Ra3 satisfy formula (I), the second surface 322 and the third surface 323 have substantially the same surface roughness. Therefore, a substantially uniform anchor effect is exerted between the second buildup insulating layer 212 and the second surface 322 and the third surface 323. As a result, variation in adhesion between the second buildup insulating layer 212 and the second surface 322 and the third surface 323 is reduced, and substantially uniform adhesion is exerted.

[0034] 2, the second buildup insulating layer 212 may also contain an inorganic insulating filler 22. The inorganic insulating filler 22 is as described above, and a detailed description thereof will be omitted. The proportion of the inorganic insulating filler 22 contained in the second buildup insulating layer 212 is not limited, and may be, for example, 75 mass % or more of the inorganic insulating filler 22 contained in the second buildup insulating layer 212. The proportion of the inorganic insulating filler 22 is as described above, and a detailed description thereof will be omitted.

[0035] A portion of the inorganic insulating filler 22 may be located in at least a portion of the recesses 32a located on the first surface 321, the second surface 322, and the third surface 323. Specifically, as shown in region Y in FIG. 3 , inorganic insulating filler 22 having a diameter smaller than the opening of the recess 32a may be located in the recess 32a. The opening of the recess 32a may be, for example, 0.1 μm or more and 1 μm or less. The inorganic insulating filler 22 has a smaller CTE (coefficient of thermal expansion) than the resin. Therefore, by being located in the recess 32a, stress on the wiring is reduced even when thermal stress is applied to the substrate during reflow or mounting. As a result, reliability is improved.

[0036] The second buildup insulating layer 212 may have an interface region 212a with the first buildup insulating layer 211 and a non-interface region 212b other than the interface region 212a. The interface region 212a refers to the region from the contact surface between the first buildup insulating layer 211 and the second buildup insulating layer 212 to 10% of the thickness of the second buildup insulating layer 212.

[0037] When the second buildup insulating layer 212 contains the inorganic insulating filler 22 as described above, the content of the inorganic insulating filler 22 in the interface region 212a may be less than the content of the inorganic insulating filler 22 in the non-interface region 212b. With this configuration, the proportion of resin (an insulating material) is higher in the interface region 212a than in the non-interface region 212b. As a result, the adhesion between the first buildup insulating layer 211 and the second buildup insulating layer 212 is improved, and peeling at the contact surfaces between the first buildup insulating layer 211 and the second buildup insulating layer 212 is reduced.

[0038] 2 , when the first buildup insulating layer 211 is in contact with the core conductor layer 30, the first buildup insulating layer 211 may have a contact area 211a with the core conductor layer 30 and a non-contact area 211b other than the contact area 211a. The contact area 211a refers to the area from the contact surface between the first buildup insulating layer 211 and the core conductor layer 30 to 10% of the thickness of the first buildup insulating layer 211.

[0039] The content of inorganic insulating filler 22 in the contact region 211a may be less than the content of inorganic insulating filler 22 in the non-contact region 211b. With this configuration, the contact region 211a has a higher proportion of resin (insulating material) than the non-contact region 211b. As a result, the adhesion between the first buildup insulating layer 211 and the core conductor layer 30 is improved, and peeling at the contact surface between the first buildup insulating layer 211 and the core conductor layer 30 is reduced. Furthermore, since the non-contact region 211b has a higher content of inorganic insulating filler 22, the content of inorganic insulating filler 22 is higher near the wiring conductor 32. Because the filler has a low dielectric loss tangent, the transmission loss of the wiring conductor 32 is further reduced.

[0040] The core conductor layer 30 has a first contact surface 301 in contact with the buildup layer (buildup insulating layer 21) and a second contact surface 302 in contact with the core insulating layer 20. In FIG. 2 , the buildup insulating layer 21 is the first buildup insulating layer 211. The arithmetic mean roughness of the first contact surface 301 and the arithmetic mean roughness of the second contact surface 302 are not limited. For example, the arithmetic mean roughness of the first contact surface 301 may be smaller than the arithmetic mean roughness of the second contact surface 302. This configuration reduces the surface roughness of the first contact surface 301 facing the wiring conductor 32. A return current corresponding to the signal flowing through the wiring conductor 32 also flows through the ground layer of the core conductor layer 30. Therefore, a small surface roughness of the first contact surface 301 reduces the influence of transmission loss due to the skin effect. As a result, electrical characteristics are improved.

[0041] Next, an example of a method for forming build-up layers in the wiring board 1 according to one embodiment will be described. First, a core layer is prepared. The core layer is not limited as long as a core conductor layer 30 is located on at least one surface of a core insulating layer 20. Typically, a through-hole conductor 30a is located in the core insulating layer 20, electrically connecting the top and bottom surfaces of the core insulating layer 20.

[0042] Next, the core layer is subjected to a surface treatment. The surface treatment is not limited, and may be performed using a chemical solution such as an etching solution. In the surface treatment, the arithmetic mean roughness of the surface of the core conductor layer 30 (corresponding to the "first contact surface 301" in Figures 2 and 3) may be smaller than that of the opposite surface (corresponding to the "second contact surface 302" in Figures 2 and 3).

[0043] Next, the surface of the core layer is covered with the material of the first buildup insulating layer 211. Examples of the material of the first buildup insulating layer 211 include prepreg containing a resin such as the above-mentioned epoxy resin. The material of the first buildup insulating layer 211 contains the inorganic insulating filler 22 at a ratio of 75 mass % or more, as described above.

[0044] Next, a curing process is performed to harden the material of the first build-up insulating layer 211. During the curing process, the flow of resin is controlled by adjusting the temperature and pressure conditions. As a result, a portion with a low proportion of inorganic insulating filler 22 and a high proportion of resin and a portion with a high proportion of inorganic insulating filler 22 and a low proportion of resin are formed. The portion with a low proportion of inorganic insulating filler 22 and a high proportion of resin corresponds to the contact region 211a shown in FIG. 2, and the portion with a high proportion of inorganic insulating filler 22 and a low proportion of resin corresponds to the non-contact region 211b shown in FIG. 2.

[0045] A two-stage curing process can also form a region with a high resin content and a region with a low resin content. When the two-stage curing process is performed, the first stage can be performed under processing conditions of, for example, 100° C. or higher and 140° C. or lower for 20 minutes or longer and 40 minutes or shorter, and the second stage can be performed under processing conditions of, for example, 160° C. or higher and 190° C. or lower for 20 minutes or longer and 60 minutes or shorter.

[0046] After the curing process, the material of the first build-up insulating layer 211 is subjected to laser processing and desmearing to form via holes. A seed layer is formed by electroless plating on the surface of the material of the first build-up insulating layer 211 and on the inner wall surfaces of the via holes. The seed layer is formed of a metal such as copper. After the seed layer is formed, a dry film resist is formed to obtain a desired pattern (conductor layer). Next, a build-up conductor layer 31 including a wiring conductor 32 is formed on the surface of the material of the first build-up insulating layer 211 by electrolytic plating, and via hole conductors 31a are formed in the via holes. After the build-up conductor layer 31 and the via hole conductors 31a are formed, the dry film resist is peeled off. After the dry film resist is peeled off, the seed layer in the portion covered with the dry film resist is removed.

[0047] Next, the wiring conductor 32 is subjected to a surface treatment to roughen the surface of the wiring conductor 32. Examples of the surface treatment include a CZ treatment using a treatment solution manufactured by MEC Co., Ltd. The surface roughness of the wiring conductor 32 is controlled by adjusting the flow rate of the CZ treatment solution. Specifically, the flow rate of the CZ treatment solution is adjusted so that the first surface 321 shown in FIG. 2 is relatively smooth and the second surface 322 and the third surface 323 are relatively rough.

[0048] Next, the surface of the first buildup insulating layer 211 and the surface of the buildup conductor layer 31 including the wiring conductor 32 are coated with the material of the second buildup insulating layer 212. The material of the second buildup insulating layer 212 may be the same as the material of the first buildup insulating layer 211. By repeating the process from coating with the material of the second buildup insulating layer 212 to the CZ treatment, a buildup layer having the desired number of layers is formed. When coating with the material of the second buildup insulating layer 212, the coated buildup insulating layer 21 can be considered as the first buildup insulating layer 211.

[0049] Next, a mounting structure according to the present disclosure will be described. As shown in FIG. 1 , a mounting structure 10 according to one embodiment includes a wiring board 1 according to one embodiment and an electronic component 6 located on the surface of the wiring board 1. A build-up conductor layer 31 in an opening of a solder resist 4 is connected to an electrode of the electronic component 6 via solder 5. As described above, examples of the electronic component 6 include a semiconductor integrated circuit element and an optoelectronic element. The electronic component 6 may be located on both surfaces of the wiring board 1, or the electronic component 6 may be located on one surface and, for example, a motherboard may be located on the other surface.

[0050] The embodiments of the present disclosure have been described above. However, the invention according to the present disclosure is not limited to the above embodiments, and various modifications and improvements are possible within the scope of the present disclosure as shown in (1) to (10) below.

[0051] (1) A wiring board according to the present disclosure includes a core layer including a core insulating layer and a core conductor layer, and a buildup layer located on at least one surface of the core layer. The buildup layer includes a first buildup insulating layer, a buildup conductor layer located on the first buildup insulating layer, and a second buildup insulating layer covering the first buildup insulating layer and the buildup conductor layer. The first buildup insulating layer contains an inorganic insulating filler at a ratio of 75% by mass or more. The buildup conductor layer includes at least two wiring conductors located adjacent to each other and parallel to each other in a planar view. The at least two wiring conductors have first surfaces located opposite each other on the surface covered by the second buildup insulating layer, and second surfaces located opposite the first buildup insulating layer. The first arithmetic mean roughness of the first surface is smaller than the second arithmetic mean roughness of the second surface. (2) The wiring board according to (1) above, wherein the surface of the outermost wiring conductor of the at least two wiring conductors that is covered with the second build-up insulating layer further includes a third surface located on the opposite side of the first surface. The third arithmetic mean roughness of the third surface is greater than the first arithmetic mean roughness. (3) The wiring board according to (1) or (2) above, wherein the at least two wiring conductors include differential signal wiring. (4) The wiring board according to any one of (1) to (3) above, wherein the first arithmetic mean roughness is 300 nm or less. (5) The wiring board according to any one of (2) to (4) above, wherein the second build-up insulating layer contains an inorganic insulating filler in a proportion of 75 mass % or more. The inorganic insulating filler is located in at least some of the recesses located on the first surface, the second surface, and the third surface. (6) In the wiring board described in any one of (1) to (5) above, the second build-up insulating layer contains an inorganic insulating filler in a proportion of 75 mass% or more and has an interface region with the first build-up insulating layer and a non-interface region other than the interface region. The content of inorganic insulating filler in the interface region is less than the content of inorganic insulating filler in the non-interface region. (7) In the wiring board described in any one of (1) to (6) above, the first build-up insulating layer is in contact with the core conductor layer and has a contact region with the core conductor layer and a non-contact region other than the contact region.The content of inorganic insulating filler in the contact region is less than the content of inorganic insulating filler in the non-contact region. (8) In the wiring board described in any one of (1) to (7) above, the core conductor layer has a first contact surface in contact with the buildup layer and a second contact surface in contact with the core insulating layer. The arithmetic mean roughness of the first contact surface is smaller than the arithmetic mean roughness of the second contact surface. (9) In the wiring board described in any one of (2) to (8) above, when the second arithmetic mean roughness is Ra2 and the third arithmetic mean roughness is Ra3, the following formula (I) is satisfied: 0.95Ra2≦Ra3≦1.05Ra2 (I) (10) A mounting structure according to the present disclosure includes the wiring board described in any one of (1) to (9) above and an electronic component mounted on the wiring board.

[0052] REFERENCE SIGNS LIST 1 wiring substrate 20 core insulating layer 21 build-up insulating layer 211 first build-up insulating layer 211a contact region 211b non-contact region 212 second build-up insulating layer 212a interface region 212b non-interface region 22 inorganic insulating filler 30 core conductor layer 30a through-hole conductor 301 first contact surface 302 second contact surface 31 build-up conductor layer 31a via-hole conductor 32 wiring conductor 321 first surface 322 second surface 323 third surface 32a recess 4 solder resist 5 solder 6 electronic component 10 mounting structure

Claims

1. A wiring board comprising: a core layer including a core insulating layer and a core conductor layer; and a buildup layer located on at least one surface of the core layer, wherein the buildup layer includes a first buildup insulating layer, a buildup conductor layer located on the first buildup insulating layer, and a second buildup insulating layer covering the first buildup insulating layer and the buildup conductor layer, wherein the first buildup insulating layer contains an inorganic insulating filler in a proportion of 75 mass% or more, wherein the buildup conductor layer includes at least two wiring conductors located adjacent to each other and parallel to each other in a planar view, wherein the at least two wiring conductors have, on the surface covered by the second buildup insulating layer, first surfaces located opposite each other and a second surface located opposite the first buildup insulating layer, and wherein a first arithmetic mean roughness of the first surface is smaller than a second arithmetic mean roughness of the second surface.

2. The wiring board according to claim 1, further comprising a third surface located opposite to the first surface on the surface covered with the second build-up insulating layer of the outermost wiring conductor of the at least two wiring conductors, and a third arithmetic mean roughness of the third surface is greater than the first arithmetic mean roughness.

3. The wiring board according to claim 1 or 2, wherein the at least two wiring conductors include differential signal wiring.

4. The wiring board according to any one of claims 1 to 3, wherein the first arithmetic mean roughness is 300 nm or less.

5. A wiring board according to any one of claims 2 to 4, wherein the second build-up insulating layer contains the inorganic insulating filler in a proportion of 75 mass% or more, and the inorganic insulating filler is located in at least some of the recesses located on the first surface, the second surface, and the third surface.

6. A wiring board according to any one of claims 1 to 5, wherein the second build-up insulating layer contains the inorganic insulating filler in a proportion of 75 mass% or more, has an interface region with the first build-up insulating layer and a non-interface region other than the interface region, and the content of the inorganic insulating filler in the interface region is less than the content of the inorganic insulating filler in the non-interface region.

7. A wiring board according to any one of claims 1 to 6, wherein the first build-up insulating layer is in contact with the core conductor layer and has a contact area with the core conductor layer and a non-contact area other than the contact area, and the content of the inorganic insulating filler in the contact area is less than the content of the inorganic insulating filler in the non-contact area.

8. A wiring board according to any one of claims 1 to 7, wherein the core conductor layer has a first contact surface in contact with the build-up layer and a second contact surface in contact with the core insulating layer, and the arithmetic mean roughness of the first contact surface is smaller than the arithmetic mean roughness of the second contact surface.

9. The wiring board according to any one of claims 2 to 8, wherein the second arithmetic mean roughness is Ra2 and the third arithmetic mean roughness is Ra3, and the wiring board satisfies the following formula (I): 0.95Ra2≦Ra3≦1.05Ra2 (I) 10. A mounting structure comprising: a wiring board according to any one of claims 1 to 9; and an electronic component mounted on the wiring board.

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