Storage device, electronic equipment, and control method for storage device

Abstract

A storage device according to an embodiment of the present invention includes: a magnetoresistive element the resistance state of which can be varied between a first state and a second state by the application of voltage; a selection element that is connected to the magnetoresistive element; a load resistance circuit the resistance value of which is variable; and a write circuit that imparts voltage to the magnetoresistive element via the load resistance circuit. The write circuit switches voltage between a first voltage for setting the resistance state to the first state and a second voltage for setting the resistance state to the second state and outputs such voltage.

Description

Storage device, electronic device, and storage device control method

[0001] The present disclosure relates to a storage device, an electronic device, and a method for controlling a storage device.

[0002] Magnetoresistive random access memory (MRAM) using magnetoresistive elements maintains its state depending on the magnetization state of a ferromagnetic material, and is therefore nonvolatile, retaining data even when power is turned off. Examples of MRAM include VC-MRAM, which utilizes voltage-controlled magnetic anisotropy (VCMA). Patent Document 1 discloses a technique for reversing magnetization by applying a pulse voltage to a magnetoresistive element having the VCMA effect. In Patent Document 1, an initial read is performed as the first step after writing begins.

[0003] JP 2018-92696 A

[0004] Y. C. Wu et al., "Deterministic and field-free voltage-controlled MRAM for high performance and low power applications," 2020 IEEE Symposium on VLSI Technology, July 16, 2020

[0005] However, in the technology of Patent Document 1, the initial read increases the processing time of the entire write process. For this reason, it is desirable to omit the initial read, but omitting the initial read causes erroneous writing, thereby reducing the accuracy of data writing. Furthermore, in the technology of Patent Document 1, it is difficult to appropriately control the pulse width required for magnetization reversal in the pulse voltage, and it is difficult to apply the pulse voltage to the magnetoresistive element with high accuracy, which reduces the accuracy of data writing.

[0006] Therefore, the present disclosure provides a storage device, an electronic device, and a method for controlling a storage device that can improve data writing accuracy.

[0007] The memory device according to the embodiment comprises a magnetoresistive element whose resistance state can be changed between a first state and a second state by applying a voltage, a selection element connected to the magnetoresistive element, a load resistance circuit whose resistance value can be changed, and a write circuit that applies a voltage to the magnetoresistive element via the load resistance circuit, and the write circuit outputs a first voltage that changes the resistance state to the first state and a second voltage that changes the resistance state to the second state.

[0008] An electronic device according to an embodiment includes a memory device for storing data, the memory device including a magnetoresistive element whose resistance state can be changed between a first state and a second state by applying a voltage, a selection element connected to the magnetoresistive element, a load resistance circuit whose resistance value can be changed, and a write circuit that applies a voltage to the magnetoresistive element via the load resistance circuit, and the write circuit outputs a first voltage that changes the resistance state to the first state and a second voltage that changes the resistance state to the second state by changing the voltage.

[0009] A control method for a memory device according to an embodiment includes a write circuit applying a voltage to a magnetoresistive element whose resistance state can be changed between a first state and a second state by applying a voltage via a load resistance circuit whose resistance value can be changed, and the write circuit outputs a first voltage that changes the resistance state to the first state and a second voltage that changes the resistance state to the second state, by changing the voltage.

[0010] 1 is a diagram showing an example of the configuration of a memory device according to the first embodiment; FIG. 2 is a diagram showing an example of the configuration of a memory cell according to the first embodiment; FIG. 3 is a diagram showing an example of the configuration of various circuits including a load resistance circuit according to the first embodiment; FIG. 4 is a diagram showing a flowchart of a write process according to the first embodiment; FIG. 5 is a diagram showing a timing chart of a write process to a high resistance according to the first embodiment; FIG. 6 is a diagram showing a timing chart of a write process to a low resistance according to the first embodiment; FIG. 7 is a graph showing the voltage dependence of perpendicular magnetic anisotropy of a magnetoresistive element according to the first embodiment; FIG. 8 is a diagram for explaining voltage division when a voltage is applied to a magnetoresistive element via a load resistance according to the first embodiment; FIG. 9 is a diagram showing the behavior of a magnetization vector due to voltage application via a fixed resistor according to the first embodiment; FIG. 10 is a diagram showing the behavior of a magnetization vector due to voltage application via another fixed resistor according to the first embodiment; FIG. 11 is a diagram schematically showing the time change of voltage division according to the first embodiment; FIG. 12 is a diagram for explaining a magnetization motion simulation result of a magnetoresistive element whose initial state is a low resistance state according to the first embodiment; FIG. 13 is a diagram for explaining a magnetization motion simulation result of a magnetoresistive element whose initial state is a high resistance state according to the first embodiment; FIG. 14 is a diagram for explaining high resistance writing by rectangular pulse application according to the first embodiment; FIG. 15 is a diagram for explaining high resistance writing by non-rectangular pulse application according to the first embodiment. FIG. 1 is a diagram for explaining another example of high resistance writing according to the first embodiment. FIG. 2 is a diagram for explaining voltage waveforms of various shapes according to the first embodiment. FIG. 3 is a diagram for explaining another example of high resistance writing according to the first embodiment. FIG. 4 is a diagram for explaining another example of high resistance writing according to the first embodiment. FIG. 5 is a diagram for explaining a configuration example of a write pulse generating circuit according to the first embodiment. FIG. 6 is a diagram for explaining an operation example of the write pulse generating circuit according to the first embodiment. FIG. 7 is a diagram for explaining an operation example of the write pulse generating circuit according to the first embodiment. FIG. 8 is a diagram for explaining a configuration example of another write pulse generating circuit according to the first embodiment. FIG. 9 is a diagram schematically showing a write unit according to the second embodiment. FIG. 10 is a circuit diagram showing a configuration example of a write unit according to the second embodiment. FIG. 11 is a circuit diagram showing a configuration example of a read unit according to the second embodiment.Fig. 10 is a diagram for explaining high resistance writing by applying a rectangular pulse according to a second embodiment. Fig. 11 is a diagram for explaining high resistance writing by applying a non-rectangular pulse according to a second embodiment. Fig. 12 is a diagram showing an application example of a memory device according to each embodiment. Fig. 13 is a diagram showing a configuration example of an imaging device according to an application example. Fig. 14 is a diagram showing a configuration example of a distance measuring device according to an application example.

[0011] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the drawings. The embodiments include examples and modifications. Note that the technology according to the present disclosure is not limited to the embodiments. In the following embodiments, the same components are basically designated by the same reference numerals, and redundant explanations will be omitted.

[0012] The present inventors developed a compact model of an MTJ with a VCMA effect written in Verilog-A language that can be incorporated into a SPICE (Simulation Program with Integrated Circuit Emphasis) simulator. As a result of research using SPICE simulations with this MTJ model, they invented a non-toggle write method. In the non-toggle write method disclosed herein, for example, in a memory cell in which a cell transistor and an MTJ are connected in series and a load resistor connected in series to the memory cell, different voltages are applied to the memory cell and the load resistor when writing state 1 and when writing state 0. In this case, the applied voltage is divided between the MTJ and the load resistor, and the divided voltage applied to the MTJ changes depending on the state already written in the MTJ. As a result, it is possible to prevent erroneous writes when state 1 has been written and state 1 is to be written, and when state 0 has been written and state 0 is to be written. Therefore, while the toggle-type write method of the prior art required reading of the initial state before writing, the non-toggle-type write method of the present disclosure does not require reading of the initial state before writing. This makes it possible to reduce the read time and power consumption required for the initial read. The non-toggle-type write method of the present disclosure will be described in detail later.

[0013] The present disclosure will be described in the following order: 1. First Embodiment 1-1. Configuration Example of a Memory Device 1-2. Configuration Example of a Memory Cell 1-3. Configuration Examples of Various Circuits Including a Load Resistance Circuit 1-4. Example of a Write Process 1-5. Example of a Timing Chart of a Write Process 1-6. Example of Voltage Dependence of Perpendicular Magnetic Anisotropy of a Magnetoresistive Element 1-7. Example of Voltage Division by a Load Resistor 1-8. Example of Behavior of a Magnetization Vector by Application of Voltage via a Load Resistor 1-9. Example of a Write Voltage Waveform 1-10. Write Pulse Generation Circuit 2. Second Embodiment 2-1. Configuration Example of a Write Unit 2-2. Example of a Write Voltage Waveform 3. Functions and Effects of Each Embodiment 4. Other Embodiments 5. Application Examples 5-1. Various Devices 5-2. Imaging Device 5-3. Distance Measuring Device 6. Supplementary Notes

[0014] <1. First embodiment> <1-1. Configuration example of storage device> An example of the configuration of a storage device 100 according to the first embodiment will be described with reference to Fig. 1. Fig. 1 is a diagram showing an example of the configuration of the storage device 100 according to the first embodiment.

[0015] 1, a memory device 100 includes a memory cell array 1. The memory device 100 is an example of a memory device that stores data based on the magnetization direction of a magnetic material.

[0016] The memory cell array 1 includes a plurality of memory cells 10. The memory cells 10 are arranged in a two-dimensional matrix. Each of these memory cells 10 stores data. Each of the memory cells 10 is connected to a bit line BL, a source line SL, and a word line WL. For example, each of the plurality of word lines WL is wired to extend in the row direction, and each of the plurality of bit lines BL and the plurality of source lines SL is wired to extend in the column direction. Each of the bit lines BL, source lines SL, and word lines WL functions, for example, as a control line.

[0017] Each memory cell 10 has a magnetoresistive element (magnetoresistive effect element) 11 and a selection element 12. The magnetoresistive element 11 is, for example, a voltage-controlled magnetoresistive element whose resistance value is variable by applying a voltage. For example, an MTJ (Magnetic Tunnel Junction) element is used as the magnetoresistive element 11. The MTJ element has, for example, a voltage-controlled magnetic anisotropy (VCMA) effect. The selection element 12 is connected to one end of the magnetoresistive element 11 and controls the application of voltage, current, etc. to the magnetoresistive element 11. For example, various transistors are used as the selection element 12.

[0018] The memory cells 10 share one source line SL for every two columns. That is, each of the memory cells 10 arranged in two columns is connected to two bit lines BL and one source line SL (2BL / 1SL). Note that each of the memory cells 10 may have one source line SL for each column. That is, each of the memory cells 10 arranged in one column may be connected to one bit line BL and one source line SL (1BL / 1SL).

[0019] In addition to the memory cell array 1, the memory device 100 includes a peripheral circuit 20. In the example of Fig. 1, the peripheral circuit 20 has an I / O (input / output circuit) 21, a control circuit 22, a voltage generation circuit 23, a write circuit 24, a read circuit 25, a bit line address decoder 26, a bit line control circuit 27, a word line address decoder 28, a word line control circuit 29, and a sense amplifier 30. The basic configuration of such a memory is publicly known, so the basic configuration will be briefly described.

[0020] The I / O 21 enables the transfer of commands related to reading and writing data, addresses of memory cells 10 to be accessed, data, etc. between external circuits of the memory device 100 (e.g., a central processing unit, an arithmetic unit, etc.) and the control circuit 22 of the memory device 100.

[0021] In response to a command, the control circuit 22 controls the writing and reading of data to and from the memory cell 10. Specifically, the control circuit 22 receives a command (e.g., a command for writing or reading) from an external circuit, and controls the writing and reading of data based on the received command.

[0022] The voltage generating circuit 23 generates a voltage (for example, a pulse voltage) used to read and write data from and to the memory cell 10. Note that a voltage (power supply voltage) required for circuit operation is provided separately.

[0023] The write circuit 24 controls the voltage (for example, pulse voltage) used to write data to the memory cell 10 based on a control signal from the control circuit 22. The write circuit 24 has a load resistance circuit 241. The load resistance circuit 241 will be described in detail later.

[0024] The read circuit 25 controls the voltage (for example, pulse voltage) used to read data from the memory cell 10 , that is, to detect the resistance value of the magnetoresistive element 11 , based on a control signal from the control circuit 22 .

[0025] The bit line address decoder 26 selects a bit line BL of the memory cell array 1 based on a control signal from the control circuit 22. For example, the bit line address decoder 26 obtains the address (BL address) of the bit line BL corresponding to the address received by the I / O 21 described above.

[0026] The bit line control circuit 27 selects and controls the bit line BL corresponding to the address of the bit line address decoder 26. The bit line control circuit 27 is connected to each of the bit lines BL.

[0027] The word line address decoder 28 selects a word line WL of the memory cell array 1 based on a control signal from the control circuit 22. For example, the word line address decoder 28 obtains the address (WL address) of the word line WL corresponding to the address received by the I / O 21 described above.

[0028] The word line control circuit 29 selects and controls the word line WL corresponding to the address of the word line address decoder 28. The word line control circuit 29 is connected to each of the word lines WL.

[0029] The sense amplifier 30 detects data read from the memory cell 10 via the source line SL, that is, the resistance state (resistance value) of the magnetoresistive element 11. The sense amplifier 30 is connected to each of the source lines SL.

[0030] <1-2. Configuration Example of Memory Cell> A configuration example of the memory cell 10 according to the first embodiment will be described with reference to Fig. 2. Fig. 2 is a diagram showing a configuration example of the memory cell 10 according to the first embodiment.

[0031] As shown in FIG. 2 , the memory cell 10 includes a magnetoresistive element 11 and a selection element 12. The magnetoresistive element 11 and the selection element 12 are connected in series between a bit line BL and a source line SL. In the example of FIG. 2 , a voltage that can be applied to the memory cell 10 and the load resistance circuit 241 is referred to as voltage V. The voltage V is controlled by the write circuit 24 or the read circuit 25 (see FIG. 1 ), and is applied to the memory cell 10 via the load resistance circuit 241. In other words, the voltage V is applied to the memory cell 10 including the load resistance circuit 241. Note that the resistance value of the selection element 12 is much smaller than that of the magnetoresistive element 11 and the load resistance circuit 241.

[0032] The magnetoresistive element 11 is, for example, an MTJ element having a VCMA effect, and has a stacked structure. In the example of FIG. 2, for convenience of explanation, an XYZ coordinate system for the magnetoresistive element 11 is illustrated. The X-axis direction and Y-axis direction correspond to the plane directions of the layers. The X-axis direction, Y-axis direction, and XY plane direction may also be referred to as the horizontal direction. The Z-axis direction corresponds to the direction perpendicular to the plane directions of the layers (stacking direction). The Z-axis direction may also be referred to as the vertical direction.

[0033] The magnetoresistive element 11 includes a fixed layer 111, a tunnel barrier layer 112, a recording layer 113, and multiple magnetic field generation layers 114 and 115. In the example of FIG. 2 , the magnetic field generation layer 115, the fixed layer 111, the tunnel barrier layer 112, the recording layer 113, and the magnetic field generation layer 114 are stacked in the positive direction of the Z axis in the order shown. Various known materials may be used for the materials of each layer. Only one of the magnetic field generation layers 114 and 115 may be present.

[0034] The fixed layer 111 is a magnetic layer whose magnetization direction is fixed, and is also called a reference layer, etc. The magnetization of the fixed layer 111 is fixed, for example, in the positive direction of the Z axis.

[0035] The tunnel barrier layer 112 is a non-magnetic layer provided between the fixed layer 111 and the recording layer 113 .

[0036] The recording layer 113 is a magnetic layer whose magnetization direction changes, and is also called a free layer, etc. The magnetization of the recording layer 113 changes, for example, between the positive direction of the Z axis and the negative direction of the Z axis.

[0037] The arrangement of the fixed layer 111 and the recording layer 113 may be opposite to that in the example of Fig. 2. In that case, the recording layer 113, the tunnel barrier layer 112, and the fixed layer 111 are stacked in the positive direction of the Z axis in the order shown.

[0038] The magnetic field generation layer 114 generates a horizontal magnetic field. That is, the memory cell 10 is configured so that the recording layer 113 is subjected to a magnetic field (horizontal magnetic field) in the plane direction of the layer (XY plane direction). In the example of FIG. 2 , the magnetic field generation layer 114 and the tunnel barrier layer 112 are provided to sandwich the recording layer 113.

[0039] The magnetic field generation layer 114 may be provided to sandwich the fixed layer 111 together with the tunnel barrier layer 112. A method other than the magnetic field generation layer 114 may also be used to generate the horizontal magnetic field. For example, the horizontal magnetic field may be generated by forming a magnet layer above (the positive Z-axis direction side) or below (the negative Z-axis direction side) the magnetoresistive element 11. The horizontal magnetic field may also be generated by arranging a permanent magnet in the periphery.

[0040] The magnetic field generation layer 115 generates a perpendicular magnetic field. That is, the memory cell 10 is configured so that the recording layer 113 is also subjected to a magnetic field (perpendicular magnetic field) in a direction perpendicular to the plane of the layer (Z-axis direction). In the example of FIG. 2 , the magnetic field generation layer 115 and the tunnel barrier layer 112 are disposed to sandwich the fixed layer 111.

[0041] The magnetic field generation layer 115 may be provided to sandwich the recording layer 113 together with the tunnel barrier layer 112. A method other than the magnetic field generation layer 115 may also be used to generate the perpendicular magnetic field. For example, the perpendicular magnetic field may be generated by forming a magnet layer above (the positive Z-axis direction side) or below (the negative Z-axis direction side) the magnetoresistive element 11. The perpendicular magnetic field may also be generated by arranging a permanent magnet in the periphery.

[0042] The selection element 12 is, for example, a field effect transistor (FET). One of the drain terminal and source terminal of the selection element 12 is connected to the magnetoresistive element 11. The other of the drain terminal and source terminal of the selection element 12 is connected to a source line SL. The gate terminal of the selection element 12 is connected to a word line WL. A voltage signal from the word line WL is applied to the gate of the selection element 12, turning on the selection element 12, thereby connecting the magnetoresistive element 11 to the bit line BL and the source line SL, and applying a voltage V to the magnetoresistive element 11, etc.

[0043] The resistance state (resistance value R) of the magnetoresistive element 11 is in a low resistance state (low resistance value R Ｌ ) and high resistance state (high resistance value R Ｈ ), data (e.g., 0 or 1) is written to the memory cell 10. The low resistance state is a state in which the magnetization directions of the fixed layer 111 and the recording layer 113 are the same (parallel state), and the high resistance state is a state in which the magnetization directions of the fixed layer 111 and the recording layer 113 are different (anti-parallel state). For example, the magnetization direction of the recording layer 113 is reversed between the positive direction of the Z axis and the negative direction of the Z axis, so that the resistance state of the magnetoresistive element 11 switches between a low resistance state and a high resistance state. For example, data corresponding to the low resistance state is 0, and data corresponding to the high resistance state is 1.

[0044] According to the magnetoresistive element 11 described above, not only a horizontal magnetic field but also a vertical magnetic field is used. The vertical magnetic field causes the magnetization component m of the recording layer 113 to change. Ｚ The change in magnetic field energy from -1 to 1 has asymmetry. Ｚ The range in which the magnetization component m Ｚ <0), that is, by designing the magnetic field energy to be minimum when the magnetization of the recording layer 113 approaches the negative Z-axis direction, it is possible to suppress the oscillation of the magnetization direction and reverse it to the negative Z-axis direction. Ｈ It can be made into.

[0045] As mentioned above, the basic structure of the magnetoresistive element 11 is a sandwich structure in which a non-magnetic insulating thin film is sandwiched between two magnetic thin films. This structure is called a magnetic tunnel junction (MTJ). Because the non-magnetic thin film is very thin, only a few nanometers thick, a tunnel current flows when a voltage is applied to both ends of the element. The magnitude of this tunnel current is characterized by its dependence on the relative angle between the magnetizations of the two magnetic layers. This is called the tunnel magnetoresistance (TMR) effect. In MRAM, the magnetization of one of the two magnetic layers (the fixed layer 111) is fixed, and the magnetization of the other magnetic layer (the recording layer 113) is controlled by an external field. Examples of external fields used to control the magnetization direction include methods using voltage-controlled magnetic anisotropy (VCMA). The TMR effect is used to read the state.

[0046] As described above, writing to the memory cell 10 is performed by reversing the resistance state of the magnetoresistive element 11. Ｌ ) and high resistance state (high resistance value R Ｈ ) is inverted by applying a predetermined write voltage to the magnetoresistive element 11. Reading is performed by applying a predetermined read voltage to the magnetoresistive element 11 and detecting the current flowing through the memory cell 10. The read voltage is preferably a voltage of a different polarity from the write voltage.

[0047] <1-3. Configuration Examples of Various Circuits Including Load Resistance Circuit> Configuration examples of various circuits including the load resistance circuit 241 according to the first embodiment will be described with reference to Fig. 3. Fig. 3 is a diagram showing configuration examples of various circuits including the load resistance circuit 241 according to the first embodiment.

[0048] 3, the load resistance circuit 241 includes a plurality of fixed resistors R1 and R2 and a switch SW1. In the example of FIG. 3, the load resistance circuit 241 is provided on a wiring path between the voltage generation circuit 23 and the bit line control circuit 27.

[0049] The fixed resistors R1 and R2 function as load resistors. １ is the resistance value R of the fixed resistor R2 ２ is smaller than (R １ <R ２ ). The switch SW1 switches the wiring path upon receiving a switching signal from the control circuit 22. For example, the switch SW1 switches between the wiring path passing through the fixed resistor R1 and the wiring path passing through the fixed resistor R2. That is, the load resistance circuit 241 can be connected to the voltage generation circuit 23 and the bit line control circuit 27 by switching the wiring path passing through each of the fixed resistors R1 and R2 using the switch SW1.

[0050] The load resistor circuit 241 is a circuit that switches between the fixed resistors R1 and R2 to change the resistance value. １ , resistance value R ２ For example, the load resistance circuit 241 sets the resistance value of the magnetoresistive element 11 to a high resistance value R Ｈ When writing to a high resistance, a voltage V is applied to the magnetoresistive element 11 via a fixed resistor R1, and the resistance value of the magnetoresistive element 11 is changed to a low resistance value R ＬWhen programming to a low resistance, i.e., when writing to a low resistance, a voltage V is applied to the magnetoresistive element 11 via the fixed resistor R2. For example, the magnitude of the voltage V when writing may be the same when programming to a low resistance and when writing to a high resistance, or may be different.

[0051] The bit line address decoder 26 has the function of connecting (turning on) only the bit line BL of the memory cell 10 to be accessed to the voltage generation circuit 23 via the load resistance circuit 241 for the address instructed by the control circuit 22, and leaving the other bit lines BL unconnected (turned off).

[0052] The bit line control circuit 27 passes a write signal (program signal) only to the bit line BL that is to be accessed based on the control signal of the bit line address decoder 26. The potential applied to the bit line BL that is not accessed can be switched to GND potential (ground potential) or floating potential.

[0053] The word line address decoder 28 has the function of connecting (turning on) only the word line WL of the memory cell 10 to be accessed to the voltage generation circuit 23 for the address instructed by the control circuit 22, and leaving the other word lines WL unconnected (turned off).

[0054] The word line control circuit 29 turns on the selection element 12 only for the word line WL to be accessed based on the control signal from the word line address decoder 28. For the word lines WL that are not accessed, the GND potential is applied to turn off the selection element 12. A negative voltage may be used instead of the GND potential as long as it can turn off the selection element 12.

[0055] The source line SL is connected to GND during writing (programming) and is connected to the sense amplifier 30 during reading. Reading is performed by, for example, detecting the current flowing through the memory cell 10 with the sense amplifier 30.

[0056] The configuration of the load resistance circuit 241 described above is not limited to the configuration shown in FIG. 3. That is, the configuration shown in FIG. 3 is merely an example, and the storage device 100 according to the embodiment can have various configurations. For example, a load resistance circuit 241 with a different configuration may have variable resistors instead of the fixed resistors R1 and R2. A variable resistor is a resistor whose resistance value is variable. This variable resistor functions as a load resistor. Such a load resistance circuit 241 changes the resistance value of the variable resistor in response to control from the control circuit 22. For example, the load resistance circuit 241 changes the resistance value of the variable resistor to a resistance value R １ or resistance value R ２ Change to.

[0057] <1-4. Example of Write Processing> An example of the write processing according to the first embodiment will be described with reference to Fig. 4. Fig. 4 is a diagram showing a flowchart of the write processing according to the first embodiment.

[0058] The control circuit 22 (for example, a state machine included in the control circuit 22) controls the write process. The flowchart starts when a write command and write data are input from the I / O 21 to the control circuit 22. For convenience, data corresponding to low resistance (low resistance state) is 0, and data corresponding to high resistance (high resistance state) is 1.

[0059] 4, in step S11, it is determined whether the write is to a high resistance, i.e., whether the write data is 1. If it is determined that the write data is 1 (step S11: Yes), in step S12, the load resistance is set to the fixed resistor R1, i.e., the resistance value of the load resistance is set to the resistance value R of the fixed resistor R1. １ is set to

[0060] On the other hand, if it is determined in step S11 that the write data is not 1 (step S11: No), in step S13, the load resistor is set to the fixed resistor R2, that is, the resistance value of the load resistor is set to the resistance value R of the fixed resistor R2. ２ is set to

[0061] In step S14, the set resistance value R１ or resistance value R ２ The program is executed using the above-mentioned method. The program is a write operation that reverses the resistance state of the magnetoresistive element 11, and data is written to the magnetoresistive element 11 in question.

[0062] This completes the write process. The write process refers to the entire process involved in recording data, including, for example, setting and programming the load resistor.

[0063] In the above program, the write circuit 24 applies a predetermined voltage V to the magnetoresistive element 11 via the fixed resistor R1 or R2 of the load resistor circuit 241. As a result, the resistance value R of the magnetoresistive element 11 becomes a high resistance value R Ｈ or low resistance value R Ｌ to be turned into

[0064] <1-5. Example of Timing Chart of Write Process> An example of a timing chart of the write process according to the first embodiment will be described with reference to Fig. 5 and Fig. 6. Fig. 5 is a timing chart of the write process to a high resistance according to the first embodiment. Fig. 6 is a timing chart of the write process to a low resistance according to the first embodiment.

[0065] In step S12 or step S13 shown in FIG. 4, the control circuit 22 sends the setting of the fixed resistor R1 or R2 to the load resistance circuit 241, and also sends the address to be programmed to the word line address decoder 28 and the bit line address decoder 26.

[0066] Specifically, as shown in FIG. 5, when the resistance setting signal is OFF, the control circuit 22 sends the setting of the fixed resistor R1 to the load resistance circuit 241 (Set R １ The load resistance circuit 241 switches the switch SW1 in accordance with the setting sent from the control circuit 22, and sets the load resistance to a fixed resistance R1.

[0067] The control circuit 22 also sends a programming target address (WL address: ADRS) to the word line address decoder 28 and sends a programming target address (BL address: ADRS) to the bit line address decoder 26 .

[0068] The word line address decoder 28 decodes the address input from the control circuit 22 and turns on the corresponding word line WL (WL control). This turning on connects the corresponding word line WL to the voltage generating circuit 23.

[0069] The bit line address decoder 26 decodes the address input from the control circuit 22 and turns on the corresponding bit line BL (BL control). This turning on connects the corresponding bit line BL to the load resistance circuit 241.

[0070] When both the word line WL and the bit line BL are turned on, a voltage V is applied only to the memory cell 10 at the corresponding address and the fixed resistor R1. This voltage V is a pulse voltage.

[0071] As shown in FIG. 6, when the resistance setting signal is on, the control circuit 22 sends the setting of the fixed resistor R2 to the load resistance circuit 241 (Set R ２ The load resistance circuit 241 switches the switch SW1 in accordance with the setting sent from the control circuit 22, and sets the load resistance to a fixed resistance R2.

[0072] 5, but the load resistance is set to the fixed resistance R2. Therefore, when both the word line WL and the bit line BL are turned on, the voltage V is applied only to the memory cell 10 at the corresponding address and the fixed resistance R2.

[0073] Here, it is desirable that the pulse width of the voltage V is, for example, 0.1 ns or more and 20 ns or less. If the pulse width is 0.1 ns or more, precession occurs reliably, and if the pulse width is 20 ns or less, the precession settles (stabilizes), but if the pulse width exceeds 20 ns, the magnetization is completely oriented in the direction of the external magnetic field, and the precession ends.

[0074] The voltage (e.g., magnitude, waveform, etc.) is the same for writing to a high resistance and writing to a low resistance, but may be different for writing to a high resistance and writing to a low resistance. The voltage is a pulse voltage, but is not limited to this.

[0075] <1-6. Example of Voltage Dependence of Perpendicular Magnetic Anisotropy of Magnetoresistive Element> An example of the voltage dependence of the perpendicular magnetic anisotropy of the magnetoresistive element 11 according to the first embodiment will be described with reference to FIG. 7. FIG. 7 is a graph showing the voltage dependence of the perpendicular magnetic anisotropy (constant) of the magnetoresistive element 11 according to the first embodiment. The horizontal axis of the graph represents voltage V. The vertical axis of the graph represents the perpendicular magnetic anisotropy of the recording layer 113 of the magnetoresistive element 11.

[0076] As shown in FIG. ｃ The perpendicular magnetic anisotropy becomes almost zero near the voltage V ｃ A smaller voltage V Ｌ At this voltage, perpendicular magnetic anisotropy remains, and ｃ Larger voltage V Ｈ In the region where the perpendicular magnetic anisotropy is negative, the recording layer 113 has in-plane magnetic anisotropy. The larger the perpendicular magnetic anisotropy, the easier it is for the recording layer 113 to be magnetized in the perpendicular direction. More specifically, when the perpendicular magnetic anisotropy is positive, the recording layer 113 is easily magnetized in the perpendicular direction (Z-axis direction). When the perpendicular magnetic anisotropy is negative, the recording layer 113 is easily magnetized in the horizontal direction (XY plane direction).

[0077] Here, "perpendicular" refers to the Z-axis direction perpendicular to the XY plane to which the external magnetic field is applied, and "in-plane" refers to the XY plane. When there is in-plane magnetic anisotropy, the magnetization vector rotates in the XY plane, but does not rotate in the Z-axis direction, and therefore does not reverse.

[0078] <1-7. Example of voltage division by load resistance> An example of voltage division by load resistance according to the first embodiment will be described with reference to Fig. 8. Fig. 8 is a diagram for explaining voltage division when a voltage V is applied to the magnetoresistive element 11 via a load resistance (fixed resistance R1 or fixed resistance R2) according to the first embodiment.

[0079] 8A shows a write operation to a high resistance, which changes a low resistance state to a high resistance state, and a write operation to maintain the high resistance state. FIG. 8B shows a write operation to a low resistance, which changes a high resistance state to a low resistance state, and a write operation to maintain the low resistance state.

[0080] As shown in FIG. 8A, in a system (circuit) in which a fixed resistor R1 and a magnetoresistive element 11 are connected in series, a voltage V ｃ In the same system, if the magnetoresistive element 11 is in a high resistance state, the voltage divided into the fixed resistor R1 is small, and the voltage of the magnetoresistive element 11 is V ｃ Bigger V Ｈ This becomes:

[0081] In detail, when a voltage V is applied to the magnetoresistive element 11 in the low resistance state and the fixed resistor R1, the voltage of the magnetoresistive element 11 is V ｃ Therefore, the perpendicular magnetic anisotropy becomes almost 0, and reversal occurs. On the other hand, when a voltage V is applied to the magnetoresistive element 11 in the high resistance state and the fixed resistor R1, the voltage of the magnetoresistive element 11 becomes the voltage V Ｈ Therefore, the perpendicular magnetic anisotropy becomes smaller than 0, and reversal does not occur (is maintained).

[0082] As shown in FIG. 8B, in a system in which the fixed resistor R2 and the magnetoresistive element 11 are connected in series, a voltage V ｃ In the same system, if the magnetoresistive element 11 is in a low resistance state, the voltage divided into the fixed resistor R2 is large, and the voltage of the magnetoresistive element 11 is V ｃ Smaller V Ｌ This becomes:

[0083] In detail, when a voltage V is applied to the magnetoresistive element 11 in the high resistance state and the fixed resistor R2, the voltage of the magnetoresistive element 11 is Vｃ Therefore, the perpendicular magnetic anisotropy becomes almost 0, and reversal occurs. On the other hand, when a voltage V is applied to the magnetoresistive element 11 in the low resistance state and the fixed resistor R2, the voltage of the magnetoresistive element 11 becomes the voltage V Ｌ Therefore, the perpendicular magnetic anisotropy becomes larger than 0, and reversal does not occur (is maintained).

[0084] In this way, the setting of the load resistance circuit 241 differs depending on whether the resistance state of the magnetoresistive element 11 is programmed from a high resistance state to a low resistance state or from a low resistance state to a high resistance state. For example, the load resistance circuit 241 uses a fixed resistor R1 when programming the resistance state of the magnetoresistive element 11 from a low resistance state to a high resistance state, and uses a fixed resistor R2 when programming the resistance state of the magnetoresistive element 11 from a high resistance state to a low resistance state.

[0085] 9 and 10 , an example of the behavior of the magnetization vector due to voltage application via the load resistance, i.e., the fixed resistance R1 or the fixed resistance R2, according to the first embodiment will be described. Fig. 9 is a diagram showing the behavior of the magnetization vector due to voltage application via the fixed resistance R1 according to the first embodiment. Fig. 10 is a diagram showing the behavior of the magnetization vector due to voltage application via another fixed resistance R2 according to the first embodiment.

[0086] In the examples of FIGS. 9 and 10, the magnetization vector (m ｘ , m ｙ , m ｚ ) The magnetization vector is positive in the z-axis direction (m ｚ >0), it indicates a low resistance state, and the magnetization vector is negative in the z-axis direction (m ｚ <0) indicates a high resistance state. １ (for example, 0.5 MΩ) is the resistance value R of the fixed resistor R2 ２ (for example, 2.0 MΩ).

[0087] Graph (a1) (middle graph) and graph (a2) (lower graph) in FIG. 9 show the magnetization vector (mｘ , m ｙ , m ｚ Graph (b1) (middle graph) and graph (b2) (lower graph) in FIG. 10 show the behavior of the magnetization vector (m ｘ , m ｙ , m ｚ ) behavior.

[0088] In the graph (a1) of FIG. 9, the low resistance state (m ｚ When a voltage V is applied to the magnetoresistive element 11 in a low resistance state (m ｚ >0) to a high resistance state (m ｚ <0).

[0089] In the graph (a2) in FIG. 9, the high resistance state (m ｚ When a voltage V is applied to the magnetoresistive element 11 in a high resistance state (m<0) and the fixed resistor R1, the magnetoresistive element 11 is in a high resistance state (m ｚ <0, and remains in the high resistance state (m ｚ <0).

[0090] In the graph (b1) of FIG. 10, the high resistance state (m ｚ When a voltage V is applied to the magnetoresistive element 11 in a high resistance state (m<0) and the fixed resistor R2, the magnetoresistive element 11 enters a high resistance state (m ｚ <0 to the low resistance state (m ｚ >0).

[0091] In the graph (b2) in FIG. 10, the low resistance state (m ｚ When a voltage V is applied to the magnetoresistive element 11 in a low resistance state (m ｚ >0), and the low resistance state (m ｚ >0).

[0092] In this way, to put the magnetoresistive element 11 into a high resistance state, it is sufficient to set a fixed resistance R1 and apply a voltage V to the magnetoresistive element 11 via the fixed resistance R1, and to put the magnetoresistive element 11 into a low resistance state, it is sufficient to set a fixed resistance R2 and apply a voltage V to the magnetoresistive element 11 via the fixed resistance R2. This eliminates the need to perform an initial read to determine whether or not to execute a program. Therefore, since the initial read is no longer necessary, the write time can be shortened. Furthermore, since the power consumed in the initial read is eliminated, low power consumption can be achieved. Furthermore, even if the initial read is not necessary, erroneous writing does not occur, and therefore write accuracy can be improved.

[0093] As a write method that does not require an initial read, it is also possible to switch the gate voltage of the select transistor serving as the select element 12 between writing the magnetoresistive element 11 from a low resistance state to a high resistance state and writing from a high resistance state to a low resistance state. Changing the gate voltage has the effect of changing the on-resistance of the select transistor, allowing the voltage applied to the magnetoresistive element 11 to be controlled depending on whether the magnetoresistive element 11 has a high resistance or a low resistance. However, in this case, controlling the gate voltage of the select transistor may make it difficult to control the on-resistance of the select transistor or may result in an inability to obtain the desired resistance value, potentially preventing the desired operation from being achieved. This reduces the accuracy of data writing. Using the load resistance circuit 241, as described above, makes it easier and more accurate to control the load resistance of the magnetoresistive element 11, thereby enabling the desired operation to be achieved. Therefore, data write accuracy can be improved compared to controlling the gate voltage of the select transistor.

[0094] <1-9. Example of Write Voltage Waveform> An example of a write voltage waveform according to the first embodiment will be described with reference to FIGS.

[0095] In the above-described embodiment, the voltage V applied to the system (circuit) in which the load resistance circuit 241 and the magnetoresistive element 11 are connected in series is a so-called rectangular pulse that is constant over time. In the example of FIGS. 9 and 10 , a voltage of 3.0 V is applied from 1 ns (nsec) to 2 ns (nsec), but this voltage V does not change over time. Looking at the behavior of the magnetization vectors shown at the bottom of FIGS. 9 and 10 , it can be seen that the orientation of the magnetization vector changes over time after voltage application. Because the resistance value of the magnetoresistive element 11 changes depending on the orientation of the magnetization vector, the division of the voltage V by the load resistance circuit 241 (fixed resistor R1 or fixed resistor R2) and the magnetoresistive element 11 changes over time after voltage application.

[0096] 11 is a diagram showing a schematic diagram of a time change in the divided voltage according to the first embodiment. As shown in FIG. 11, in H write (write to high resistance), when the initial state is a low resistance state, a voltage V ｃ The voltage division between the magnetoresistive element 11 and the fixed resistor R1 is adjusted so that the voltage V ＷＰ When the magnetoresistive element 11 is written to a high resistance state by writing by applying a write voltage (write voltage), the magnetoresistive element 11 changes to a high resistance state, and the voltage division between the magnetoresistive element 11 and the fixed resistor R1 becomes different from that before writing. Specifically, since the magnetoresistive element 11 has a higher resistance than before writing, a larger voltage division is applied to the magnetoresistive element 11, and the voltage V ｃ An excess voltage greater than .gtoreq..times ...

[0097] On the other hand, in the L write (write to low resistance), when the initial state is a high resistance state, a voltage V ｃ However, when the magnetoresistive element 11 is written to a low resistance state by writing, the magnetoresistive element 11 changes to a low resistance state, and the voltage division between the magnetoresistive element 11 and the fixed resistor R2 becomes different from that before writing. Specifically, since the magnetoresistive element 11 has a lower resistance than before writing, a smaller voltage division is applied to the magnetoresistive element 11, and the voltage V ｃA deficit voltage less than .gtoreq.

[0098] Ideally, even when the magnetoresistive element 11 is changing state, the voltage V ｃ It is desirable to apply a voltage Vcc to the magnetoresistive element 11. However, since the resistance of the magnetoresistive element 11 changes during the write operation, the voltage division between the magnetoresistive element 11 and the fixed resistor (fixed resistor R1 or fixed resistor R2) also changes. The optimal value of the load resistance due to the fixed resistor is not obvious. Therefore, in order to obtain the optimal load resistance ratio for the magnetoresistive element 11, a magnetization motion simulation was performed by changing the load resistance ratio. As a result, the magnetization motion simulation results were obtained. Note that the resistance change of the magnetoresistive element 11 during the write operation is not limited to the change shown in FIG. 11.

[0099] 12 is a diagram for explaining the magnetization motion simulation result of the magnetoresistive element 11 whose initial state is a low resistance state (initial state L) according to the first embodiment. FIG. 13 is a diagram for explaining the magnetization motion simulation result of the magnetoresistive element 11 whose initial state is a high resistance state (initial state H) according to the first embodiment.

[0100] In the examples of FIGS. 12 and 13, the V ＷＰ is the voltage applied to the entire circuit in which the load resistance circuit 241 and the magnetoresistive element 11 are connected in series. In the example of FIG. 12, the load resistance ratio on the vertical axis on the left side of the lower graph is the load resistance ratio to the resistance value of the magnetoresistive element 11 in the low resistance state. In the example of FIG. 13, the load resistance ratio on the vertical axis on the left side of the lower graph is the load resistance ratio to the resistance value of the magnetoresistive element 11 in the high resistance state. Ｚ is the vertical component of magnetization, and the strength is shown by gradation. The horizontal axis of each graph is V ＷＰ is the time during which the voltage is applied.

[0101] As shown in FIG. 12 , when writing to a high resistance state to change a low resistance state to a high resistance state, the appropriate load resistance ratio is estimated to be within a range of 0.74 to 1.08, and for example, the optimal load resistance ratio is estimated to be approximately 0.91 and the pulse width is estimated to be approximately 1.3 ns. On the other hand, as shown in FIG. 13 , when writing to a low resistance state to change a high resistance state to a low resistance state, the appropriate load resistance ratio is estimated to be within a range of 1.14 to 1.68, and for example, the optimal load resistance ratio is estimated to be approximately 1.56 and the pulse width is estimated to be approximately 1.5 ns or more. However, these numerical values ​​are merely examples and may be changed depending on various conditions. Based on such an appropriate or optimal load resistance ratio, the resistance value of the load resistor of the load resistor circuit 241 (for example, the resistance value R of the fixed resistor R1) is calculated. １ or the resistance value R of the fixed resistor R2 ２ ) should be determined.

[0102] (Example of high resistance writing with rectangular pulse) FIG. 14 is a diagram for explaining high resistance writing (writing to high resistance) by applying a rectangular pulse according to the first embodiment. In the example of FIG. 14, the voltage is constant. Also, the resistance value R of the fixed resistor R1 is １ is 0.91 times the resistance value of the magnetoresistive element 11 in the low resistance state (r=0.91). Note that writing is normally performed with a pulse voltage, but for the sake of explanation, the simulation was performed with a voltage that continues for a certain period of time. During actual writing, it is assumed that the voltage will be turned off at the desired timing.

[0103] 14 shows an upper graph, a middle graph, and a lower graph. The vertical axis of the upper graph is V ＷＰ is the voltage applied to the entire circuit in which the load resistance circuit 241 and the magnetoresistive element 11 are connected in series. ＭＴＪ is the voltage applied to the magnetoresistive element 11. Ｚ is the perpendicular component of magnetization. The horizontal axis of each graph represents time. These are the same in other figures (e.g., Figures 15, 16, 18, 19, 27, and 28).

[0104] As shown in FIG. 14, when H write (high resistance write) is performed, the appropriate voltage V ＭＴＪ is applied (see the middle graph), the magnetoresistive element 11 in the low resistance state starts magnetization motion and approaches the ideal high resistance state in about 1.3 ns (see the bottom graph). After that, the magnetoresistive element 11 returns to its original low resistance state by precession. To complete writing to the high resistance state, the voltage application should be stopped when the pulse width becomes 1.3 ns. At this time, the magnetoresistive element 11, which is initially in the high resistance state (H), receives the excessive voltage V ＭＴＪ Since the pulse width is 1.3 ns, magnetization motion does not start, and the high resistance state remains even when the pulse width becomes 1.3 ns (see the lower graph).

[0105] 14, whether the initial state is a high-resistance state or a low-resistance state, non-toggle writing can be achieved, in which the state becomes high-resistance after a pulse is applied. When the initial state is a low-resistance state, the state oscillates due to precession, but the z component of the magnetization when it is closest to the ideal high-resistance state is −0.57.

[0106] (Example of high resistance writing with non-rectangular pulse) Fig. 15 is a diagram for explaining high resistance writing by applying a non-rectangular pulse according to the first embodiment. In the example of Fig. 15, unlike Fig. 14, the voltage is not constant, but is a non-rectangular voltage that changes over time. Specifically, the voltage applied at the start of writing is 1.5 V (first amplitude value), and after 2.0 ns it becomes 1.26 V (second amplitude value), and this voltage is maintained until the end of the waveform. In addition, the resistance value R of the fixed resistor R1 １ is 0.76 times the resistance value of the magnetoresistive element 11 in the low resistance state (r=0.76).

[0107] As shown in FIG. 15, when H write (high resistance write) is performed, similarly to FIG. 14, the appropriate voltage V ＭＴＪis applied (see the middle graph), the magnetoresistive element 11 in the low resistance state starts magnetization motion and approaches the ideal high resistance state in about 1.6 ns (see the bottom graph). After that, the magnetoresistive element 11 returns to its original low resistance state by precession. To complete writing to the high resistance state, the voltage application should be stopped when the pulse width reaches 1.6 ns. At this time, the magnetoresistive element 11, which is initially in the high resistance state (H), receives the excessive voltage V ＭＴＪ Since the pulse width is 1.6 ns, the magnetization motion does not start, and the high resistance state remains even when the pulse width becomes 1.6 ns (see the graph at the bottom).

[0108] 15, whether the initial state is a high resistance state or a low resistance state, non-toggle writing can be realized, in which the state becomes a high resistance state after a pulse is applied. When the initial state is a low resistance state, the state oscillates due to precession, and the z component of the magnetization when it is closest to the ideal high resistance state is −0.77.

[0109] This is closer to the ideal high-resistance state than the rectangular pulse shown in Figure 14. When writing to VC-MRAM, it is better to get as close to the high-resistance state as possible, taking into account the effects of thermal disturbance. For this reason, writing with the non-rectangular pulse shown in Figure 15 can be said to be more desirable than writing with the rectangular pulse shown in Figure 14.

[0110] In FIG. 14, in which a rectangular pulse is applied, the voltage V applied to the magnetoresistive element 11 in the low resistance state (L) is ＭＴＪ , the resistance increases with magnetization movement, exceeding 0.9 V. The desirable write voltage at the start of voltage application was about 0.8 V, but the resistance change in the magnetoresistive element 11 caused a change in the voltage division between the magnetoresistive element 11 and the fixed resistor (fixed resistor R1 or R2), resulting in excessive voltage application. As a result, the precession does not take an ideal shape, and the z component of the magnetization remains at -0.57 when it approaches the ideal high-resistance state.

[0111] In contrast, in FIG. 15 where a non-rectangular pulse is applied, the voltage V applied to the magnetoresistive element 11 in the low resistance state (L) is ＭＴＪ As can be seen, the decrease in the write voltage itself offsets the effect of the increased resistance of the magnetoresistive element 11, and the voltage applied to the magnetoresistive element 11 is kept below 0.9 V. As a result, the precession approaches an ideal shape, and the z component of the magnetization reaches −0.77 when it is closest to the ideal high resistance state.

[0112] As mentioned above, the voltage V ＷＰ By using a non-rectangular pulse (write voltage), the magnetization motion can be made closer to ideal precession, resulting in highly reliable writing.

[0113] Note that a non-rectangular pulse or a rectangular pulse may be used depending on whether high resistance writing or low resistance writing is performed. For example, a non-rectangular pulse may be used for high resistance writing, and a rectangular pulse may be used for low resistance writing. That is, the waveforms of the non-rectangular pulse and the rectangular pulse may be different or the same in high resistance writing and low resistance writing. Furthermore, the magnitudes of the voltages of the non-rectangular pulse and the rectangular pulse may be different or the same in high resistance writing and low resistance writing.

[0114] (Another Example of High Resistance Write) FIG. 16 is a diagram for explaining another example of high resistance write according to the first embodiment. In the example of FIG. 16, a non-rectangular pulse similar to that of FIG. 15 is used, but its shape is different. Specifically, a voltage of 1.5 V (first amplitude value) is applied at the start of write, and after 1.4 ns, it becomes 1.00 V (second amplitude value), and this voltage is maintained until the end of the waveform. In addition, the resistance value R of the fixed resistor R1 １ is 0.74 times the resistance value of the magnetoresistive element 11 in the low resistance state (r=0.74).

[0115] In the write operation shown in FIG. 16, non-toggle write is possible as in FIGS. 14 and 15, but the voltage V ＷＰBy adjusting the shape of the write voltage, it is possible to realize magnetization motion without precession. This makes it possible to write to the high-resistance state without stopping the voltage application at the desired timing, which is called long-pulse writing.

[0116] The voltage waveform is not limited to a waveform that maintains a constant voltage as shown in Fig. 16. For example, it is possible to select a voltage waveform of various shapes as long as it is possible to control the magnetization movement.

[0117] 17 is a diagram illustrating various voltage waveform shapes according to the first embodiment. As shown in FIG. 17 , any voltage waveform, as indicated by the dotted line, is possible as long as it does not exceed a predetermined voltage Va after a predetermined time t1. Examples of the arbitrary voltage waveform include a waveform A1 in which the voltage becomes zero at the predetermined time t1, a linear waveform A2 in which the voltage gradually decreases after the predetermined time t1, a curved waveform A3 in which the voltage decreases in a step-like manner after the predetermined time t1, and a waveform A4 in which the voltage remains constant after the predetermined time t1.

[0118] The slope of the linear waveform A2 and the shape of the curved waveform A3 are not limited to the waveforms shown in Fig. 17. Furthermore, the slope of the linear waveform A2 before the predetermined time t1 may be different from the slope after the predetermined time t1. Furthermore, in the waveform A4, the constant voltage is the predetermined voltage Va, but the constant voltage is not limited to the predetermined voltage Va as long as it does not exceed the predetermined voltage Va.

[0119] (Another Example of High Resistance Writing) FIG. 18 is a diagram for explaining another example of high resistance writing according to the first embodiment. Although an example of high resistance writing has been explained in FIGS. 15 and 16, low resistance writing can also be performed using a non-rectangular pulse. In the example of FIG. 18, a non-rectangular pulse similar to that in FIGS. 15 and 16 is used, but its shape is different. Specifically, a voltage of 1.5 V (first amplitude value) is applied at the start of writing, and after 2.2 ns, it becomes 1.00 V (second amplitude value), and this voltage is maintained until the end of the waveform. In addition, the resistance value R of the fixed resistor R1 １is 0.80 times the resistance value of the magnetoresistive element 11 in the low resistance state, and the resistance value R ２ is 0.80 times the resistance value of the magnetoresistive element 11 in the high resistance state (r=0.80).

[0120] 18, non-rectangular pulses with the same waveform are used for both high resistance writing and low resistance writing. As a result, the pulse waveform during writing and the resistance values ​​R of the fixed resistors R1 and R2 are determined depending on the write data. １ , R ２ However, since writing is performed under the same conditions regardless of the initial state, the writing method is toggle-type writing, and in order to write a desired state, an initial read before writing is required.

[0121] (Another Example of High Resistance Write) FIG. 19 is a diagram for explaining another example of high resistance write according to the first embodiment. In the example of FIG. 19, write is performed in two steps. In the two steps, pulses with different waveforms are used for low resistance write and high resistance write, and a rectangular pulse is used for low resistance write in step 1, and a non-rectangular pulse is used for high resistance write in step 2. The resistance value R of the fixed resistor R1 is １ is 0.80 times the resistance value of the magnetoresistive element 11 in the low resistance state (r=0.80). ２ is 1.56 times the resistance value of the magnetoresistive element 11 in the high resistance state (r=1.56).

[0122] As shown in Figure 19, in step 1, a low resistance state is written by applying a rectangular pulse. At this time, if the initial state is a low resistance state, the resistance state of the magnetoresistive element 11 remains in the low resistance state. In other words, by writing in step 1, the resistance state of the magnetoresistive element 11 becomes a low resistance state regardless of the initial state. In the case of low resistance writing, the write operation can be completed in step 1. On the other hand, in the case of high resistance writing, writing is performed in step 2 with a non-rectangular pulse as described above. As a result, the magnetoresistive element 11 in the low resistance state becomes a high resistance state.

[0123] In this way, in both the low resistance writing and the high resistance writing, a writing operation is performed using a rectangular pulse in step 1, and then, in the case of high resistance writing, a writing operation is performed using a non-rectangular pulse in step 2.

[0124] 1-10. Write Pulse Generation Circuit The write pulse generation circuits 200, 210 according to the first embodiment will be described with reference to FIGS. 20 to 23. Each write pulse generation circuit 200, 210 generates a write pulse (pulse voltage). These write pulse generation circuits 200, 210 are included in the write circuit 24, for example.

[0125] 20 is a diagram showing an example of the configuration of a write pulse generating circuit 200 according to the first embodiment. As shown in Fig. 20, the write pulse generating circuit 200 is composed of a CR circuit 202, a transfer gate 203, and a negative feedback amplifier circuit using an operational amplifier 204. The transfer gate 203 controls the conduction / cutoff of an output 206 of the CR circuit 202 and a non-inverting input 207 of the operational amplifier 204.

[0126] 21 and 22 are diagrams for explaining an example of the operation of the write pulse generating circuit 200 according to the first embodiment.

[0127] 21 , a rectangular rising voltage is input to input terminal 201 of write pulse generating circuit 200. The rectangular signal input to input terminal 201 is converted by CR circuit 202 into a waveform with a smooth rising time. Transfer gate 203 conducts output 206 of CR circuit 202 to non-inverting input 207 of operational amplifier 204 only between time 2031 and time 2032. A signal corresponding to the difference between the signal input to the non-inverting input terminal and the negative feedback signal input to the inverting input terminal is output from output terminal 205 as a write pulse from the negative feedback amplifier circuit.

[0128] 22, a rectangular falling voltage is input to input terminal 201 of write pulse generating circuit 200. The rectangular signal input to input terminal 201 is converted by CR circuit 202 into a waveform with a smooth falling time. Transfer gate 203 conducts output 206 of CR circuit 202 to non-inverting input 207 of operational amplifier 204 only between time 2031 and time 2032. A signal corresponding to the difference between the signal input to the non-inverting input terminal and the negative feedback signal input to the inverting input terminal is output from output terminal 205 as a write pulse from the negative feedback amplifier circuit.

[0129] Fig. 23 is a diagram showing an example of the configuration of another write pulse generation circuit 210 according to the first embodiment. As shown in Fig. 23, the write pulse generation circuit 210 has a waveform memory 211 and a D / A conversion circuit 212. This write pulse generation circuit 210 generates a write pulse using the waveform memory 211 and the D / A conversion circuit 212.

[0130] The waveform data of the write pulse is stored in the waveform memory 211. The waveform data of the write pulse is composed of time-series data of a plurality of words, each of which has N bits that can select an output level from 2N levels. The waveform memory 211 is provided with N ports for reading, and these N ports are respectively connected to N input terminals of the D / A conversion circuit 212.

[0131] The D / A conversion circuit 212 receives waveform data of the write pulse from the waveform memory 211 in units of N-bit data (one word), converts it into an analog signal, and outputs it as a write pulse. This D / A conversion circuit 212 can be configured, for example, with a ladder resistor circuit or the like.

[0132] By using these write pulse generating circuits 200, 210, the waveform of the write pulse can be obtained with a high degree of freedom, and the write pulses of the above-mentioned embodiments (for example, rectangular pulses, non-rectangular pulses, etc.) can be obtained easily and with a high degree of freedom. In the example of Figure 23, the number of bits N in one word is set to "3" so that the output level can be determined from 23 levels, but this number is not particularly limited.

[0133] 2. Second Embodiment In the second embodiment, the non-rectangular pulse (non-rectangular pulse voltage) according to the first embodiment is used in a self-adaptive write method (self-adaptive write operation).

[0134] 2-1. Configuration Example of Write Unit> A first configuration example of the write unit 50 according to the second embodiment will be described with reference to Fig. 24 to Fig. 26. The write unit 50 is included in the write circuit 24 according to the first embodiment (see Fig. 1).

[0135] FIG. 24 is a schematic diagram showing a write unit 50 according to the second embodiment. As shown in FIG. 24, the write unit 50 includes a write voltage generating unit 51, a voltage applying unit 52, a read unit 53, a comparing unit 54, a feedback unit 55, and a write selecting unit 56. The write unit 50 is provided, for example, for each bit line BL or for a predetermined number of bit lines BL, and is connected to each bit line BL. In other words, one write unit 50 may be provided for each bit line BL, or for a predetermined number of bit lines BL, and may be shared by the predetermined number of bit lines BL. Note that the configuration of each unit of the write unit 50 shown in FIG. 24 is merely exemplary, and other configurations may also be used.

[0136] The write voltage generating unit 51 has a state 0 write voltage line 101 (WR0), a state 1 write voltage line 102 (WR1), a write data line 103 (WD), and a write signal line 106 (WE2) as input terminals. The state 0 write voltage line 101, the state 1 write voltage line 102, and the write data line 103 are connected to the control circuit 22 (see FIG. 1). The write signal line 106 is connected to the write selection unit 56.

[0137] Under the control of the control circuit 22, a voltage for writing state 0 (e.g., a low resistance state) is applied to the state 0 write voltage line 101, and a voltage for writing state 1 (e.g., a high resistance state) is applied to the state 1 write voltage line 102. These voltages (voltage values) will be referred to as VWR0 and VWR1. The voltages VWR0 and VWR1 have different values. Furthermore, under the control of the control circuit 22, an off voltage is applied to the write data line 103 when writing state 0, and an on voltage is applied to the write data line 103 when writing state 1.

[0138] The off-voltage is a voltage that, when applied to the gate of an n-channel MOS transistor, causes the drain terminal and source terminal of the n-channel MOS transistor to become non-conductive, and can be, for example, a ground voltage. The on-voltage is a voltage that, when applied to the gate of an n-channel MOS transistor, causes the drain terminal and source terminal of the n-channel MOS transistor to become conductive, and can be, for example, a power supply voltage. The voltage of the write data line 103 is denoted as VWD.

[0139] The write voltage generating unit 51 outputs either the voltage VWR0 of the state 0 write voltage line 101 or the voltage VWR1 of the state 1 write voltage line 102 to the voltage applying unit 52 in accordance with the voltage VWD. Specifically, the write voltage generating unit 51 outputs the voltage VWR0 when the voltage VWD is an off voltage, and outputs the voltage VWR1 when the voltage VWD is an on voltage. However, when the voltage of the write signal line 106 (a write selection voltage indicating whether or not a write operation is to be performed) is an off voltage (a voltage indicating that writing is not to be performed), the write voltage generating unit 51 outputs an off voltage or an on voltage to the voltage applying unit 52 regardless of the value of the voltage VWD. The voltage of the write signal line 106 will be written as VWE2.

[0140] The voltage application unit 52 outputs a voltage that depends on the voltage output from the write voltage generation unit 51 to the bit line BL. The voltage output from the write voltage generation unit 51 will be referred to as VWR, and the voltage of the bit line BL will be referred to as VBL. The voltage application unit 52 outputs the voltage VBL to the read unit 53. The memory cell 10 is connected to the voltage application unit 52 via the bit line BL. The voltage application unit 52 includes a load resistance circuit 241 (e.g., fixed resistors R1 and R2) according to the first embodiment. Therefore, the voltage VWR0 or VWR1 is applied to the memory cell 10 via the load resistance circuit 241. In other words, the voltage VWR0 or VWR1 is applied to the entire circuit that directly connects the load resistance circuit 241 and the memory cell 10.

[0141] The read unit 53 refers to the voltage VBL output from the voltage application unit 52 and reads the state (e.g., state 0 or state 1) of the magnetoresistive element 11 of the memory cell 10 to be written. The read unit 53 has the write data line 103 as another input terminal. To read the state of the magnetoresistive element 11, the read unit 53 can use the voltage VWD. The read unit 53 outputs the read data, i.e., a read voltage corresponding to the read data, to the comparison unit 54. This voltage will be written as VRD. The voltage VRD is an off voltage when the state of the magnetoresistive element 11 is state 0, and is an on voltage when it is state 1.

[0142] The comparison unit 54 compares the read data (e.g., the read state of the magnetoresistive element 11) with the write data (e.g., the target state of the magnetoresistive element 11) by referring to the voltage VRD output from the read unit 53. The comparison unit 54 has the write data line 103 as another input terminal. To perform the comparison, the comparison unit 54 can use the voltage VWD. The comparison unit 54 outputs a comparison voltage according to the comparison result to the feedback unit 55. This voltage will be referred to as VCMP. The voltage VCMP is an on voltage when the read data and the write data are equal, and an off voltage when they are different. Alternatively, the voltage VCMP may be an off voltage when the read data and the write data are equal, and an on voltage when they are different.

[0143] The read data is data indicating that the magnetoresistive element 11 is in state 0 or state 1, and the write data is data specifying that the magnetoresistive element 11 is in state 0 or state 1. If the read data and the write data are the same, it means that the state of the magnetoresistive element 11 is the same, and if the read data and the write data are different, it means that the state of the magnetoresistive element 11 is different.

[0144] The feedback unit 55 references the voltage VCMP output from the comparison unit 54 to determine whether to continue or abort the write. The feedback unit 55 has a write start signal line 104 (EN) as another input terminal. To determine whether to continue or abort the write, the feedback unit 55 can use the voltage of the write start signal line 104. This voltage will be written as VEN. The voltage VEN is an ON voltage when writing starts and an OFF voltage at other times. The feedback unit 55 references the voltage VCMP and the voltage VEN and outputs a write continue signal to the write selection unit 56. This voltage will be written as VWE. The voltage VWE is an ON voltage when writing continues and an OFF voltage when writing is aborted.

[0145] The write selection unit 56 selects whether to continue or stop writing by referring to the voltage VWE output from the feedback unit 55. The write selection unit 56 has a write selection line 105 (SE) as another input terminal. To select whether to continue or stop writing, the write selection unit 56 can use the voltage of the write selection line 105. This voltage will be written as VSE. The voltage VSE is an ON voltage when writing is performed and an OFF voltage when writing is not performed. When the voltage VSE is an ON voltage, the write selection unit 56 outputs the voltage VWE to the write voltage generation unit 51 as is, and when the voltage VSE is an OFF voltage, it outputs an OFF voltage to the write voltage generation unit 51. As described above, this voltage is VWE2.

[0146] Fig. 25 is a circuit diagram showing an example of the configuration of the writing unit 50 according to the second embodiment. Fig. 25 shows a more detailed circuit diagram of the writing unit 50 shown in Fig. 24. However, Fig. 25 is merely one example of the configuration of the writing unit 50, and the writing unit 50 is not limited to this configuration. Note that, although the operation of the circuit diagram shown in Fig. 25 can be easily understood by comparing it with the explanation of Fig. 24 above, some supplementary explanation will be provided.

[0147] The write voltage generating unit 51 has two multiplexers MUX0 and MUX1. The voltage applying unit 52 has a p-channel MOS transistor P0. The comparing unit 54 has an inverter INV3 and an XOR gate XOR0. The feedback unit 55 has a p-channel MOS transistor P1, two n-channel MOS transistors N0 and N1, and an inverter INV4. The write selecting unit 56 has an AND gate AND0.

[0148] When the voltage VEN of the write start signal line 104 becomes an ON voltage, the p-channel MOS transistor P1 becomes conductive and the n-channel MOS transistor N1 becomes insulating, thereby charging the output voltage VWE of the feedback unit 55 to an ON voltage. Since the voltage VEN is a trigger signal that starts writing, once the voltage VWE is charged to an ON voltage, the voltage VEN is turned OFF. The time duration during which the voltage VEN becomes an ON voltage is preferably, but not limited to, approximately 0.1 ns to 1 ns. Since no write operation occurs when the voltage VSE of the write selection line 105 is an OFF voltage, only the case where the voltage VSE is an ON voltage will be considered here. The voltages VWE and VWE2 become ON voltages, starting the write operation. The voltage signal then propagates sequentially through the write selection unit 56, the write voltage generation unit 51, the voltage application unit 52, the read unit 53, and the comparison unit 54.

[0149] The output voltage VCMP of the comparator 54 is an ON voltage when the read data and the write data are equal, and an OFF voltage when they are different. Alternatively, the output voltage VCMP of the comparator 54 is an OFF voltage when the read data and the write data are equal, and an ON voltage when they are different. In the circuit diagram shown in FIG. 25, the output voltage VCMP of the comparator 54 is an ON voltage when the read data and the write data are equal, and an OFF voltage when they are different. Thus, when the read data and the write data are different, i.e., when writing must continue, the n-channel MOS transistor N0 is insulated. As a result, the output voltage VWE of the feedback unit 55 remains charged to an ON voltage, and writing continues. Conversely, when the read data and the write data are equal, i.e., when writing must be stopped, the n-channel MOS transistor N0 is made conductive. Furthermore, since the voltage VEN is at an OFF voltage as described above, the n-channel MOS transistor N1 is also made conductive. Then, the charge stored in the output terminal of the feedback unit 55 is discharged through the n-channel MOS transistors N0 and N1. As a result, the output voltage VWE of the feedback circuit 55 becomes the off voltage, and writing is stopped.

[0150] As described above, by using the write unit 50 according to the second embodiment, it is possible to realize a self-adaptive write operation in which writing continues when the read data and the write data are different, and writing is stopped when they are the same. For example, since there is no need to control the pulse width of the write voltage, i.e., the write pulse width, it is possible to reduce the write error rate and improve the stability of the write operation. Normally, the optimal write pulse width varies for each magnetoresistive element 11, but since an appropriate write pulse width is automatically set for each magnetoresistive element 11, the write error rate can be reduced.

[0151] 25 can have any configuration as long as it can read out the state of the selected magnetoresistive element 11. Furthermore, a write data line 103 (WD) can be used for reading. That is, the read unit 53 can have a bit line BL and a write data line 103 as input terminals, and a read data line (RD) as an output terminal.

[0152] 26 is a circuit diagram showing an example of the configuration of a readout unit 53 according to the second embodiment. The readout unit 53 shown in Fig. 26 has three inverters INV0, INV1, and INV2 and one multiplexer MUX2. The bit line BL is connected to each input terminal of two inverters INV0 and INV1, which have different threshold voltages.

[0153] The output terminals of the inverters INV0 and INV1 are connected to the input terminals of a multiplexer MUX2, whose output terminal is connected to the input terminal of the inverter INV2, whose output terminal is connected to the read data line (RD).

[0154] The multiplexer MUX2 has as another input terminal the write data line 103. Depending on the voltage of the write data line 103, the multiplexer MUX2 connects one of the output terminals of the two inverters INV0 and INV1 to the input terminal of the inverter INV2.

[0155] <2-2. Example of Write Voltage Waveform> An example of a write voltage waveform according to the second embodiment will be described with reference to FIGS. 27 and 28. FIG.

[0156] (Example of high resistance writing with rectangular pulse) Fig. 27 is a diagram for explaining high resistance writing by applying a rectangular pulse according to the second embodiment. In Fig. 27, the voltage is constant. The resistance value R of the fixed resistor R1 １ is 0.91 times the resistance value of the magnetoresistive element 11 in the low resistance state (r=0.91).

[0157] As shown in FIG. 27, when H write (high resistance write) is performed, the appropriate voltage V ＭＴＪ Since a voltage is applied (see the middle graph), the magnetoresistive element 11 in the low resistance state begins magnetization motion and approaches its ideal high resistance state in about 1.3 ns (see the bottom graph). The magnetoresistive element 11 then returns to its original low resistance state through precession. The write operation is the self-adaptive write operation described above. Therefore, the feedback operation, which continues writing when the read data and the write data are different and stops writing when they become the same, is performed within the allowable time T1. In the example of FIG. 27, the allowable time T1 for the feedback operation is very short, approximately 0.5 ns or less.

[0158] (Example of high resistance writing with non-rectangular pulse) Fig. 28 is a diagram for explaining high resistance writing by applying a non-rectangular pulse according to the second embodiment. In Fig. 28, unlike Fig. 27, the voltage is not constant, but is a non-rectangular voltage that changes over time. Specifically, the voltage applied at the start of writing is 1.5 V (first amplitude value), and after 2.2 ns it becomes 1.00 V (second amplitude value), and this voltage is maintained until the end of the waveform. Also, the resistance value R of the fixed resistor R1１ is 0.80 times the resistance value of the magnetoresistive element 11 in the low resistance state (r=0.80).

[0159] As shown in FIG. 28, when high resistance writing (H writing) is performed, similarly to FIG. 27, the appropriate voltage V ＭＴＪ Since a voltage is applied (see the middle graph), the magnetoresistive element 11 in the low resistance state begins magnetization motion, reaches the ideal high resistance state in about 1.8 ns (see the bottom graph), and remains in the high resistance state thereafter. The write is the self-adaptive write operation described above. Therefore, the feedback operation described above is performed within the allowable time T2. In the example of FIG. 28, the allowable time T2 for the feedback operation is longer than that in FIG. 27, at approximately 3.2 ns or more, and there is no time restriction.

[0160] In this way, by using a non-rectangular pulse for high resistance writing, the allowable time for feedback operation can be extended, which can reduce the write error rate and improve the stability of the write operation.

[0161] 3. Functions and Effects of Each Embodiment As described above, the memory device 100 includes the magnetoresistive element 11, the resistance state of which can be changed between a first state (e.g., a high resistance state) and a second state (e.g., a low resistance state) by application of a voltage, the selection element 12 connected to the magnetoresistive element 11, the load resistance circuit 241, the resistance value of which can be changed, and the write circuit 24 that applies a voltage to the magnetoresistive element 11 via the load resistance circuit 241. The write circuit 24 outputs a first voltage that changes the resistance state to the first state and a second voltage that changes the resistance state to the second state (see, for example, FIGS. 1 to 19 ). This makes it possible to apply an appropriate voltage to the magnetoresistive element 11 depending on whether the resistance state of the magnetoresistive element 11 is to be the first state or the second state, regardless of the resistance state of the magnetoresistive element 11 before writing, i.e., without performing an initial read, thereby improving data writing accuracy.

[0162] Furthermore, one or both of the first voltage and the second voltage may be a pulse voltage (see FIG. 5, FIG. 6, etc.), which allows an appropriate voltage to be applied to the magnetoresistive element 11.

[0163] Furthermore, the waveforms of the first voltage and the second voltage may be different from each other (see FIGS. 15 and 19, etc.), thereby making it possible to reliably apply an appropriate voltage to the magnetoresistive element 11.

[0164] Furthermore, the first voltage and the second voltage may have different magnitudes (see FIGS. 15 and 19), which allows an appropriate voltage to be applied to the magnetoresistive element 11 with reliability.

[0165] The pulse waveform of the pulse voltage may be non-rectangular (see, for example, FIGS. 15 to 19), which allows an appropriate voltage to be applied to the magnetoresistive element 11 with reliability.

[0166] Alternatively, both the first voltage and the second voltage may be pulse voltages, with the first voltage having a non-rectangular pulse waveform and the second voltage having a rectangular pulse waveform (see, for example, FIG. 19 ), thereby ensuring that an appropriate voltage is applied to the magnetoresistive element 11.

[0167] The non-rectangular pulse waveform may also be a waveform in which the amplitude gradually decreases from a first amplitude value greater than 0 to a second amplitude value (see, for example, FIGS. 15 to 17 ). This ensures that an appropriate voltage is applied to the magnetoresistive element 11.

[0168] The non-rectangular pulse waveform may have an amplitude that gradually decreases from a first amplitude value to a second amplitude value and maintains the second amplitude value until the end of the waveform (see, for example, FIGS. 15 to 17 ). This ensures that an appropriate voltage is applied to the magnetoresistive element 11.

[0169] The non-rectangular pulse waveform may also have a shape in which the amplitude gradually decreases from a first amplitude value to a second amplitude value and then decreases from the second amplitude value in a linear, curved, or step-like manner (see, for example, FIG. 17 ), thereby ensuring that an appropriate voltage is applied to the magnetoresistive element 11.

[0170] Furthermore, the write circuit 24 may divide the first voltage or the second voltage and apply it to the load resistance circuit 241 and the magnetoresistive element 11 (see, for example, FIGS. 3 to 6 ). This can reliably improve the accuracy of writing data.

[0171] Furthermore, the load resistance circuit 241 may be connected to the side of the magnetoresistive element 11 opposite to the side of the selection element 12 (see FIGS. 2 and 3, etc.). This can reliably improve the accuracy of writing data.

[0172] The load resistance circuit 241 may also include a plurality of fixed resistors (e.g., fixed resistor R1, fixed resistor R2) each having a different fixed resistance value, and a switch SW1 for switching between a plurality of wiring paths passing through each of the plurality of fixed resistors (see FIG. 3). This allows the load resistance circuit 241 to be realized with a simple configuration.

[0173] The plurality of fixed resistors may include a first fixed resistor (e.g., fixed resistor R1) and a second fixed resistor (e.g., fixed resistor R2), and the write circuit 24 may apply a first voltage to the magnetoresistive element 11 via the first fixed resistor when changing the resistance state to the first state, and may apply a second voltage to the magnetoresistive element 11 via the second fixed resistor when changing the resistance state to the second state (see, for example, FIGS. 3 to 6 ). This reliably improves write accuracy.

[0174] The resistance value R of the first fixed resistor １ is the resistance value R of the second fixed resistor ２ (See FIGS. 9 and 10.) This can reliably improve the writing accuracy.

[0175] The resistance value R of the first fixed resistor １ may be set for the resistance value of the magnetoresistive element 11 whose resistance state is in the second state (see FIG. 12). This can reliably improve the write accuracy.

[0176] The resistance value R of the second fixed resistor ２may be set for the resistance value of the magnetoresistive element 11 whose resistance state is the first state (see FIG. 13). This can reliably improve the write accuracy.

[0177] The memory device 100 further includes a read unit 53 that reads the resistance state (e.g., low resistance state or high resistance state) of the magnetoresistive element 11, and the read unit 53 reads the resistance state while the write circuit 24 (e.g., voltage application unit 52) ​​is outputting the first voltage or the second voltage to the magnetoresistive element 11, and the write circuit 24 may control the above-mentioned operation in accordance with the resistance state read by the read unit 53 (see, for example, FIGS. 24 and 25 ). This allows the operation of outputting the first voltage or the second voltage to the magnetoresistive element 11 to be controlled in accordance with the resistance state read by the read unit 53, regardless of the resistance state of the magnetoresistive element 11 before writing, thereby improving the stability of the write operation.

[0178] Furthermore, the write circuit 24 may continue the above-described operation when the resistance state read by the read unit 53 differs from the target resistance state, and may stop the above-described operation when the resistance state read by the read unit 53 is the same as the target resistance state (see FIGS. 24 and 25, etc.). This makes it possible to realize self-adaptive writing, thereby reliably improving the stability of the write operation.

[0179] 4. Other Embodiments The configurations and processes according to the above-described embodiments (including examples and modified examples) may be implemented in various different forms other than the above-described embodiments. For example, the configurations and processes are not limited to the above-described examples and may be implemented in various forms. Furthermore, for example, the configurations, processing procedures, specific names, or information including various data and parameters shown in the above documents and drawings may be changed arbitrarily unless otherwise specified.

[0180] Furthermore, the components and processes according to the above-described embodiments (including examples and modifications) do not necessarily have to be physically configured as shown in the drawings. In other words, the specific forms of distribution and integration of the components and processes are not limited to those shown in the drawings, and all or part of them may be functionally or physically distributed or integrated in any unit depending on various loads, usage conditions, etc.

[0181] Furthermore, the configurations and processes of the above-described embodiments (including examples and modified examples) may be combined as appropriate. For example, at least a part of an embodiment may be combined as appropriate with at least a part of another embodiment. Furthermore, the effects of the embodiments are merely examples and are not intended to be limiting, and other effects may also be obtained.

[0182] <5. Application Examples> <5-1. Various Devices> An application example of the storage device 100 according to the above-described embodiment (including examples and modifications) will be described with reference to Fig. 29. Fig. 29 is a diagram showing an application example of the storage device 100 according to the above-described embodiment. The storage device 100 may be applied to various cases, namely, various devices (for example, electronic devices), as follows.

[0183] As shown in FIG. 29 , the storage device 100 is used in, for example, “devices for capturing images for viewing, such as digital cameras and portable devices with camera functions,” “devices for traffic use, such as in-vehicle sensors for capturing images of the front, rear, surroundings, and interior of a vehicle for safe driving such as automatic stopping and for recognizing the driver's state, surveillance cameras for monitoring moving vehicles and roads, and distance measuring sensors for measuring distances between vehicles,” “devices for home appliances such as TVs, refrigerators, and air conditioners for capturing images of user gestures and operating the device in accordance with the gestures,” “devices for medical and healthcare use, such as endoscopes and devices for capturing blood vessel images by receiving infrared light,” “devices for security use, such as surveillance cameras for crime prevention and cameras for person authentication,” “devices for beauty use, such as skin measuring devices for capturing images of the skin and microscopes for capturing images of the scalp,” “devices for sports use, such as action cameras and wearable cameras for sports use,” and “devices for agriculture, such as cameras for monitoring the condition of fields and crops.”

[0184] The technology according to the present disclosure can be applied to various products. For example, the technology according to the present disclosure may be realized as an electronic device mounted on any type of moving body, such as an automobile, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, a personal mobility device, an airplane, a drone, a ship, a robot, a construction machine, or an agricultural machine (tractor). Furthermore, for example, the technology according to the present disclosure may be realized as an electronic device mounted on an endoscopic surgery system, a microsurgery system, or the like.

[0185] <5-2. Imaging Device> An imaging device 300 according to an application example will be described with reference to Fig. 30. Fig. 30 is a diagram showing an example of the configuration of the imaging device 300 according to an application example. The imaging device 300 is an example of an electronic device to which the storage device 100 according to any of the above-described embodiments is applied. Examples of the imaging device 300 include electronic devices such as digital still cameras, video cameras, smartphones and mobile phones with imaging functions.

[0186] 30, the imaging device 300 includes an optical system 301, a shutter device 302, an imaging element (solid-state imaging device) 303, a control circuit (drive circuit) 304, a signal processing circuit 305, a monitor 306, and a memory 307. The imaging device 300 is capable of capturing still images and moving images.

[0187] The optical system 301 includes one or more lenses. The optical system 301 guides light from a subject (incident light) to the image sensor 303, and forms an image on the light receiving surface of the image sensor 303.

[0188] The shutter device 302 is disposed between the optical system 301 and the image sensor 303. The shutter device 302 controls the light irradiation period and the light blocking period for the image sensor 303 under the control of the control circuit 304.

[0189] The image sensor 303 accumulates signal charges for a certain period of time in response to light that is focused on the light receiving surface via the optical system 301 and the shutter device 302. The signal charges accumulated in the image sensor 303 are transferred in accordance with a drive signal (timing signal) supplied from the control circuit 304. The image sensor 303 may be, for example, a solid-state image sensor.

[0190] The control circuit 304 outputs a drive signal that controls the transfer operation of the image sensor 303 and the shutter operation of the shutter device 302 , thereby driving the image sensor 303 and the shutter device 302 .

[0191] The signal processing circuit 305 performs various signal processing on the signal charges output from the image sensor 303. The image (image data) obtained by the signal processing performed by the signal processing circuit 305 is supplied to a monitor 306 and also to a memory 307.

[0192] The monitor 306 displays moving or still images captured by the image sensor 303 based on the image data supplied from the signal processing circuit 305. As the monitor 306, for example, a panel-type display device such as a liquid crystal panel or an organic EL (Electro Luminescence) panel is used.

[0193] The memory 307 stores image data supplied from the signal processing circuit 305, i.e., image data of moving images or still images captured by the image sensor 303. As the memory 307, for example, the storage device 100 according to any one of the above-described embodiments is used.

[0194] In the imaging device 300 configured in this way, by applying the storage device 100 according to the above embodiment as the memory 307, it is possible to obtain the same effects as those of the above embodiment.

[0195] <5-3. Distance Measuring Device> A distance measuring device 400 according to an application example will be described with reference to Fig. 31. Fig. 31 is a diagram showing an example of the configuration of the distance measuring device 400 according to an application example. This distance measuring device 400 is an example of an electronic device to which the storage device 100 according to any of the above-described embodiments is applied.

[0196] 31 , distance measuring device (distance image sensor) 400 includes a light source unit 401, an optical system 402, an image sensor (solid-state image sensor) 403, a control circuit (drive circuit) 404, a signal processing circuit 405, a monitor 406, and a memory 407. Distance measuring device 400 projects light from light source unit 401 toward an object and receives light (modulated light or pulsed light) reflected from the surface of the object, thereby obtaining a distance image according to the distance to the object.

[0197] The light source unit 401 projects light toward the subject. For example, a vertical cavity surface emitting laser (VCSEL) array that emits laser light as a surface light source, or a laser diode array in which laser diodes are arranged in a line, is used as the light source unit 401. The laser diode array is supported by a predetermined drive unit (not shown) and scanned in a direction perpendicular to the direction in which the laser diodes are arranged.

[0198] The optical system 402 includes one or more lenses. The optical system 402 guides light from a subject (incident light) to the image sensor 403, and forms an image on the light receiving surface (sensor portion) of the image sensor 403.

[0199] The image sensor 403 accumulates signal charges in response to light that is imaged on the light receiving surface via the optical system 402. A distance signal indicating a distance determined from a light receiving signal (APD OUT) output from the image sensor 403 is supplied to a signal processing circuit 405. As the image sensor 403, for example, a solid-state image sensor such as an image sensor is used.

[0200] The control circuit 404 outputs a drive signal (control signal) that controls the operation of the light source unit 401, the image sensor 403, and the like, thereby driving the light source unit 401, the image sensor 403, and the like.

[0201] The signal processing circuit 405 performs various signal processing on the distance signal supplied from the image sensor 403. For example, the signal processing circuit 405 performs image processing (e.g., histogram processing, peak detection processing, etc.) to construct a distance image based on the distance signal. The image (image data) obtained by the signal processing performed by the signal processing circuit 405 is supplied to a monitor 406 and also to a memory 407.

[0202] The monitor 406 displays the distance image captured by the image sensor 403 based on the image data supplied from the signal processing circuit 405. The monitor 406 may be, for example, a panel display device such as a liquid crystal panel or an organic EL panel.

[0203] The memory 407 stores the image data supplied from the signal processing circuit 405, i.e., the image data of the distance image captured by the image sensor 403. As the memory 407, for example, the storage device 100 according to any one of the above-described embodiments is used.

[0204] In the distance measuring device 400 configured in this way, by applying the storage device 100 according to the above embodiment as the memory 407, it is possible to obtain the same effects as in the above embodiment.

[0205] As described above, the storage device 100 according to the above-described embodiments can be implemented in various electronic devices. For example, the storage device 100 according to any of the above-described embodiments may be installed in various electronic devices, such as an HDD (hard disk drive), a notebook PC (personal computer), a mobile device (e.g., a smartphone or tablet PC), a PDA (personal digital assistant), a wearable device, a game device, or a music device, in addition to the imaging device 300 or the distance measuring device 400. For example, the storage device 100 may be used as various types of memory, such as storage.

[0206] <6. Supplementary Notes> The present technology may also be configured as follows. (1) A storage device including: a magnetoresistive element whose resistance state is changeable between a first state and a second state by application of a voltage; a selection element connected to the magnetoresistive element; a load resistance circuit whose resistance value is changeable; and a write circuit that applies a voltage to the magnetoresistive element via the load resistance circuit, wherein the write circuit outputs a first voltage that changes the resistance state to the first state and a second voltage that changes the resistance state to the second state, by changing the first voltage and the second voltage. (2) The storage device according to (1), wherein one or both of the first voltage and the second voltage are pulse voltages. (3) The storage device according to (2), wherein the waveforms of the first voltage and the second voltage are different. (4) The storage device according to (2) or (3), wherein the magnitudes of the first voltage and the second voltage are different. (5) The storage device according to any one of (2) to (4), wherein the pulse waveform of the pulse voltage is non-rectangular. (6) The storage device according to (5), wherein both the first voltage and the second voltage are pulse voltages, the pulse waveform of the first voltage is non-rectangular, and the pulse waveform of the second voltage is rectangular. (7) The storage device according to (5) or (6), wherein the non-rectangular pulse waveform has a shape in which the amplitude gradually decreases from a first amplitude value greater than 0 to a second amplitude value. (8) The storage device according to (7), wherein the non-rectangular pulse waveform has a shape in which the amplitude gradually decreases from the first amplitude value to the second amplitude value and maintains the second amplitude value until the end of the waveform. (9) The storage device according to (7), wherein the non-rectangular pulse waveform has a shape in which the amplitude gradually decreases from the first amplitude value to the second amplitude value and decreases from the second amplitude value in a linear, curved, or stepwise manner. (10) The storage device according to any one of (1) to (9), wherein the write circuit divides the first voltage or the second voltage and applies the divided voltage to the load resistance circuit and the magnetoresistive element. (11) The storage device according to any one of (1) to (10), wherein the load resistance circuit is connected to the magnetoresistive element on the side opposite to the selection element side.(12) The memory device according to any one of (1) to (11), wherein the load resistance circuit includes a plurality of fixed resistors each having a different fixed resistance value, and a switch that switches between a plurality of wiring paths that pass through the plurality of fixed resistors. (13) The memory device according to (12), wherein the plurality of fixed resistors include a first fixed resistor and a second fixed resistor, and wherein the write circuit applies the first voltage to the magnetoresistive element via the first fixed resistor when changing the resistance state to the first state, and applies the second voltage to the magnetoresistive element via the second fixed resistor when changing the resistance state to the second state. (14) The memory device according to (13), wherein the resistance value of the first fixed resistor is smaller than the resistance value of the second fixed resistor. (15) The memory device according to (13) or (14), wherein the resistance value of the first fixed resistor is set to the resistance value of the magnetoresistive element when the resistance state is in the second state. (16) The storage device according to any one of (13) to (15), wherein a resistance value of the second fixed resistor is set to a resistance value of the magnetoresistive element when the resistance state is the first state. (17) The storage device according to any one of (1) to (16), further comprising a read unit that reads the resistance state of the magnetoresistive element, wherein the read unit reads the resistance state while the write circuit is outputting the first voltage or the second voltage to the magnetoresistive element, and the write circuit controls the operation according to the resistance state read by the read unit. (18) The storage device according to (17), wherein the write circuit continues the operation when the resistance state read by the read unit is different from a target resistance state, and stops the operation when the resistance state read by the read unit is the same as the target resistance state.(19) An electronic device comprising: a storage device for storing data, the storage device comprising: a magnetoresistive element whose resistance state is changeable between a first state and a second state by application of a voltage; a selection element connected to the magnetoresistive element; a load resistance circuit whose resistance value is variable; and a write circuit that applies a voltage to the magnetoresistive element via the load resistance circuit, wherein the write circuit outputs a first voltage that changes the resistance state to the first state and a second voltage that changes the resistance state to the second state, by changing the first voltage and the second voltage that changes the resistance state to the second state. (20) A method for controlling a storage device, the write circuit applying a voltage to the magnetoresistive element whose resistance state is changeable between a first state and a second state by application of a voltage via the load resistance circuit whose resistance value is variable, and the write circuit outputs a first voltage that changes the resistance state to the first state and a second voltage that changes the resistance state to the second state, by changing the first voltage and the second voltage that changes the resistance state to the second state. (21) An electronic device comprising the storage device according to any one of (1) to (18). (22) A method for controlling a storage device, for controlling the storage device according to any one of (1) to (18).

[0207] 1 Memory cell array 10 Memory cell 11 Magnetoresistance element 12 Selection element 20 Peripheral circuit 21 I / O 22 Control circuit 23 Voltage generation circuit 24 Write circuit 25 Read circuit 26 Bit line address decoder 27 Bit line control circuit 28 Word line address decoder 29 Word line control circuit 30 Sense amplifier 50 Write section 51 Write voltage generation section 52 Voltage application section 53 Read section 54 Comparison section 55 Feedback section 56 Write selection section 100 Storage device 101 State 0 write voltage line 102 State 1 write voltage line 103 Write data line 104 Write start signal line 105 Write selection line 106 Write signal line 111 Fixed layer 112 Tunnel barrier layer 113 Recording layer 114 Magnetic field generation layer 115 Magnetic field generation layer 200 Write pulse generation circuit 201 Input terminal 202 CR circuit 203 Transfer gate 204 Operational amplifier 205 Output terminal 206 Output 207 Non-inverting input 210 Write pulse generating circuit 211 Waveform memory 212 D / A conversion circuit 241 Load resistance circuit 300 Imaging device 307 Memory 400 Distance measuring device 407 Memory R1 Fixed resistor R2 Fixed resistor

Claims

1. A memory device comprising: a magnetoresistive element whose resistance state can be changed between a first state and a second state by applying a voltage; a selection element connected to the magnetoresistive element; a load resistance circuit whose resistance value can be changed; and a write circuit that applies a voltage to the magnetoresistive element via the load resistance circuit, wherein the write circuit outputs a first voltage that changes the resistance state to the first state and a second voltage that changes the resistance state to the second state, by changing the voltage.

2. The memory device according to claim 1, wherein one or both of the first voltage and the second voltage is a pulse voltage.

3. The storage device according to claim 2, wherein the waveforms of the first voltage and the second voltage are different from each other.

4. The memory device according to claim 2, wherein the first voltage and the second voltage have different magnitudes.

5. The storage device according to claim 2, wherein the pulse waveform of the pulse voltage is non-rectangular.

6. The memory device according to claim 5, wherein both the first voltage and the second voltage are pulse voltages, the pulse waveform of the first voltage is non-rectangular, and the pulse waveform of the second voltage is rectangular.

7. The storage device according to claim 5, wherein the non-rectangular pulse waveform has an amplitude that gradually decreases from a first amplitude value greater than 0 to a second amplitude value.

8. The storage device according to claim 7, wherein the non-rectangular pulse waveform has an amplitude that gradually decreases from the first amplitude value to the second amplitude value and maintains the second amplitude value until the end of the waveform.

9. The storage device according to claim 7, wherein the non-rectangular pulse waveform has an amplitude that gradually decreases from the first amplitude value to the second amplitude value, and then decreases from the second amplitude value in a linear, curved, or stepped manner.

10. The memory device according to claim 1, wherein the write circuit divides the first voltage or the second voltage and applies the divided voltage to the load resistance circuit and the magnetoresistive element.

11. The memory device according to claim 1, wherein the load resistance circuit is connected to the side of the magnetoresistive element opposite to the selection element side.

12. The storage device according to claim 1, wherein the load resistance circuit comprises: a plurality of fixed resistors each having a different fixed resistance value; and a switch for switching between a plurality of wiring paths passing through each of the plurality of fixed resistors.

13. The memory device described in claim 12, wherein the plurality of fixed resistors include a first fixed resistor and a second fixed resistor, and the write circuit applies the first voltage to the magnetoresistive element via the first fixed resistor when changing the resistance state to the first state, and applies the second voltage to the magnetoresistive element via the second fixed resistor when changing the resistance state to the second state.

14. The memory device according to claim 13, wherein the resistance value of the first fixed resistor is smaller than the resistance value of the second fixed resistor.

15. The memory device according to claim 13, wherein the resistance value of the first fixed resistor is set to the resistance value of the magnetoresistive element when the resistance state is in the second state.

16. The memory device according to claim 13, wherein the resistance value of the second fixed resistor is set to the resistance value of the magnetoresistive element when the resistance state is in the first state.

17. The memory device according to claim 1, further comprising a read unit that reads the resistance state of the magnetoresistive element, wherein the read unit reads the resistance state while the write circuit is outputting the first voltage or the second voltage to the magnetoresistive element, and the write circuit controls the operation in accordance with the resistance state read by the read unit.

18. The memory device according to claim 17, wherein the write circuit continues the operation if the resistance state read by the read unit differs from the target resistance state, and stops the operation if the resistance state read by the read unit is the same as the target resistance state.

19. An electronic device comprising: a memory device for storing data, the memory device comprising: a magnetoresistive element whose resistance state is changeable between a first state and a second state by application of a voltage; a selection element connected to the magnetoresistive element; a load resistance circuit whose resistance value is changeable; and a write circuit that applies a voltage to the magnetoresistive element via the load resistance circuit, wherein the write circuit outputs a first voltage that changes the resistance state to the first state and a second voltage that changes the resistance state to the second state, by changing the voltage.

20. A method for controlling a memory device, comprising: a write circuit applying a voltage to a magnetoresistive element, the resistance state of which can be changed between a first state and a second state by applying a voltage, via a load resistance circuit having a variable resistance value; and the write circuit outputting a first voltage that changes the resistance state to the first state and a second voltage that changes the resistance state to the second state, by changing the voltage.

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