Memory cell

Abstract

Provided is a memory cell with which it is possible to reliably inject a charge into a floating gate even if the film thickness of a gate insulating film has been increased. A memory cell 1a has a configuration in which a program transistor 2a is constituted by a PMOS transistor and electrons can be injected into a floating gate FG by hot electron injection using CHE. Due to this configuration, the memory cell 1a is configured so that a charge can be reliably injected into the floating gate FG even if the film thickness of gate insulating films 8a, 8b, 8c has been increased.

Description

memory cell

[0001] The present invention relates to a memory cell.

[0002] Conventionally, nonvolatile semiconductor memory devices using single-layer polysilicon have been known, and are used as multi-time programmable memories or one-time programmable memories. Patent Document 1 discloses a nonvolatile semiconductor memory device using single-layer polysilicon, in which an erase capacitor, a read transistor, a program transistor, and a control capacitor share a single floating gate. In the nonvolatile semiconductor memory device disclosed in Patent Document 1, charges are injected into the floating gate by the quantum tunneling effect.

[0003] JP 2014-86435 A

[0004] However, since nonvolatile semiconductor memory devices using single-layer polysilicon are expected to be used in various ways, the thickness of the gate insulating film may be increased, but if the thickness of the gate insulating film is increased, it may become difficult to inject charges into the floating gate by the quantum tunneling effect.

[0005] The present invention has been made in consideration of the above points, and has as its object to provide a memory cell that can reliably inject charges into the floating gate even when the thickness of the gate insulating film is increased.

[0006] The memory cell of the present invention is a memory cell of a nonvolatile semiconductor memory device and comprises a program transistor and a read transistor, the program transistor being formed in an N-type well and having a drain which is a P-type diffusion layer formed on the surface of the N-type well, a source which is a P-type diffusion layer formed on the surface of the N-type well and separated from the drain, a gate insulating film provided on the N-type well between the drain and the source, and a floating gate provided on the gate insulating film, the read transistor being formed in an N-type well and having a drain which is a P-type diffusion layer formed on the surface of the N-type well, a source which is a P-type diffusion layer formed on the surface of the N-type well and separated from the drain, a gate insulating film provided on the N-type well between the drain and the source, and a floating gate provided on the gate insulating film, the floating gate of the program transistor and the floating gate of the read transistor being electrically connected.

[0007] According to the present invention, even if the thickness of the gate insulating film is increased, charges can be reliably injected into the floating gate.

[0008] FIG. 3 is a schematic diagram showing a cross-sectional side configuration of a memory cell according to a first embodiment; FIG. 4 is a schematic diagram showing an example of a planar layout of the memory cell shown in FIG. 1; FIG. 3A is a graph for explaining the characteristics of a PMOS transistor with a standard gate length, and FIG. 3B is a graph for explaining the characteristics of a PMOS transistor with a gate length shorter than the standard gate length; FIG. 4 is a schematic diagram showing a cross-sectional side configuration of a memory cell according to a second embodiment; FIG. 5 is a schematic diagram showing a cross-sectional side configuration of a memory cell according to a third embodiment; and FIG. 6 is a schematic diagram showing an example of a planar layout of the memory cell shown in FIG.

[0009] Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the drawings. In this specification and drawings, components having substantially the same functional configurations are designated by the same reference numerals, and redundant description will be omitted.

[0010] (1) First Embodiment (1-1) Configuration of Memory Cell According to First Embodiment FIG. 1 is a schematic diagram showing a cross-sectional side configuration of a memory cell 1a according to the first embodiment. The memory cell 1a according to the first embodiment is used in a non-volatile semiconductor memory device that is a multi-time programmable memory. FIG. 2 is a schematic diagram showing an example of a planar layout of the memory cell 1a shown in FIG. 1. Note that FIG. 1 is a schematic diagram showing a cross-sectional side configuration of the memory cell 1a taken along the line A-A' in FIG. 2.

[0011] The memory cell 1a includes a program transistor 2a, a read transistor 3a, and an erase capacitor 4a provided on a P-type substrate PSub. The substrate PSub is a semiconductor substrate made of P-type single crystal silicon containing impurities such as boron.

[0012] The program transistor 2a is a P-channel MOS (Metal Oxide Semiconductor) FET (Field Effect Transistor) and is formed in an N-type well PrNW provided in a substrate PSub. A drain PD, which is a P-type diffusion layer, is formed on the surface of the N-type well PrNW, and a source PS, which is a P-type diffusion layer, is formed at a position spaced apart from the drain PD. A gate insulating film 8a made of silicon oxide or the like is provided on the N-type well PrNW between the drain PD and the source PS. A floating gate FG capable of accumulating charge is provided on the gate insulating film 8a. The floating gate FG is formed of P-type polysilicon containing impurities such as boron.

[0013] The thickness of the gate insulating film 8a of the program transistor 2a (the distance from the surface of the N-type well PrNW to the underside of the floating gate FG) is preferably 16 nm or more, more preferably 20 nm or more, and most preferably 30 nm or more. In the memory cell 1a according to this embodiment, even if the thickness of the gate insulating film 8a is increased, charges can be injected into the floating gate FG by a write method using CHE (Channel Hot Electron) injection (described later). The preferred range of the thickness of the gate insulating film 8a of the program transistor 2a will be described in "(1-2) Principle of Data Write Operation" below.

[0014] The source PS of the program transistor 2a is connected to a source line L ＰＳ is connected to the source line L ＰＳ A predetermined voltage is applied to the drain PD of the program transistor 2a via the drain line L ＰＤ The N-type well PrNW in which the program transistor 2a is formed is connected to a well voltage line L Ｐ is connected to the well voltage line L Ｐ A predetermined voltage is applied via the

[0015] The read transistor 3a is a P-channel MOSFET formed in an N-type well RNW provided in the substrate PSub. A drain RD, which is a P-type diffusion layer, is formed on the surface of the N-type well RNW, and a source RS, which is also a P-type diffusion layer, is formed at a position spaced apart from the drain RD. A gate insulating film 8b made of silicon oxide or the like is provided on the N-type well RNW between the drain RD and the source RS. A floating gate FG electrically connected to the floating gate FG of the program transistor 2a is provided on the gate insulating film 8b.

[0016] The source RS of the read transistor 3a is connected to the source line L ＲＳ is connected to the source line L ＲＳA predetermined voltage is applied to the drain RD of the read transistor 3a via the drain line L ＲＤ The N-type well RNW in which the read transistor 3a is formed is connected to a well voltage line L Ｒ is connected to the well voltage line L Ｒ A predetermined voltage is applied via the

[0017] The thickness of the gate insulating film 8b of the read transistor 3a (the distance from the surface of the N-type well RNW to the underside of the floating gate FG) is preferably the same as the thickness of the gate insulating films 8a, 8c of the program transistor 2a and the erase capacitor 4a. By making the thickness of the gate insulating film 8b of the read transistor 3a the same as the thickness of the gate insulating films 8a, 8c of the program transistor 2a and the erase capacitor 4a, the gate insulating films 8a, 8b, 8c of the program transistor 2a, read transistor 3a, and erase capacitor 4a can be formed collectively during the manufacture of the memory cell 1a.

[0018] In the substrate PSub, a P-type well PW1 is formed between an N-type well PrNW in which the program transistor 2a is formed and an N-type well RNW in which the read transistor 3a is formed. The N-type well PrNW in which the program transistor 2a is formed and the N-type well RNW in which the read transistor 3a is formed are electrically isolated by the P-type well PW1. In addition, an element isolation layer 6 is provided between an active region AR1 on the surface of the N-type well PrNW in which the program transistor 2a is formed and an active region AR2 on the surface of the N-type well RNW in which the read transistor 3a is formed. The active region AR1 of the program transistor 2a and the active region AR2 of the read transistor 3a are electrically isolated by the element isolation layer 6.

[0019] The erase capacitor 4a is a PMOS capacitor formed in an N-type well ENW provided in the substrate PSub. A gate insulating film 8c made of silicon oxide or the like is provided on the N-type well ENW. A floating gate FG electrically connected to the floating gates FG of the program transistor 2a and the read transistor 3a is provided on the gate insulating film 8c.

[0020] The N-type well ENW in which the erase capacitor 4a is formed is connected to a well voltage line L Ｅ is connected to the well voltage line L Ｅ A predetermined voltage is applied via the

[0021] The thickness of the gate insulating film 8c of the erase capacitor 4a (the distance from the surface of the N-type well ENW to the underside of the floating gate FG) is preferably 16 nm or more, more preferably 20 nm or more, and most preferably 30 nm or more. The preferred range of the thickness of the gate insulating film 8c of the erase capacitor 4a will be explained in "(1-5-1) Data Erasure Operation Using SHH Injection" below.

[0022] In the substrate PSub, a P-type well PW2 is formed between an N-type well RNW in which the read transistor 3a is formed and an N-type well ENW in which the erase capacitor 4a is formed. The N-type well RNW in which the read transistor 3a is formed and the N-type well ENW in which the erase capacitor 4a is formed are electrically isolated by the P-type well PW2. In addition, an element isolation layer 6 is formed between an active region AR2 on the surface of the N-type well RNW in which the read transistor 3a is formed and an active region AR3 on the surface of the N-type well RNW of the erase capacitor 4a. The active region AR2 of the read transistor 3a and the active region AR3 of the erase capacitor 4a are electrically isolated by the element isolation layer 6.

[0023] As shown in FIG. 2 , in memory cell 1a, one floating gate FG is shared by program transistor 2a, read transistor 3a, and erase capacitor 4a. In memory cell 1a according to this embodiment, program transistor 2a, read transistor 3a, and erase capacitor 4a are linearly arranged, and floating gate FG extends so as to intersect with active region AR1 of program transistor 2a, active region AR2 of read transistor 3a, and active region AR3 of erase capacitor 4a. The floating gate FG arranged in active region AR1 of program transistor 2a is formed in a rectangular shape in a plan view. In a plan view, a source PS, which is a P-type diffusion layer, and a drain PD, which is also a P-type diffusion layer, are arranged opposite each other across the floating gate FG in the short direction of the floating gate FG.

[0024] The source PS is connected to the source line L ＰＳ The drain PD is provided with a columnar contact 10s connected to the drain line L ＰＤ In the program transistor 2a according to this embodiment, the length of the floating gate FG in the short-side direction is the "gate length," and the length of the region sandwiched between the source PS and the drain PD in the short-side direction of the floating gate FG is the "effective gate length LgefP."

[0025] The floating gate FG arranged in the active region AR2 of the read transistor 3a is formed in a rectangular shape in a plan view, and is formed continuously from the floating gate FG of the program transistor 2a. In a plan view, a source RS which is a P-type diffusion layer and a drain RD which is also a P-type diffusion layer are arranged opposite each other with the floating gate FG sandwiched therebetween. The source RS is connected to a source line L. ＲＳ The drain RD is provided with a columnar contact 11s connected to the drain line L ＲＤ A columnar contact 11d is provided to be connected to the

[0026] In the read transistor 3a according to this embodiment, the length of the floating gate FG in the short-side direction is the "gate length," and the length of the region sandwiched between the source RS and drain RD in the short-side direction of the floating gate FG is the "effective gate length LgefR." Here, the effective gate length LgefP of the floating gate FG of the above-mentioned program transistor 2a is selected to be smaller than the effective gate length LgefR of the floating gate FG of the read transistor 3a.

[0027] The floating gate FG arranged in the active region AR3 of the erase capacitor 4a is formed in a rectangular shape in a plan view, and is formed continuously from the floating gates FG of the program transistor 2a and the read transistor 3a. In this embodiment, the floating gate FG arranged in the active region AR2 of the read transistor 3a extends linearly to the region where the erase capacitor 4a is formed, with its short side length remaining the same.

[0028] The floating gate FG covers the active region AR3 of the erase capacitor 4a, and does not intersect with the active region AR3. If the floating gate FG intersects with the active region AR3, variations in the shape of the edge of the floating gate FG on the active region AR3 will cause variations in the voltage at which the avalanche phenomenon occurs during the data erase operation by SHH injection, which will be described later. By configuring the floating gate FG to cover the active region AR3 of the erase capacitor 4a, it is possible to reduce variations in the voltage at which the avalanche phenomenon occurs, and data can be erased reliably by SHH injection.

[0029] 2, in a plan view, the area where the floating gate FG arranged in the program transistor 2a faces the active region AR1 of the program transistor 2a is shown as a1, the area where the floating gate FG arranged in the read transistor 3a faces the active region AR2 of the read transistor 3a is shown as a2, and the area where the floating gate FG arranged in the erase capacitor 4a faces the active region AR3 of the erase capacitor 4a is shown as a3.

[0030] In this embodiment, the area a3 where the floating gate FG of the erase capacitor 4a faces the active region AR3 is preferably 10% or less, and more preferably 5% or less, of the total area (area a1 + area a2 + area a3) obtained by adding together the area a1 where the floating gate FG of the program transistor 2a faces the active region AR1, the area a2 where the floating gate FG of the read transistor 3a faces the active region AR2, and the area a3 where the floating gate FG of the erase capacitor 4a faces the active region AR3. By setting the area a3 to 10% or less of the total area (area a1 + area a2 + area a3), the coupling ratio of the erase capacitor 4a can be reduced, and the potential of the floating gate FG can be prevented from being affected during data write and erase operations. By setting the area a3 to 5% or less of the total area (area a1 + area a2 + area a3), the coupling ratio of the erase capacitor 4a can be further reduced, and the potential of the floating gate FG can be further prevented from being affected during a data write operation or a data erase operation. Details will be described in "(1-4) Data Write Operation."

[0031] In this embodiment, it is also preferable that the area a2 of the active region AR2 facing the floating gate FG of the read transistor 3a is larger than the area a1 of the active region AR1 facing the floating gate FG of the program transistor 2a, thereby enhancing the effect of effectively increasing the potential of the floating gate FG due to capacitive coupling when a high positive well voltage Vrw is applied to the N-type well RNW of the read transistor 3a.

[0032] The memory cell 1a can be fabricated by performing the film formation process, photolithography process, etching process, impurity injection process, and other processes that are typical manufacturing processes for PMOS transistors, and therefore the manufacturing method will not be described here.

[0033] (1-2) Data Write Operation Principle Next, the data write operation principle in memory cell 1a will be described. Here, FIG. 3A is a graph illustrating the characteristics of a PMOS transistor with a standard gate length, and FIG. 3B is a graph illustrating the characteristics of a PMOS transistor with a gate length shorter than the standard gate length. The gate length of the PMOS transistor with the standard gate length in FIG. 3A is equal to the gate length of a PMOS transistor in a standard logic circuit of a nonvolatile semiconductor memory device in which the PMOS transistor is used. This gate length is the minimum processing dimension of the process generation in which the nonvolatile semiconductor memory device is manufactured.

[0034] 3A and 3B are graphs showing the drain current ("-Id" in FIG. 3), substrate current ("Ib" in FIG. 3), and gate current ("|Ig|" in FIG. 3) versus gate voltage when the well voltage and source voltage of a PMOS transistor are each set to 0 [V], a negative high voltage of -10 [V] is applied to the drain, and the gate voltage is changed from +10 [V] to -20 [V]. The horizontal axis shows the gate voltage [V], and the vertical axis shows the logarithmic current value (absolute value of the current) [A] of each current.

[0035] In a PMOS transistor with a standard gate length shown in 3A of Fig. 3, the drain current increases rapidly when the gate voltage exceeds the threshold voltage. On the other hand, in a PMOS transistor with a gate length shorter than the standard gate length shown in 3B of Fig. 3, a punch-through state occurs, and drain current flows even when the gate voltage is lower than the threshold voltage (hereinafter, the gate voltage with a larger absolute value toward the negative voltage side will be referred to as "high" and the gate voltage with a larger absolute value toward the positive voltage side will be referred to as "low").

[0036] FIG. 3 shows gate currents due to carrier injection by hot carrier injection modes, DAHE (Drain Avalanche Hot Electron), DAHH (Drain Avalanche Hot Hole), BBHE (Band-to-Band Tunneling Induced Hot Electron), CHH (Channel Hot Hole), and CHE (Channel Hot Electron).

[0037] In DAHE injection, electrons gaining energy in a large horizontal electric field near the drain when the channel is pinched off are injected into the Si-SiO ２ The DAHH injection is a process in which holes gain energy in a large horizontal electric field near the drain when the channel is pinched off and are injected into the gate oxide film. ２ It is injected into the gate oxide film by overcoming the energy barrier at the interface. DAHE injection and DAHH injection cause the gate current to peak just before the drain current starts to flow and the substrate current reaches its peak. This current is particularly noticeable in PMOS transistors, where a more positive voltage than the drain is applied to the gate, making electrons more likely to be injected and DAHE dominates. DAHH injection occurs in a narrower range of gate voltages than DAHE injection, and the rate of injection is low, but hole injection also occurs, so it can occur in PMOS transistors as well. Gate current due to BBHE injection occurs when the gate voltage is a large positive value and the drain-substrate voltage is high. CHH injection occurs when holes gain energy from the electric field in the horizontal direction of the channel and are transported to the Si-SiO２ The electrons are injected into the gate oxide film by crossing the energy barrier at the interface, which can cause gate current to occur at large negative gate voltages.

[0038] Next, CHE injection will be explained. In a PMOS transistor with a standard gate length shown in 3A of FIG. 3, the drain current is cut off at a gate voltage of 0 [V], so no gate current due to CHE injection is observed. However, when the gate length is small and the drain voltage is high, the PMOS transistor enters a punch-through state, and the drain current cannot be cut off even if the gate voltage is lowered. The carriers that have gained energy from the electric field in the horizontal direction of the channel and become hot are transported by the electric field in the vertical direction of the channel to the Si-SiO ２ The electrons are injected into the gate oxide film by crossing the energy barrier at the interface. In FIG. 3B, a gate current due to CHE injection is observed in the gate voltage range of +9 V to 0 V. This phenomenon has not been discussed before. The inventors of this application focused on the CHE phenomenon, which has not been discussed before and is prominent in PMOS transistors in the punch-through state, and utilized it for writing data.

[0039] The memory cell 1a according to this embodiment writes data by injecting charge into the floating gate FG of the program transistor 2a using CHE injection in the PMOS transistor in the punch-through state. To achieve a punch-through PMOS transistor, the memory cell 1a according to this embodiment has a small effective gate length LgefP of the floating gate FG of the program transistor 2a. The effective gate length LgefP of the floating gate FG of the program transistor 2a is preferably set smaller than the effective gate length of the transistors in the standard logic circuit of the nonvolatile semiconductor memory device in which the memory cell 1a is used. Furthermore, the effective gate length LgefP of the floating gate FG of the program transistor 2a is preferably set smaller than the minimum processing dimension of the process generation in which the nonvolatile semiconductor memory device is manufactured.

[0040] Specific methods for reducing the effective gate length LgefP of the program transistor 2a include, for example, reducing the gate length of the program transistor 2a in a photolithography process and / or an etching process. Alternatively, the source PS and drain PD of the program transistor 2a may be implanted inside the edge of the floating gate FG by oblique ion implantation, thereby reducing the distance between the source PS and drain PD. Another method is to provide a constriction or notch in a portion of the floating gate FG on the active region AR1 of the program transistor 2a.

[0041] Although the description herein has been given of a case in which the effective gate length LgefP of the program transistor 2a is reduced to achieve a punch-through state and charge is injected into the floating gate FG of the program transistor 2a using CHE injection, the present invention is not limited to this. For example, instead of reducing the effective gate length LgefP of the program transistor 2a, the impurity concentration of the channel of the program transistor 2a may be adjusted to lower the threshold voltage, making punch-through easier than with transistors in standard logic circuits. Even with this method, charge can be injected into the floating gate FG of the program transistor 2a using CHE injection.

[0042] In a PMOS transistor in a punch-through state, the subthreshold swing, which is the amount of change in gate voltage required to increase the drain current by one digit, deteriorates and becomes a large value. The subthreshold swing of the program transistor 2a of the memory cell 1a according to this embodiment when the drain voltage is −10 V is preferably greater than 400 mV / dec.

[0043] In a PMOS transistor in a punch-through state, the drain current increases with increasing drain voltage even in the saturation region due to drain-induced barrier lowering (DIBL) and the channel length modulation effect. In the program transistor 2a of the memory cell 1a according to this embodiment, the channel length modulation ratio, which is the ratio of the drain current in the saturation region when the drain voltage is −10 V to the drain current in the saturation region when the drain voltage is −2 V, is preferably two or more.

[0044] A PMOS transistor in the punch-through state has a small on / off ratio. The on / off ratio, which is the ratio of the on-current when the drain voltage is −10 V and the gate voltage is −10 V to the off-current when the drain voltage is −10 V and the gate voltage is 0 V, of the program transistor 2 a of the memory cell 1 a according to this embodiment is preferably five orders of magnitude or less.

[0045] In the memory cell 1a according to this embodiment, the subthreshold swing of the program transistor 2a is larger than the subthreshold swing of the read transistor 3a. In the memory cell 1a according to this embodiment, the channel length modulation ratio of the program transistor 2a is larger than the channel length modulation ratio of the read transistor 3a. In the memory cell 1a according to this embodiment, the on / off ratio of the program transistor 2a is smaller than the on / off ratio of the read transistor 3a.

[0046] (1-3) In a configuration in which a read transistor is provided separately from a program transistor, when CHE injection is used for data write operations, it is preferable to reduce the effective gate length LgefP of the program transistor 2a to create a situation in which punch-through occurs in the program transistor 2a. Furthermore, the occurrence of CHE may result in degradation of transistor characteristics. For example, if a configuration is used in which a read transistor 3a is not provided and data read operations are also performed using the program transistor 2a, the threshold voltage Vth of the read information may shift, potentially narrowing the allowable read limit and causing other problems.

[0047] Therefore, in this embodiment, in order to avoid the occurrence of problems when a read operation is performed using the program transistor 2a, a configuration is adopted in which the program transistor 2a for writing data and the read transistor 3a for reading data are provided separately, and the program transistor 2a is not used for reading data but is used exclusively for writing data. Furthermore, in order to generate CHE in the program transistor 2a, the effective gate length LgefP is made small so that a punch-through state occurs, while in order to prevent the punch-through state in the read transistor 3a, it is preferable to make the effective gate length LgefR larger than the effective gate length LgefP of the program transistor 2a.

[0048] The effective gate length LgefR of the floating gate FG of the read transistor 3a is preferably the same as the effective gate length of a transistor in a standard logic circuit of the nonvolatile semiconductor memory device that the memory cell 1a is used in. Furthermore, the effective gate length LgefR of the floating gate FG of the read transistor 3a is preferably the minimum processing dimension of the process generation in which the nonvolatile semiconductor memory device is manufactured.

[0049] For this reason, the memory cell 1a according to this embodiment has a configuration in which the effective gate length LgefP of the floating gate FG of the program transistor 2a is selected to be smaller than the effective gate length LgefR of the floating gate FG of the read transistor 3a.

[0050] (1-4) Data Write Operation Next, we will explain the data write operation using CHE injection in memory cell 1a. Table 1 below shows specific examples of voltage combinations (voltage examples) during data write operations in the "Write" column. The voltage values ​​shown in Table 1 are in "V".

[0051] When data is written by the program transistor 2a, the substrate PSub is set to 0 [V], for example. Also, the program transistor 2a is applied with a source voltage V of +12 [V], for example. ＰＳis applied to the source PS, the drain PD is set to 0 [V], and a well voltage Vprw of +12 [V] is applied to the N-type well PrNW. As a result, in the program transistor 2a, hot electrons are injected into the floating gate FG by CHE injection, overcoming the energy barrier at the interface between the N-type well PrNW and the gate insulating film 8a and the energy barrier of the gate insulating film 8a. The program transistor 2a is in a data-written state with the hot electrons injected into the floating gate FG accumulated. The source voltage V ＰＳ The well voltage Vprw is set to +12 [V] as an example, but it can be set to a higher voltage within a range that does not exceed the junction breakdown voltage of the source PS and the N-type well PrNW, and by setting a higher voltage, the data write speed can be increased. For example, if the junction breakdown voltage of the source PS and the N-type well PrNW is 17 [V], the source voltage V ＰＳ The well voltage Vprw can be set to a maximum of about 16.5 [V].

[0052] During a data write operation, for example, the source RS and drain RD of the read transistor 3a are opened, and a well voltage Vrw of +16 V is applied to the N-type well RNW. The well voltage Vrw applied to the N-type well RNW of the read transistor 3a is preferably a voltage equal to or greater than the well voltage Vprw applied to the N-type well PrNW of the program transistor 2a (a positive voltage whose absolute value is equal to or greater than the well voltage Vprw).

[0053] For example, when a well voltage Vprw of +12 V is applied, applying a well voltage Vrw of +16 V can shift the potential of the floating gate FG during a data write operation more positively than when no well voltage Vprw is applied, thereby improving the efficiency of hot electron injection in the CHE. In other words, if the gate voltage in a PMOS transistor is referred to as "high" when its absolute value is greater toward the negative voltage side and "low" when its absolute value is greater toward the positive voltage side, the voltage of the floating gate FG can be effectively lowered by capacitive coupling, thereby improving the efficiency of hot electron injection in the CHE. This can, for example, shorten the data write time. In this embodiment, the N-type well RNW of the read transistor 3a is physically and electrically separated from the N-type well PrNW of the program transistor 2a. Therefore, a well voltage Vrw of a different voltage value can be applied to the N-type well RNW of the read transistor 3a from that of the N-type well PrNW of the program transistor 2a.

[0054] Furthermore, the area a2 of the active region AR2 facing the floating gate FG of the read transistor 3a is selected to be larger than the area a1 of the active region AR1 facing the floating gate FG of the program transistor 2a and the area a3 of the active region AR3 facing the floating gate FG of the erase capacitor 4a. This can enhance the effect of effectively lowering the potential of the floating gate FG due to capacitive coupling when a high positive well voltage Vrw is applied to the N-type well RNW of the read transistor 3a.

[0055] During a data write operation, for example, in the erase capacitor 4a, the N-type well ENW is opened. Here, the larger the area of ​​the active region facing the floating gate FG, the greater the effect of the well voltage on the potential of the floating gate FG due to capacitive coupling. In the erase capacitor 4a, the area a3 where the floating gate FG faces the active region AR3 is 10% or less of the above-mentioned total area (area a1 + area a2 + area a3), so that the effect of the well voltage Vew of the N-type well ENW on the potential of the floating gate FG due to capacitive coupling can be reduced.

[0056] The memory cell 1a according to this embodiment utilizes CHE injection in a PMOS transistor in a punch-through state, and writes data by setting the floating gate FG to a positive voltage. As shown in FIG. 3B, the drain current Id when the floating gate FG is at a positive voltage is smaller than the drain current Id when the floating gate FG is at a negative voltage. This reduces power consumption during writing.

[0057] (1-5) Data Erase Operation (1-5-1) Data Erase Operation Using SHH Injection Next, a data erase operation in the memory cell 1a will be described. In the memory cell 1a according to this embodiment, data is erased by injecting hot holes into the floating gate FG by SHH (Substrate Hot Hole) injection.

[0058] In a PMOS capacitor, when the gate voltage is fixed at 0 V and a high positive voltage is applied to the well, the current flowing from the well to the gate increases rapidly when the positive voltage applied to the well exceeds, for example, approximately 40 V. This is due to SHH injection. SHH injection is thought to occur when the electric field applied to the band of the N-type well in a PMOS capacitor becomes stronger, accelerating holes. The accelerated holes collide with the lattice to generate new carriers, creating a virtuous cycle of carrier generation, resulting in avalanche. This avalanche phenomenon does not occur with FN (Fowler-Nordheim) tunneling. Using SHH injection, holes can be injected into the floating gate FG more quickly than using FN tunneling. Furthermore, using SHH injection can reduce the area a3 where the floating gate FG of the erase capacitor 4a faces the active region AR3.

[0059] Table 1 above shows specific examples of voltage combinations (voltage examples) during a data erase operation by SHH injection in the "Erase" column. When erasing data using the erase capacitor 4a, the substrate PSub is set to 0 [V]. Furthermore, in the erase capacitor 4a, a well voltage Vew of, for example, 40 [V] or more is applied to the N-type well ENW. From the perspective of fast data erasure, the voltage range of the well voltage Vew applied to the N-type well ENW is preferably higher than the voltage that causes the avalanche phenomenon. Here, 40 [V] or more is used as the voltage that causes the avalanche phenomenon. However, the voltage that causes the avalanche phenomenon depends on the well concentration and depth, and therefore varies depending on the semiconductor manufacturing conditions. In the program transistor 2a, the source PS and drain PD are open, and the N-type well PrNW is set to 0 [V]. In the read transistor 3a, the source RS and drain RD are open, and the N-type well RNW is set to 0 [V].

[0060] As described above, the larger the area of ​​the active region facing the floating gate FG, the greater the effect of the well voltage on the potential of the floating gate FG due to capacitive coupling. In the memory cell 1a according to this embodiment, the area a3 where the floating gate FG of the erase capacitor 4a faces the active region AR3 is smaller than the total area (area a1 + area a2 + area a3) of the area a1 where the floating gate FG of the program transistor 2a faces the active region AR1, the area a2 where the floating gate FG of the read transistor 3a faces the active region AR2, and the area a3 of the active region AR3 facing the floating gate FG of the erase capacitor 4a, and the coupling ratio expressed as area a3 / (area a1 + area a2 + area a3) is small (for example, 5% or less). For this reason, in this embodiment, even if a high well voltage Vew is applied to the active region AR3 of the erase capacitor 4a, which has a small area a3 facing the floating gate FG, the high voltage is unlikely to affect the floating gate FG. Therefore, in the erase capacitor 4a, most (e.g., 95% or more) of the high well voltage Vew can be used for bending the band of the N-type well ENW and injecting holes.

[0061] Furthermore, in memory cell 1a, the coupling ratio of program transistor 2a (area a1 / (area a1+area a2+area a3)) and the coupling ratio of read transistor 3a (area a2 / (area a1+area a2+area a3)) are large, so by setting well voltage Vprw and well voltage Vrw to 0 [V] during the erase operation, the potential of floating gate FG can be adjusted so that it does not float relative to 0 [V].

[0062] When SHH injection is used as a data erasing method, high-energy hot holes are injected into the floating gate by overcoming the energy barrier of the gate insulating film, but this energy may cause defects in the gate insulating film, and holes may be trapped in these defects.

[0063] Here, as shown in publicly known document 1 (Tunnel oxide and ETOX flash scaling limitation) and publicly known document 2 (Limitations on Oxide Thicknesses in FLASH EEPROM Application), it is generally believed that if the thickness of the gate insulating film is about 8 nm, the probability that electrons in the floating gate will tunnel through the gate insulating film will be sufficiently small so that no problems will arise in retaining data.

[0064] When holes are trapped in defects in the gate insulating film, the probability of electrons tunneling through the gate insulating film is highest when the trap is located near the center of the gate insulating film in the thickness direction. As described above, the minimum thickness of the gate insulating film that can ensure reliability is approximately 8 nm. Therefore, to ensure reliability even when holes are trapped, the film thickness from the trap position to the substrate should be approximately 8 nm, and the film thickness from the trap position to the floating gate should also be approximately 8 nm. For these reasons, when using the data erasure method using SHH, it is preferable that the film thickness of the gate insulating film 8c be 16 nm or more.

[0065] When writing data by hot carrier injection, hot hole injection by DAHH occurs in a region where the gate voltage is close to 0 V. Therefore, even when writing by injecting hot electrons into the floating gate by CHE injection, the hot hole injection by DAHH may not be prevented depending on the potential of the floating gate. Hot holes by DAHH may also be trapped by defects in the gate insulating film.

[0066] From the above, it is preferable that the thickness of the gate insulating film 8a is 16 nm or more even in the program transistor 2a in which data is written by injecting hot electrons into the floating gate FG.

[0067] (1-5-2) Data Erasure Operation Using FN TunnelingIn the above-described embodiment, the case where data is erased by injecting hot holes from the N-type well ENW of the erase capacitor 4a into the floating gate FG by SHH injection has been described, but the present invention is not limited to this.For example, data may be erased by injecting holes from the N-type well ENW of the erase capacitor 4a into the floating gate FG by FN tunneling.

[0068] In the FN tunneling, tunneling current does not flow unless the electric field applied to the gate insulating film exceeds a certain value (for example, 12 MV / cm), so the thicker the gate insulating film, the higher the applied voltage must be. On the other hand, in the case of SHH, the generation of hot holes is determined by the well concentration and the well band slope, so it is less affected by the thickness of the gate insulating film. Therefore, when erasing data by SHH injection, it is not necessary to increase the positive voltage applied to the N-type well ENW even if the thickness of the gate insulating film 8c is thick.

[0069] (1-6) Data Read Operation Next, the data read operation in the memory cell 1a will be described. In the above Table 1, specific examples of voltage combinations (voltage examples) during the data read operation are shown in the "Read" column. When reading data, for example, in the read transistor 3a, the drain RD is set to 0 [V] and further, the source voltage V is set to 5 [V]. ＲＳ is applied to the source RS, and a well voltage Vrw of 5 V is applied to the N-type well RNW. In the program transistor 2a, the source PS and drain PD are opened, and a well voltage Vprw of, for example, 5 V is applied to the N-type well PrNW. In the erase capacitor 4a, the N-type well ENW is opened.

[0070] For example, in a memory cell 1a in which electrons are stored in the floating gate FG (data is written), the threshold voltage (hereinafter also referred to as Vth) of the read transistor 3a is low (the direction in which the gate voltage has a larger absolute value toward the negative voltage side is referred to as "high" and the direction in which the gate voltage has a larger absolute value toward the positive voltage side is referred to as "low"). Therefore, when data is read, the read transistor 3a is turned on, and a large current flows between the source RS and drain RD of the read transistor 3a. On the other hand, in a memory cell 1a in which electrons are not stored in the floating gate FG (data is not written), the Vth of the read transistor 3a is high (the direction in which the gate voltage has a larger absolute value toward the negative voltage side is referred to as "high" and the direction in which the gate voltage has a larger absolute value toward the positive voltage side is referred to as "low"). Therefore, when data is read, the read transistor 3a is turned off, and a small current flows between the source RS and drain RD. This allows data to be read from the memory cell 1a by, for example, detecting the current flowing between the source RS and drain RD of the read transistor 3a.

[0071] (1-7) Functions and Effects The memory cell 1a according to this embodiment includes a program transistor 2a formed in the N-type well PrNW and a read transistor 3a formed in the N-type well RNW. The program transistor 2a is a PMOS transistor having a drain PD which is a P-type diffusion layer formed on the surface of the N-type well PrNW, a source PS which is a P-type diffusion layer formed on the surface of the N-type well PrNW and separated from the drain PD, a gate insulating film 8a provided on the N-type well PrNW between the drain PD and the source PS, and a floating gate FG provided on the gate insulating film 8a.

[0072] The read transistor 3a is a PMOS transistor having a drain RD which is a P-type diffusion layer formed on the surface of the N-type well RNW, a source RS which is a P-type diffusion layer formed on the surface of the N-type well RNW and separated from the drain RD, a gate insulating film 8b provided on the N-type well RNW between the drain RD and the source RS, and a floating gate FG provided on the gate insulating film 8b. The floating gate FG of the program transistor 2a and the floating gate FG of the read transistor 3a are electrically connected.

[0073] The memory cell 1a according to this embodiment has a configuration in which the program transistor 2a is a PMOS transistor and electrons can be injected into the floating gate FG by hot electron injection using CHE. Therefore, even if the thickness of the gate insulating film 8a is increased, charge can be reliably injected into the floating gate FG.

[0074] In addition, in the memory cell 1a, electrons are injected into the floating gate FG by CHE injection, which shortens the data write time compared to write operations using FN tunneling. Also, in the memory cell 1a, by configuring the program transistor 2a as a PMOS transistor, the voltage for hot carrier injection can be lower than when configured as an NMOS transistor, and data can be written at a low voltage.

[0075] Furthermore, the memory cell 1a according to this embodiment is provided with an erase capacitor 4a, and since data can be repeatedly written and erased using the program transistor 2a and the erase capacitor 4a, it can be used as a memory cell of a multi-time programmable memory.

[0076] In the memory cell 1a, the read transistor 3a is provided separately from the program transistor 2a, so that even if data write / erase operations are repeatedly performed and characteristic degradation occurs due to repeated CHE injection in the program transistor 2a, the read transistor 3a does not experience characteristic degradation and can read Vth with high accuracy.

[0077] In addition, in the memory cell 1a, the N-type well PrNW in which the program transistor 2a is formed and the N-type well RNW in which the read transistor 3a is formed are electrically separated, thereby shortening the data write time.

[0078] The erase capacitor 4a is formed in an N-type well ENW electrically isolated from the N-type well PrNW in which the program transistor 2a is formed and the N-type well RNW in which the read transistor 3a is formed. The erase capacitor 4a is a PMOS capacitor having a gate insulating film 8c provided on the N-type well ENW and a floating gate FG provided on the gate insulating film 8c. The floating gate FG of the erase capacitor 4a is electrically connected to the floating gate FG of the program transistor 2a and the floating gate FG of the read transistor 3a.

[0079] In the memory cell 1a according to this embodiment, the erase capacitor 4a is configured as a PMOS capacitor and is configured to inject holes into the floating gate FG by hot hole injection using SHH. This allows holes to be injected into the floating gate FG faster than when using FN tunneling, thereby shortening the erase time. Furthermore, when erasing data using SHH, holes can be injected without increasing the well voltage Vew, even if the gate insulating film 8c of the erase capacitor 4a is thick. Furthermore, erasing data using SHH injection reduces the area a3 where the floating gate FG of the erase capacitor 4a faces the active region AR3, thereby reducing the coupling ratio of the erase capacitor 4a. Reducing the coupling ratio of the erase capacitor 4a reduces the effect of the well voltage Vew on the potential of the floating gate FG, allowing a high well voltage Vew to be applied to the N-type well ENW, thereby efficiently injecting holes into the floating gate FG.

[0080] (1-8) Other Embodiments of the First Embodiment In the first embodiment described above, the memory cell 1a used in a nonvolatile semiconductor memory device that is a multi-time programmable memory has been described, but the present invention is not limited to this. For example, the memory cell may be used in a nonvolatile semiconductor memory device that is a one-time programmable memory. In a memory cell of a one-time programmable memory, the erase capacitor 4a is not required, so the memory cell is configured to include a program transistor 2a and a read transistor 3a.

[0081] Furthermore, even in a memory cell 1a that does not have an erase capacitor 4a, data write and read operations can be performed in the same manner as the above-mentioned "(1-4) Data Write Operation" and "(1-6) Data Read Operation." Specific examples (voltage examples) of voltage combinations in the data write and read operations at this time are also the same as the voltage values ​​shown in Table 1.

[0082] (2) Second embodiment (2-1) Configuration of memory cell according to second embodiment In the first embodiment described above, the memory cell 1a is described in which the N-type well PrNW in which the program transistor 2a is formed and the N-type well RNW in which the read transistor 3a is formed are electrically separated, but the present invention is not limited to this, and the memory cell may have a single N-type well in which the N-type well in which the program transistor is formed and the N-type well in which the read transistor is formed are electrically connected.

[0083] The memory cell according to the second embodiment is characterized in that the N-type well PrNW in which the program transistor 2a is formed and the N-type well RNW in which the read transistor 3a is formed, which are shown in FIG. 1 in the first embodiment described above, are provided as a single electrically connected N-type well. The following description will focus on the configuration that differs from the first embodiment.

[0084] 4, in the memory cell 1b, a program transistor 2b and a read transistor 3b are formed in one N-type well PRNW provided in the substrate PSub. A well voltage line L ＰＲ is connected to the well voltage line L ＰＲ A predetermined voltage is applied via the

[0085] (2-2) Data Write, Erase, and Read Operations Table 2 below shows specific examples (voltage examples) of voltage combinations in the data write, erase, and read operations in memory cell 1b. The voltage values ​​shown in Table 2 are in "V."

[0086] Table 2 differs from Table 1 described in the memory cell 1a according to the first embodiment in that it does not have the columns for N-type well PrNW and N-type well RNW, but has a column for N-type well PRNW. The column for N-type well PRNW in Table 2 specifies the same voltage values ​​as the column for N-type well PrNW in Table 1. In the memory cell 1b, by applying the voltages as shown in Table 2 above, data write, erase, and read operations can be performed in the same way as the memory cell 1b according to the first embodiment described above. Note that the data write, erase, and read operations in the second embodiment are the same as the above-described "(1-4) Data Write Operation," "(1-5) Data Erase Operation," and "(1-6) Data Read Operation," except for the operation of applying different well voltages Vprw and Vrw to the N-type well PrNW and N-type well RNW, and therefore will not be described here.

[0087] (2-3) Actions and Effects In the memory cell 1b according to the second embodiment described above, the program transistor 2b is configured as a PMOS transistor, and electrons can be injected into the floating gate FG by hot electron injection using CHE. Therefore, even if the thickness of the gate insulating film 8a is increased, charge can be reliably injected into the floating gate FG.

[0088] In the memory cell 1b of the second embodiment, the program transistor 2b and the read transistor 3b are formed in one N-type well PRNW, so there is no need to form the P-type well PW1 provided in the first embodiment in the substrate PSub, which simplifies the structure and reduces the area of ​​the memory cell 1b.

[0089] (2-4) Other Embodiments of the Second Embodiment In the second embodiment described above, the memory cell 1b used in a nonvolatile semiconductor memory device that is a multi-time programmable memory has been described, but the present invention is not limited to this. For example, the memory cell may be used in a nonvolatile semiconductor memory device that is a one-time programmable memory. The memory cell of the one-time programmable memory does not require the erase capacitor 4a, so it is configured to consist of a program transistor 2b and a read transistor 3b.

[0090] Furthermore, in the memory cell 1b that does not have the erase capacitor 4a, data write and read operations can be performed in the same manner as "(1-4) Data Write Operation" and "(1-6) Data Read Operation" in the first embodiment described above. Specific examples (voltage examples) of voltage combinations during the data write and read operations at this time are also the same as the voltage values ​​shown in Table 2.

[0091] (3) Third Embodiment (3-1) Configuration of Memory Cell According to Third Embodiment FIG. 5 is a schematic diagram showing a side cross-sectional configuration of a memory cell 1c according to a third embodiment. The memory cell 1c according to the third embodiment is used in a nonvolatile semiconductor memory device that is a multi-time programmable memory. FIG. 6 is a schematic diagram showing an example of a planar layout of the memory cell 1c shown in FIG. 5. Note that FIG. 5 is a schematic diagram showing a side cross-sectional configuration of the memory cell 1c taken along the line CC' in FIG. 6.

[0092] The memory cell 1c has a program transistor 2c, a read transistor 3c, and an erase capacitor 4c provided on a P-type substrate PSub. The memory cell 1c according to the third embodiment differs from the memory cell 1a according to the first embodiment in the configuration of the erase capacitor 4c. Here, a description of the program transistor 2c and read transistor 3c, which have the same configuration as the memory cell 1a according to the first embodiment, will be omitted to avoid redundancy, and the following description will focus on the configuration of the erase capacitor 4c, which is different from that of the first embodiment.

[0093] The erase capacitor 4c is an NMOS capacitor with a diffusion layer, and is formed in a P-type well EPW electrically isolated from the substrate PSub. The P-type well EPW is surrounded by a deep N-type well DNW and an N-type well NW in a triple-well structure, electrically isolating it from the substrate PSub. An N-type diffusion layer ED is formed on the surface of the P-type well EPW. A gate insulating film 8c made of silicon oxide or the like is provided on the P-type well EPW adjacent to the N-type diffusion layer ED. A floating gate FG electrically connected to the floating gates FG of the program transistor 2c and the read transistor 3c is provided on the gate insulating film 8c.

[0094] The N-type diffusion layer ED of the erase capacitor 4c is connected to a diffusion layer voltage line L ＥＤ is connected, and the diffusion layer voltage line L ＥＤ A predetermined voltage is applied to the P-type well EPW in which the erase capacitor 4c is formed through a well voltage line L ＥＰ is connected to the well voltage line L ＥＰ A predetermined voltage is applied to the deep N-type well DNW surrounding the P-type well EPW via a well voltage line L ＥＰ Other well voltage lines L ＥＮ is connected to the other well voltage line L ＥＮ A predetermined voltage is applied via the

[0095] The thickness of the gate insulating film 8c of the erase capacitor 4c (the distance from the surface of the P-type well EPW to the underside of the floating gate FG) is preferably 16 nm or more, more preferably 20 nm or more, and most preferably 30 nm or more. The preferred range of the thickness of the gate insulating film 8c of the erase capacitor 4c will be explained in "(3-3) Data Erasure Operation Using BBHH Injection" below.

[0096] In the substrate PSub, a P-type well PW2 and an N-type well NW are formed between an N-type well RNW in which the read transistor 3c is formed and a P-type well EPW in which the erase capacitor 4c is formed. The P-type well EPW in which the erase capacitor 4c is formed is surrounded by the N-type well NW and a deep N-type well DNW formed below the P-type well EPW, and is electrically isolated from the substrate PSub. The N-type well RNW in which the read transistor 3c is formed and the N-type well NW surrounding the P-type well EPW in which the erase capacitor 4c is formed are electrically isolated by the P-type well PW2.

[0097] An element isolation layer 6 is formed between an active region AR2 on the surface of the N-type well RNW in which the read transistor 3c is formed and an active region AR3 on the surface of the P-type well EPW of the erase capacitor 4c. The active region AR2 of the read transistor 3c and the active region AR3 of the erase capacitor 4c are electrically isolated by the element isolation layer 6.

[0098] 6, in memory cell 1c, one floating gate FG is shared by program transistor 2c, read transistor 3c, and erase capacitor 4c. In memory cell 1c according to this embodiment, program transistor 2c, read transistor 3c, and erase capacitor 4c are linearly arranged. The floating gate FG extends to intersect with active region AR1 of program transistor 2c and active region AR2 of read transistor 3c, and overlaps with part of active region AR3 of erase capacitor 4c.

[0099] The floating gate FG arranged in the active region AR3 of the erase capacitor 4c is formed in a rectangular shape in a plan view, and is formed continuously from the floating gates FG of the program transistor 2c and the read transistor 3c. In this embodiment, the floating gate FG arranged in the active region AR2 of the read transistor 3c extends linearly to the region where the erase capacitor 4c is formed, with the same length in the short direction. In a plan view, an N-type diffusion layer ED is arranged adjacent to the floating gate FG in the direction in which the floating gate FG of the erase capacitor 4c extends. A diffusion layer voltage line L is connected to the N-type diffusion layer ED. ＥＤ A columnar contact 12d is provided to be connected to the

[0100] 6 also shows the area a3 where the floating gate FG arranged in the erase capacitor 4c faces the active region AR3 of the erase capacitor 4c. In the third embodiment, the area a3 where the floating gate FG of the erase capacitor 4c faces the active region AR3 is preferably 20% or less, and more preferably 10% or less, of the total area (area a1 + area a2 + area a3) obtained by adding together the area a1 where the floating gate FG of the program transistor 2c faces the active region AR1, the area a2 where the floating gate FG of the read transistor 3c faces the active region AR2, and the area a3 where the floating gate FG of the erase capacitor 4c faces the active region AR3. By setting the area a3 to 20% or less of the total area (area a1 + area a2 + area a3), the coupling ratio of the erase capacitor 4c can be reduced, and it is possible to prevent the potential of the floating gate FG from being affected during a data write operation or a data erase operation. By setting the area a3 to 10% or less of the total area (area a1 + area a2 + area a3), it is possible to further reduce the coupling ratio of the erase capacitor 4c, and it is possible to further prevent the potential of the floating gate FG from being affected during a data write operation or a data erase operation.

[0101] Note that the memory cell 1c can also be fabricated by performing the film formation process, photolithography process, etching process, impurity injection process, etc., which are typical manufacturing processes for PMOS transistors, and therefore the manufacturing method thereof will not be described here. Also, in the third embodiment, the explanations regarding the "principle of the data write operation in a memory cell" and the "configuration in which a read transistor is provided separately from a program transistor" are the same as those in the first embodiment described above, and therefore will not be repeated here.

[0102] (3-2) Data Write Operation Next, specific examples of voltage combinations (voltage examples) during a data write operation using CHE injection in memory cell 1c are shown in the "Write" column of Table 3 below. The voltage values ​​shown in Table 3 are in "V."

[0103] The voltages applied to each part of the program transistor 2c and the read transistor 3c during a data write operation are the same as those in the first embodiment. During a data write operation, the erase capacitor 4c opens, for example, the N-type diffusion layer ED, the P-type well EPW, and the deep N-type well DNW. Here, the larger the area of ​​the active region facing the floating gate FG, the greater the effect of the well voltage on the potential of the floating gate FG due to capacitive coupling. In the erase capacitor 4c, the area a3 where the floating gate FG faces the active region AR3 is 20% or less of the total area (area a1 + area a2 + area a3), so that the effect of the well voltage Vew of the P-type well EPW on the potential of the floating gate FG due to capacitive coupling can be reduced.

[0104] (3-3) Data Erasing Operation Using BBHH Injection Next, a data erasing operation in the memory cell 1c will be described. Unlike the first embodiment, the memory cell 1c according to the third embodiment erases data by injecting hot holes into the floating gate FG using BBHH (Band-to-Band Tunneling induced Hot Hole injection) injection.

[0105] In an NMOS transistor, when a positive high voltage is applied to the drain and a negative high voltage is applied to the gate, holes are accelerated from the drain toward the well, and the energy of the holes allows them to cross the barrier of the gate insulating film and be injected into the gate. This phenomenon is known as the BBHH phenomenon (see, "A New Observation of Band-to-Band Tunneling Induced Hot-Carrier Stress Using Charge-Pumping Technique," IEEE Electron Device Letters, vol. 21, No. 3, pp. 123 (2000)). Hole injection using the BBHH phenomenon (BBHH injection) can inject holes into the floating gate FG faster than FN tunneling. Furthermore, BBHH injection can reduce the area a3 where the floating gate FG of the erase capacitor 4c and the active region AR3 face each other. Furthermore, holes can be injected into the floating gate FG without applying a high voltage of 40 V or more to the well of the erase capacitor 4c, as in the SHH injection of the first embodiment.

[0106] In Table 3 above, the "Erase" column shows specific examples (voltage examples) of voltage combinations during the data erase operation by BBHH injection. In this case, as in the first embodiment described above, in the program transistor 2a, the source PS and drain PD are open, and the N-type well PrNW is set to 0 [V]. In the read transistor 3a, the source RS and drain RD are open, and the N-type well RNW is set to 0 [V]. In addition, the substrate PSub is set to 0 [V].

[0107] In the erase capacitor 4c, for example, a diffusion layer voltage V of 14 [V] is applied to the N-type diffusion layer ED. ＥＤ is applied to the deep N-type well DNW, and a well voltage Vew of 7 [V] is applied to the P-type well EPW. A well voltage Venw that satisfies the condition for applying a forward bias to the junction between the deep N-type well DNW and the P-type well EPW may be applied to the deep N-type well DNW, and a well voltage Venw of, for example, 8 [V] may be applied.

[0108] As described above, the larger the area of ​​the active region facing the floating gate FG, the greater the effect of the well voltage on the potential of the floating gate FG due to capacitive coupling. In the memory cell 1c according to this embodiment, the area a3 where the floating gate FG of the erase capacitor 4c faces the active region AR3 is smaller than the total area (area a1 + area a2 + area a3) of the area a1 where the floating gate FG of the program transistor 2c faces the active region AR1, the area a2 where the floating gate FG of the read transistor 3c faces the active region AR2, and the area a3 of the active region AR3 facing the floating gate FG of the erase capacitor 4c, and the coupling ratio expressed as area a3 / (area a1 + area a2 + area a3) is small (for example, 10% or less). Therefore, in this embodiment, even if a high well voltage Vew of 7 V is applied to the active region AR3 of the erase capacitor 4 a, which has a small area a3 facing the floating gate FG, the high voltage is unlikely to affect the floating gate FG.

[0109] Furthermore, in memory cell 1c, the coupling ratio of program transistor 2c (area a1 / (area a1+area a2+area a3)) and the coupling ratio of read transistor 3c (area a2 / (area a1+area a2+area a3)) are large, so by setting the well voltage Vprw and the well voltage Vrw to 0 [V] during the erase operation, the potential of floating gate FG can be adjusted so that it does not float relative to 0 [V].

[0110] Therefore, a diffusion layer voltage V of 14 [V] is applied to the N-type diffusion layer ED. ＥＤ is applied to the N-type diffusion layer ED, a well voltage Vew of 7 [V] is applied to the P-type well EPW, and the potential of the floating gate FG is adjusted so that it does not float relative to 0 [V]. Considering the potential of the P-type well EPW as a reference, a positive high voltage of 7 [V] is applied to the N-type diffusion layer ED, and a negative high voltage of -7 [V] is applied to the floating gate FG, and holes can be injected into the floating gate FG by BBHH injection. The BBHH phenomenon occurs when the erase capacitor 4c is turned on by applying a positive high voltage of 7 [V] to the N-type diffusion layer ED and a negative high voltage of -7 [V] to the floating gate FG. ＥＤThis is caused by the bias conditions of magnitude relationship: > well voltage Vew of P-type well EPW > voltage of floating gate FG.

[0111] When BBHH injection is used as a data erasing method, similar to the case of using SHH injection in the first embodiment, high-energy hot holes are injected into the floating gate by overcoming the energy barrier of the gate insulating film, but this energy may cause defects in the gate insulating film, and holes may be trapped in these defects.

[0112] In the third embodiment, as described above, the minimum thickness of the gate insulating film that can ensure reliability is about 8 nm according to Publicly Known Documents 1 and 2, so in order to ensure reliability even when holes are trapped, it is sufficient that the film thickness from the trap position to the substrate is about 8 nm, and the film thickness from the trap position to the floating gate is also about 8 nm. For these reasons, even when using the data erasing method using BBHH, it is preferable that the film thickness of the gate insulating film 8c is 16 nm or more.

[0113] (3-4) Data Read Operation As shown in Table 3 above, the voltages applied to each part of the program transistor 2c and the read transistor 3c during a data read operation in the third embodiment are the same as those in the first embodiment. In the erase capacitor 4c, the N-type diffusion layer ED, the P-type well EPW, and the deep N-type well DNW are open. As a result, in the memory cell 1c as in the first embodiment, data can be read by detecting, for example, the current flowing between the source RS and drain RD of the read transistor 3c.

[0114] (3-5) Functions and Effects The memory cell 1c according to the third embodiment also has a configuration in which electrons can be injected into the floating gate FG by hot electron injection using CHE, and thus can achieve the same effects as those of the first embodiment. In addition, in the memory cell 1c according to the third embodiment, the erase capacitor 4a is formed in a P-type well EPW electrically isolated from the substrate PSub by a triple-well structure. The erase capacitor 4c is an NMOS capacitor with a diffusion layer, having an N-type diffusion layer ED formed on the surface of the P-type well EPW, a gate insulating film 8c formed on the P-type well EPW adjacent to the N-type diffusion layer ED, and a floating gate FG formed on the gate insulating film 8c. The floating gate FG of the erase capacitor 4c is electrically connected to the floating gate FG of the program transistor 2c and the floating gate FG of the read transistor 3c.

[0115] As described above, the memory cell 1c according to the third embodiment has an erase capacitor 4c configured as an NMOS capacitor with a diffusion layer, and has a configuration in which holes can be injected into the floating gate FG by hot hole injection using BBHH, so holes can be injected into the floating gate FG faster than when using FN tunneling, thereby shortening the erase time. Furthermore, when erasing data using BBHH, holes can be injected without increasing the well voltage Vew even if the thickness of the gate insulating film 8c of the erase capacitor 4c is thick.

[0116] Furthermore, by configuring the erase capacitor 4c as an NMOS capacitor with a diffusion layer and erasing data using BBHH injection, holes can be injected into the floating gate FG without applying a high voltage of 40 V or more to the well, making it possible to erase at a low voltage, compared to when configuring the erase capacitor as a PMOS capacitor and erasing data using SHH injection. The area a3 where the floating gate FG of the erase capacitor 4c faces the active region AR3 can be reduced, making it possible to reduce the coupling ratio of the erase capacitor 4c. By reducing the coupling ratio of the erase capacitor 4c, the potential of the floating gate FG is adjusted so that it does not float relative to 0 V, and the diffusion layer voltage V ＥＤ > Well voltage V of P-type well EPW > Voltage V of floating gate FG ＦＧ By setting the bias conditions such that the magnitude relationship is satisfied, the BBHH phenomenon occurs, and holes can be efficiently injected into the floating gate FG.

[0117] (4) The memory cells 1a to 1c according to the first to third embodiments may be used in a nonvolatile semiconductor memory device having circuits that operate at a plurality of different power supply voltages. When the nonvolatile semiconductor memory device has a circuit that operates at a low power supply voltage and has a gate insulating film thickness of less than 16 nm and a circuit that operates at a high power supply voltage and has a gate insulating film thickness of 16 nm or more, the memory cells 1a to 1c are used in the circuit that has a gate insulating film thickness of 16 nm or more.

[0118] 1a, 1b, 1c Memory cell 2a, 2b, 2c Program transistor 3a, 3b, 3c Read transistor 4a, 4c Erase capacitor 8a, 8b, 8c Gate insulating film ED N-type diffusion layer EPW P-type well DNW Deep N-type well FG Floating gate PrNW, RNW, ENW, PRNW N-type well PS, RS Source PD, RD Drain

Claims

1. A memory cell of a nonvolatile semiconductor memory device, comprising: a program transistor; and a read transistor; the program transistor is formed in an N-type well, and has a drain which is a P-type diffusion layer formed on the surface of the N-type well, a source which is a P-type diffusion layer formed on the surface of the N-type well and separated from the drain, a gate insulating film provided on the N-type well between the drain and the source, and a floating gate provided on the gate insulating film; the read transistor is formed in an N-type well, and has a drain which is a P-type diffusion layer formed on the surface of the N-type well, a source which is a P-type diffusion layer formed on the surface of the N-type well and separated from the drain, a gate insulating film provided on the N-type well between the drain and the source, and a floating gate provided on the gate insulating film; the floating gate of the program transistor and the floating gate of the read transistor are electrically connected.

2. The memory cell according to claim 1, wherein the thickness of the gate insulating film of the program transistor and the gate insulating film of the read transistor is 16 nm or more.

3. The memory cell according to claim 1, wherein the effective gate length of the floating gate of said program transistor is smaller than the effective gate length of the floating gate of said read transistor.

4. The memory cell according to claim 1, wherein the threshold voltage of said program transistor is a voltage on the positive voltage side relative to the threshold voltage of said read transistor.

5. The memory cell according to claim 1, wherein the N-type well in which the program transistor is formed and the N-type well in which the read transistor is formed are electrically connected to each other to form a single N-type well.

6. The memory cell according to claim 1, wherein the N-type well in which the program transistor is formed and the N-type well in which the read transistor is formed are electrically isolated from each other.

7. The memory cell according to claim 1, wherein the area of ​​the active region of said read transistor facing said floating gate of said read transistor is larger than the area of ​​the active region of said program transistor facing said floating gate of said program transistor.

8. The memory cell according to any one of claims 1 to 7, further comprising an erase capacitor, the erase capacitor being formed in an N-type well electrically isolated from the N-type well in which the program transistor is formed and the N-type well in which the read transistor is formed, and having a gate insulating film provided on the N-type well and a floating gate provided on the gate insulating film, the floating gate of the erase capacitor being electrically connected to the floating gate of the program transistor and the floating gate of the read transistor.

9. The memory cell according to claim 8, wherein the area of ​​the active region of the erase capacitor facing the floating gate of the erase capacitor is 10% or less of the total area of ​​the active region of the program transistor facing the floating gate of the program transistor, the active region of the read transistor facing the floating gate of the read transistor, and the active region of the erase capacitor facing the floating gate of the erase capacitor.

10. The memory cell of claim 8, wherein the active area of ​​said erase capacitor is covered by said floating gate.

11. The memory cell according to claim 6, further comprising an erase capacitor formed in a P-type well, the erase capacitor having an N-type diffusion layer formed on the surface of the P-type well, a gate insulating film provided on the P-type well adjacent to the N-type diffusion layer, and a floating gate provided on the gate insulating film, the floating gate of the erase capacitor being electrically connected to the floating gate of the program transistor and the floating gate of the read transistor.

12. The memory cell according to claim 11, wherein the thickness of the gate insulating film of the program transistor, the gate insulating film of the read transistor, and the gate insulating film of the erase capacitor is 16 nm or more.

13. The memory cell according to claim 11, wherein the area of ​​the active region of the erase capacitor facing the floating gate of the erase capacitor is 20% or less of the total area of ​​the active region of the program transistor facing the floating gate of the program transistor, the active region of the read transistor facing the floating gate of the read transistor, and the active region of the erase capacitor facing the floating gate of the erase capacitor.

14. The erase capacitor is configured to apply a voltage V to the N-type diffusion layer during an erase operation. ＥＤ , a well voltage V applied to the P-type well, and a voltage V of the floating gate. ＦＧ But, V ＥＤ >Vew>V ＦＧ The memory cell of claim 11 , wherein the memory cell satisfies a bias condition of:

15. The memory cell according to any one of claims 1 to 7, wherein the nonvolatile semiconductor memory device is a multi-time programmable memory.

16. The memory cell according to any one of claims 1 to 7, wherein the nonvolatile semiconductor memory device is a one-time programmable memory.

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