Systems and methods for component based on-chip buffering

Abstract

Methods, systems, and apparatus for selecting buffering components for conduction paths in integrated circuits. One of the methods includes selecting a set of buffering components from a list of buffering components that have equal wire lengths but different driving strength values. An updated list of buffering components can be generated by removing those buffering components that have at least one time delay value that is greater than a threshold value. An ordered set of buffering components can be selected form the updated list based at least on the distance between two node locations on the integrated circuit design. In some instances, the list can be extended by adding buffering components with wire length values between wire length values of two buffering components in the list.

Description

[0001] SYSTEMS AND METHODS FOR COMPONENT BASED ON-CHIP BUFFERING

[0002] TECHNICAL FIELD

[0003] This specification relates to integrated circuit design, and more particularly to determining buffering components for placement between two nodes in the integrated circuit.

[0004] BACKGROUND

[0005] Integrated circuits can include multiple electrical devices and components. These devices and components include electrical nodes, which can be connected with interconnects that are formed using a combination of metal layers. For nodes with large distances therebetween, the interconnects connecting them can have large resistances and capacitances, which can degrade the signal transmission. In such instances, one or more buffer components can be utilized that boost the signal on the interconnects between the nodes.

[0006] SUMMARY

[0007] This specification describes techniques for selecting buffering components for placement between two nodes in an integrated circuit design. In particular, the specification describes techniques for selecting buffering components based on a list of buffering components, where the list is modified by removing buffering components that may be sub- optimal. In some implementations, the techniques include selecting buffering components from the list a set of buffering components that have equal wire lengths but different driving strengths. The list is updated by removing from the list those buffering components that have a time delay value that is greater than a threshold value. By removing these buffering components, the updated list excludes buffering components that have long time delays for given wire lengths. An electronic design tool, based on the updated list and a given distance between the two nodes, can select an ordered set of buffering components for placement between the two nodes.

[0008] The specification also describes techniques for modifying a list of buffering components by adding additional buffering components that have different wire lengths to that included in the list. In particular, an additional list of buffering components can be generated where the buffering components have wire lengths that are between two different wire lengths of a pair of buffering components in the list. In some examples, one or more of the buffering components in the additional list can be generated using transistor level

[0009] I simulation tools to provide accurate timing information. The additional list of buffering components can be combined with the list of buffering components to form an extended list of buffering components. An electronic design tool, based on the extended list of buffering components and a given distance between the two nodes, can select an ordered set of buffering components for placement between the two nodes.

[0010] Particular examples of the subject matter described in this specification can be implemented so as to realize one or more of the following advantages. Performance of electronic design automation tools such as electronic design tools can be improved by reducing the size of the list of buffering components. In traditional approaches, the list of buffering components can be very large, and can impact the processing performance of electronic design tools that use the list to determine buffering solutions for interconnects on integrated circuits. By reducing the size of the list of buffering components, the processing performance of the electronic design tools can be improved. Further, sub-optimal buffering components are removed from the list. This reduces the risk of sub-optimal buffering components from being selected by the electronic design tool and improves the quality and performance of the integrated circuit.

[0011] In some implementations, the techniques include adding additional buffering components to the list, which can enhance the resolution of wire lengths available for section by the electronic design tool without undue time overhead. In particular, the buffering components added to the list can include wire lengths that are smaller than those already in the list. This can allow the electronic design tool to select buffering components from a wider range, or a higher resolution, of wire lengths the sum of wire lengths of which more accurately reflect the desired length of the conduction path between the two nodes. While the buffering components in the list can be determined based on actual transistor level data, the added buffering components can be determined based on the techniques described herein, such as interpolation. Generating actual transistor level data can take substantially longer than interpolation. Therefore, the resolution of the buffering components in the list can be improved without a large time and resource overhead. Moreover, in some instances, transistor level data for very fine resolutions of wire lengths may not be available, but can be easily generated using interpolation or other simulation techniques. Traditional approaches typically utilize transistor level data from previous designs to generate buffering component data. But if the previous designs do not include buffering components with the desired wire lengths, then the transistor level data would have to be simulated, which can be costly in terms resources and time. By utilizing the techniques discussed herein, such as, for example. interpolation, the list can be improved with buffering components having fine resolution wire lengths without a large time and resource overhead.

[0012] One or more of the techniques discussed herein can improve the performance of the integrated circuit design by including buffering components with improved delay compared to those designed using traditional techniques. The updated lists of buffering components can provide an electronic design tool with buffering components with optimal delays for given wire lengths and driving strengths to select from. In one aspect, the disclosure relates to a method for determining buffering components for placement between two nodes on an integrated circuit design, including: generating a list of buffering components, each buffering component, in the list of buffering components, having a driving strength value indicating a power output of the buffering component, a wire length indicating a length of an interconnect connected with the buffering component, and at least one time delay indicating signal transmission delay through the buffering component; selecting a set of buffering components, from the list of buffering components, that have equal wire lengths but different driving strength values; generating an updated list of buffering components by removing, from the list of buffering components, those buffering components from the set of buffering components that have at least one time delay value that is greater than a threshold value; receiving a first node location and a second node location on the integrated circuit design; and determining, based at least on the updated list of buffering components and an estimated distance on the integrated circuit design between the first node location and the second node location, an ordered set of buffering components for placement between the first node location and the second node location on the integrated circuit design.

[0013] In some aspects, generating the updated list of buffering components includes adding buffering components by interpolation. In some aspects, the at least one time delay is a mean delay. In some aspects, at least two buffering components in the ordered set of buffering components have different wire lengths. In some aspects, generating the list of buffering components includes determining the at least one time delay of each of the buffering components in the list of buffering components based on transistor level simulation.

[0014] In some aspects, the estimated distance on the integrated circuit design between the first node location and the second node location is at least 300 micrometers. In some aspects, a sum of wire lengths of the ordered set of buffering components is equal to the estimated distance on the integrated circuit between the first node location and the second node location. In some aspects, the method further includes determining the ordered set of buffering components based additionally on circuit conditions such as power, voltage, and temperature.

[0015] In another aspect, the disclosure relates to a method for determining buffering components for placement between two nodes on an integrated circuit design, including selecting, from a first list of buffering components, two buffering components having two different wire lengths, wherein each buffering component in the first list of buffering components having a driving strength value indicating a power output of the buffering component, a wire length indicating a length of an interconnect connected with the buffering component, and at least one time delay indicating signal transmission delay through the buffering component; generating a second list of buffering components, each buffering component in the second list of buffering components having wire lengths that are between the two different wire lengths of the selected two buffering components; generating an extended list of buffering components based on adding the second list of buffering components to the first list of buffering components; receiving a first node location and a second node location on the integrated circuit design; and determining, based at least on the extended list of buffering components and an estimated distance on the integrated circuit design between the first node location and the second node location, an ordered set of buffering components for placement between the first node location and the second node location on the integrated circuit design.

[0016] In some aspects, the method further includes selecting a set of buffering components, from the extended list of buffering components, that have equal wire lengths but different drive strength values; and removing, form the extended list of buffering components, those buffering components from the set of buffering components that have at least one time delay value that is greater than a threshold value.

[0017] In some aspects, at least two buffering components in the ordered set of buffering components have different wire lengths. In some aspects, generating the extended list of buffering components includes determining the at least one time delay of each of the buffering components in the extended list of buffering components based on transistor level simulation. In some aspects, the estimate distance on the integrated circuit design between the first node location and the second node location is at least 300 micrometers. In some aspects, wire lengths of the buffering components in the second list of buffering components are separated by a wire length step.

[0018] In another aspect, the disclosure relates to one or more non-transitory computer- readable storage media storing instructions that when executed by one or more processors cause the one or more processors to perform operations for determining buffering components for placement between two nodes on an integrated circuit design, the operations including: generating a list of buffering components, each buffering component, in the list of buffering components, having a driving strength value indicating a power output of the buffering component, a wire length indicating a length of an interconnect connected with the buffering component, and at least one time delay indicating signal transmission delay through the buffering component; selecting a set of buffering components, from the list of buffering components, that have equal wire lengths but different driving strength values; generating an updated list of buffering components by removing, from the list of buffering components, those buffering components from the set of buffering components that have at least one time delay value that is greater than a threshold value; receiving a first node location and a second node location on the integrated circuit design; and determining, based at least on the updated list of buffering components and an estimated distance on the integrated circuit design between the first node location and the second node location, an ordered set of buffering components for placement between the first node location and the second node location on the integrated circuit design.

[0019] In some aspects, generating the updated list of buffering components includes adding buffering components by interpolation. In some aspects, the at least one time delay is a mean delay. In some aspects, at least two buffering components in the ordered set of buffering components have different wire lengths. In some aspects, generating the list of buffering components includes determining the at least one time delay of each of the buffering components in the list of buffering components based on transistor level simulation. In some aspects, the estimated distance on the integrated circuit design between the first node location and the second node location is at least 300 micrometers. In some aspects, a sum of wire lengths of the ordered set of buffering components is equal to the estimated distance on the integrated circuit between the first node location and the second node location. In some aspects, the operations further include determining the ordered set of buffering components based additionally on circuit conditions such as power, voltage, and temperature.

[0020] In another aspect, the disclosure is related to one or more non-transitory computer- readable storage media storing instructions that when executed by one or more processors cause the one or more processors to perform operations for determining buffering components for placement between two nodes on an integrated circuit design, the operations including: selecting, from a first list of buffering components, two buffering components having two different wire lengths, wherein each buffering component in the first list of buffering components having a driving strength value indicating a power output of the buffering component, a wire length indicating a length of an interconnect connected with the buffering component, and at least one time delay indicating signal transmission delay through the buffering component; generating a second list of buffering components, each buffering component in the second list of buffering components having wire lengths that are between the two different wire lengths of the selected two buffering components; generating an extended list of buffering components based on adding the second list of buffering components to the first list of buffering components; receiving a first node location and a second node location on the integrated circuit design; and determining, based at least on the extended list of buffering components and an estimated distance on the integrated circuit design between the first node location and the second node location, an ordered set of buffering components for placement between the first node location and the second node location on the integrated circuit design.

[0021] In some aspects, the operations further include selecting a set of buffering components, from the extended list of buffering components, that have equal wire lengths but different drive strength values; and removing, form the extended list of buffering components, those buffering components from the set of buffering components that have at least one time delay value that is greater than a threshold value. In some aspects, at least two buffering components in the ordered set of buffering components have different wire lengths. In some aspects, generating the extended list of buffering components includes determining the at least one time delay of each of the buffering components in the extended list of buffering components based on transistor level simulation. In some aspects, the estimate distance on the integrated circuit design between the first node location and the second node location is at least 300 micrometers. In some aspects, wire lengths of the buffering components in the second list of buffering components are separated by a wire length step.

[0022] In another aspect, the disclosure relates to a system, including one or more processors; and one or more storage devices storing instructions that when executed by the one or more processors to perform operations for determining buffering components for placement between two nodes on an integrated circuit design, the operations including: generating a list of buffering components, each buffering component, in the list of buffering components, having a driving strength value indicating a power output of the buffering component, a wire length indicating a length of an interconnect connected with the buffering component, and at least one time delay indicating signal transmission delay through the buffering component; selecting a set of buffering components, from the list of buffering components, that have equal wire lengths but different driving strength values; generating an updated list of buffering components by removing, from the list of buffering components, those buffering components from the set of buffering components that have at least one time delay value that is greater than a threshold value; receiving a first node location and a second node location on the integrated circuit design; and determining, based at least on the updated list of buffering components and an estimated distance on the integrated circuit design between the first node location and the second node location, an ordered set of buffering components for placement between the first node location and the second node location on the integrated circuit design.

[0023] In some aspects, generating the updated list of buffering components includes adding buffering components by interpolation. In some aspects, the at least one time delay is a mean delay. In some aspects, at least two buffering components in the ordered set of buffering components have different wire lengths. In some aspects, generating the list of buffering components includes determining the at least one time delay of each of the buffering components in the list of buffering components based on transistor level simulation. In some aspects, the estimated distance on the integrated circuit design between the first node location and the second node location is at least 300 micrometers. In some aspects, a sum of wire lengths of the ordered set of buffering components is equal to the estimated distance on the integrated circuit between the first node location and the second node location. In some aspects, the operations further including: determining the ordered set of buffering components based additionally on circuit conditions such as power, voltage, and temperature.

[0024] In another aspect, the disclosure is related to a system, including: one or more processors; and one or more storage devices storing instructions that when executed by the one or more processors to perform operations for determining buffering components for placement between two nodes on an integrated circuit design, the operations including: selecting, from a first list of buffering components, two buffering components having two different wire lengths, wherein each buffering component in the first list of buffering components having a driving strength value indicating a power output of the buffering component, a wire length indicating a length of an interconnect connected with the buffering component, and at least one time delay indicating signal transmission delay through the buffering component; generating a second list of buffering components, each buffering component in the second list of buffering components having wire lengths that are between the two different wire lengths of the selected two buffering components; generating an extended list of buffering components based on adding the second list of buffering components to the first list of buffering components; receiving a first node location and a second node location on the integrated circuit design; and determining, based at least on the extended list of buffering components and an estimated distance on the integrated circuit design between the first node location and the second node location, an ordered set of buffering components for placement between the first node location and the second node location on the integrated circuit design.

[0025] In some aspects, the operations further including: selecting a set of buffering components, from the extended list of buffering components, that have equal wire lengths but different drive strength values; and removing, form the extended list of buffering components, those buffering components from the set of buffering components that have at least one time delay value that is greater than a threshold value. In some aspects, at least two buffering components in the ordered set of buffering components have different wire lengths. In some aspects, generating the extended list of buffering components includes determining the at least one time delay of each of the buffering components in the extended list of buffering components based on transistor level simulation. In some aspects, the estimate distance on the integrated circuit design between the first node location and the second node location is at least 300 micrometers. In some aspects, wire lengths of the buffering components in the second list of buffering components are separated by a wire length step

[0026] Other implementations of this and other aspects include corresponding systems, apparatus, and computer programs, configured to perform the actions of the methods, encoded on computer storage devices. A system of one or more computers can be so configured by virtue of software, firmware, hardware, or a combination of them installed on the system that in operation causes the system to perform the actions. One or more computer programs can be so configured by virtue of having instructions that, when executed by a data processing apparatus, cause the apparatus to perform the actions.

[0027] The details of one or more embodiments of the subject matter of this specification are set forth in the accompanying drawings and the description below. Other features, aspects, and advantages of the subject matter will become apparent from the description, the drawings, and the claims.

[0028] BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 is a block diagram of a portion of an example integrated circuit design.

[0030] Figure 2 shows an example list of buffering components and an example structure of a buffering component. Figure 3 shows a flow diagram of an example process for removing one or more sub- optimal buffering components from a list of buffering components.

[0031] Figure 4 shows an example technique for generating an updated list of buffering components.

[0032] Figure 5 shows an example ordered set of buffering components selected by the electronic design tool.

[0033] Figure 6 shows a flow diagram of an example process for generating an extended list of buffering components and selecting buffering components based on the extended list.

[0034] Figure 7 shows an example technique for generating an expanded list of buffering components.

[0035] Figure 8 is a diagram illustrating an example of a computing system.

[0036] Like reference numbers and designations in the various drawings indicate like elements.

[0037] DETAILED DESCRIPTION

[0038] Figure 1 is a block diagram of a portion of an example integrated circuit design 100. The integrated circuit design 100 includes a first electronic device 102 and a second electronic device 104. The first electronic device 102 and the second electronic device 104 can include semiconductor devices such as, for example, transistors, diodes, resistors, etc. The first electronic device 102 includes a first node location 106 and the second electronic device 104 includes a second node location 108. The first node location 106 and the second node location 108 can be locations on an interconnect or a terminal of a device within the respective electronic device. The first node location 106 and the second node location 108 can in some examples be connected by one or more interconnects. For example, some integrated circuits include multiple metal layers that can be patterned to form interconnects. In the example shown in Figure 1, the integrated circuit includes three metal layers, a first metal layer 110, a second metal layer 112, and a third metal layer 114. These metal layers can be patterned to form an electrical connection between the first node location 106 and the second node location 108. For example, an electrical conduction path can be formed by one or more segments of the first metal layer 110, one or more segments of the second metal layer 112, and one or more segments of the third metal layer 114. As shown in the cross-sectional view, vias can connect segments in one metal layer to segments in other metal layers to form a conductive path betw een the first node location 106 and the second node location 108. Long conductive paths between the first node location 106 and the second node location 108 can cause degradation of signals between the two nodes. For example, each of the segments of the metal layers that form the conductive path between the two nodes have resistance and capacitance associated with them. For long conductive paths such as, for example, greater than 300 pm, the signal degradation can be severe enough to fall outside of the noise margins of the components coupled with the two nodes. For example, signal transmitted from the first node location 106 may get degraded to an extent that it may be difficult to distinguish the signal between a logical ‘0’ and a logical ‘ 1’. The long conduction path can also introduce undesirable propagation delays, which can degrade the integrated circuit performance and / or synchronization.

[0039] One approach to mitigating the signal degradation over long conduction paths can include introducing buffers along the conduction paths. These buffers can boost the signal strength but can add propagation delays to the signals. Electronic design tools can be used in selecting buffer components for placement on the conduction path. However, the electronic design tools may provide sub-optimal solutions. For example, in some instances, the electronic design tools may not take into consideration a driving strength of buffering components and may provide a solution that inserts the same buffer components at equal wire lengths along the conduction path. Such a solution, while providing some mitigation to signal degradation, may introduce undesired propagation delay. Furthermore, the electronic design tools may rely on lists or databases of buffering components from which buffering components for placement along the conduction path can be selected. These lists or databases may be too large and can therefore result in long runtimes for the electronic design tool to select the appropriate buffering components. In addition, the lists of databases may include sub-optimal buffering components, the selection of which can result in undesired delay in the conduction path. The techniques discussed herein provide solutions to one or more of the above discussed problems associated with introducing buffering components in integrated circuit designs.

[0040] Electronic design tools can receive the first node location 106 and the second node location 108. among other inputs, to determine a set of buffering components that can be placed along the conduction path betw een the first node location 106 and the second node location 108.

[0041] Figure 2 shows an example list of buffering components 200 and an example structure of a buffering component 202. The list of buffering components 200 includes N buffering components. The example buffering component 202 can include a buffer 204 (labeled as “Stage TV”) and a wire 206. The buffer 204 can be an inverter or a plurality of inverters. In some examples, the buffer 204 can include an even number of inverters such that the output of the buffering component is same as the input to the buffering component. In some examples, the buffer 204 can include an odd number of inverters such that the output of the buffering component is an inverted form of the input of the buffering component. The buffer 204 can have an associated driving strength. Generally, the driving strength can indicate the power output of the buffering component and can particularly indicate the power output of the buffer 204. For example, the driving strength of the buffer 204 can be expressed in terms of the power output of the buffer 204, e.g., V x I, where V and I are the output voltage and current, respectively, of the buffer 204. In some examples, in particular where the output voltage is constant across the buffers, the driving strength of the buffer 204 may be expressed in terms of the output current. In yet other examples, the driving strength can be expressed in terms of multiples of the driving strength of a unit buffer. For example, if the driving strength of the unit buffer is DI, then the driving strength of other buffers can be expressed as multiples of DI such as, for example, D4 or DI 6. In some instances, the driving strength can be expressed in terms of an integer multiple of DI. In some other instance, the driving strength can be expressed in terms of a rational number multiple of the driving strength DI of the unit buffer (e.g., DI.5, D12.2, etc.).

[0042] The wire 206 can correspond to a length of a conductor or interconnect coupled with the output of the buffer 204. In the example shown in Figure 2. the wire 206 can be represented by a resistance-capacitance (RC) model. However, the wire 206 could be represented differently such as, for example, based on a resistance-inductance-capacitance (RLC) model, or other models. In some examples, the foundry where the integrated circuit is to be fabricated can provide a value for resistance per unit pm or a value for the capacitance per unit pm, both of which can be used for the representation RC model. In some instances, the values can be integrated into an Elmore delay RC model, however, other models can also be used. In some instances, the model representing the wire 206 can take into account the metal layer on which the wire 206 is formed as different metal layers may have different sheet resistances and unit capacitances.

[0043] Each buffering component 202 may be preceded by a previous stage buffer 208 and may be followed by a next stage buffer 210. For example, in instances where a set of buffering components are positioned in series over a conduction path, the previous stage buffer 208 can be the buffer of the buffering component of the previous stage in the set of buffering components. Similarly, the next stage buffer 210 can be the buffer of the next stage of buffering component in the set of buffering components. While Figure 2 shows inverters for the previous stage buffer 208 and the next stage buffer 210, it should be noted that any of the previous or next stages can include non-inverting buffers.

[0044] A propagation delay of the buffering component 202 can be viewed as the propagation delay between the input of the buffer 204 and the output of the buffering component 202 at the end of the wire 206 that is opposite to the end of the wire coupled with the output of the buffer 204. The propagation delay can be measured, for example, as the time lapse between a position on a rising or falling edge of a signal at the input of the buffer 204 (the input of the buffering component 202) and a similar position on the rising or falling edge of the signal at the output of the wire 206 (the output of the buffering component 202).

[0045] The list of buffering component 200 can include values for various parameters associated with the buffering components. For example, the list can include columns associated with a driving strength of a previous stage buffer, (Stage N-l), driving strength of the current buffering component (Stage N), a routing layer on which the wire is formed (Routing layer), a wire length of the wire 206 (Wire Length), driving strength of the next stage (Stage N+l), a mean delay indicating a mean value of all delays measured or simulated for the buffering component (Delay Mean), and a variance measurement that indicates the variance in the delay values around the mean (Delay Sigma). The mean delay and variance can indicate the signal transmission delay through the buffering component. The driving strength in the list of buffering component 200 is indicated by “INVDx7’ where "x“ can be a real number. For example, some of the buffering components have a driving strength of INDV1, while some other buffering components have a driving strength of INVD16. A higher number for “x” in “INVDx” indicates a higher driving strength. While the list of buffering components 200 shows only three different values of driving strength, it should be noted that driving strength may have other values as well.

[0046] The list of buffering components 200 includes buffering components with various values of wire lengths. For example, the list includes wire lengths of 10, 50, and 100 pm. These wire lengths are only example values, and buffering components with other wire lengths may also be included.

[0047] Electronic design tools can receive as input the total wire length between the first node location 106 and the second node location 108, the list of buffering components 200, and determine a set of buffering components for placement on the conduction path between the two nodes. For example, given that the total wire length between the two nodes is 160 pm, the electronic design tool may select three buffering components with wire lengths 10 pm, 50 pm, and 100 pm, for placement between the two nodes. In some instances, the electronic design tool may also receive as input process, voltage, and temperature (PVT) conditions, routing layer, etc. to determine the set of buffering components. In some instances, the list of buffering components 200 can be very large, which can affect the time it takes for the electronic design tool to select the set of buffering components. In some other instances, the list of buffering components 200 can include sub-optimal buffering components such as. for examples, ones having long or undesirable time delays. The presence of such sub-optimum buffering components in the list of buffering components 200 may increase the risk of the electronic design tool selecting the one or more of the sub- optimal buffering components as the set of buffering components suggested for placement on the conduction path between the two nodes.

[0048] Figure 3 shows a flow diagram of an example process 300. In particular, the process 300 can describe a method for removing one or more sub-optimal buffering components from the list of buffering components 200. The process 300 can be executed by one or more processors running the electronic design tool.

[0049] The process 300 can include generating a list of buffering components, each buffering component having a driving strength value, a wire length, and at least one time delay (302). At least one example of generating a list of buffering components is described in relation to Figure 2, which shows a list of buffering components 200 and which includes buffering components having driving strength values (INVDx). a wire length (Wire Length) and at least one time delay (Delay Mean / Delay Sigma).

[0050] The process 300 can also include selecting a set of buffering components, from the list of buffering components, that have equal wire lengths but different driving strength values (304). The electronic design tool can search the list of buffering components 200 shown in Figure 2 to determine the buffering components that have equal wire lengths such as, for example, 10 pm. The electronic design tool can select the set of buffering components that have the same wire length of 10 pm but different driving strength values. For example, the electronic design tool can select buffering components with index 001 and N-2 in the list of buffering components 200. The selected components have the same wire length of 10 pm but have different driving strength for the current buffer (Stage N). In some instances, the selected set of buffering components can have different driving strengths only with respect to the current buffer (Stage N). In some other examples, the selected set of buffering components can have different driving strengths with respect to the previous stage buffer (Stage N-l), or current stage buffer (Stage N) or the next stage buffer (Stage N+l). The process 300 can also include generating an updated list of buffering components by removing from the list of buffering components those buffering components from the set of buffering components that have at least one time delay value that is greater than a threshold value (306). Figure 4 shows an example technique for generating an updated list of buffering components. In particular, Figure 4 shows a set of buffering components 402, which can be selected from the list of buffering components such as, for example, the list of buffering components 200 shown in Figure 2. The set of buffering components 402 can include buffering components that have the same wire length but different driving strength values. In the example shown in Figure 4, the driving strength values of the current buffer (Stage N) are different across the set of buffering components 402. The electronic design tool can identify those buffering components from the set of buffering components 402 that have at least one time delay value that is greater than a threshold value. One example approach of such identification is shown in Figure 4, where each point on a graph 404 represents a buffering component, with the at least one time delay values on the y-axis and the driving strength values on the x-axis. The electronic design tool can determine a threshold time delay value 406 corresponding to a threshold time delay value. One or more of the buffering components having time delay values that is greater than the threshold time delay value can be removed. In the example show n in Figure 4, the buffering components 408 that have their respective time delay values greater than the threshold time delay value 406 can be removed. The removal of these buffering components is shown in the list 410. where four buffering components, corresponding to four points on the graph 404 that have time delay values greater than the threshold time delay value 406, are removed (indicated by strike-through). These buffering components can be removed from the list of buffering components from which the set of buffering components 402 was selected. In some examples, the threshold time delay value 406 can be based on a percentage time delay over a predetermined time delay value. For example, the threshold time delay value 406 can be 30% from the lowest time delay value of the set of buffering components 402. That is, buffering components having a time delay value greater than 1.3 times the lowest time delay value can be removed.

[0051] In some examples, the electronic design tool can repeat the above process for other wire lengths as well. Thus, while Figure 4 show s the example wire length of 100, the electronic design tool can select buffering components for removal for other wire lengths such as, for example, 10 and 50. from the list of buffering components 200. The process 300 can further include receiving a first node location and a second node location on the integrated circuit design (308). The electronic design tool can receive the locations, on the integrated circuit design, of the nodes between which the electronic design tool has to insert buffering components. For example, the locations of the nodes can include the locations of the first node location 106 (Figure 1) and the second node location 108 (Figure 1).

[0052] The process 300 can also include determining, based on the updated list of buffering components and an estimated distance on the integrated circuit design between the first node location and the second node location, an ordered set of buffered components for placement between the first node location and the second node location in the integrated circuit design (310). The electronic design tool can determine the total wire length between the first node location and the second node location. Based on the determined wire length, the electronic design tool can determine the number of buffering components to select from the updated list of buffering components. In some instances, the electronic design tool can employ a solver algorithm to determine the number of buffering components that provide the smallest time delay across conduction path. Solver algorithms can include, for example, van Ginneken type buffer insertion algorithms. These, and other buffer insertion algorithms, given a buffer library (such as, for example, the list of buffering components discussed herein), can determine a set of buffering components for insertion in a conduction path to address signal degradation. Typically, the solver algorithms can operate under some constraints such as, for example, total delay not to exceed a certain value, the power consumption of the buffering components not to exceed a certain power value, etc. The solver algorithm can take these constraints into consideration and select a set of buffering components for insertion into the conduction path. Other solver algorithms such as, for example, genetic algorithms and simulated annealing algorithms can also be utilized to determine a set of buffering components for insertion in a conduction path. In particular, these algorithms can be utilized to determine an optimized set of buffering components selected from the list of buffering components that satisfy given constraints for delay, power, conduction path length, etc. For example, these algorithms can select the set of buffering components from the list of buffering components such that the wire lengths add up to the conduction path length and provide the lowest delay, lowest power consumption, etc. The electronic design tool can select those buffering components whose respective wire lengths, when summed, is equal to an estimated distance between the first node location and the second node location. Furthermore, the electronic design tool can select those buffering components whose respective mean time delays, when summed, is the lowest possible total mean time delay.

[0053] As mentioned above, the electronic design tool can select an ordered set of buffered components. Two buffering components can be considered to be an ordered set of buffering components when the driving strength value of the next stage buffer of the first buffering component is equal to the driving strength value of the current stage buffer of the second buffering component. Figure 5 shows an example ordered set of buffering components selected by the electronic design tool. In particular, Figure 5 shows an updated list of buffering components 502, and an ordered set of buffering components 504 determined based on the updated list of buffering components 502. The ordered set of buffering components 504 include four buffering components: a first buffering component 506. a second buffering component 508, a third buffering component 510, and a fourth buffering component 512. The sum of the wire lengths of the ordered set of buffering components 504 is 340 pm. The driving strength value of the next stage buffer (Stage N+l) of the first buffering component is INVD10. which is equal to the driving strength value of the current stage buffer (Stage N) of the second buffering component 508. Similarly, the driving strength of the next stage buffer (Stage N+l) of the second buffering component 508 is INVD12, which is equal to the driving strength value of the current stage buffer (Stage N) of the third buffering component 510, and so on. Thus, the electronic design tool not only selects the ordered set of buffering components 504 from the updated list of buffering components 502 that have wire lengths that add up to the estimated distance on the integrated circuit between the first node location and the second node location, but also satisfy the ordering requirement. In some examples, selecting an ordered set of buffering components 504 can have the benefit of having the total delay of the buffering components 504 over the conduction path to close to the sum of the delays of individual buffering components 504 selected for the conduction path.

[0054] In some instances, the electronic design tool may select the buffering components without the ordering requirement mentioned above. That is, the electronic design tool may select a set of buffering components from the updated list of buffering components based at least on the estimated distance on the integrated circuit between the first node location and the second node location, but without requiring that the driving strength value of the next stage buffer of a first buffering component is equal to the driving strength value of the current stage buffer of a second subsequent buffering component. In some such instances where the buffering components are not ordered, the list of buffering components may not include information about the driving strengths of the previous stage and the next stage buffers, and may include the signal strength values of only the current stage buffers of each buffering component.

[0055] The removal of the buffering components with large time delays removes sub-optimal buffering components from the list of buffering components. Therefore, the risk of the electronic design tool selecting sub-optimal buffering components for placement over the conduction path can be reduced. Moreover, removal of sub-optimal buffering components from the list of buffenng components reduces the size of the list. Having relatively shorter lists can reduce the time taken by the electronic design tool to select the buffering components for placement on the conduction path. Thus, the speed of operation of the electronic design tool can be improved, thereby improving the speed of the integrated circuit design process.

[0056] In yet another approach to improving the selection of buffering components, the electronic design tool can expand the list of buffering components. Specifically, the electronic design tool can add buffering components with additional wire length values to the list of buffering components. In some examples, the wire length values of the added buffering components can be smaller than the wire lengths already in the list of buffering components.

[0057] Figure 6 shows a flow diagram of an example process 600 for generating an extended list of buffering components and selecting buffering components based on the extended list. The process 600 can include selecting, from a first list of buffering components, two buffering components having two different wire lengths, where each buffering component in the first list of buffering components having a driving strength value indicating a power output of the buffering component, a wire length indicating a length of an interconnect connected with the buffering component, and at least one time delay indicating signal transmission delay through the buffering component (602). Figure 7 shows an example technique for generating an expanded list of buffering components. In particular, Figure 7 shows a first list of buffering components 702 and an extended list of buffering components 704 generated based on the first list of buffering components 702. The first list of buffering components 702 can be similar to the list of buffering components 200 discussed herein in relation to Figure 2. The electronic design tool can select, for example, the first two buffering components (index 001 and 002 in the first list of buffering components 702), from the first list of buffering components 702, having two different wire lengths of 10 pm and 50 pm. It should be noted that the wire lengths shown in Figure 7 are only examples, and that other implementations could include different wire lengths. The process 600 can also include generating a second list of buffering components having wire lengths that are between the two different wire lengths of the selected two buffering components (604). The electronic design tool can generate a second list of buffering components 706 having wire lengths that are between the two different wire lengths of 10 pm and 50 pm. For example, the second list of buffering components 706 can have wire lengths of 20 pm. 30 pm. and 40 pm. In the example shown in Figure 7, the second list of buffering components includes three buffering components. It should be noted that the second list of buffering components can include one or more buffering components. For example, Figure 7 show s another second list of buffering components 708 that can be generated to include wire lengths that are between a different two selected buffering components (index 0002 and 0003 in the first list of buffering components 702) with wire lengths of 50 pm and 100 pm and can include four buffering components.

[0058] In one example, the electronic design tool can generate the second list of buffeting components based on interpolation. As an example, the electronic design tool can determine a wire length step and then add one or more buffering components having wire lengths separated by the wire length step. For example, in the second list of buffering components shown in Figure 7, the electronic design tool can determine the wire length step to be equal to 10 pm. In some examples, the second list of buffer components can be separated by the same wire length step, while in some other examples, the second list of buffering components can be separated by unequal wire length steps. In some examples, the electronic design tool can use the same driving strength values as the one of the two selected buffering components for the second list of buffering components 706. For example, in the second list of buffering components 706, the electronic design tool can use the driving strength values for the previous stage buffer (Stage N-l), the cunent stage buffer (Stage N) and the next stage buffer (Stage N+l) to be the same as the respective driving strength values of one of the two selected buffering components (index 001 or 002 in the first list of buffering components 702). The electronic design tool can determine the at least one timing delay for the second list of buffering components 706 based on simulation of the buffering components. In some other examples, the electronic design tool can determine the at least one delay for the second list of buffering components 706 based on interpolating between the at least one time delay values for the two selected buffering components (index 001 and 002 in the first list of buffering components 702). In some examples, the electronic design tool can employ regression methods (e.g., liner regression, polynomial regression, etc.) to determine the driving strength and time delay values for the second list of buffering components. For example, the electronic design tool can determine analytical representations (e.g., equations) of the driving strengths or the time delays of the first list of buffering components 702. Based on the analytical representations, the electronic design tool can user interpolation to determine the second set of buffering components. In some examples, the electronic design tool can determine the second set of buffering components based, at least in part, on extrapolation.

[0059] The process 600 can also include generating an extended list of buffering components based on adding the second list of buffering components to the first list of buffering components (606). Figure 7 shows an example of the extended list of buffering components 704. which the electronic design tool can generate based on the first list of buffering components 702 and the second list of buffering components 706 (and 708). The electronic design tool can re-index the buffering components such that the second list of buffering components are indexed between the two selected buffering components from the first list of buffering components 702.

[0060] The process 600 can also include receiving a first node location and a second node location on the integrated circuit design (608). The electronic design tool can receive the locations on the integrated circuit design the locations of the nodes between which the electronic design tool has to insert buffering components. For example, the locations of the nodes can include the locations of the first node location 106 (Figure 1) and the second node location 108 (Figure 1).

[0061] The process 600 can also include determining, based at least on the extended list of buffering components and an estimated distance on the integrated circuit design between the first node location and the second node location, an ordered set of buffering components for placement between the first node location and the second node location (610). The electronic design tool can determine the total wire length between the first node location and the second node location. Based on the determined wire length, the electronic design tool can determine the number of buffering components to select from the extended list of buffering components. The manner in which the electronic design tool selects the buffering components from the extended list of buffering components can be similar to that discussed above in relation to Figure 3 where the electronic design tool selects buffering components from the updated list of buffering components. In some examples, the electronic design tool can select a set of ordered buffering components from the extended list of buffering components 704 for placement on the conduction path between the first and the second node locations, while in some other examples the electronic design tool may selected un-ordered buffering components for placement on the conduction path in a manner similar to that discussed above in relation to Figure 3.

[0062] Adding additional buffering components to the list can improve the resolution of wire lengths available for selection by the electronic design tool for placement on the conduction path between two nodes. The electronic design tool can select buffering components from a wider range or a higher resolution of wire lengths which can result in increased accuracy and reduced delay. In some instances, parameters (e.g.. driving strength values and time delays) of the added buffering components can be determined from transistor level data, in some other examples, the electronic design tool can determine the parameters based on interpolation. Generating actual transistor level data can take substantially longer than interpolation. Therefore, the resolution of the buffering components in the list can be improved without a large time and resource overhead.

[0063] In some examples, the electronic design tool can combine the techniques discussed in relation to Figures 3 and 6. In particular, the electronic design tool can expand the list of buffering components by adding a second list of buffering components as discussed in relation to Figure 6 and remove sub-optimal buffering components as discussed in relation to Figure 3. In some examples, the electronic design tool can first generate an extended list of buffering components as discussed in relation to Figure 6 follow ed by removal of sub- optimal buffer components as discussed in relation to Figure 3. In some other examples, the electronic design tool can first remove sub-optimal buffer components form a list of buffering components to generate an updated list of buffering components as discussed in relation to Figure 3 follow ed by expanding the updated list of buffering components to generate an extended list of buffering components as discussed in relation to Figure 6

[0064] Utilizing one or both the techniques of pruning and expanding the list of buffering components can provide substantial improvements. For example, experimental data shows that electronic design tools that utilize the techniques discussed herein to determine a set of buffering components for placement on a conduction path between tw o node locations can run about 30 times or more faster than electronic design tools that do not utilize the techniques discussed herein. In one example, an electronic design tool can have a runtime of about 30 minutes to select a set of buffering components from a list of buffering components for placement on a conduction path having a wire length of about 300 pm. In contrast, an electronic design tool utilizing the techniques discussed herein can have a runtime of only about 70 seconds. In another example, total conduction path delays of buffering components selected using traditional electronic design tools can be considerably greater than the total conduction path delays of buffering components selected using the techniques discussed herein. Experimental data shows that for conduction path lengths that are greater than about 300 pm, the total conduction path delays of buffering components selected using the techniques discussed herein show an improvement of up to 50% over traditional techniques. Thus, the techniques discussed herein not only improve the speed with which integrated circuit design can be earned out but also improve the performance of the integrated circuits that are designed using these techniques.

[0065] Figure 8 is a diagram illustrating an example of a computing system, e.g., used for electronic design, and, in particular, for selection of buffering components in integrated circuits. The computing system includes computing device 800 and a mobile computing device 850 that can be used to implement the techniques described herein. For example, one or more processes, electronic design tools, and data can be implemented on or stored in the computing device 800 or the mobile computing device 850.

[0066] The computing device 800 is intended to represent various forms of digital computers, such as laptops, desktops, workstations, personal digital assistants, servers, blade servers, mainframes, and other appropriate computers. The mobile computing device 850 is intended to represent various forms of mobile devices, such as personal digital assistants, cellular telephones, smart-phones, mobile embedded radio systems, radio diagnostic computing devices, and other similar computing devices. The components shown here, their connections and relationships, and their functions, are meant to be examples only, and are not meant to be limiting.

[0067] The computing device 800 includes a processor 802, a memoiy 804, a storage device 806, a high-speed interface 808 connecting to the memoi ' 804 and multiple high-speed expansion ports 810. and a low-speed interface 812 connecting to a low-speed expansion port 814 and the storage device 806. Each of the processor 802, the memory 804, the storage device 806, the high-speed interface 808, the high-speed expansion ports 810, and the low- speed interface 812, are interconnected using various busses, and may be mounted on a common motherboard or in other manners as appropriate. The processor 802 can process instructions for execution within the computing device 800. including instructions stored in the memory 804 or on the storage device 806 to display graphical information for a GUI on an external input / output device, such as a display 816 coupled to the high-speed interface 808. In other implementations, multiple processors and / or multiple buses may be used, as appropriate, along with multiple memories and types of memory. In addition, multiple computing devices may be connected, with each device providing portions of the operations (e.g., as a server bank, a group of blade servers, or a multi-processor system). In some implementations, the processor 802 is a single threaded processor. In some implementations, the processor 802 is a multi-threaded processor. In some implementations, the processor 802 is a quantum computer.

[0068] The memory 804 stores information within the computing device 800. In some implementations, the memory 804 is a volatile memory unit or units. In some implementations, the memory 804 is a non-volatile memory unit or units. The memory 804 may also be another form of computer-readable medium, such as a magnetic or optical disk.

[0069] The storage device 806 is capable of providing mass storage for the computing device 800. In some implementations, the storage device 806 may be or include a computer-readable medium, such as a floppy disk device, a hard disk device, an optical disk device, or a tape device, a flash memory or other similar solid-state memory device, or an array of devices, including devices in a storage area network or other configurations. Instructions can be stored in an information carrier. The instructions, when executed by one or more processing devices (for example, processor 802), perform one or more methods, such as those described above. The instructions can also be stored by one or more storage devices such as computer- or machine-readable mediums (for example, the memory 804, the storage device 806, or memory on the processor 802). The high-speed interface 808 manages bandwidth-intensive operations for the computing device 800, while the low-speed interface 812 manages lower bandwidth-intensive operations. Such allocation of functions is an example only. In some implementations, the high-speed interface 808 is coupled to the memory 804, the display 816 (e.g., through a graphics processor or accelerator), and to the high-speed expansion ports 810, which may accept various expansion cards (not shown). In the implementation, the low-speed interface 812 is coupled to the storage device 806 and the low-speed expansion port 814. The low-speed expansion port 814, which may include various communication ports (e.g., USB, Bluetooth, Ethernet, wireless Ethernet) may be coupled to one or more input / output devices, such as a keyboard, a pointing device, a scanner, or a networking device such as a switch or router, e.g., through a network adapter.

[0070] The computing device 800 may be implemented in a number of different forms, as show n in the figure. For example, it may be implemented as a standard server 820, or multiple times in a group of such servers. In addition, it may be implemented in a personal computer such as a laptop computer 822. It may also be implemented as part of a rack server system 824. Alternatively, components from the computing device 800 may be combined with other components in a mobile device, such as a mobile computing device 850. Each of such devices may include one or more of the computing device 800 and the mobile computing device 850. and an entire system may be made up of multiple computing devices communicating with each other.

[0071] The mobile computing device 850 includes a processor 852, a memory 864, an input / output device such as a display 854, a communication interface 866, and a transceiver 868, among other components. The mobile computing device 850 may also be provided with a storage device, such as a micro-drive or other device, to provide additional storage. Each of the processor 852, the memon 864, the display 854, the communication interface 866, and the transceiver 868, are interconnected using various buses, and several of the components may be mounted on a common motherboard or in other manners as appropriate.

[0072] The processor 852 can execute instructions within the mobile computing device 850. including instructions stored in the memory 864. The processor 852 may be implemented as a chipset of chips that include separate and multiple analog and digital processors. The processor 852 may provide, for example, for coordination of the other components of the mobile computing device 850, such as control of user interfaces, applications run by the mobile computing device 850, and wireless communication by the mobile computing device 850.

[0073] The processor 852 may communicate with a user through a control interface 858 and a display interface 856 coupled to the display 854. The display 854 may be, for example, a TFT (Thin-Film-Transistor Liquid Crystal Display) display or an OLED (Organic Light Emitting Diode) display, or other appropriate display technology. The display interface 856 may include appropriate circuitry for driving the display 854 to present graphical and other information to a user. The control interface 858 may receive commands from a user and convert them for submission to the processor 852. In addition, an external interface 862 may provide communication with the processor 852, so as to enable near area communication of the mobile computing device 850 with other devices. The external interface 862 may provide, for example, for wired communication in some implementations, or for wireless communication in other implementations, and multiple interfaces may also be used.

[0074] The memory 864 stores information within the mobile computing device 850. The memory 864 can be implemented as one or more of a computer-readable medium or media, a volatile memory unit or units, or a non-volatile memory' unit or units. An expansion memory' 874 may also be provided and connected to the mobile computing device 850 through an expansion interface 872. which may include, for example, a SIMM (Single In Line Memory Module) card interface. The expansion memory 874 may provide extra storage space for the mobile computing device 850, or may also store applications or other information for the mobile computing device 850. Specifically, the expansion memory 874 may include instructions to carry out or supplement the processes described herein, and may include secure information also. Thus, for example, the expansion memory 874 may be provide as a security module for the mobile computing device 850, and may be programmed with instructions that permit secure use of the mobile computing device 850. In addition, secure applications may be provided via the SIMM cards, along with additional information, such as placing identifying information on the SIMM card in a non-hackable manner.

[0075] The memory may include, for example, flash memory' and / or NVRAM memory' (nonvolatile random access memory), as discussed below. In some implementations, instructions are stored in an information carrier such that the instructions, when executed by one or more processing devices (for example, processor 852), perform one or more methods, such as those described above. The instructions can also be stored by one or more storage devices, such as one or more computer- or machine-readable mediums (for example, the memory 864. the expansion memory 874, or memory on the processor 852). In some implementations, the instructions can be received in a propagated signal, for example, over the transceiver 868 or the external interface 862.

[0076] The mobile computing device 850 may communicate wirelessly through the communication interface 866, which may include digital signal processing circuitry’ in some cases. The communication interface 866 may provide for communications under various modes or protocols, such as GSM voice calls (Global System for Mobile communications), SMS (Short Message Service), EMS (Enhanced Messaging Service), or MMS messaging (Multimedia Messaging Sendee), CDMA (code division multiple access), TDMA (time division multiple access), PDC (Personal Digital Cellular), WCDMA (Wideband Code Division Multiple Access), CDMA2000, or GPRS (General Packet Radio Service), LTE, 4G / 5G / 6G cellular, among others. Such communication may occur, for example, through the transceiver 868 using a radio frequency. In addition, short-range communication may occur, such as using a Bluetooth, Wi-Fi, or other such transceiver (not shown). In addition, a GPS (Global Positioning System) receiver module 870 may provide additional navigation- and location-related wireless data to the mobile computing device 850, which may be used as appropriate by applications running on the mobile computing device 850.

[0077] The mobile computing device 850 may also communicate audibly using an audio codec 860. which may receive spoken information from a user and convert it to usable digital information. The audio codec 860 may likewise generate audible sound for a user, such as through a speaker, e.g., in a handset of the mobile computing device 850. Such sound may include sound from voice telephone calls, may include recorded sound (e.g., voice messages, music files, among others) and may also include sound generated by applications operating on the mobile computing device 850.

[0078] The mobile computing device 850 may be implemented in a number of different forms, as shown in the figure. For example, it may be implemented as a cellular telephone 880. It may also be implemented as part of a smart-phone 882, personal digital assistant, or other similar mobile device.

[0079] Embodiments of the subject matter and the functional operations described in this specification can be implemented in digital electronic circuitry, in tangibly-embodied computer software or firmware, in computer hardware, including the structures disclosed in this specification and their structural equivalents, or in combinations of one or more of them. Embodiments of the subject matter described in this specification can be implemented as one or more computer programs, i.e., one or more modules of computer program instructions encoded on a tangible nontransitory storage medium for execution by, or to control the operation of, data processing apparatus. The computer storage medium can be a machine- readable storage device, a machine-readable storage substrate, a random or serial access memory device, or a combination of one or more of them. Alternatively or in addition, the program instructions can be encoded on an artificially-generated propagated signal, e.g., a machine-generated electrical, optical, or electromagnetic signal, that is generated to encode information for transmission to suitable receiver apparatus for execution by a data processing apparatus.

[0080] The term “data processing apparatus” refers to data processing hardware and encompasses all kinds of apparatus, devices, and machines for processing data, including by way of example a programmable processor, a computer, or multiple processors or computers. The apparatus can also be, or further include, special purpose logic circuitry, e.g., an FPGA (field programmable gate array) or an ASIC (applicationspecific integrated circuit). The apparatus can optionally include, in addition to hardware, code that creates an execution environment for computer programs, e.g.. code that constitutes processor firmware, a protocol stack, a database management system, an operating system, or a combination of one or more of them. -

[0081] A computer program which may also be referred to or described as a program, software, a software application, an app. a module, a software module, a script, or code) can be written in any form of programming language, including compiled or interpreted languages, or declarative or procedural languages, and it can be deployed in any form, including as a standalone program or as a module, component, subroutine, or other unit suitable for use in a computing environment. A program may, but need not, correspond to a file in a file system. A program can be stored in a portion of a file that holds other programs or data, e.g., one or more scripts stored in a markup language document, in a single file dedicated to the program in question, or in multiple coordinated files, e.g., files that store one or more modules, sub-programs, or portions of code. A computer program can be deployed to be executed on one computer or on multiple computers that are located at one site or distributed across multiple sites and interconnected by a data communication network.

[0082] The processes and logic flows can also be performed by special purpose logic circuitry, e.g., an FPGA or an ASIC, or by a combination of special purpose logic circuitry and one or more programmed computers. Computers suitable for the execution of a computer program can be based on general or special purpose microprocessors or both, or any other kind of central processing unit. Generally, a central processing unit will receive instructions and data from a readonly memory or a random access memory or both. The essential elements of a computer are a central processing unit for performing or executing instructions and one or more memory devices for storing instructions and data. The central processing unit and the memory can be supplemented by, or incorporated in, special purpose logic circuitry. Generally, a computer will also include, or be operatively coupled to receive data from or transfer data to. or both, one or more mass storage devices for storing data, e.g.. magnetic, magneto-optical disks, or optical disks. However, a computer need not have such devices. Moreover, a computer can be embedded in another device, e.g., a mobile telephone, a personal digital assistant (PDA), a mobile audio or video player, a game console, a Global Positioning System (GPS) receiver, or a portable storage device, e.g.. a universal serial bus (USB) flash drive, to name just a few.

[0083] Computerreadable media suitable for storing computer program instructions and data include all forms of non-volatile memory7, media and memory devices, including by way of example semiconductor memory devices, e.g., EPROM, EEPROM, and flash memory devices; magnetic disks, e.g., internal hard disks or removable disks; magneto-optical disks; and CD-ROM and DVD-ROM disks. -While this specification contains many specific implementation details, these should not be construed as limitations on the scope of any invention or on the scope of what may be claimed, but rather as descriptions of features that may be specific to particular embodiments of particular inventions. Certain features that are described in this specification in the context of separate embodiments can also be implemented in combination in a single embodiment. Conversely, various features that are described in the context of a single embodiment can also be implemented in multiple embodiments separately or in any suitable subcombination. Moreover, although features may be described above as acting in certain combinations and even initially be claimed as such, one or more features from a claimed combination can in some cases be excised from the combination, and the claimed combination may be directed to a subcombination or variation of a subcombination.

[0084] Similarly, while operations are depicted in the drawings and recited in the claims in a particular order, this should not be understood as requiring that such operations be performed in the particular order shown or in sequential order, or that all illustrated operations be performed, to achieve desirable results. In certain circumstances, multitasking and parallel processing may be advantageous. Moreover, the separation of various system modules and components in the embodiments described above should not be understood as requiring such separation in all embodiments, and it should be understood that the described program components and systems can generally be integrated together in a single software product or packaged into multiple software products.

[0085] Particular embodiments of the subject matter have been described. Other embodiments are within the scope of the following claims. For example, the actions recited in the claims can be performed in a different order and still achieve desirable results. As one example, the processes depicted in the accompanying figures do not necessarily require the particular order shown, or sequential order, to achieve desirable results. In some cases, multitasking and parallel processing may be advantageous.

[0086] What is claimed is:

Claims

CLAIMS1. A method for determining buffering components for placement between two nodes on an integrated circuit design, comprising: generating a list of buffering components, each buffering component, in the list of buffering components, having a driving strength value indicating a power output of the buffering component, a wire length indicating a length of an interconnect connected with the buffering component, and at least one time delay indicating signal transmission delay through the buffering component; selecting a set of buffering components, from the list of buffering components, that have equal wire lengths but different driving strength values; generating an updated list of buffering components by removing, from the list of buffering components, those buffering components from the set of buffering components that have at least one time delay value that is greater than a threshold value; receiving a first node location and a second node location on the integrated circuit design; and determining, based at least on the updated list of buffering components and an estimated distance on the integrated circuit design between the first node location and the second node location, an ordered set of buffering components for placement between the first node location and the second node location on the integrated circuit design.

2. The method of claim 1 , wherein generating the updated list of buffering components includes adding buffering components by interpolation.

3. The method of claim 1, wherein the at least one time delay is a mean delay.

4. The method of claim 1, wherein at least two buffering components in the ordered set of buffering components have different wire lengths.

5. The method of claim 1, wherein generating the list of buffering components includes determining the at least one time delay of each of the buffering components in the list of buffering components based on transistor level simulation.

6. The method of claim 1 , wherein the estimated distance on the integrated circuit design between the first node location and the second node location is at least 300 micrometers.

7. The method of claim 1, wherein a sum of wire lengths of the ordered set of buffering components is equal to the estimated distance on the integrated circuit between the first node location and the second node location.

8. The method of claim 1, further comprising: determining the ordered set of buffering components based additionally on circuit conditions such as power, voltage, and temperature.

9. A method for determining buffering components for placement between two nodes on an integrated circuit design, comprising: selecting, from a first list of buffering components, two buffering components having two different wire lengths, wherein each buffering component in the first list of buffering components having a driving strength value indicating a power output of the buffering component, a wire length indicating a length of an interconnect connected with the buffering component, and at least one time delay indicating signal transmission delay through the buffering component; generating a second list of buffering components, each buffering component in the second list of buffering components having wire lengths that are between the two different wire lengths of the selected two buffering components; generating an extended list of buffering components based on adding the second list of buffering components to the first list of buffering components; receiving a first node location and a second node location on the integrated circuit design; and determining, based at least on the extended list of buffering components and an estimated distance on the integrated circuit design between the first node location and the second node location, an ordered set of buffering components for placement between the first node location and the second node location on the integrated circuit design.

10. The method of claim 9, further comprising: selecting a set of buffering components, from the extended list of buffering components, that have equal wire lengths but different drive strength values; andremoving, form the extended list of buffering components, those buffering components from the set of buffering components that have at least one time delay value that is greater than a threshold value.

11. The method of claim 9, wherein at least two buffering components in the ordered set of buffering components have different wire lengths.

12. The method of claim 9, wherein generating the extended list of buffering components includes determining the at least one time delay of each of the buffering components in the extended list of buffering components based on transistor level simulation.

13. The method of claim 9, wherein the estimate distance on the integrated circuit design between the first node location and the second node location is at least 300 micrometers.

14. The method of claim 9, wherein wire lengths of the buffering components in the second list of buffering components are separated by a wire length step.

15. One or more non-transitory computer-readable storage media storing instructions that when executed by one or more processors cause the one or more processors to perform operations for determining buffering components for placement between two nodes on an integrated circuit design, the operations comprising: generating a list of buffering components, each buffering component, in the list of buffering components, having a driving strength value indicating a power output of the buffering component, a wire length indicating a length of an interconnect connected with the buffering component, and at least one time delay indicating signal transmission delay through the buffering component; selecting a set of buffering components, from the list of buffering components, that have equal wire lengths but different driving strength values; generating an updated list of buffering components by removing, from the list of buffering components, those buffering components from the set of buffering components that have at least one time delay value that is greater than a threshold value; receiving a first node location and a second node location on the integrated circuit design; anddetermining, based at least on the updated list of buffering components and an estimated distance on the integrated circuit design between the first node location and the second node location, an ordered set of buffering components for placement between the first node location and the second node location on the integrated circuit design.

16. The computer-readable storage media of claim 15, wherein generating the updated list of buffering components includes adding buffering components by interpolation.

17. The computer-readable storage media of claim 15, wherein the at least one time delay is a mean delay.

18. The computer-readable storage media of claim 15, wherein at least two buffering components in the ordered set of buffering components have different wire lengths.19 The computer-readable storage media of claim 15, wherein generating the list of buffering components includes determining the at least one time delay of each of the buffering components in the list of buffering components based on transistor level simulation.

20. The computer-readable storage media of claim 15, wherein the estimated distance on the integrated circuit design between the first node location and the second node location is at least 300 micrometers.

21. The computer-readable storage media of claim 15, wherein a sum of wire lengths of the ordered set of buffering components is equal to the estimated distance on the integrated circuit between the first node location and the second node location.

22. The computer-readable storage media of claim 15, the operations further comprising: determining the ordered set of buffering components based additionally on circuit conditions such as power, voltage, and temperature.

23. One or more non-transitory computer-readable storage media storing instructions that when executed by one or more processors cause the one or more processors to perform operations for determining buffering components for placement between two nodes on an integrated circuit design, the operations comprising:selecting, from a first list of buffering components, two buffering components having two different w ire lengths, wherein each buffering component in the first list of buffering components having a driving strength value indicating a power output of the buffering component, a wire length indicating a length of an interconnect connected with the buffering component, and at least one time delay indicating signal transmission delay through the buffering component; generating a second list of buffering components, each buffering component in the second list of buffering components having ware lengths that are between the two different wire lengths of the selected two buffering components; generating an extended list of buffering components based on adding the second list of buffering components to the first list of buffering components; receiving a first node location and a second node location on the integrated circuit design; and determining, based at least on the extended list of buffering components and an estimated distance on the integrated circuit design between the first node location and the second node location, an ordered set of buffering components for placement between the first node location and the second node location on the integrated circuit design.

24. The computer-readable storage media of claim 23, the operations further comprising: selecting a set of buffering components, from the extended list of buffering components, that have equal wire lengths but different drive strength values; and removing, form the extended list of buffering components, those buffering components from the set of buffering components that have at least one time delay value that is greater than a threshold value.

25. The computer-readable storage media of claim 23, wherein at least tw o buffering components in the ordered set of buffering components have different wire lengths.

26. The computer-readable storage media of claim 23, wherein generating the extended list of buffering components includes determining the at least one time delay of each of the buffering components in the extended list of buffering components based on transistor level simulation.

27. The computer-readable storage media of claim 23, wherein the estimate distance on the integrated circuit design between the first node location and the second node location is at least 300 micrometers.

28. The computer-readable storage media of claim 23, wherein wire lengths of the buffering components in the second list of buffering components are separated by a wire length step.

29. A system, comprising: one or more processors; and one or more storage devices storing instructions that when executed by the one or more processors to perform operations for determining buffering components for placement between two nodes on an integrated circuit design, the operations comprising: generating a list of buffering components, each buffering component, in the list of buffering components, having a driving strength value indicating a power output of the buffering component, a wire length indicating a length of an interconnect connected with the buffering component, and at least one time delay indicating signal transmission delay through the buffering component; selecting a set of buffering components, from the list of buffering components, that have equal wire lengths but different driving strength values; generating an updated list of buffering components by removing, from the list of buffering components, those buffering components from the set of buffering components that have at least one time delay value that is greater than a threshold value; receiving a first node location and a second node location on the integrated circuit design; and determining, based at least on the updated list of buffering components and an estimated distance on the integrated circuit design between the first node location and the second node location, an ordered set of buffering components for placement between the first node location and the second node location on the integrated circuit design.

30. The system of claim 29, wherein generating the updated list of buffering components includes adding buffering components by interpolation.

31. The system of claim 29, wherein the at least one time delay is a mean delay.

32. The system of claim 29, wherein at least two buffering components in the ordered set of buffering components have different wire lengths.

33. The system of claim 29, wherein generating the list of buffering components includes determining the at least one time delay of each of the buffering components in the list of buffering components based on transistor level simulation.

34. The system of claim 29, wherein the estimated distance on the integrated circuit design between the first node location and the second node location is at least 300 micrometers.

35. The system of claim 29, wherein a sum of wire lengths of the ordered set of buffering components is equal to the estimated distance on the integrated circuit between the first node location and the second node location.

36. The system of claim 29, the operations further comprising: determining the ordered set of buffering components based additionally on circuit conditions such as power, voltage, and temperature.

37. A system, comprising: one or more processors; and one or more storage devices storing instructions that when executed by the one or more processors to perform operations for determining buffering components for placement between two nodes on an integrated circuit design, the operations comprising: selecting, from a first list of buffering components, two buffering components having two different wire lengths, wherein each buffering component in the first list of buffering components having a driving strength value indicating a power output of the buffering component, a wire length indicating a length of an interconnect connected with the buffering component, and at least one time delay indicating signal transmission delay through the buffering component; generating a second list of buffering components, each buffering component in the second list of buffering components having wire lengths that are between the two different wire lengths of the selected two buffering components;generating an extended list of buffering components based on adding the second list of buffering components to the first list of buffering components; receiving a first node location and a second node location on the integrated circuit design; and determining, based at least on the extended list of buffering components and an estimated distance on the integrated circuit design between the first node location and the second node location, an ordered set of buffering components for placement between the first node location and the second node location on the integrated circuit design.

38. The system of claim 37, the operations further comprising: selecting a set of buffering components, from the extended list of buffering components, that have equal wire lengths but different drive strength values; and removing, form the extended list of buffering components, those buffering components from the set of buffering components that have at least one time delay value that is greater than a threshold value.

39. The system of claim 37, wherein at least two buffering components in the ordered set of buffering components have different wire lengths.

40. The system of claim 37, wherein generating the extended list of buffering components includes determining the at least one time delay of each of the buffering components in the extended list of buffering components based on transistor level simulation.

41. The system of claim 37, wherein the estimate distance on the integrated circuit design between the first node location and the second node location is at least 300 micrometers.

42. The system of claim 37, wherein wire lengths of the buffering components in the second list of buffering components are separated by a wire length step.

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