Memory device with command / address (CA) failure recovery

Abstract

An integrated circuit (IC) memory device includes a command / address (CA) interface to receive CA information at multiple CA input circuits during a first mode of operation. The CA interface includes CA decoder circuitry to decode the CA information via a first CA decoding protocol during the first mode of operation. During a CA recovery mode of operation, the first CA decoding protocol is changed in response to detection of a CA error associated with a failed CA input circuit.

Description

UNITED STATES PATENT APPLICATIONFORMEMORY DEVICE WITH COMMAND / ADDRESS (CA) FAILURE RECOVERYInventor(s): Torsten Partsch Robert Palmer John Eric LinstadtPrepared By: Peninsula Patent Group 2644 Placer St.Santa Cruz, California 95062 Tel.: 650-468-9654MEMORY DEVICE WITH COMMAND / ADDRESS (CA) FAILURE RECOVERYTECHNICAL FIELD

[0001] The disclosure herein relates to memory devices, memory controllers, related methods, systems and modules that employ such devices.BRIEF DESCRIPTION OF THE DRAWINGS

[0002] Embodiments of the disclosure are illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings and in which like reference numerals refer to similar elements and in which:

[0003] FIG. 1 illustrates one embodiment of a memory system including a memory device and a host memory controller that employs command / address (CA) failure recovery circuits and techniques.

[0004] FIG. 2 illustrates a flowchart of steps for one embodiment of operating the memory device of FIG. 1.

[0005] FIG. 3 illustrates a flowchart of steps for one embodiment of operating the host memory controller of FIG. 1.

[0006] FIG. 4 illustrates a further embodiment of a memory system that is similar to the system of FIG. 1.

[0007] FIG. 5 illustrates a flowchart of steps employed in adjusting a CA encoding protocol via a spare pin assignment for the memory system of FIG. 4.

[0008] FIG. 6 illustrates a timing chart with event timings corresponding to the steps of FIG. 5.

[0009] FIG. 7 illustrates an additional embodiment of a memory system that is similar to the system of FIG. 1.

[0010] FIG. 8 illustrates a flowchart of steps employed in adjusting a CA encoding protocol by repacketizing CA information over fewer CA links for the memory system of FIG. 7.

[0011] FIG. 9 illustrates a chart showing various CA remappings in the event of a CA fault in the memory system of FIG. 7.

[0012] FIG. 10 illustrates a timing chart with event timings corresponding to the steps of FIG. 8.

[0013] FIG. 11 illustrates an embodiment of a memory system that employs a three- dimensional stacked (3DS) memory device with a separate chip ID (CID) interface that employs command / address (CA) failure recovery circuits and techniques.

[0014] FIG. 12 illustrates a timing chart with event timings corresponding to operation of the memory system of FIG. 11 in a CA fault mode.DETAILED DESCRIPTION

[0015] Embodiments of memory devices, memory controllers, methods, systems and associated integrated circuit devices are disclosed herein. One embodiment of an integrated circuit (IC) memory device includes a command / address (CA) interface to receive CA information at multiple CA input circuits during a first mode of operation. The CA interface includes CA decoder circuitry to decode the CA information via a first CA decoding protocol during the first mode of operation. During a CA recovery mode of operation, the first CA decoding protocol is changed in response to detection of a CA error associated with a failed CA input circuit. In some embodiments, the change in the first CA decoding protocol is made to support a substitution of a spare CA input circuit for the failed CA input circuit. In other embodiments, the first CA decoding protocol is changed to support repacketized CA information over a subset of the multiple CA input circuits. By changing the first CA decoding protocol in the event of a CA input circuit failure, operability of theCA interface may be recovered in a cost-efficient manner without discarding or replacing the entire memory device.

[0016] Referring now to FIG. 1, one embodiment of a memory system, generally designated 100, includes a host memory controller 102 and a memory device 104. The host memory controller 102 includes a host memory interface 106 for transferring data and command / address (CA) signals with the memory device 104 via a set of data links 108 and a set of CA links 110. For some embodiments, one or more spare CA links, such as at 111 (in phantom) may optionally be provided for redundancy purposes and to potentially provide host-generated CA error information to the memory device 104, as described more fully below.

[0017] With continued reference to FIG. 1, for one embodiment, the host memory controller 102 is a dynamic random access memory (DRAM) controller, with the memory device 104 realized as a DRAM memory device. In some embodiments, the host memory controller 102 and the memory device 104 may be embodied as integrated circuits, or chips. Other embodiments may employ the host memory controller 102 as a circuit in a host central processing unit (CPU) (not shown). Specific embodiments for the host memory controller 102 and the memory device 104 may be compliant with various DRAM standards, including double data rate (DDR) variants, low power (LPDDR) versions, high bandwidth (HBM), and graphics (GDDR) types, to name but a few. Other embodiments may include multi-chip modules that, for example, employ stacked memory die, or stacked packages. Additional embodiments may stack memory die and logic die together in a common package, or in separate packages stacked upon each other. Yet other embodiments may employ multiple memory devices on a substrate (not shown) in a memory module configuration for high-capacity applications.

[0018] Further referring to FIG. 1, for one embodiment, the host memory interface 106 includes bidirectional data input / output (VO) circuitry 112 and unidirectional CA I / O circuitry 114. CA encoder circuitry 116 packages CA information into a protocol that is compatible with the type of memory device 104 that is utilized and manages pin assignments for the transmission of the CA information via the CA I / O circuitry 114. To manage and control typical read and write data transfers during a mission mode of operation, mission mode control circuitry 118 is provided in the host memory controller 102. CA fault control circuitry 120 manages and controls various CA recovery procedures during a CA recovery mode of operation. CA recovery circuitry 122 cooperates with the CA fault control circuitry 120 to execute a change in protocol for the CA encoder circuitry 116 when a CA fault is detected.

[0019] With continued reference to FIG. 1, for one embodiment, the memory device 104 includes a device memory interface 124 for transferring (transmitting and receiving) the data with the data links 108 via a set of device data I / O circuits 126, and receiving the command / address (CA) signals from the CA links 110 via a set of device CA I / O circuits 128. CA decoder circuitry 130 decodes the received encoded CA information as command, address and control signals and provides the command, address and control signals to memory core circuitry 132 along path 134 during the mission mode of operation. In one embodiment, the CA decoder circuitry 130 includes error detection circuitry 131 that generates a straightforward error code or checksum for the received CA information (over the relatively small number of CA links 110), and utilizes it to monitor for received CA errors that might indicate a persistent CA error. For some embodiments, during CA fault recovery operations, a loopback path 136 couples the CA decoder circuitry 130 to the set of device data I / O circuits 126. This allows for received CA information to be transferred back to the host memory controller 102 in an effort to detect a location of a CA fault.

[0020] In an effort to detect CA-related failures and to recover the use of C A circuitry that may be impaired by a single-CA fault, the memory system 100 is configured to dynamically operate in the mission and CA fault recovery modes of operation, generally based on the presence or absence of one or more detected persistent CA errors. By employing such a recovery technique, a given memory system may continue to operate without costly replacement or overall complete loss of the system.

[0021] FIG. 2 illustrates a flowchart of steps for one specific embodiment of a method that may be performed to operate the memory device 104 in a manner that dynamically switches from a mission mode of operation to a CA fault recovery mode of operation to allow for recovery of CA functionality that may be impaired by a persistent CA fault. By changing a CA protocol used in the transfer of CA information from the host memory controller 102 to the memory device 104, the CA fault may be cost-effectively repaired without the loss of the entire memory device.

[0022] Further referring to FIG. 2, during the mission mode of operation, sequences of commands are generally received at the CA I / O circuitry 128. As each command is received, such as at 202, a determination is made, at 204, as to whether the command is a standard data transfer command, such as a read or write command, or a CA repair instruction. For one specific embodiment, if the received command is a standard data transfer command, and not a CA repair instruction, then the CA decoder circuitry 130 generates an on-device checksum value associated with the received CA command information, at 206, and compares it to a host-generated checksum value produced by the host memory controller 102 during transmission of the CA command information. If the checksum values match, during a determination carried out at 208, then the CA information is verified as error-free, and the command is executed by the memory device, at 210, with operation returning to receiving a subsequent command, at 202.

[0023] With continued reference to FIG. 2, in the event that the checksum comparison results in a mismatch between the checksums, at 208, then the CA information is viewed as error corrupted, and the received command is ignored, at 212. The memory device 104 then alerts the host memory controller 102 of the failure, at 214, by sending an alert signal to the host memory controller 102 via a side-band path or backchannel (not shown). For one embodiment, once alerted, the host memory controller may have the option to enter the CA fault recovery mode, or retry transmission of the memory access operation involving the failed CA information should the failure be deemed transient and non-persistent.

[0024] Referring now to FIG. 3, and with the host memory controller 102 operating in mission mode, at 302, receipt of the alert signal from the memory device 102 causes the host memory controller 102 to enter the CA failure mode of operation, at 304. For some embodiments, switching to the CA failure mode of operation may be triggered by receiving one or more alert signal indications from the memory device 102, and / or based on a threshold CA error rate that is indicative of persistent CA failures. Once the host memory controller 102 switches operation to the CA fault recovery mode, the CA fault control circuitry 120 instructs the CA recovery circuitry 122 to generate a key or coded pattern of signals for transmission to the memory device 104 along the set of CA links 110, at 306. The key or pattern generally represents a form of command for the memory device 104 to enter the CA fault mode of operation.

[0025] For one embodiment, the key may take the form of a reliably identifiable command pattern transmitted along one or more of the original CA links or a spare CA link, regardless of which CA resource fails. Other embodiments may pull the spare CA link low for a predetermined number of cycles, indicating a failure condition. Yet other embodiments may intentionally drive an illegal command sequence, such as three or more consecutive “activate” commands, to trigger entry into the CA fault recovery mode.

[0026] Referring back to FIG. 2, the key or pattern generated and transmitted by the host memory controller 102 is received by the memory device 104, at 202. At 204, the key is determined to be a CA repair entry or instruction. In response to the key, the memory device 104 closes access to the memory core circuitry 132 and carries out self-refresh operations, at 216, to preserve data stored in the core circuitry 132. Once the memory core circuitry is closed to accesses, then the memory device 104 enters the CA fault recovery mode of operation, at 218, which for some embodiments involves enabling the loopback path 136 such that the host memory controller 102 and the memory device 104 cooperate in a CA loopback configuration for diagnosing the cause and specific location of the fault associated with the detected CA errors.

[0027] Referring back to FIG. 3, once the memory device 104 enters the CA fault mode of operation, the host memory controller 102 performs one or more tests over the CA circuitry and paths, at 308, from the host CA I / O circuitry 114, along the CA links 110, and to the device CA I / O circuitry 128. The tests may involve a sequence of signal patterns generated by the CA recovery circuitry 122, sent by the host memory controller 102 over the CA links 110, received by the device CA I / O circuitry 128, decoded by the CA decoder circuitry 130, and looped-back to the host memory controller 102 via the loopback path 136 and the device data I / O circuitry 126. The test patterns may generally be designed to isolate a given failure location along the CA signal paths, which may be more accurately determined through the loopback technique.

[0028] With continued reference to FIG. 3, once the tests at 308 are completed, a determination is made, at 310, as to whether the tests confirmed a persistent CA failure. If the tests indicate a one-off non-persistent CA error, then operation may revert back to the mission mode, at 302. Should the testing confirm the presence of a persistent CA error, then a further determination is made, at 312, as to whether the CA failure is repairable. If the CAfailure is deemed catastrophic, such as involving a channel-wide or rank failure, at 314, then any further CA failure recovery operations are terminated, and the memory device 104 may be alerted as to the unrepairability of the CA failure, at 220 (FIG. 2).

[0029] Further referring to FIG. 3, should the CA failure be deemed repairable, at 312, then the CA fault control circuitry 120 instructs the CA recovery circuitry 122 to adjust the CA encoding protocol applied by the CA encoder circuitry 116, at 316. After the encoding protocol is changed, further tests may be performed to verify that the failure is repaired, such as through a determination at 222 (FIG. 2) or the system may directly revert to the mission mode of operation, at 302. For a first specific embodiment, the change in the CA encoding protocol involves substituting a defective CA VO circuit or CA link with a spare CA I / O circuit or CA link, and carrying out a reassignment of the overall CA interface for the newly added I / O circuit and / or link. Embodiments of such a redundant recovery scheme are described below with respect to FIGs. 4 - 6. In another specific embodiment, the change in the CA encoding protocol involves disabling the failed CA VO circuit and / or CA link, and reformatting the CA information to be transferred over fewer CA links.Embodiments of such a reformatting recovery scheme are described below with respect to FIGs. 7 - 11.

[0030] Referring now to FIG. 4, one specific embodiment of a memory system, generally designated 400, is shown that is configured to perform CA failure recovery operations by changing CA protocol encodings to support the substitution of failed CA circuitry with redundant CA resources. The memory system 400 is similar to the system 100 of FIG. 1, and includes a host memory controller 402 and a memory device 404. The host memory controller 402 includes a host memory interface 406 that communicates with the memory device 404 via a set of data links 408 and a set of CA links 410. One or more spare CA link circuits 412 provides a redundant end-to-end CA resource that may beswapped-in to replace a CA link that is determined to be corrupted or damaged. The spareCA link circuit 412 includes a host-side spare CA I / O circuit 414 that communicates with a device-side CA I / O circuit 416 along a spare CA signal path 418.

[0031] Further referring to FIG. 4, the host memory controller 402 includes mission mode circuitry 420 to manage and control typical data and CA transfers between the host memory controller 402 and the memory device 404 during a mission mode of operation. The mission mode circuitry 420 couples to CA pin assignment circuitry 422 which assigns certain CA links for transferring certain portions of the CA information to the memory device 404. The CA pin assignments form a portion of an overall CA information encoding protocol.

[0032] With continued reference to FIG. 4, the system 400 includes CA fault control circuitry 424 to manage CA recovery procedures during a CA fault recovery mode of operation. The CA fault control circuitry 424 employs a CA fault state machine 426 coupled to the mission mode circuitry 420, and the CA pin assignment circuitry 422. For one embodiment, test circuitry in the form of a pattern generator 428 is provided to produce test signals for transmission across the CA links during the CA fault recovery mode of operation. The test signals are compared to expected test signals by compare circuitry 430 to search for and isolate a given failed CA circuit.

[0033] Further referring to FIG. 4, for one embodiment, the host memory controller 402 implements CA recovery circuitry in the form of a selector or multiplexer 434. The multiplexer 434 includes a first signal input 436 that feeds CA information from the CA pin assignment circuitry 422 that was originally designated for feeding to a failed CA circuit. The multiplexer 434 includes a second signal input 437 that receives a key or code from the CA fault state machine 426 that may be applied for transfer during a certain stage of the CA fault recovery operations, and described more fully below. A control input 438 receives acontrol signal from the CA fault state machine 426 that directs the multiplexer 434 to pass the reassigned CA information or the key information along the spare CA link circuit 412.

[0034] With continued reference to FIG. 4, for one embodiment, the memory device 404 is similar to the memory device 104 of FIG. 1, and includes a device memory interface 440 for transferring (transmitting and receiving) the data with the data links 408 via a set of device data I / O circuits 442, and receiving the command / address (CA) signals from the CA links 410 via a set of device CA I / O circuits 444. CA decoder circuitry 446 in the form of a device multiplexer or crossbar circuit 448 and a device CA state machine 450 decodes the received encoded CA information as command, address and control signals and provides the command, address and control signals to memory core circuitry 452 along path 454 during the mission mode of operation. In one embodiment, the device CA state machine 450 includes error detection circuitry 456 that generates a straightforward error code or checksum for the received CA information (over the relatively small number of CA links 410), and utilizes it to monitor (such as through a comparison to a checksum supplied by the host memory controller 402) for received CA errors that might indicate a persistent CA error. For some embodiments, during CA fault recovery operations, a loopback path 458 couples the device multiplexer circuit 448 to the set of device data I / O circuits 442 for transmission of test pattern information back to the host memory controller 402.

[0035] In operation, the memory system 400 generally follows similar steps described in the flowcharts of FIGs. 2 and 3, along with more specific steps in how the host memory controller 402 adjusts the CA encoding protocol, as shown in FIG. 3 at 316. FIG. 5 illustrates one embodiment of a sequence of steps to adjust a CA encoding protocol via a spare CA pin assignment, at 502. The steps of FIG. 5 assume that the memory system 400 has already performed the steps of FIGs 2 and 3 up to the point where the host adjusts the CA encoding protocol, at 316, to recover use of the CA interface. The additional sequencesteps provided in FIG. 5 to perform the adjustment to the CA encoding protocol include having the host memory controller 402 determining a new CA pin assignment that includes at least a substitution of the failed CA circuit with the spare CA link circuitry 412, at 504. The new CA pin assignment may merely identify the spare CA link circuitry 412 as substituting for the failed CA link, or may identify one or more other CA pin assignments that provide for a more efficient swapping-in of the redundant CA resource. Once the new pin assignment is determined, the host memory controller 402 dispatches a second key to the memory device 404, at 506, using the CA interface (such as known good existing links or the spare CA link), and then sends a code over the data interface links 408 that identify the new CA pin assignment for decoding purposes, at 508. After the correction code is received at the memory device 404, the host sends a third key, at 510, indicating a return to the mission mode of operation with the new pin assignment incorporated into the device CA decoder circuitry 446. After a predetermined time, both the host memory controller and the memory device begin operating in the mission mode, at 512.

[0036] FIG. 6 illustrates a timing chart that shows various timings for the events described above with regard to FIG. 5 that are associated with the memory system 400 during the CA fault recovery mode of operation. The top waveform, at 602, illustrates a system clock signal CLK. Timings for grouped CA waveforms are shown at 604, with grouped data waveforms at 606 and spare CA circuit waveforms at 608. At 610, the CA interface signals 604 exhibit a CA error or failure condition that is detected through use of a checksum technique or other method. Dispatching of the first key by the host memory controller 402 along the spare CA link 608, at 612, causes the memory device 404 to enter into the CA fault recovery mode. The host memory controller 402 then sends a test pattern of signals along the CA interface, at 614, with the memory device 404 configured in a loopback mode such that the test pattern of CA signals is fed back to the host memorycontroller 402, such as at 616, along the data interface 606. Once the host memory controller 402 determines the location of the CA error, the second key is sent along the spare CA link 608, at 618, followed by the error correction code sent along the data interface 606, at 620. The third key is then sent along the spare CA link 608, at 620, to bring the system into the mission mode of operation, at 624.

[0037] Referring now to FIG. 7, another specific embodiment of a memory system, generally designated 700, is shown that is configured to perform CA failure recovery operations by changing CA protocol encodings to support disabling of a subset of the CA links (where the subset includes at least one failed CA link resource), and reformatting the CA information for transfer over fewer CA links. The memory system 700 is similar to the system 100 of FIG. 1, and includes a host memory controller 702 and a memory device 704. The host memory controller 702 includes a host memory interface 706 that communicates with the memory device 704 via a set of data links 708 and a set of CA links 710.

[0038] Further referring to FIG. 7, the host memory controller 702 includes mission mode circuitry 720 to manage and control typical data and CA transfers between the host memory controller 702 and the memory device 704 during a mission mode of operation. The mission mode circuitry 720 couples to CA pin assignment circuitry 722 which assigns certain CA links for transferring certain portions of the CA information to the memory device 704. The CA pin assignments form a portion of an overall CA information encoding protocol.

[0039] With continued reference to FIG. 7, the system 700 includes CA fault control circuitry 724 to manage CA recovery procedures during a CA fault recovery mode of operation. The CA fault control circuitry 724 employs a CA fault state machine 726 coupled to the mission mode circuitry 720, and the CA pin assignment circuitry 722. Forone embodiment, test circuitry in the form of a pattern generator 728 is provided to produce test signals for transmission across the CA links during the CA fault recovery mode of operation. The test signals are compared to expected test signals by compare circuitry 730 to search for and isolate a given failed CA circuit.

[0040] Further referring to FIG. 7, for one embodiment, the host memory controller 702 implements protocol selection circuitry 732 that repacketizes the CA information over a subset of the non-failing CA links, and passes the repacketized CA information to the CA pin assignment circuitry 722.

[0041] With continued reference to FIG. 7, for one embodiment, the memory device 704 is similar to the memory device 104 of FIG. 1, and includes a device memory interface 734 for transferring (transmitting and receiving) the data with the data links 708 via a set of device data I / O circuits 736, and receiving the command / address (CA) signals from the CA links 710 via a set of device CA I / O circuits 738. CA decoder circuitry 740 decodes the received encoded CA information as command, address and control signals and provides the command, address and control signals to memory core circuitry 742 along path 744 during the mission mode of operation. In one embodiment, a device CA state machine 746 includes error detection circuitry 748 that generates a straightforward error code or checksum for the received CA information (over the relatively small number of CA links 710), and utilizes it to monitor for received CA errors that might indicate a persistent CA error. For some embodiments, during CA fault recovery operations, a loopback path 750 couples the CA decoder circuitry 740 to the set of device data VO circuits 736 for transmission of test pattern information back to the host memory controller 702.

[0042] In operation, the memory system 700 generally follows similar steps described in the flowcharts of FIGs. 2 and 3, along with more specific steps in how the host memory controller 702 adjusts the CA encoding protocol, as shown in FIG. 3 at 316. FIG. 8illustrates one embodiment of a sequence of steps to adjust a CA encoding protocol via repacketizing over fewer CA links, at 802. The steps of FIG. 8 assume that the memory system 700 has already performed the steps of FIGs 2 and 3 up to the point where the host adjusts the CA encoding protocol, at 316, to recover use of the CA interface. The additional sequence steps provided in FIG. 8 include having the host memory controller 702 disable the failed CA resource(s), at 804. The host memory controller 702 then selects a new encoding protocol that repacketizes the CA information over a reduced subset of the remaining CA links, at 806. For some embodiments, the adjusted CA encoding protocol may include all of the remaining non-failed CA links, or a subset of the remaining links that optimizes performance and bandwidth.

[0043] FIG. 9 illustrates examples of how the CA information may be repacketized using fewer CA links. The upper left portion of FIG. 9 illustrates how the CA information is originally packetized for transfer along fourteen CA links (CAO - CA13) over two clock cycles. The upper right portion of FIG. 9 shows how the CA information may be repacketized by splitting the CA interface into four separate sections, and remapping the CA information over a reduced subset of CA links, over an additional third clock cycle, depending on where the CA failure resides. As an example, should a CA error be detected for any of CA links CAO - CA3, such at 902, then links CAO - CA3 are disabled, and the CA information repacketized along CA links CA4 - CAI 3 over three clock cycles, at 904. The lower left portion of FIG. 9 illustrates how the CA information may be originally packetized for transfer along fourteen CA links (CAO - CA13) over a single clock cycle, with the corresponding lower right portion illustrating a remapping to two cycles. For some embodiments, open unused fields, such as at 906, may be utilized to transfer checksum information from the host memory controller 702 to the memory device 704.

[0044] Referring back to the flowchart of FIG. 8, after the host memory controller 702 selects a repacketized format for the CA encoding protocol that recovers use of the CA interface, the host memory controller 702 sends a second key along the CA interface, at 808, followed by a correction code that identifies the newly selected CA encoding protocol, at 810. At 812, the host memory controller 702 dispatches a third key along the CA interface to return the system to the mission mode of operation. The memory device 704 then disables the failed CA resource(s) at its end, at 814.

[0045] For some embodiments, additional steps may be employed after the memory device disables the failed CA resource(s). For example, at 816, the host memory controller 702 may reconfigure or reprogram one or more timing parameters associated with memory device operation. One example might involve reprogramming a CAS latency, or tCL timing parameter, which generally represents a number of cycles between sending a column address to the memory device 704 and the beginning of data in response. Other timings may also be reprogrammed, depending on the application. Another step that may be taken is to retrain the memory interface circuits, at 818, to verify that the fault-recovered CA circuitry satisfies all timing constraints to properly operate. The system may then return to the mission mode of operation, at 820.

[0046] FIG. 10 illustrates a timing chart that shows various timings for the events described above with regard to FIG. 8 that are associated with the memory system 700 during the CA fault recovery mode of operation. The top waveform, at 1002, illustrates a system clock signal CLK. Timings for grouped CA waveforms are shown at 1004, with grouped data waveforms at 1006. At 1008, the CA interface signals 1004 exhibit a CA error or failure condition that is detected through use of a checksum technique or other method. Dispatching of the first key by the host memory controller 702 along the CA links 710, at 1010, causes the memory device 704 to enter into the CA fault recovery mode. The hostmemory controller 702 then sends a test pattern of signals along the CA interface 710, at1012, with the memory device 704 configured in a loopback mode such that the test pattern of CA signals is fed back to the host memory controller 702, at 1014, along the data interface 708. Once the host memory controller 702 determines the location of the CA error, the second key is sent along the CA links 710, at 1016, followed by the correction code that includes the new CA packetized mapping, which is sent along the data interface 708, at 1018. The third key is then sent along the CA links 710, at 1020, to bring the system into the mission mode of operation, at 1022.

[0047] For one specific embodiment, the memory system 700 described above utilizes no spare CA resources for CA failure recovery operations. In other embodiments, the reformatting techniques described above may be combined with spare CA resources to form a hybrid CA failure recovery technique where a limited number of spare CA resources may be combined with a reformatting of the CA information to improve transfer efficiency and / or bandwidth, depending on the application.

[0048] FIG. 11 illustrates a memory system, generally designated 1100, that employs a three-dimensional stacked (3DS) memory device. For one embodiment, the memory system 1100 includes a host memory controller 1102 that couples to a memory device 1104 via multiple data links 1106, a chip identification (CID) link 1108, and multiple CA links 1110. In some embodiments, the CID link 1108 may be omitted, with the CID information being transmitted over one or more of the CA links 1110. For other embodiments, such as for high-bandwidth memory (HBM) applications, stack ID (SID) information may be used instead of the CID information, and transmitted over one or more of the CA links 1110. A spare CA link 1112 may also be included in the system. The host memory controller 1102 may take the form of any of the host memory controllers described herein.

[0049] For one embodiment, the memory device 1104 takes the form of a threedimensional stacked (3DS) memory device where multiple memory die 1114, 1116 and 1118 are vertically arranged in a stack to form a single package. The lowermost die of the stack, at 1114, is configured as a master die that generally controls accesses to the upper minion die 1116 and 1118. The master die 1114 includes a memory interface 1120 that may take the form of any of the memory interfaces described in prior embodiments, with one embodiment including a spare CA I / O circuit, such as at 1122, and others omitting spare CA resources and utilizing repacketized CA information to recover a failed CA interface. While the other die 1116 and 1118 may employ minion interface circuitry similar to that of the master die 1114, the minion interface circuitry is generally disabled.

[0050] Further referring to FIG. 11, for one embodiment, each of the memory die 1114, 1116, and 1118 include memory core circuitry 1124 and CA decoding circuitry 1126. The CA decoding circuitry includes a multiplexer circuit 1128 that receives the CA information from CA I / O circuits 1130, and a device state machine 1132.

[0051] In operation, the memory system 1100 performs CA fault recovery functions similar to the systems described above, whether through substituting failed CA resources for spare ones, or repacketizing CA information over a subset of functioning CA resources that don’t include the failed CA resource(s). In an effort to ensure that entering into a loopback mode allows for all of a stacked set of die to be accessible to the host memory controller during a fault recovery mode of operation, a chip ID (or SID, depending on the memory type) is encoded in each key transmission. The CID / SID information behaves like an encoded logical rank or bank group address, and is used to address each of the physical memory devices (or 4H stacks in HBM) behind the master device on the base layer of the stack. The corresponding chip identified in the CID / SID information is then included in theloopback path. Additionally, for one embodiment, the overall loopback path includes the top die 1118.

[0052] FIG. 12 illustrates a timing chart similar to those shown in FIGs. 6 and 10, but for a 3DS memory device context utilizing the separate CID link 1108. The top waveform, at 1202, illustrates a system clock signal CLK. Timings for grouped CA waveforms are shown at 1204, with grouped data waveforms at 1206 and spare CA circuit waveforms at 1208. A chip ID (CID) waveform is shown at 1210. At 1212, the CA interface signals 1204 exhibit a CA error or failure condition that is detected in one of the stacked die through use of a checksum technique or other method. Dispatching of the first key by the host memory controller 1102 along the spare CA link 1208, at 1214, along with a chip ID signal (corresponding to the die with the failed CA resource) along the CID link 1108, at 1216, causes the memory device 1104 to enter into the CA fault recovery mode. The host memory controller 1102 then sends a test pattern of signals along the CA interface, at 1218, with the memory device 1104 configured in a loopback mode such that the test pattern of CA signals is fed back to the host memory controller 1102 along the data interface 1106, at 1220. Once the host memory controller 1102 determines the location of the CA error, the second key is sent along the spare CA link 1208, at 1222, along with the chip ID, at 1224, which is followed by the error correction code sent along the data interface 1206, at 1226. The third key is then sent along the spare CA link 1208, at 1228, along with the chip ID, at 1230, to bring the system into the mission mode of operation, at 1232.

[0053] When received within a computer system via one or more computer-readable media, such data and / or instruction-based expressions of the above described circuits may be processed by a processing entity (e.g., one or more processors) within the computer system in conjunction with execution of one or more other computer programs including, without limitation, net-list generation programs, place and route programs and the like, togenerate a representation or image of a physical manifestation of such circuits. Such representation or image may thereafter be used in device fabrication, for example, by enabling generation of one or more masks that are used to form various components of the circuits in a device fabrication process.

[0054] In the foregoing description and in the accompanying drawings, specific terminology and drawing symbols have been set forth to provide a thorough understanding of the present disclosure. In some instances, the terminology and symbols may imply specific details that are not required to practice aspects of the disclosure. For example, any of the specific numbers of bits, signal path widths, signaling or operating frequencies, component circuits or devices and the like may be different from those described above in alternative embodiments. Also, the interconnection between circuit elements or circuit blocks shown or described as multi-conductor signal links may alternatively be singleconductor signal links, and single conductor signal links may alternatively be multiconductor signal links. Signals and signaling paths shown or described as being single- ended may also be differential, and vice-versa. Similarly, signals described or depicted as having active-high or active-low logic levels may have opposite logic levels in alternative embodiments. Component circuitry within integrated circuit devices may be implemented using metal oxide semiconductor (MOS) technology, bipolar technology or any other technology in which logical and analog circuits may be implemented. With respect to terminology, a signal is said to be “asserted” when the signal is driven to a low or high logic state (or charged to a high logic state or discharged to a low logic state) to indicate a particular condition. Conversely, a signal is said to be “deasserted” to indicate that the signal is driven (or charged or discharged) to a state other than the asserted state (including a high or low logic state, or the floating state that may occur when the signal driving circuit is transitioned to a high impedance condition, such as an open drain or open collectorcondition). A signal driving circuit is said to “output” a signal to a signal receiving circuit when the signal driving circuit asserts (or deasserts, if explicitly stated or indicated by context) the signal on a signal line coupled between the signal driving and signal receiving circuits. A signal line is said to be “activated” when a signal is asserted on the signal line, and “deactivated” when the signal is deasserted. Additionally, the prefix symbol “ / ” attached to signal names indicates that the signal is an active low signal (i.e., the asserted state is a logic low state). A line over a signal name (e.g., ‘ < signal name > ’) is also used to indicate an active low signal. The term “coupled” is used herein to express a direct connection as well as a connection through one or more intervening circuits or structures. Integrated circuit device “programming” may include, for example and without limitation, loading a control value into a register or other storage circuit within the device in response to a host instruction and thus controlling an operational aspect of the device, establishing a device configuration or controlling an operational aspect of the device through a one-time programming operation (e.g., blowing fuses within a configuration circuit during device production), and / or connecting one or more selected pins or other contact structures of the device to reference voltage lines (also referred to as strapping) to establish a particular device configuration or operation aspect of the device. The term “exemplary” is used to express an example, not a preference or requirement.

[0055] While aspects of the disclosure have been described with reference to specific embodiments thereof, it will be evident that various modifications and changes may be made thereto without departing from the broader spirit and scope of the disclosure. For example, features or aspects of any of the embodiments may be applied, at least where practicable, in combination with any other of the embodiments or in place of counterpart features or aspects thereof. Accordingly, the specification and drawings are to be regarded in an illustrative rather than a restrictive sense.

Claims

CLAIMS1. An integrated circuit (IC) memory device comprising: a command / address (CA) interface to receive CA information at multiple CA input circuits during a first mode of operation, the CA interface comprising CA decoder circuitry to decode the CA information via a first CA decoding protocol during the first mode of operation; and wherein during a CA recovery mode of operation, the first CA decoding protocol is changed in response to detection of a CA error associated with a failed CA resource.

2. The IC memory device of claim 1, further comprising: a spare CA input circuit; andCA pin assignment circuitry, during the CA recovery mode of operation, to substitute the spare CA input circuit for the failed CA resource.

3. The IC memory device of claim 2, wherein: during the first mode of operation, and prior to detection of the CA error, the spare CA input circuit carries error information used in detecting the CA error.

4. The IC memory device of claim 2, wherein: the CA interface switches from the first mode of operation to the CA recovery mode of operation in response to a bit sequence provided by the spare CA input circuit.

5. The IC memory device of claim 1, wherein: the CA interface switches from the first mode of operation to the CA recovery mode of operation in response to a non-standards-compliant command sequence provided by the CA information.

6. The IC memory device of claim 1, further comprising:CA packet reformatting circuitry, during the CA recovery mode of operation, to repacketize the CA information over a subset of the multiple CA input circuits, the subset of the multiple CA input circuits omitting the failed CA resource.

7. The IC memory device of claim 1, realized as a dynamic random access memory (DRAM) device comprising DRAM storage cells.

8. The IC memory device of claim 7, wherein: during the CA recovery mode of operation, the DRAM storage cells operate in a self-refresh mode of operation.

9. The IC memory device of claim 1, wherein: during the CA recovery mode of operation, the CA interface forms a loopback configuration.

10. A method of operation in a memory device, the method comprising: receiving CA information at multiple command / address (CA) input circuits during a first mode of operation; decoding the CA information via a first CA decoding protocol during the first mode of operation; detecting a CA error caused by a failed CA resource; and during a CA recovery mode of operation, changing the first CA decoding protocol in response to the detecting of the CA error.

11. The method of claim 10, wherein the changing of the first CA decoding protocol in response to the detecting of the CA error comprises: substituting a spare CA input circuit for the failed CA resource.

12. The method of claim 11, further comprising: during the first mode of operation, and prior to detection of the CA error, receiving error information from the spare CA input circuit, the error information used in detecting the CA error.

13. The method of claim 11, further comprising: switching from the first mode of operation to the CA recovery mode of operation in response to a bit sequence provided by the spare CA input circuit.

14. The method of claim 10, further comprising: switching from the first mode of operation to the CA recovery mode of operation in response to a non-standards-compliant command sequence provided by the CA information.

15. The method of claim 10, wherein the changing of the first CA decoding protocol in response to the detecting of the CA error comprises: repacketizing the CA information over a subset of the multiple CA input circuits, the subset of the multiple CA input circuits omitting the failed CA resource.

16. An integrated circuit (IC) dynamic random access memory (DRAM) device, comprising: at least one DRAM die; and at least one command / address (CA) interface formed in the at least one DRAM die to receive CA information at multiple CA input circuits during a mission mode of operation, the CA interface comprising CA decoder circuitry to decode the CA information via a first CA decoding protocol during the mission mode of operation; and wherein during a CA recovery mode of operation, the first CA decoding protocol is changed in response to detection of a CA error by an error code, the CAerror associated with a failed CA resource.

17. The IC DRAM device of claim 16, further comprising: multiple DRAM die stacked vertically; and wherein all of the multiple DRAM die enter the CA recovery mode of operation in response to detection of the CA error.

18. The IC DRAM device of claim 16, further comprising: a spare CA input circuit; andCA pin assignment circuitry, during the CA recovery mode of operation, to substitute the spare CA input circuit for the failed CA resource.

19. The IC DRAM device of claim 16, further comprising:CA packet reformatting circuitry, during the CA recovery mode of operation, to repacketize the CA information over a subset of the multiple CA input circuits, the subset of the multiple CA input circuits omitting the failed CA resource.

20. The IC DRAM device of claim 16, wherein: the error code comprises an error checksum.

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