High temperature ESC for better temperature uniformity and control

Abstract

An electrostatic chuck (ESC) for use in a plasma processing chamber includes a baseplate with a plurality of coolant channels disposed in multiple steps and a dielectric plate with at least a multi-layer radio frequency (RF) grid layer to deliver RF power from an RF source and a multi-zone heater layer to provide heat to the wafer. A plurality of porous plugs are defined within the ESC to deliver conductive gas to fill a gap between the ESC and a wafer received for processing so as to enable uniform heat transfer to the wafer.

Description

HIGH TEMPERATURE ESC FOR BETTER TEMPERATURE UNIFORMITY AND CONTROLBACKGROUND1. Field of the Invention

[0001] The present embodiments relate to an Electrostatic chuck used in a semiconductor processing equipment, and in particular, to an Electrostatic chuck for use in high temperature application.2. Description of the Related Art

[0002] In semiconductor processing, a substrate undergoes various operations to form features that define integrated circuits (IC). The substrate is received on an electrostatic chuck (ESC) disposed in a lower portion of a processing chamber. The ESC provides a supporting surface and reliably holds the substrate in place by applying an attractive force during processing. Conventional ESCs are designed for use in both low temperature and high temperature applications. However, use of the ESCs in high temperature applications oftentimes require consideration of various factors in order to achieve the desired thermal uniformity. Some of the factors that need to be taken into consideration include design of the radio frequency (RF) feed, design of the heater (e.g., embedded heater), material used for backfill, design of channels for delivering conductive gases, etc. For instance, the RF feed (e.g., edge feed) design of the conventional ESCs can lead to potential RF grounding risk, especially when the ESCs are used for high power delivery. The bonding material used in the ESCs have a higher risk of ESC debonding, especially when the temperature goes beyond a certain limit. The channels (i.e., through-holes) used for supplying conductive gases (e.g., Helium) had reasonably sized through-holes that allowed RF to pass in and cause potential plasma light up, especially during high voltage applications. Additionally, the material used for the baseplate of the ESC does not support high bias voltage.

[0003] There is, therefore, a need for an ESC that is designed for high bias voltage operation and include hardware that can withstand high temperature, avoid plasma light-up, reduce or eliminate debonding of the bonding material, and provide a conducive environment for high temperature applications and achieve high throughput with a smaller number of devices.

[0004] It is in this context that embodiments of the invention arise.SUMMARY

[0005] Various implementations describe devices and systems that can be used for performing not only low voltage operations but also high voltage operations and include hardware for withstanding high temperature environment. In various implementations described herein, an Electrostatic chuck (ESC) is designed for use in performing high voltage operations and include a stepped-up baseplate for housing a plurality of coolant channels and a dielectric plate for housing other components of the ESC for effective radio frequency (RF) delivery and prevent RF grounding risk.

[0006] The dielectric plate includes a multi-layer, radio frequency (RF) grid layer for providing high bias voltage uniformly and reducing risk of RF grounding, a multi -zone embedded heater layer with optimized boundary to deliver high temperature to the wafer, a plurality of porous plugs to allow conductive gases to flow to a top of the ESC, to name a few. A bonding layer is disposed between the baseplate and the dielectric plate and is made of a material that is capable of withstanding higher wafer temperature. The plurality of coolant channels is defined using bifilar coils to enable higher heat exchange and provide thermal uniformity, while reducing amount of coolant volume.

[0007] The dielectric plate can be a ceramic plate and include a plurality of layers of ceramic in which the RF grid layer and the heater layer are embedded. The embedded heater layer with optimized boundary meets high temperature requirements. The multi-layer RF grid layer provides a staggered RF conduction path to prevent clacking risk. The porous plugs are designed to prevent plasma light-up and clogging risk during flow of conductive gas(es). The material and the thickness of the material used in defining the bonding layer and the optimized coolant channels are designed to support high wafer temperature. The exposed sections of the ESC are spray coated with a dielectric material to withstand high bias voltage thereby improving reliability and lifetime of the ESC.

[0008] In one implementation, an electrostatic chuck (ESC) for use in a plasma processing chamber, is defined. The ESC includes a baseplate, a dielectric plate, a bonding layer and a plurality of porous plugs. The baseplate is disposed in a lower portion of the ESC and includes a plurality of coolant channels distributed uniformly throughout. The dielectric plate is disposed over the baseplate. The dielectric plate includes a heater layer disposed in a bottom section of the dielectric plate, a radio frequency grid layer disposed over the heater layer, and a plurality of porous plugs disposed uniformly within the dielectric plate. The plurality of porousplugs provides a channel for a conductive gas to flow from a gas source to a top surface of the dielectric plate. The bonding layer is disposed between the baseplate and the dielectric plate to provide a seal.

[0009] In another implementation, a processing chamber is disclosed. The processing chamber includes an upper structure, a lower structure and a confinement ring defined between the upper structure and the lower structure to define a plasma region therebetween. The upper structure is defined at a top portion of the processing chamber and is configured to inject process gas received from a process gas source into the processing chamber. The lower structure is defined at a bottom portion of the processing chamber and includes an electrostatic chuck (ESC). The lower structure is oriented opposite to the upper structure to define a plasma region therebetween. The ESC provides a support surface for receiving and supporting a wafer for processing. The ESC includes a baseplate, a dielectric plate and a bonding layer. The baseplate includes a plurality of coolant channels distributed uniformly throughout. The dielectric plate is disposed over the baseplate. The dielectric plate includes at least a heater layer disposed in a bottom section of the dielectric plate and a radio frequency grid layer disposed over the heater layer. The bonding layer is disposed between the baseplate and the dielectric plate to provide a seal. A plurality of porous plugs is distributed uniformly and is defined to extend from a bottom surface of the baseplate to a top surface of the dielectric plate. The plurality of porous plugs provides a channel for a conductive gas supplied from a gas source to flow from a gas source through the channel and out of the top surface of the dielectric plate.

[0010] Other aspects will become apparent from the following detailed description, taken in conjunction with the accompanying drawings.BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1A illustrates a simplified high level block diagram of a semiconductor plasma processing chamber that uses an Electrostatic Chuck for receiving and supporting a wafer during processing, in accordance with one implementation.

[0012] Figure IB illustrates a simplified high level block diagram of a semiconductor plasma processing chamber that engages an injector for supplying process gas into a plasma region and an Electrostatic Chuck for receiving and supporting a wafer during processing, in accordance with an alternate implementation.

[0013] Figure 2A illustrates a detailed cross-sectional view of the electrostatic chuck used in the processing chamber, in accordance with one implementation. Figure 2B illustrates an expanded view of a portion of an outer edge of the ESC, in accordance with oneimplementation. Figure 2C illustrates an expanded view of an outer portion of the ESC showing details of a baseplate and a dielectric plate, in accordance with one implementation.

[0014] Figure 3 A illustrates an integrated view of different metal layers embedded inside the dielectric plate of the ESC, in accordance with one implementation. Figures 3B and 3C illustrate details of the different metal layers embedded inside the dielectric plate, in accordance with one implementation.

[0015] Figure 4A illustrates an integrated view of an RF grid layer, in accordance with one implementation. Figures 4B-4E illustrate different layers of the RF grid layer identifying different orientations of connection pads, in accordance with one implementation. Figure 4F illustrates an expanded view of a connection pad showing a shape, in accordance with one implementation. Figure 4G illustrates the different orientations of the connection pads in different layers that are integrated into the RF grid layer in accordance with one implementation.

[0016] Figure 5A illustrates a cross-section view of a baseplate showing the plurality of coolant channels that are defined in a stepped manner, in accordance with one implementation.

[0017] Figure 5B illustrates a top view of the coolant channels distributed in the base plate, in some implementations.

[0018] Figure 6A illustrates a cross-sectional view of the ESC showing a porous plug defined thereon, in accordance with one implementation. Figure 6B illustrates an expanded cross-sectional view of the porous plug showing different components, in accordance with one implementation.

[0019] Figure 7 illustrates an embedded heater layer showing dual zone heaters for providing heat to the ESC, in accordance with one implementation.

[0020] Figure 8 illustrates a cross-sectional view of a portion of the ESC that employs a twisted wire heater connection for connecting a heat source to heater elements disposed in the heater layer, in accordance with one implementation.DESCRIPTION

[0021] Embodiments of the disclosure illustrate examples of an Electrostatic Chuck (ESC) used in a plasma processing chamber. The ESC is designed to handle high temperature operations as well as support lower temperature operations for different processes. Depending on the materials to etch and processes to perform, the ESC is designed for both low temperature (e.g., -60 deg C) and high temperature (e.g., 150 deg C or higher) applications. Certain etchingprocesses demand very high power radio frequency (RF) feed / bias voltage and wafer temperature as high as 250 deg C. Broadly speaking, the ESC includes a multi-layered radio frequency (RF) grid for providing high bias voltage and an embedded multi-zone heater layer. The RF grid ensures that the RF power delivered during high power operation is uniformly distributed and is not subject to potential RF grounding risk.

[0022] Wafer level temperature non-uniformity is one of the major concerns for high and low temperature applications and the conventional ESCs are not designed to handle such extreme temperature applications. Consequently, in the convention ESCs, there was a higher risk of bond failure and mechanical failure due to thermal stresses at high temperature. Additionally, there was a higher probability of RF grounding risk, arcing risk, conductive gas light-up, etc., at high RF and bias power.

[0023] The various embodiments of the ESCs defined herein are designed to handle the high temperature operations without the risk of bond failure and mechanical failure. Further, the ESCs are designed so that they can be employed in an existing 300 mm processing chamber and facility to process 200 mm diameter wafer, without having to re-design the processing chamber. In some implementations, the 200 mm diameter wafers are used to accomplish high throughput with less number of semiconductor devices.

[0024] The RF power is provided via RF gaskets disposed on a bottom surface of the ESC and positioned approximately midway between a center and outer edge of the ESC to define a flow path to the RF grid layer that is offset from the center of the ESC. The multilayered RF grid defines a staggered structure with distinct connection patterns to avoid clacking (i.e., Electromagnetic interference) while delivering high RF power during operation. The RF grid includes a plurality of RF grid plates stacked over one another and include a plurality of connection pads defined in each RF grid plate proximal to an outer circumference of the RF grid plate. The stacking is done by aligning the connection pads in each layer to define a conduction path that is staggered. The staggered conduction path helps in improving power delivery while reducing parasitic inductance (and parasitic conductance) and clacking effect.

[0025] The heater layer includes multi-zone heater elements with enhanced heater boundary to provide thermal uniformity for high temperature applications. Heating wires to supply the heat to the heater layer are designed to prevent or reduce detachment of the wires during high temperature operations. Conductive gases, such as Helium, are supplied through a plurality of porous plugs defined in the ESC and are designed to prevent plasma light-up whilemaintaining high temperature coefficient for RF power supplied to the wafer received on the ESC.

[0026] The ESC includes a lower baseplate with stepped up coolant channels distributed uniformly, and an upper dielectric plate, such as a ceramic plate with a plurality of layers for housing and connecting different components, such as the RF grid layer, the heater layer, etc., of the ESC. A bonding layer is defined between the dielectric plate and the baseplate. The dielectric plate can be made of ceramic and is defined as a stepped-up structure. The stepped ceramic structure is designed to reduce edge seal bond erosion and increase reliability. A plurality of coolant channels is disposed in the baseplate. Coolant channels are optimized to better control thermal non-uniformity for a varying range of temperatures. The coolant channels are defined in different steps with the coolant channels in each step sized so as to have same overall surface area of the coolant channels in the different steps is substantially same. By maintaining overall surface area substantially same, it is possible to maintain low flow volume of coolant while achieving uniform heat-transfer coefficient (HTC) throughout.

[0027] The ESC with the distinct stepped ceramic structure, stepped-up coolant channels to correspond with the dimensions of the stepped ceramic structure, the multi-layer RF grid layer, the embedded multi-zone heater layer, and porous plugs for conducting conductive gases, such as Helium, all ensure that the ESC is capable of handling a high temperature operation.

[0028] With the general understanding of the disclosure, specific embodiments will now be described with reference to the different figures. It should be appreciated that the present embodiments can be implemented in numerous ways, such as a device, a system, a process, or a method. Several embodiments are described below.

[0029] Figure 1 A illustrates a simplified, high-level block diagram of a semiconductor plasma processing chamber in which an ESC designed for both high and low temperature applications is engaged, in accordance with one implementation. It should be noted that the plasma processing chamber of Figure 1 A shows only some of the components that are essential in describing the various embodiments and that other components that are essential for performing the different operations are not shown in order to not obscure the essential embodiments. The processing chamber 10 includes a plurality of components that are configured to enclose a plasma region 13. The processing chamber 10 includes a top portion 10a and a bottom portion 10b. A chamber body 10c extends for a height from a top surface of the bottom portion 10b up to a bottom surface of the top portion 10a. The top portion 10a includesan upper structure that is coupled to a process gas source and is configured to inject process gas(es) into the processing chamber 10 to generate plasma. The bottom portion 10b includes a lower structure that is oriented opposite to the upper structure to define a plasma region between the upper and the lower structures. The upper structure disposed in the top portion 10a of the processing chamber 10 includes a showerhead 11, in some implementation. In some implementations, the showerhead 11 is a single unit. In other implementations, the showerhead 11 can be a multi-unit structure (not shown) having an inner electrode (e.g., inner showerhead) and an outer electrode (e.g., outer showerhead). In some implementations, the showerhead 11 is coupled to a set of inductive coupled plasma (ICP) coils 21, which are configured to provide the power from a power source, (e.g., a radio frequency (RF) power source) to the showerhead 11 to ignite the plasma within the plasma region 13. The ICP coils 21 are grounded to provide a return path for the power. In alternate implementations, the showerhead 11 can be coupled to any other power source to receive the power for igniting the plasma. In some implementations, a size (e.g., width or diameter) of the showerhead is greater than a size of the ESC 20 received in the bottom portion 10b of the processing chamber 10. In alternate implementations, the size of the showerhead can be equal to the size of the ESC 20. In some implementations, instead of the showerhead, the upper structure disposed in the top portion 10a of the processing chamber 10 includes a plurality of inlet holes distributed along a bottom surface of the upper structure that is facing the plasma region 13. The plurality of inlet holes is used to provide the process gas from the process gas source into the plasma region 13.

[0030] Figure IB shows an alternate implementation of the plasma processing chamber 10 in which the upper structure of the top portion 10a includes an injector 24. In such implementations, the injector 24 is coupled to the process gas source and is used to supply the process gas(es) into the plasma region 13 defined in the processing chamber 10. Consequently, the injector 24 is coupled to the set of ICP coils 21, which provides the power to the process gas, so as to ignite the plasma within the plasma region 13. This implementation is different from the implementation illustrated in Figure 1 A, which included the showerhead 11 coupled to the process gas source and configured to supply the process gas(es) into the processing chamber.

[0031] In some implementations, the showerhead 11 is configured to be received on top of an adapter 22. The adapter 22 provides a support surface for receiving the showerhead 11. In some implementations where the showerhead is a multi-unit structure, the outer electrode is coupled to the adapter 22. In some implementations where the showerhead is a single unit structure, the outer edge of the showerhead is coupled to the adapter 22. In some implementations, the upper structure is coupled to the lower structure through a couplingcomponent. In some implementations, the coupling component can be a liner that lines an inside surface of the processing chamber. In alternate implementations, the coupling component can be a confinement ring. In the implementations where the coupling component is a liner, the liner 23 provided to line an inside surface of the chamber body 10c is defined to include a top horizontal section 23a, a middle vertical section 23b and a bottom horizontal section 23c. The top horizontal section 23a is disposed over a top surface of the chamber body 10c and a vertical section 23b extends from the top surface of the chamber body 10c to the bottom horizontal section 23c that is defined below an electrostatic chuck (ESC) received in the bottom portion 10b of the processing chamber 10. The adapter 22 is received over the top horizontal section 23a of liner 23. The bottom horizontal section 23c is configured to couple with the bottom surface of the ESC 20.

[0032] In some implementations, the showerhead 11 is coupled to a process gas source (not shown) and is configured to inject the process gas from the process gas source into the plasma region 13 and the ICP coils 21 are configured to heat the process gas before it is injected into the plasma region 13.

[0033] In some implementations, an injector 24 is provided in the showerhead disposed in the top portion 10a of the processing chamber 10. The injector is configured to provide the process gases for generating plasma within the plasma region defined in the processing chamber 10. In some implementations, the injector 24 may be coupled to or have a flow valve integrated within to control flow of the process gas(es) into the processing chamber 10.

[0034] The bottom portion 10b of the processing chamber 10 includes at least an Electrostatic chuck (ESC) 20. The ESC 20 provides a support surface for receiving and supporting a wafer ‘w’ during processing. The ESC 20 can also include an edge ring 19 that is disposed adjacent to and surround a wafer receiving section defined on the ESC 20. The ESC 20 is powered using a power supply, such as radio frequency (RF) power supply 16 via a match network 17, in some implementations. An RF gasket 108 (Figure 2 A) is disposed on a bottom surface of the ESC 20 and is coupled to the RF power supply 16 via the match network 17. The RF power is supplied through the RF gasket to an RF grid layer (not shown) defined in the ESC 20 by following an RF flow path. The RF power provides the necessary power to uniformly heat a gap between the ESC 20 and a wafer w. In some implementations, a single RF power supply (also referred to as “RF generator”) 16 is used to power the ESC 20. In other implementations, more than one RF generator 16 may be connected to the ESC 20, and such RF generators 16 can be configured to operate at various frequencies (e.g., 100kHz, 400kHz, 2MHz, 13.56 MHz, 27 MHz, 60 MHz, etc.). The RF power supplied by the RF generator(s) 16 can be controlled using a signal from a controller 18. Consequently, the RF generator(s) 16 are coupled to the controller 18 and configured to receive the signal from the controller 18 and responsively supply appropriate power through the RF gasket 108.

[0035] A plurality of porous plug assemblies is defined in the ESC 20. The porous plug assemblies are coupled to a conductive gas source 14 and include channels that are configured to flow a conductive gas, such as Helium, supplied from the conductive gas source 14 to a top surface of the ESC 20. A flow valve 15 coupled to the conductive gas source 14 is used to control the flow of the conductive gas through different components of the porous plug assemblies, ensure efficient flow of the conductive gas and prevent plasma light-up. The flow valve 15 is coupled to the controller 18 and configured to receive the flow signal from the controller 18 to control flow of the conductive gas through the porous plugs. Details of the different components of the ESC 20 will be described in detail with reference to Figures 2A, 2B and 2C. Details of the porous plug assemblies will be described in detail with reference to Figures 6A and 6B.

[0036] Simply speaking, the electrostatic chuck (ESC) structure discussed in detail with reference to the different figures includes a dielectric plate that is a multi-layer structure. The multi-layer structure includes at least a radio frequency (RF) grid layer that is defined using RF grid plates stacked one on top of another in a vertical orientation. Each grid plate includes a plurality of connection pads that are disposed uniformly proximal to the outer periphery (i.e., outer circumference) of the grid plate. The connection pads of one layer (e.g., a first layer) are aligned over corresponding connection pads disposed in a successive layer (i.e., a second layer) to form the RF grid layer. The aligned connection pads in the multiple layers of the RF grid plates define a staggered conduction path for the RF power supplied from a bottom surface to a top surface of the RF grid layer. As noted, the staggered conduction path helps in improving power delivery while preventing clacking effect.

[0037] Figure 2A illustrates a cross-sectional view of the ESC 20 showing the different components that enable the ESC 20 to be engaged in both high temperature as well as low temperature applications, in some implementations. Figures 2B and 2C provide expanded view of a portion of the ESC 20 illustrated in Figure 2A. Referring simultaneously to Figures 2A, 2B and 2C, the ESC 20 is shown to include at least a baseplate 101, a dielectric plate 102 and a bonding layer 106 that is disposed between the baseplate 101 and the dielectric plate 102. The baseplate 101 is defined in a bottom portion of the ESC 20. The baseplate extends for a width within the processing chamber and includes a plurality of coolant channels 107 definedthroughout. In the implementation illustrated in Figures 2 A, 2B and 2C, the baseplate 101 is defined to have a stepped profile. The stepped profile is defined to include one or more steps. In some implementations, the stepped profile of the baseplate 101 may be defined to reduce the width of a top surface of the baseplate to a reduced width. In some implementations, the reduced width is defined based on a size of the wafer that is received for processing.

[0038] In the implementation illustrated in Figures 2 A, 2B and 2C, the baseplate 101 includes a first step ‘si’ and a second step ‘s2’. The first step si is defined at a periphery of the baseplate 101 and is defined to extend for a first width ‘wsf and a first height ‘hsi’. A second step s2 is defined immediately above the first step si and is defined to extend for a second width ‘ws2’ and a second height ‘hS2’. In some implementations, the first height hsi is defined to be greater than the second height hsi. In other implementations, the first height hsi and the second height hs2 may be equal. The first width wsiof the first step si may be defined based on a width of the baseplate and the size of the wafer that is received for processing. In some implementations, the first width wsiof the first step si is defined to be between about 53 mm and about 59 mm. In some implementations, the second width wS2 of the second step s2 is defined to be between about 3 mm and about 3.6 mm. The second width wS2 is defined to extend between about 3 mm and about 3.6 mm to accommodate a seal ring. In some implementations, portions of the baseplate 101 is hard anodized. For instance, a top surface (101b) of the baseplate 101 is non-anodized aluminum while remaining portions of the baseplate 101, including a bottom surface (101b) is anodized. In such implementations, the exposed portions of the baseplate 101 that are not anodized are thermally spray coated 111 with a material that is capable of withstanding the higher voltage. The thermal spray coating is done to extend the lifetime of the ESC 20 and for improving reliability. In some implementations, the material used for spray coating the exposed portions of the baseplate 101 is Aluminum Oxide (AI2O3). In some implementations, the thermal spray coating is performed for a thickness defined between 0.30 mm and 0.45 mm. In Figures 2A, 2B and 2C, an outer edge of the bottom surface 101a, the lateral sides 101c, the surfaces (i.e., both the top surface and riser) of steps 1 and 2 (si, s2) defined in the baseplate 101 are thermally spray coated, wherein the areas that are thermally spray coated are non-anodized surfaces. The baseplate 101 is not restricted to aluminum but can be made of other materials that is capable of withstanding the thermal conditions within the processing chamber.

[0039] The bottom surface 101a of the baseplate 101 includes a channel ‘cl’ that is configured to receive an RF gasket 108, in some implementations. The RF gasket 108 is coupled to a RF power supply 16 (of Figure 1 A, e.g., one or more RF generators) via a matchnetwork 17 (of Figure 1A) and is configured to receive a continuous RF power from the RF generators. The RF power received at the RF gasket 108 disposed in the bottom surface 101a flows through the metal baseplate 101 defining an RF flow path 113 to supply the RF power to an RF grid defined in a dielectric plate disposed over the baseplate 101. In addition to channel cl for receiving the RF gasket 108, the bottom surface 101a of the baseplate 101 can include a second channel c2. The second channel c2, in some implementations, can be configured to receive an O-ring (i.e., a second seal O-ring) 132. The second seal O-ring 132 may be used for sealing the baseplate to a bottom surface of the processing chamber 10, in some implementations.

[0040] In some implementations, the plurality of coolant channels 107 defined in the baseplate 101 are stepped up to correspond with the stepped profile of the baseplate 101. Thus, in the implementations illustrated in Figures 2A, 2B and 2C, the plurality of coolant channels includes a first set of coolant channels disposed below the first step si defined in the baseplate 101, a second set of coolant channels disposed below the second step s2 and a third set of coolant channels disposed below the top surface 101b of the baseplate 101, wherein each set of coolant channels has a distinct height and width.

[0041] Figure 5A illustrates an example implementation in which three sets of coolant channels are defined in the baseplate 101 to correspond with the distinct areas defined from the steps si and s2 in the baseplate 101. Of course, the number of sets of coolant channels can vary based on the number of steps defined in the baseplate 101. As shown in Figures 2A-2C and 5, a first set of coolant channels 107a is defined and is uniformly disposed in a first area below the first step si and is defined to extend for a first height hl and a first width wl; a second set of coolant channels 107b is defined and is uniformly disposed in a second area below a portion of the second step s2 and is defined to extend for a second height h2 and a second width w2; and a third set of coolant channels 107c is defined and is uniformly disposed in a third area below the top surface 101b of the baseplate 101 and is defined to extend for a third height h2 and a third width w2. In some implementations, the first height hl is defined to be about 0.52” and the first width is defined to be about 0.34”. The second height h2 is defined to be about 0.7” and the second width w2 is defined to be about 0.27”. The third height h3 is defined to be about 0.8” and the third width w3 is defined to be about 0.25”. Of course, the aforementioned dimensions are provided as examples and variations in the dimensions can also be envisioned depending on the size of the ESC 20. When the height of a coolant channel increases (e.g., h2 to h3) from one step to another, the corresponding width decreases (e.g., w2 to w3). The distinct heights and widths of each set of the coolant channels in different steps are defined so as to havesubstantially same or similar flow cross-sectional area to allow uniform amount of coolant flow (i.e., uniform flow velocity for the coolant) and to improve thermal uniformity and higher heat exchange.

[0042] Figure 5B illustrates an overhead view of the coolant channels 107 defined in the base plate, in some implementations. The location and size of the coolant channels are defined to improve thermal uniformity, support high wafer temperature, better heat transfer, and cover a wider surface area. The surface area covered by the coolant channels 107 in the ESCs described in the implementations illustrated in Figures 5 A and 5B is at least about 2.5 times greater than existing ESCs, allowing the ESCs with the coolant channels 107 to be used for wider range of operating conditions.

[0043] It should be noted that the baseplate 101 can include additional components to assist in mounting the baseplate 101 to the processing chamber and for performing other operations.

[0044] Referring back to Figure Figures 2A, 2B and 2C, the bonding layer 106 is disposed above the baseplate 101 and extends the width of the top surface of the baseplate 101. The bonding layer is made of a material that is capable of withstanding high temperature application. In some implementations, the material used for the bonding layer as well as the thickness of the bonding layer are defined to also support lower wafer temperature. In some implementations, the thickness of the bonding layer 106 is defined to be between about 1 mm and about 3 mm. The material used in the bonding layer 106 is selected to provide a reliable bonding of the aluminum baseplate 101 to the dielectric plate 102 disposed on top of the bonding layer 106, is capable of withstanding both the high temperature as well as low temperature applications, and minimize and prevent occurrence of ESC debonding. In some implementations, the bonding layer 106 is defined to withstand a temperature range of between about 20 deg C to about 200 deg C, and have a thermal conductivity range of between about 1.8 to about 2.3 watts / meter-Kelvin. In some implementations, the bonding layer 106 includes a plurality of conductive paths 106a distributed uniformly throughout for flowing the RF power supplied by the RF power supply 16 via the RF gasket 108 disposed on a bottom surface 101a of the dielectric plate 102, for onward transmission to an RF grid layer 104 disposed in the dielectric plate 102. In some implementations, the number of conductive paths 106a in the bonding layer 106 is equal to the number of conductive paths defined in the dielectric plate 102. In some implementations, the number of conductive paths in the dielectric plate 102 is defined by the number of connection pads defined within the dielectric plate 102. In some implementations, the number of conductive paths 106a is defined to be about 12. In alternateimplementations, the number of conductive paths 106a can be more than or less than 12. In some implementations, the material used for defining the bonding layer is selected to be thermally conductive and electrically insulated (i.e., non-conductive). In some implementations, the bonding material includes one or a combination of nitride and oxide compounds (e.g., aluminum nitride, boron nitride, silicon nitride, aluminum oxide, beryllium oxide, etc.).

[0045] Continuing to refer to Figures 2A, 2B and 2C, the dielectric plate 102 is disposed over the bonding layer 106, such that the bonding layer 106 bonds the baseplate 101 to the dielectric plate 102 to define the integrated ESC 20. The dielectric plate 102, in some implementations, is made of ceramic, and is, therefore, also alternately referred to as ceramic plate 102. The ceramic plate 102 includes a plurality of components that assist in providing high temperature applications and to provide clamping force for holding a wafer ‘w’ in place, when the wafer w is received over the ESC 20 for processing. In some implementations, the ceramic plate 102 includes at least a heater layer 103, an RF grid layer 104, and a plurality of porous plugs 105 to name a few. In addition to the aforementioned components, a clamping layer (not shown) can also be included to provide a clamping force to the wafer w received on the ESC 20.

[0046] In some implementations, the ceramic plate (i.e., dielectric plate) 102 extends for a width that is defined to support and hold the wafer w, when received in the processing chamber 10. In some implementations, the width of the ceramic plate 102 is defined to at least cover a width of the wafer w. In some implementations, the ceramic plate 102 is defined to include a stepped profile. The stepped profile of the ceramic plate 102 is defined to include a step (ws2) that causes the bottom section of the ceramic plate 102 to extend outwardly for a width that is equal to the width wS2 of step 2 (s2) of the baseplate 101 and for a height. The height of the bottom section and the height of the step defined in the ceramic plate 102 constitutes an overall height of the ceramic plate 102. The overall height of the ceramic plate 102 is defined so as to accommodate the various components of the ceramic plate 102. In some implementations, a top surface 102b of the ceramic plate 102 extends for a width that is at least equal to a width of the wafer w received thereon. In alternate implementations, the wafer w extends beyond (i.e., overhangs) the width of the top surface 102b of the ceramic plate 102. The overall width of the step in the bottom section of the ceramic plate 102 is defined to be greater than the width of the underlying bonding layer 106, which is also the width of the top surface 101b of the baseplate 101, in some implementations. In alternate implementations, the width of the underlying bonding layer 106 is greater than the width of the top surface 101b of the baseplate 101. Figure 2C shows one such implementation. In some implementations, the overall width of the step of the ceramic plate 102 is equal to the outer diameter of step s2 of thebaseplate 101. In other implementations, the overall width of the step of the ceramic plate 102 can be greater than or less than the outer diameter of step s2 of the baseplate 101. The outward extension of the ceramic plate step defines an overhang ‘ohl’ over the baseplate 101, such that a gap is defined between a top surface of the step s2 of the baseplate 101 and a bottom surface of the overhang ‘ohl’ of the ceramic plate 102. In some implementations, the gap is used to receive an edge seal O-ring 110. The ceramic plate 102 is designed with the stepped profile to reduce edge seal bond erosion and to increase reliability of the ESC 20.

[0047] In some implementations, an edge ring 19 is disposed over the top surface of the step of the ceramic plate 102. The edge ring 19 is defined to be co-planar with the wafer w, when the wafer w is received on the top surface of the ceramic plate 102. The edge ring 19 is defined adjacent to an outer periphery of the wafer w, when received on the ceramic plate 102, so as to extend the plasma region from the edge of the wafer w to an outer edge of the edge ring19. The top surface 102b of the ceramic plate 102 includes a plurality of kinematic support pins 121. The kinematic support pins 121 are also referred to herein as a ‘mesa’. The kinematic support pins (mesa) 121 are provided for supporting the wafer w, when received over the ESC20. A clamping force is applied to the wafer w through a clamping layer (not shown) defined in the ceramic plate 102, to hold the wafer w in place during processing. An ESC-to-wafer gap 122 is defined between the surface of the wafer w and the top surface of the ceramic plate 102, when the wafer w rests on the mesa (kinematic support pins) 121. A plurality of porous plugs 105 are defined in the ceramic plate 102. The porous plugs 105 are coupled to a conductive gas source 14, such as Helium gas source, through a flow valve 15 and configured to allow the Helium gas (i.e., conductive gas) to flow through the porous plugs out to the top surface of the ceramic plate 102 so as to fill the ESC-to-wafer gap 122. The Helium gas assists in maintaining uniform heat transfer from the ESC 20 to the wafer w. In some implementations, the flow of the Helium gas from the conductive gas source 14 is controlled via the flow valve 15 using signals from a controller 19 coupled to the flow valve 15. Details of the different components of the porous plugs 105 will be defined with respect to Figures 6A and 6B.

[0048] Figure 6A illustrates a cross-sectional view of a porous plug assembly defined in the ESC 20 and Figure 6B illustrates an expanded cross-sectional view of a top portion showing the porous plug 105, in some implementations. Referring simultaneously to Figures 6A and 6B, each porous plug assembly includes a plurality of components that is configured to extend the helium gas flow path from the bottom surface 101a of the baseplate 101 through the body of the baseplate 101 and the ceramic plate 102 and terminate at a top end of a channel tip 105c. Each porous plug 105 is connected to a through-hole 105e defined in the base plate 101,and a plurality of the through-holes 105e are connected to Helium delivery line within the baseplate 101. The through-hole 105e extends from the Helium delivery line of the gas source 14 to a lower end of a bush section 105a. The bush section 105a extends from the lower end to the top surface 101b of the baseplate 101. A porous section 105b of the porous plug 105 extends from the top surface 101b of the baseplate 101 (i.e., from the top of the bush section 105a) for a length within the ceramic plate 102. In some implementations, the length of the porous section 105b is defined to ensure that the conductive gas flows through and the plasma light-up does not occur within porous plug 105. Plasma light-up (i.e., arc’ing) occurs, especially during high temperature and / or high RF power application, when the plasma flows into a gap defined either within the porous plug 105 or between the ESC 20 and the wafer w. In order to avoid occurrence of such light-up, the porous section 105b of the porous plug 105 is filled with porous material along its length so as to allow conductive gas, such as Helium, to flow and avoid the plasma from flowing into the gaps.

[0049] In some implementations, the porous material of the porous section 105b is defined to be a ceramic cylinder with a plurality of holes defined thereon. In some other implementations, the porous material is a ceramic sponge with holes defined through the body of the ceramic sponge. In these implementations, the conductive gas (e.g., Helium gas) flowing from the conductive gas source fills the holes in the porous material (i.e., metallic sponge) so that the plasma generated in the plasma region does not flow into the gap and light-up. The porous plug 105 terminates in a channel tip 105c. The channel tip 105c extends from the top of the porous section 105b to the top surface 102b of the ceramic plate 102. A plug gasket 105d is disposed between the bush section 105a and the porous section 105b. The channel within the bush section 105a and the channel tip 105c are through-holes and the porous section 105b is filled with the porous material. This design of the porous plug 105 prevents clogging of the conductive gas (i.e., Helium) and improves flow of the conductive gas to the gap 122 defined between the ESC 20 and the wafer w (i.e., ESC-to-wafer gap 122), thereby enhancing electrical conductivity between the ESC 20 and the wafer w. In these implementations, the ESC 20 is in electrical contact with the wafer through the conductive gas.

[0050] Helium clogging can occur within the porous plug 105 that can reduce the pressure of the Helium applied in the space between the backside of the wafer, when received on the ESC, and the ceramic plate 102. The reduced pressure can adversely affect the temperature non-uniformity on top of the wafer surface. Helium clogging may occur due to particle generation during bond degassing (i.e., during bond formation between baseplate 101 and the ceramic plate (i.e., dielectric plate) 102). To reduce clogging of porous plug 105, a plug gasket105d is plugged in-between the bush section 105a and the porous section 105b (i.e., at the intersection of the portion of the baseplate 101 and the ceramic plate 102). The plug gasket 105d is used to separate and trap the particles released from the bond material used for bonding the baseplate and the ceramic plate 102 during degassing, thereby preventing the particles of the bond material from making its way into the channel defined in the porous plug assembly and interfering with the Helium flow. In some implementations, the plug gasket 105d is made of a material that can sustain extreme temperature range that is performed in the processing chamber. In some implementations, the plug gasket 105d is made of baked Silicone with Aluminum Oxide (AI2O3). It should be understood that the material used for plug gasket 105d is provided as a mere example and should not be considered restrictive and that other materials that are suitable for the process engaged in the processing chamber can also be used.

[0051] Referring back to Figures 2A, 2B and 2C, the ceramic plate (i.e., dielectric plate) 102 disposed over the bonding layer 106 and the baseplate 101 is a multi-layer structure housing a plurality of components that are used to ensure thermal uniformity during high temperature applications. Some of the components that are housed in the ceramic plate 102 include a heater layer 103 and a RF grid layer 104, which is a multilayer structure. As can be seen, the heater layer 103 is embedded within the ceramic plate 102 with optimized boundary and includes multi-zone heater elements (or simply referred to as “heaters”). In some implementations, the heater layer is a two-zone heater layer with an inner heater and an outer heater disposed on a single plane. In some implementations, the inner heater is designed to cover a central region (i.e., a first zone) and the outer heater is designed to cover a peripheral region (i.e., a second zone) of the plane of the heater layer. Each of the heaters in the multi-zone heater layer 103 is connected to the heat source through a corresponding heater wire. In some implementations, each heater connects to a distinctly different heat source. In such implementations, the different heat sources allow for finer control of temperature uniformity by defining and controlling distinct duty-cycles (e.g., an inner heater is connected to a first heat source to control a first duty cycle and the outer heater is connected to a second heat source to control a second duty-cycle). In alternate implementations, all the heaters connect to a single heat source. Details of controlling the temperature of each heater defined in the multi-zone heater layer 103 will be discussed with reference to Figure 7. Details of the connection of the multi-zone heater layer 103 to the respective heat source will be discussed with reference to Figure 8.

[0052] Figure 7 shows a multi -zone heater layer 103 used for providing high temperature to the wafer w, in some implementations. In this implementation, a two-zone heaterlayer is modelled, wherein each zone is covered by a heater element (simply referred to as ‘heater’). It is to be noted that the multi-zone heater layer is not restricted to two zones but can be extended to include 3 or more heater zones as well. The heater elements are disposed on a single plane and embedded as a layer above the RF grid layer 104 within the ceramic plate 102. In one implementation, a first zone (FZ) heater is defined in the center portion of the heater layer 103 and is covered by an inner heater (TC 2), and a second zone (SZ) is defined adjacent to the first zone FZ and covers the peripheral portion of the heater layer 103. The second zone SZ is heated by an outer heater (TC 1). Each of the inner and the outer heater element is connected to a heat source using a twisted wire connection (117). The heater layer 103 has distinct heater duty cycle to achieve the desired temperature of each zone. For example, a first heater duty cycle is defined for the first zone FZ and a second heater duty cycle is defined for the second zone SZ. Each of the bias duty cycles is capable of achieving a range of between about 5% to about 50%, in some implementations, in order to achieve desired high temperature range from about 70 deg C to about 200 deg C and a temperature non-uniformity of less than 10 deg C. In other implementations, each of the bias duty cycles is capable of achieving a range of between about 15% to about 70%. In some implementations, the first heater zone FZ heated by the first heater extends up to a first width Wfz and the second heater zone heated by the second heater extends from an outer edge of the first width Wfz to a second width Wsz. In some implementations, the width Wfz of the first heater zone FZ extends to about 150 mm of the heater layer 103 and the width Wsz of the second heater zone SZ extends from about 150 mm to about 197.5 mm for a total (ring) width of about 47.5 mm. The first zone FZ and the second zone SZ are configured to provide heat for the entirety of the wafer surface. The first heater zone and the second heater zone, in some implementations, are each accurately and optimally controlled using a corresponding Proportional Integral Derivative (PID) controller. For example, the first zone heater (TC 2) is controlled by a PID inner heater controller (i.e., PIDih controller) and the second zone heater (TC 1) is controlled by a PID outer heater controller (i.e., PIDoh controller), as illustrated in Figure 7.

[0053] In the above implementation, a 200 mm wafer is received for processing and widths of the first zone FZ and the second zone SZ are configured to extend to cover almost the entire width of the wafer w (i.e., 197.5 mm for the 200 mm wafer). In alternate implementations, the widths of the first and the second zones can be based on the width of the wafer w received for processing. It is to be noted that the usage of the term “about” in defining the dimensions of the various components of the ESC 20 may include a variation of + / -15%.

[0054] Figure 8 illustrates a cross-sectional view of a heater wire used to connect a heater element (also referred to as “heater”) in the heater layer 103 to a heat source (not shown). The multi-zone heater layer 103 includes at least two zones with each zone covered using a distinct heater. Of course, the number of heat zones is not restricted to two zones but can include additional zones. A heater wire 114 is used to connect a heater element in the heater layer 103 to a heat source (not shown). The heat source is, in some implementations, disposed outside the processing chamber 10 and is connected to the heater layer 103 through the heater wire 114. In alternate implementations, the heat source may be disposed inside the processing chamber 10. In some implementations, the heat source is a single heat source unit. In alternate implementations, the heat source can include a plurality of distinctly different heat source units. In some implementations, the number of distinctly different heat source units can correspond to number of heat zones defined by the heater elements disposed in the heater layer 103.

[0055] The heater wire 114 is defined by a first end, a second end and a body that extends for a length between the first end and the second end. The first end of the heater wire 114 is designed to connect to the heat source. The body of the heater wire 114 is housed within one or more insulation sleeves / insulation material (116, 118) defined in the baseplate 101 and extends from a bottom surface 101a (Figure 2A) of the baseplate 101 through the bonding layer 106, a bottom surface 102a of the ceramic plate 102 to the heater layer 103 defined in the ceramic plate 102. A second end of the heater wire 114 is designed to connect to one of the first and the second heaters in the heater layer 103. In some implementations, the second end of the heater wire 114 is connected to the heater (first or second heater) using a twisted wire connection 117. In some implementations, the twisted wire connection is designed to be in the form of a J- hook connection 117. The twisted wire connection is defined so as to prevent detachment of the heater wire 114, especially during high temperature applications.

[0056] Referring back to Figures 2A, 2B and 2C, the ceramic plate 102 includes a RF grid layer 104 that is defined above the heater layer 103. The RF grid layer is a multi-layer structure with a plurality of layers of RF grid plate disposed thereon. Details of the multi-layer RF grid layer 104 will be described in greater details with reference to Figures 3A, 3B and 3C.

[0057] Figure 3 A shows an overhead perspective view of the ceramic plate 102, in some implementations. Although the ceramic plate 102 appears as a single layer in Figure 3 A, the ceramic plate 102 actually includes multiple layers housing different components. The different components include at least the heater layer 103 and the multi-layer RF grid layer 104. In addition to the heater layer 103 and the RF grid layer 104, the ceramic plate 102 can also include a clamping layer (not shown). The clamping layer is configured to couple with a powersource to receive power for generating a clamping force for applying to a wafer w received on the ESC 20. The clamping force is designed to reliably hold the wafer w received on the ESC 20. Figure 3B shows the various layers embedded in the ceramic plate 102 and Figure 3C illustrates a cross-sectional view of the embedded layers of the different components in the ceramic plate 102. In the implementation illustrated in Figures 3B and 3C, the ceramic plate 102 is made of about 8 layers (LI, L2, L3, L4, L5, L6, L7 and L8) of metal, wherein one or more of the layers are used to house the different components. For example, layer LI is shown to be the top layer of metal that is closer to the top surface 102b of the ceramic plate 102 and include a high voltage (HV) layer. This layer can be the clamping layer that is coupled to a power source to apply the clamping force to the wafer w received on the ceramic plate 102. Below the HV layer LI, is a second layer L2 of metal that includes a plurality of HV connector pads. The HV connector pads may be configured to connect with a power source and provide the power (e.g., power for generating the clamping force) to the HV layer LI . Layers L3-L6 are disposed below the HV connector pad layer L2 and are part of the RF grid layer 104. The RF grid layer 104 is a multi-layer RF grid structure made of a plurality of RF “plates”, wherein each RF grid plate corresponds to one of the metal layers L3-L6. The top layer of the RF grid layer 104 is layer L3 and layers L4-L6 define connection pad layers having a plurality of connection pads for supplying the RF power from one or more RF generator(s) (e.g., RF power supply 16 of Figure 1 A) to the top layer L3 of the RF grid layer 104. Details of the connections used for supplying the RF power from the RF power supply 16 to the RF grid layer will be described in detail with reference to Figures 4A-4E. Below layer L6 is the multi-zone (MZ) heater layer L7 that includes at least two zones of heaters disposed on a single plane. A contact pad layer L8 is disposed below layer L7 and includes contact pads to connect the HV layer, radio frequency (RF) grid layer 104 and the heater layer 103 to the respective power sources. As can be seen from Figures 3B and 3C, the various metal layers identified in Figure 3B correspond with the respective metal layers formed in the ceramic plate 102. In addition to the various metal layers to accommodate the various components and connect! on / contact pads, the ceramic plate 102 may also include a cavity (e.g., sensor cavity) to accommodate a sensor and a contact pads cavity for receiving additional contact pads to establish connection with other components included (i.e., embedded) in the ceramic plate 102.

[0058] In some implementation, the ceramic plate 102 is defined to include a stepped profile, wherein one or more steps are defined at an outer periphery along the bottom surface 102a of the ceramic plate 102. In the example illustrated in Figure 2A, a step 102c is defined at an outer periphery along the bottom surface 102a of the ceramic plate 102. In someimplementations, the step 102c is defined to have a width ‘wscp’ which, in some implementations, is also the width wS2 of the second step s2 defined in the baseplate 101. In alternate implementations, the width wscpof step 102c can be greater than or lesser than the width Ws2 of step s2 defined in the baseplate 101. As a result of the step 102c extending outward, the diameter (i.e., bottom surface diameter ‘BSd’) of the bottom surface 102a of the ceramic plate 102 is greater than the diameter (i.e., top surface diameter ‘TSd’) of the top surface 102b of the ceramic plate 102. The difference in the top surface diameter TSd and the bottom surface diameter (BSd) of the ceramic plate 102 defines the extent to which the bottom surface 102a of the ceramic plate 102 is extended beyond the top surface diameter TSd of the ceramic plate 102. The stepped profile of the ceramic plate 102 with the step creates an overhang (‘ohl’ in Figure 2C) over the bonding layer 106 and step s2 of the baseplate 101. The dimension of the overhang ‘ohl’ is defined to prevent edge seal bond erosion and increase the overall reliability of the ESC 20.

[0059] The top surface diameter TSd of the ceramic plate 102 is sized to support the wafer w, when received for processing. In some implementations, the diameter TSd of the top surface of the ceramic plate 102 is substantially equal to the diameter of the wafer that is received for processing. In other implementations, the diameter TSd is defined to be greater than the size of the wafer w. In some implementations where the diameter TSd is greater than the size of the wafer w, the top surface 102b of the ceramic plate 102 is designed to include an edge ring 19 at the periphery. In such implementations, the diameter TSd of the top surface 102b of the ceramic plate 102 is defined to be equal to the size of the wafer w and the width of the edge ring 19. The edge ring 19 disposed at the periphery defines a pocket on the top surface 102b of the ceramic plate 102, wherein the size of the pocket is defined to accommodate the size of the wafer w. As previously noted, the top surface 102b of the ceramic plate 102 includes a plurality of mesa (kinematic support pins) 121 distributed uniformly throughout to provide support points for balancing the wafer w.

[0060] In some implementations, the top surface 101b (Figure 2A) of the baseplate 101 extends for a diameter TTDbP’ (i.e., inner top diameter of base plate 101) and the diameter of the bonding layer 106 is equal to or greater than the diameter (ITDbP) of the base plate 101. In some implementations, the diameter (TSd) of the top surface 102b of the ceramic plate 102 is greater than the diameter (ITDbP) of the top surface 101b of the baseplate 101.

[0061] Continuing to refer to Figures 3 A, 3B-1 and 3B-2, in some implementations, the height ‘hcp’ of the ceramic plate 102 is defined to be between about 4 mm and about 5 mm.In some implementations, the bonding layer 106 can be made of a single material or can be madeof a composite material, wherein the material selected is capable of withstanding the high temperature application. In some implementations, the thickness of the bonding layer 106 is between about 1.25 mm and about 1.75 mm. In some implementations, portions of the baseplate 101 is made of anodized material, such as anodized aluminum, and other portions of the baseplate 101, such as the lateral sides of the baseplate 101, the top and side surfaces of the steps si and s2 are made of non-anodized material. The portions that are made of non-anodized material are thermally spray coated to improve reliability and lifetime of ESC. In alternate implementations, the baseplate 101 is made of non-anodized material. In such implementations, the exposed portion of the baseplate 101 are thermally spray coated to improve reliability. In some implementations, the thermal spray coating is extended to an outer edge of the bottom surface 101a of the baseplate 101 to ensure that the non-anodized areas are fully protected and not exposed to the harsh environment of the processing chamber. In some implementations, the thickness of the thermal spray coating done on the non-anodized areas of the baseplate 101 is defined to be between about 0.30 mm and about 0.45 mm.

[0062] Figures 4A-4E show details of the radio frequency (RF) grid layer 104, in some implementations. As noted previously, the RF grid layer 104 is a multi-layered, stacked structure, wherein each layer is defined using a circular RF grid plate. The RF grid plates are stacked one on top of each other to form an integrated RF grid layer 104. Each RF grid plate includes a plurality of connection pads 130 and the integrated RF grid layer 104 is formed by aligning the connection pads 130 of one RF grid plate with the corresponding connections pads 130 in the successive RF grid plate. In some implementations, the RF grid layer 104 includes a total of 4 circular RF grid plates stacked on top of each other.

[0063] Figure 4A shows an overhead view of different RF grid plates stacked on top of each other to define the integrated RF grid layer 104 and Figure 4B shows an overhead view of the top layer of the RF grid layer 104. The view shown in Figure 4 A includes a view of the connection pads 130 defined in the top layer of the RF grid layer 104 aligning with the corresponding connection pads 130 defined at different orientations in the various underlying layers and the overhead view of Figure 4B shows the dimension of the connection pads (alternately referred to as “contact pads”) 130 defined in the top layer. The top layer of the RF grid layer 104 of Figure 4B corresponds with layer L3 of Figure 3B. The connection pads 130 in each RF grid plate are uniformly distributed and proximal to an outer circumference and the number of connection pads 130 defined in each RF grid plate of the RF grid layer 104 is equal to the number of connection pads 130 defined in each successive RF grid plate. The connection pads 130 are defined in each of the RF grid plate such that the connection pads 130 are disposedat substantially same distance from the perimeter of the respective RF grid plate, wherein each RF grid plate is similarly shaped and sized. The connection pads 130 are used to couple the top RF grid plate of the RF grid layer 104 to the RF power supply 16 through a match network 17. A continuous RF gasket 108 is coupled to the RF power supply 16 (Figure 1 A) through the match network 17 (Figure 1 A) to receive the RF power and forward the RF power to the top layer of the RF grid layer 104 (i.e., L3 of the ceramic plate 102 of Figure 3B). The RF power supplied via the RF gasket 108 to the top layer of the RF grid layer 104 through a RF flow path 113 (Figure 2C) defined within the baseplate 101, the conductive paths 106a (Figure 2C) defined in the bonding layer 106, and the RF conduction paths defined in the RF grid plates (i.e., L6, L5, L4, L3 of the ceramic plate 102 of Figure 3B) of the RF grid layer 104. The RF conduction paths in the RF grid plates will be described with reference to Figures 4B-4G.

[0064] In some implementations, the connection pads 130 in the top RF grid plate of the RF grid layer 104 are similar in shape and size (i.e., dimensions) as the connection pads 130 defined in each of the underlying RF grid plates. In alternate implementations, the size and shape of the connection pads 130 in the top RF grid plate are different from that of the connection pads 130 defined in each of the underlying RF grid plates. Figure 4A shows one such implementation wherein the shape of the connection pads 130 in the top layer are shown to be circular, while the shape of the connection pads 130 in the underlying RF grid plates are shown to be tear-drop shaped. Further, the size of the connection pads 130 in the top layer are shown to be different than the size of the connection pads 130 in the underlying RF grid plates.

[0065] Continuing to refer to Figure 4A, below the top layer (i.e., L3 of the ceramic plate 102) of the RF grid layer 104 are 3 additional layers of RF grid plates that correspond with layers L4-L6 of the ceramic plate 102 shown in Figure 3B. The number of layers of RF grid plates are provided as an example and that fewer or greater number of RF grid plates in the RF grid layer 104 can also be envisioned. The number of RF grid plates in the RF grid layer 104 can vary depending on the size of the RF grid layer 104 and of the RF grid plate that makes up the RF grid layer 104. Each underlying RF grid plate (i.e., corresponding to layers L4-L6) disposed below the top layer of the RF grid layer 104 includes the plurality of connection pads 130 disposed uniformly proximal to the circumference of the corresponding RF grid plate and with specific orientations to define a staggered RF grid structure. In some implementations, the connection pads 130 have a tear-drop shape. Figures 4B-4E show the connection pads 130 distributed uniformly in each of the underlying RF grid plates corresponding to layers, L4-L6. As shown, the connection pads 130 are disposed at equal distance from the perimeter of therespective RF grid plate such so that the connection pads 130 can be easily align with one another when defining the RF grid layer 104.

[0066] Figure 4B shows the top layer of the RF grid plate corresponding to layer L3 of ceramic plate 102. The connection pads 130 defined in the top layer is shown to include a round profile, although other shape, such as tear-drop shape can also be envisioned. Figure 4C shows the first underlying RF grid plate corresponding to layer L4 of ceramic plate 102 with the tear-drop shaped connection pads 130 disposed in a first orientation. Figure 4D shows the second underlying RF grid plate corresponding to layer L5 of ceramic plate 102 with the teardrop shaped connection pads 130 disposed in a second orientation, wherein the second orientation has a defined offset from the first orientation. In the implementation illustrated in Figure -4D, the connection pads 130 in the second orientation are disposed at a 90 deg offset from the first orientation. The connection pads 130 in the second RF grid plate are aligned with the corresponding connection pads 130 of the first RF grid plate. Figure 4E shows the third underlying RF grid plate corresponding to layer L6 of ceramic plate 102 with the tear-drop shaped connection pads 130 disposed in a third orientation. In the implementations illustrated in Figures 4B-4E, the connection pads in each layer of the integrated RF grid layer 104 is offset by about 90 deg from the previous layer. The amount of offset can depend on the number of RF grid plates included in the RF grid layer 104. In some implementations, when more than 3 layers of underlying RF grid plates are used to define the RF grid layer, the offset can be less than 90 deg. Thus, the orientation of the connection pads 130 in each RF grid plate can be offset based on the number of RF grid plates making up the RF grid layer 104.

[0067] Figure 4F shows an expanded view of the tear-drop shaped connection pad 130 used in flowing the RF power from the RF gasket to the top RF grid plate of the RF grid layer 104. It is noted that the connection pad 130, in the implementations shown in Figures 4A- 4E, is defined to have a specific profile, which is substantially shaped like a tear-drop. In some implementations, the profile varies from a true tear-drop shape, in that the lower portion of the connection pad 130 is substantially rounded instead of tapering to a point. The connection pads 130 are not restricted to the tear-drop shape but can be defined using other shapes so long as each of the other shapes are capable of providing a staggered RF path when aligned over another in different layers. The tear-drop shape of the connection pad 130 can be described to include an inner arc segment RIA and an outer arc segment ROA separated by a body of defined length ‘LI’. In some implementations, the outer arc segment ROA of the connection pad 130 has a radius rl that is defined to be between about 3.0 mm and about 3.5 mm and the inner arc segment RIA of the connection pad 130 has a radius r2 that is defined to be between about 4.0 mm and about 4.5mm. In some implementations, the length of the body ‘LI’ is defined to be between about 8.7 mm and about 9.3 mm.

[0068] The different orientations of the connection pads 130 in the different RF grid plates and the alignment of the substantially tear-drop shaped connection pads in the stacked RF grid layer 104 define a staggered connection that assists in reducing parasitic inductance (and capacitance), thereby reducing clacking effect (i.e., electromagnetic interference). Typically, parasitic inductance and capacitance are shown to be high in parallel connection pads, which is unavoidable. By adapting the substantial tear-drop shape, the connection pads, the parasitic inductance and capacitance can be substantially reduced. Figure 4G shows the stacked orientation of the connection pads 130 of different layers being aligned one on top of another, wherein connection pad 130a is disposed in 2ndRF grid plate (i.e., L4 of ceramic plate 102) below the top RF grid plate (i.e., L3 of ceramic plate 102) in 1storientation, connection pad 130b is disposed in 3rdRF grid plate below the connection pad 130a of the 2ndRF grid plate in 2ndorientation and connection pad 130c is disposed in the 4thRF grid plate below the connection pad 130b of the 3rdRF grid plate. The top RF grid plate delivers the RF power received through the staggered connection uniformly preventing potential grounding risk. In some implementations, the radius ROA of the outer arc segment of the connection pad 130 is defined to be between about 4.0 mm and about 4.5 mm and the radius RIA of the inner arc segment is defined to be between about 3.0 mm and about 3.5 mm. In some implementations, the length of the body ‘LI’ is defined to be between about 8.7 mm and about 9.3 mm.

[0069] A plurality of coolant channels 107 is distributed in the baseplate 101, in some implementations. In some implementations, the coolant channels 107 are defined using bifilar coils 120, wherein the wiring starts and ends in the middle. Further, the coolant channels 107 are defined as a multi-step structure. The bifilar coils and the multi-step structure of the coolant channels 107 with approximately same surface area enable the coolant channels 107 to maintain equal flow volume of the coolant and uniform heat transfer coefficient (HTC). The optimized multi-step bifilar coolant channels 107 provide for higher surface area, better coolant HTC, and temperature uniformity for a wide range of operating conditions (i.e., by maintaining temperature non-uniformity to a minimum). In some implementations, the multi-step coolant channels 107 are capable of achieving surface area that is at least 2.5 times greater than conventional ESCs that are currently in use.

[0070] The various advantages of the ESC 20 include capability to meet high temperature operations as well as low temperature operations while preventing plasma light up or grounding risk, uniform application of RF feed, optimized heat-transfer-coefficient, extendedlife and reliability, to name a few. For example, the embedded heater layer with optimized multi-zone heaters is capable of providing the high temperature to the ESC. The embedded 8 metal layers in the ceramic layer and the multi-layer RF grid enable uniform RF delivery while avoiding potential grounding risk. The bonding layer of defined thickness (e.g., about 1 mm to about 3 mm) and optimized multi-step coolant channel design support high wafer temperature. The porous plugs with gaskets are designed to reduce conductive gas (e.g., Helium) clogging risk and prevent plasma light up in the gap both inside the channels of the porous plugs and between the ESC and the wafer. The thermal spray coating on the exposed portions of the baseplate as well as in the connection holes (e.g., ESC connection holes) protect the baseplate and the connection holes thereby extending the life and reliability of the ESC. The stepped ceramic plate 102 reduces edge seal bond erosion and increases the reliability of the ESC.

[0071] While the design of the ESC has been described in detail with reference to specific implementations, it will be apparent to those skilled in the art that various changes and modifications can be made, and equivalents employed, without departing from the scope of the appended claims.

[0072] The present embodiments are to be considered as illustrative and not restrictive, and the embodiments are not to be limited to the details given herein, but may be modified within their scope and equivalents of the claims.What is claimed is:

Claims

CLAIMS1. A dielectric plate of an electrostatic chuck (ESC) for use in a plasma processing chamber, comprising: a multi-layer structure representing a radio frequency (RF) grid layer disposed within, wherein multiple layers of the RF grid layer is defined using RF grid plates stacked one on top of another, each RF grid plate having a plurality of connection pads disposed uniformly proximal to an outer circumference, the RF grid layer formed by aligning the connection pads of an RF grid plate in one layer with corresponding connection pads of another RF grid plate disposed in a successive layer of the multiple layers, the aligning of the connection pads defining a conduction path for RF power from a bottom surface of the RF grid layer to a top surface of the RF grid layer.

2. The dielectric plate of claim 1, wherein each connection pad is defined to have a teardrop shape.

3. The dielectric plate of claim 1, wherein orientation of the plurality of connection pads in each RF grid plate is defined to be distinctly different from a successive RF grid plate, so that the conduction path defined in the RF grid layer is staggered.

4. The dielectric plate of claim 1, wherein a first orientation of the plurality of connection pads defined in a first RF grid plate is offset from a second orientation of the plurality of connection pads defined in a second RF grid plate by about 90 degrees, such that the conduction path in the RF grid layer is staggered.

5. The dielectric plate of claim 1, wherein each RF grid plate of the RF grid layer is defined from a metal, and wherein the metal is Tungsten.

6. The dielectric plate of claim 1, wherein the ESC further includes, a baseplate disposed in a lower portion of the ESC, the baseplate having a plurality of coolant channels distributed uniformly throughout; and a bonding layer disposed between the baseplate and the dielectric plate, the bonding layer used to couple the dielectric plate to the baseplate.

7. The dielectric plate of claim 6, wherein the baseplate further includes a RF gasket disposed in a bottom surface and coupled to a RF power source through a matching network, the RF gasket providing the RF power to the RF grid layer in the dielectric plate through the baseplate.

8. The dielectric plate of claim 6, wherein the plurality of coolant channels is disposed in multiple steps, wherein each step of the multiple steps is designed to include a defined number of coolant channels.

9. The dielectric plate of claim 8, wherein the coolant channels in each step are defined by a distinct height and a distinct width, such that a flow cross-sectional area of the coolant channels defined in the multiple steps is substantially equal.

10. The dielectric plate of claim 8, wherein dimensions of the coolant channels disposed in the multiple steps are defined so as to exhibit substantially equal heat-transfer-coefficient and maintain substantially same flow volume.

11. The dielectric plate of claim 8, wherein the top surface of the baseplate is disposed at a defined distance from corresponding top ends of the plurality of coolant channels in each step of the multiple steps.

12. The dielectric plate of claim 6, wherein the plurality of coolant channels is defined using bifilar coils.

13. The dielectric plate of claim 6, wherein the baseplate is defined to include at least a first step disposed along an outer perimeter and defined to extend for a first width and a first height and a second step disposed above the first step and defined to extend for a second width and a second height, and wherein the dielectric plate is defined to include an overhang in a bottom section, an outer edge of the overhang aligning with an outer edge of the second step to define a gap inbetween, and wherein an O-ring is disposed in the gap between the overhang and the second step of the baseplate.

14. The dielectric plate of claim 6, wherein the ESC further includes a plurality of porous plug assemblies distributed uniformly, each porous plug assembly of the plurality of porous plug assemblies is defined to include a plurality of components that extend a flow of a conductive gas supplied from a gas source to flow from a bottom surface of the baseplate through a body of the baseplate and a body of the dielectric plate and terminate at a top surface of the dielectric plate, said each porous plug assembly providing a channel for the flow of the conductive gas supplied from the gas source.

15. The dielectric plate of claim 14, wherein said each porous plug assembly further includes, a lower section extending from a bottom surface of the baseplate to a lower end of a bush section, the lower section having a first through-hole that is coupled to the gas source; the bush section extends from the lower end of to a top surface of the baseplate; a porous section defined immediately above the bush section and configured to extend for from the top surface of the baseplate for a first length within the ceramic plate,a channel tip disposed immediately above the porous section and defined to extend for a second height to a top surface of the dielectric plate, the channel tip having a second through- hole, and a pair of gaskets disposed in the bonding layer to provide a sealing interface.

16. The dielectric plate of claim 15, wherein the porous section and the channel tip are defined in the dielectric plate, wherein the bush section is made of ceramic; and wherein the porous section is defined by a ceramic cylinder with a plurality of holes defined on a surface of the ceramic cylinder.

17. The dielectric plate of claim 15, wherein the porous section is made of ceramic, the ceramic defined to include porosity to allow the conductive gas to flow through.

18. The dielectric plate of claim 15, wherein said each porous plug is designed such that the conductive gas from the gas source flows through the first through-hole of the lower section, the bush section, the porous section, and the second through-hole of the channel tip and out over the top surface of the ESC to fill a gap defined between the top surface of the ESC and a bottom surface of a wafer, when the wafer is received on the ESC for processing.

19. The dielectric plate of claim 6, wherein the bonding layer includes a plurality of conductive paths distributed uniformly, wherein each conductive path of the plurality of conductive paths aligning with a corresponding one of a plurality of connection pads defined in the RF grid layer, the conductive paths designed to conduct radio frequency (RF) power from a RF source to the RF grid layer.

20. The dielectric plate of claim 19, wherein the bonding layer is formed from an electrically non-conductive material.

21. The dielectric plate of claim 19, wherein the bonding layer is formed from a thermally conductive material.

22. The dielectric plate of claim 19, wherein a first number of conductive paths in the bonding layer is equal to a second number of connection pads defined in the RF grid layer.

23. The dielectric plate of claim 1, wherein the multi-layer structure further includes a heater layer disposed in a bottom section of the dielectric plate, the RF grid layer disposed over the heater layer.

24. The dielectric plate of claim 1, wherein the conductive gas is a thermally conductive gas, wherein the thermally conductive gas is Helium, and wherein the dielectric plate is a ceramic plate.

25. An electrostatic chuck (ESC) for use in a plasma processing chamber, comprising:a baseplate disposed in a lower portion of the ESC, the baseplate having a plurality of coolant channels distributed uniformly throughout; a dielectric plate disposed over the baseplate, the dielectric plate is a multi-layer structure representing a radio frequency (RF) grid layer disposed within, wherein multiple layers of the RF grid layer is defined using RF grid plates stacked one on top of another, each RF grid plate having a plurality of connection pads disposed uniformly proximal to an outer circumference, the RF grid layer formed by aligning the plurality of connection pads of an RF grid plate in one layer with corresponding ones of the plurality of connection pads of another RF grid plate disposed in a successive layer of the multiple layers, the aligning of the connection pads defining a conduction path for RF power from a bottom surface of the RF grid layer to a top surface of the RF grid layer; and a bonding layer disposed between the baseplate and the dielectric plate, the bonding layer used to couple the baseplate to the dielectric plate.

26. The ESC of claim 25, wherein a first orientation of the plurality of connection pads defined in a first RF grid plate of the RF grid layer is offset from a second orientation of the plurality of connection pads defined in a second RF grid plate, such that the conduction path in the RF grid layer is staggered.

27. A processing chamber for plasma processing, comprising: an upper structure defined in a top portion of the processing chamber and is configured to inject a process gas received from a process gas source into the processing chamber; a lower structure defined in a bottom portion of the processing chamber and includes an electrostatic chuck (ESC), the lower structure is oriented opposite to the upper structure to define a plasma region therebetween, the ESC providing a support surface for a wafer received for processing, the upper structure coupled to the lower structure through a coupling component, wherein the ESC includes, a baseplate disposed in a lower portion of the ESC and includes a plurality of coolant channels distributed uniformly throughout; a dielectric plate disposed over the baseplate, the dielectric plate includes a multi-layer structure representing a radio frequency (RF) grid layer disposed within; wherein multiple layers of the RF grid layer is defined using RF grid plates stacked one on top of another, each RF grid plate having a plurality of connection pads disposed uniformly proximal to an outer circumference, the RF grid layer formed by aligning the plurality of connection pads of an RF grid plate in one layer with corresponding ones of the plurality of connection pads of another RF grid plate disposed in a successive layer of the multiple layers, the aligning of the connection pads defining a conduction path forRF power from a bottom surface of the RF grid layer to a top surface of the RF grid layer; and a bonding layer disposed between the baseplate and the dielectric plate to provide a seal.

28. The processing chamber of claim 27, wherein the upper structure includes a plurality of inlet holes distributed along a bottom surface of the upper structure facing the plasma region and is coupled to a process gas source to provide process gas through the plurality of inlet holes to the plasma region for generating plasma, a top portion of the confinement ring coupled to an outer edge of the upper structure, and wherein the upper structure is electrically grounded.

29. The processing chamber of claim 27, wherein the upper structure is a multi-unit structure and includes an inner electrode defined in a center and an outer electrode that is adjacent to and surround the inner electrode, the inner electrode includes a showerhead coupled to a process gas source to provide process gas to the plasma region for generating plasma, a top portion of the confinement ring coupled to an outer edge of the outer electrode, and wherein the upper electrode is electrically grounded.

30. The processing chamber of claim 27, wherein the coupling component is a confinement ring disposed between and coupled to the upper structure and the lower structure to enclose the plasma region.

31. The processing chamber of claim 27, further includes a chamber body that extends for a height from a top surface of the lower structure to a bottom surface of upper structure, and wherein the coupling component is a liner that is disposed to line an inside surface of the chamber body, the liner is defined by a top horizontal section, a middle vertical section, and a bottom horizontal section, the top horizontal section is disposed over a top surface of the chamber body, the bottom horizontal section is disposed below a bottom surface of the ESC and the middle vertical section extends from the top surface of the chamber body to the bottom horizontal section.

32. The processing chamber of claim 27, wherein the ESC further includes a plurality of porous plug assemblies distributed uniformly, wherein each porous plug assembly of the plurality of porous plug assemblies is defined to include a plurality of components that extend a flow of a conductive gas supplied from a gas source from a bottom surface of the baseplate to a top surface of the dielectric plate.

33. The processing chamber of claim 27, wherein the baseplate is defined to include at least a first step defined at an outer edge and extend a first step width and a first step height and asecond step defined immediately above the first step and extend inwardly from the first step for a second step width and a second step height, wherein the dielectric plate is defined to extend for a plate diameter and include an overhang in a bottom section that extends over the second step of the baseplate for the second width, a gap is defined between the overhang of the dielectric plate and the second step of the baseplate, and an O-ring is disposed in the gap between the overhang of the dielectric plate and the second step of the baseplate.

34. The processing chamber of claim 33, wherein the plate diameter of the dielectric plate is equal to a diameter of the second step of the baseplate.

35. The processing chamber of claim 33, wherein the plurality of coolant channels is disposed in the baseplate in a plurality of steps, with each step having a distinct set of coolant channels defined to extend for distinct heights and distinct widths, such that the distinct height and the distinct width of the sets of coolant channels disposed in the plurality of steps have substantially equal surface area.

36. The processing chamber of claim 33, wherein the plurality of coolant channels includes at least a first set of coolant channels disposed uniformly below the first step of the baseplate, the first set of coolant channels having a first height and a first width; a second set of coolant channels disposed uniformly below the second step of the baseplate and extending a second height and a second width; and a third set of coolant channels disposed uniformly below the top surface of the baseplate and extending a third height and a third width.

37. The processing chamber of claim 36, wherein the first height is smaller than the second height and the second height is smaller than the third height; and wherein the first width is greater than the second width and the second width is greater than the third width.

38. The processing chamber of claim 27, wherein the multi-layer structure further includes a heater layer, the heater layer disposed in a bottom section of the dielectric plate and the RF grid layer is disposed over the heater layer, and wherein the heater layer includes at least an inner heater to cover an inner zone extending a first diameter and an outer heater to cover an outer zone extending from the first diameter to a second diameter, wherein each of the inner heater and the outer heater is connected to a heat source using a corresponding heater wire.

39. The processing chamber of claim 38, wherein each heater wire includes a first end, a second end, and a body that extends for a length between the first end and the second end, the first end of said each heater wire extends from a bottom surface of the baseplate and connects to the heat source disposed below the baseplate, the second end of said each heater wire connects to the respective one of the inner heater and the outer heater disposed in the heater layer, and the body of the heater wire extends from the first end to the second end through the baseplate and the bonding layer to the heater layer, the body of the heater wire housed in an insulation sleeve defined inside the baseplate, the length of the body defined by a height of the baseplate, and wherein the first end is defined to include a twisted wire connection to reduce detachment of heater wire at high temperature.

40. The processing chamber of claim 38, wherein the heat source includes a first heat source and a second heat source, wherein the first heat source is distinctly different from the second heat source, and wherein the first heat source is connected to the inner heater and the second heat source is connected to the outer heater.

41. The processing chamber of claim 38, wherein the heat source is a single heat source and each of the inner heater and the outer heater is connected to the single heat source.

42. The processing chamber of claim 38, wherein the inner heater is connected to a first heat source to control a first duty-cycle and the outer heater is connected to a second heat source to control a second duty-cycle, the first duty-cycle being different from the second duty-cycle.

43. The processing chamber of claim 27, wherein the processing chamber is a 300 mm wafer processing chamber and the dielectric plate of the ESC defined in the lower structure is designed for processing a 200 mm wafer.

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