Online broadband voltage measurement apparatus based on FPGA + arm architecture

Abstract

An online broadband voltage measurement apparatus based on FPGA + ARM architecture, said apparatus comprising a power supply system, a secondary side voltage monitoring module, a high-speed data transmission module, and a broadband voltage inversion module; the power supply system supplies power to the secondary side output voltage monitoring module, the high-speed data transmission module, and the broadband voltage inversion module; the secondary side voltage monitoring module monitors a secondary side output voltage of a voltage transformer, pre-processes same, and then transmits the pre-processed secondary side output voltage to the broadband voltage inversion module by means of the high-speed data transmission module; and the broadband voltage inversion module inverts the secondary side output voltage to obtain a primary side voltage of the voltage transformer. In the apparatus, inversion calculation of a power grid voltage is completed by means of only a secondary side output waveform of a CVT, the electrical structure of the CVT does not need to be changed, and additional measurement devices do not need to be additionally provided inside the CVT, so that high safety and significant economic benefits are achieved.

Description

Wideband voltage on-line measuring device based on FPGA+ARM architecture TECHNICAL FIELD

[0001] The present application relates to the field of wideband voltage measurement, and particularly relates to a wideband voltage on-line measuring device based on FPGA+ARM architecture. BACKGROUND

[0002] At present, power systems are facing very serious disturbance problems. Electromagnetic energy between system devices can be dynamically interacted and rebalanced, resulting in electromagnetic transient processes such as voltage and current changes, including ferromagnetic resonance and other working conditions. Under the action of low-frequency overvoltage, the magnetic coupling performance of the voltage transformer decreases due to core saturation, and the magnetic leakage increases, resulting in distortion of the secondary voltage waveform. At present, the voltage transformer cannot measure the wideband voltage of the power grid, and the existing on-line monitoring device needs to modify the original structure of the CVT, which will damage the original electrical isolation of the CVT to a certain extent, and the safety cannot be guaranteed.

[0003] Therefore, a reasonable and effective device is needed to monitor the voltage waveform distortion caused by voltage disturbance in real time and obtain an accurate primary voltage waveform.

[0004] SUMMARY

[0005] The present application aims to provide a wideband voltage on-line measuring device based on FPGA+ARM architecture, which comprises a power supply system, a secondary side voltage monitoring module, a high-speed data transmission module and a wideband voltage inversion module.

[0006] The power supply system supplies power to the secondary side output voltage monitoring module, the high-speed data transmission module and the wideband voltage inversion module.

[0007] The secondary side voltage monitoring module monitors the output voltage of the voltage transformer on the secondary side, and performs pretreatment, and then transmits the pretreated secondary side output voltage to the wideband voltage inversion module through the high-speed data transmission module.

[0008] The wideband voltage inversion module inverts the secondary side output voltage to obtain the primary side voltage of the voltage transformer, and the steps include:

[0009] 1) The measured discrete complex frequency domain data is fitted into a transfer function form of a sum of rational fractions by a vector matching method, that is:

[0010] In the formula, H CVT -1 (s) is a transmission characteristic curve function; s is a complex frequency domain parameter; r k , p k , d is H CVT -1the residues, poles and constant term of (s) ; N F is the number of discrete complex frequency domain data;

[0011] 2) Express the inverse function H of the transmission characteristic curve of the voltage transformer with discrete state space equation -1 cvt(s), namely: CVT -1 (s) = C(sI-A) -1 B+D (2)

[0012] wherein A is an N F order diagonal matrix, whose diagonal elements are the residues in equation (1) ; B is an N F order column vector, and the element values are all 1; C is a 1 F order row vector, and the element values are the poles in equation (1) ; D = d, and is a linear term; I is a unit vector;

[0013] 3) Define the parameters a and b, namely:

[0014] wherein At is a time interval;

[0015] 4) Calculate the primary side voltage of the voltage transformer, namely: p (k) = Cx' k + Gv s (k) (4) x' k = a x' k-1 + B'v s (k-1) (5)

[0016] wherein v p (k) is the primary side voltage of the voltage transformer; v s (k) is the secondary side output voltage; x' k , x' k-1 are state variables; G is a matrix; B' is a matrix; v s (k-1) is the secondary side output voltage monitored at the k-1th time.

[0017] Further, the power supply system comprises a power supply, a synchronous step-down rectifier;

[0018] The power supply outputs a voltage with an amplitude of V FB ;

[0019] The synchronous step-down rectifier performs step-down processing on the voltage output by the power supply, so as to meet the voltage supply requirements of different levels;

[0020] The synchronous step-down rectifier realizes different levels of voltage output by changing the resistance value of the grounding resistor.

[0021] The relationship between the resistance value of the grounding resistor and the output voltage of the synchronous step-down rectifier is shown as follows:

[0022] In the formula, R2 is the resistance value of the grounding resistor; V out is the output voltage of the synchronous step-down rectifier; V FB is the output voltage of the power supply; and R1 is the resistance value of the other resistors of the synchronous step-down rectifier except the grounding resistor.

[0023] Further, the secondary-side voltage monitoring module comprises a step-down module and a full-differential amplifier.

[0024] The step-down module performs step-down processing on the secondary-side output voltage, and the step-down ratio V o is the grounding resistor of the step-down module, V all is the sum of the total resistors of the step-down module.

[0025] The full-differential amplifier performs differential amplification on the step-down secondary-side output voltage, thereby realizing the differential tracking function.

[0026] Further, the high-speed data transmission module selects a gigabit Ethernet chip.

[0027] Further, the secondary-side voltage monitoring module stores a voltage signal threshold range, and if the received voltage signal exceeds the voltage signal threshold range, an error signal is generated.

[0028] Further, the high-speed data transmission module is integrated with a Bar2Stream IP core and a FIFO module.

[0029] After the secondary-side voltage monitoring module generates and processes the secondary-side output voltage, the start signal of the Bar2Stream IP core is activated.

[0030] Under the control of the start signal, the high-speed data transmission module inputs and receives the preprocessed voltage signal through the DATA0 to DATA3 interface and writes the voltage signal into the data_back array.

[0031] Subsequently, the Bar2Stream IP core and the FIFO module successfully handshake, and the data in the data_back array is transmitted to the wideband voltage inversion module through the stream_data_out interface.

[0032] The FIFO module is used to adjust the transmission rate, so that the transmission rate of the high-speed data transmission module matches the data generation rate of the secondary-side voltage monitoring module.

[0033] Further, the secondary voltage monitoring module calls the uart_rx_over function to monitor the status of the two serial port receiving buffer to determine whether a new data packet arrives;

[0034] When the data receiving is detected to be completed, the rx_flag flag of the corresponding buffer is cleared to 0, the message state is set to 1, and the data length in the ART receiving buffer of the secondary voltage monitoring module is recorded;

[0035] When the AD_Trigger_on of the secondary voltage monitoring module is 0, the secondary voltage monitoring module is in a buffer state;

[0036] When the AD_Trigger_on is 1, the secondary voltage monitoring module is in a waiting trigger state, at this time, the state of the key is detected to identify whether there is a manual trigger event, if yes, the trigger state is entered immediately, if not, the trigger state is entered automatically after t time;

[0037] When the AD_Trigger_on is 2, the secondary voltage monitoring module is in a trigger state, and the voltage monitoring is performed, and the accurate time of triggering is recorded.

[0038] Further, when monitoring the secondary side output voltage, the secondary voltage monitoring module also calibrates the secondary side output voltage through zero point calibration and full bias calibration to eliminate bias error and gain error;

[0039] The zero point calibration step is: when there is no input signal, a plurality of sampling data are sampled, the average value is calculated, and the data is stored to ensure that the output of the AD chip is 0 when there is no input signal;

[0040] The full bias calibration step is: test input is performed at 10% and 90% of the full range of the secondary voltage monitoring module chip, the ADC offset and gain error are obtained, the transfer function slope is calculated and saved, so as to eliminate the gain error.

[0041] The transfer function slope k is as follows:

[0042] Where V 90％real is the actual voltage value under 90% full range output, V 10％real is the actual voltage value under 10% full range output, V 90％ideal is the ideal voltage value under 90% full range output, V 10％ideal is the ideal voltage value under 10% full range output.

[0043] Further, the control module is further included;

[0044] The control module generates a control command KEYWORD = value1, value2,..., valueN in the form of a string and issues the control command to the secondary side voltage monitoring module;

[0045] The control command KEYWORD includes a sampling frequency, a sampling time, a real-time time, a model parameter and a voltage signal threshold range.

[0046] Further, a visualization module is further included.

[0047] The visualization module includes a triggering interface, a real-time monitoring interface and a parameter configuration interface.

[0048] The triggering interface is used for starting wide-frequency voltage online measurement.

[0049] The real-time monitoring interface is used for displaying secondary side output voltage and primary side voltage.

[0050] The parameter configuration interface is used for configuring parameters of the control command.

[0051] The technical effect of the present application is self-evident. BRIEF DESCRIPTION OF DRAWINGS

[0052] Fig. 1 is a design flowchart of the wide-frequency voltage online measurement device based on the FPGA+ARM architecture provided by the present application.

[0053] Fig. 2 is a physical diagram of the wide-frequency voltage online measurement device based on the FPGA+ARM architecture provided by the present application.

[0054] Fig. 3 is a circuit principle diagram of a voltage reduction module.

[0055] Fig. 4 is a circuit design principle diagram of a THS4521IDR differential amplifier.

[0056] Fig. 5 is a circuit design principle diagram of a gigabit network.

[0057] Fig. 6 is a hardware connection diagram of a gigabit network port.

[0058] Fig. 7 is a schematic diagram of an AD control module.

[0059] Fig. 8 is a schematic diagram of a Bar2Stream module.

[0060] Fig. 9 is a schematic diagram of a FIFO module.

[0061] Fig. 10 is a schematic diagram of a DMA module.

[0062] Fig. 11 is a flow chart of the main program design of the ARM end software.

[0063] Fig. 12 is a schematic diagram of the event triggering interface of the host computer.

[0064] Fig. 13 is a schematic diagram of the real-time monitoring interface of the host computer.

[0065] Fig. 14 is a schematic diagram of the parameter configuration interface of the host computer. DETAILED DESCRIPTION

[0066] The application will be further described in conjunction with the embodiments below, but should not be understood as limiting the above-mentioned subject matter of the application to the following embodiments. Various substitutions and modifications can be made according to ordinary technical knowledge and conventional means in the art without departing from the above-mentioned technical idea of the application, and all of them should be included in the protection scope of the application.

[0067] Embodiment 1:

[0068] Referring to Figs. 1 to 14, a wideband voltage on-line measurement device based on FPGA+ARM architecture comprises a power supply system, a secondary side voltage monitoring module, a high-speed data transmission module and a wideband voltage inversion module.

[0069] The power supply system supplies power for the secondary side output voltage monitoring module, the high-speed data transmission module and the wideband voltage inversion module.

[0070] The secondary side voltage monitoring module monitors the output voltage of the voltage transformer on the secondary side, performs pretreatment, and then transmits the pretreated output voltage on the secondary side to the wideband voltage inversion module through the high-speed data transmission module.

[0071] The wideband voltage inversion module inverses the output voltage on the secondary side to obtain the voltage on the primary side of the voltage transformer, and the steps comprise:

[0072] 1) The measured discrete complex frequency domain data are fitted into the transfer function form of the sum of rational fractions by the vector matching method, i.e.

[0073] In the formula, H CVT -1 (s) is the transmission characteristic curve function; s is the complex frequency domain parameter; r k , p k , d are the residues, poles and constant terms of H CVT -1 (s); N F is the number of discrete complex frequency domain data.

[0074] 2) The inverse function H -1cvt(s), namely: H CVT -1 (s)=C(sI-A) -1 B+D (2)

[0075] wherein A is N F a diagonal matrix with diagonal elements being the residues in equation (1); B is N F a column vector with dimension 1×N and all elements being 1; C is 1×N F a row vector with dimension 1×N and elements being the poles in equation (1); D=d and is a linear term; I is an identity matrix;

[0076] 3) defining the parameters α and β, namely:

[0077] wherein Δt is a time interval;

[0078] 4) calculating the primary voltage of the voltage transformer, namely: v p (k)=Cx′ k +Gv s (k) (4) x′ k =αx′ k-1 +B′v s (k-1) (5)

[0079] wherein v p (k) is the primary voltage of the voltage transformer; v s (k) is the secondary output voltage; x′ k , x′ k-1 are state variables; G is a matrix; B′ is a matrix; v s (k-1) is the secondary output voltage monitored at the k-1th time.

[0080] The power supply system comprises a power supply, a synchronous step-down rectifier;

[0081] The power supply outputs a voltage with an amplitude of V FB .

[0082] The synchronous step-down rectifier performs step-down processing on the voltage output by the power supply, thereby meeting the voltage supply requirements of different levels.

[0083] The synchronous step-down rectifier realizes voltage output of different levels by changing the resistance value of the grounding resistor.

[0084] The relationship between the resistance value of the grounding resistor and the output voltage of the synchronous step-down rectifier is as follows:

[0085] In the formula, R2 is the resistance value of the grounding resistor; V out is the output voltage of the synchronous buck rectifier; V FB is the output voltage of the power supply; R1 is the resistance value of the other resistor of the synchronous buck rectifier except the grounding resistor.

[0086] The secondary-side voltage monitoring module comprises a buck module and a full-differential amplifier;

[0087] The buck module performs buck processing on the secondary-side output voltage, and the buck ratio V o is the grounding resistor of the buck module, V all is the sum of the total resistance of the buck module;

[0088] The full-differential amplifier performs differential amplification on the bucked secondary-side output voltage, thereby realizing the differential tracking function.

[0089] The high-speed data transmission module selects a gigabit Ethernet chip.

[0090] The secondary-side voltage monitoring module stores a voltage signal threshold range, and generates an error signal if the received voltage signal exceeds the voltage signal threshold range.

[0091] The high-speed data transmission module is integrated with a Bar2Stream IP core and a FIFO module.

[0092] After the secondary-side voltage monitoring module generates and processes the secondary-side output voltage, the start signal of the Bar2Stream IP core is activated.

[0093] Under the control of the start signal, the high-speed data transmission module inputs and receives the preprocessed voltage signal through the DATA0 to DATA3 interface and writes the voltage signal into the data_back array.

[0094] Subsequently, the Bar2Stream IP core and the FIFO module successfully handshake, and the data in the data_back array is transmitted to the wideband voltage inversion module through the stream_data_out interface.

[0095] The FIFO module is used to adjust the transmission rate, so that the transmission rate of the high-speed data transmission module matches the data generation rate of the secondary-side voltage monitoring module.

[0096] The secondary-side voltage monitoring module calls the uart_rx_over function to monitor the state of the two serial port receiving buffers, so as to determine whether a new data packet arrives.

[0097] When the data receiving is detected to be completed, the rx_flag flag bit of the corresponding buffer is cleared to 0, the message state is set to 1, and the data length in the ART receiving buffer of the secondary side voltage monitoring module is recorded;

[0098] When the AD_Trigger_on of the secondary side voltage monitoring module is 0, the secondary side voltage monitoring module is in a buffer state.

[0099] When the AD_Trigger_on is 1, the secondary side voltage monitoring module is in a waiting trigger state, at this time, the state of the key is detected to identify whether there is a manual trigger event, if yes, the trigger state is entered immediately, if not, the trigger state is entered automatically after t time.

[0100] When the AD_Trigger_on is 2, the secondary side voltage monitoring module is in a trigger state, and the voltage monitoring is performed, and the accurate time of triggering is recorded.

[0101] When monitoring the secondary side output voltage, the secondary side voltage monitoring module also calibrates the secondary side output voltage through zero point calibration and full bias calibration to eliminate bias error and gain error.

[0102] The zero point calibration step is: when there is no input signal, a plurality of sampling data are sampled, an average value is obtained, and the data is stored to ensure that the output of the AD chip is 0 when there is no input signal.

[0103] The full bias calibration step is: test input is performed at 10% and 90% of the full range of the secondary side voltage monitoring module chip, the ADC offset and gain error are obtained, the transfer function slope is calculated and saved, and thus the gain error is eliminated.

[0104] The transfer function slope k is as follows:

[0105] V 90％real is the actual voltage value under 90% full range output, V 10％real is the actual voltage value under 10% full range output, V 90％ideal is the ideal voltage value under 90% full range output, and V 10％ideal is the ideal voltage value under 10% full range output.

[0106] The device also includes a control module.

[0107] The control module generates a control command KEYWORD=value1,value2,...,valueN and issues it to the secondary side voltage monitoring module in the form of a string.

[0108] The control command KEYWORD includes a sampling frequency, a sampling time, a real-time time, a model parameter, and a voltage signal threshold range. The model parameter includes matrices A, B, C, and a constant D in a discrete state space equation.

[0109] The visualization module is further included.

[0110] The visualization module includes a triggering interface, a real-time monitoring interface, and a parameter configuration interface.

[0111] The triggering interface is used to start the wide-frequency voltage online measurement.

[0112] The real-time monitoring interface is used to display secondary side output voltage and primary side voltage.

[0113] The parameter configuration interface is used to configure parameters of the control command.

[0114] Embodiment 2

[0115] A wide-frequency voltage online measurement device based on an FPGA+ARM architecture includes a power supply system, a secondary side voltage monitoring module, a high-speed data transmission module, and a wide-frequency voltage inversion module.

[0116] The power supply system supplies power to the secondary side output voltage monitoring module, the high-speed data transmission module, and the wide-frequency voltage inversion module.

[0117] The secondary side voltage monitoring module monitors the secondary side output voltage of the voltage transformer, performs preprocessing, and then transmits the preprocessed secondary side output voltage to the wide-frequency voltage inversion module through the high-speed data transmission module.

[0118] The wide-frequency voltage inversion module inverses the secondary side output voltage to obtain the primary side voltage of the voltage transformer, and the steps include:

[0119] 1) The measured discrete complex frequency domain data is fitted into a transfer function form of a sum of rational fractions by a vector matching method, that is:

[0120] In the formula, H CVT -1 (s) is a transmission characteristic curve function; s is a complex frequency domain parameter; r k , p k , and d are the residue, pole, and constant term of H CVT -1 (s).

[0121] 2) The inverse function H -1 cvt(s) of the transmission characteristic curve of the voltage transformer is expressed by a discrete state space equation, that is: CVT -1 (s) = C(sI-A)-1 B+D (2)

[0122] wherein A is N F a diagonal matrix with diagonal elements being the coefficients in equation (1) ; B is N F a 1xN column vector with all elements being 1; C is a 1xN row vector with elements being the poles in equation (1) ; D = d and is a linear term; F a 1xN row vector with elements being the poles in equation (1) ; D = d and is a linear term;

[0123] 3) define the parameters a and b, i.e.

[0124] 4) calculate the primary voltage of the voltage transformer, i.e. p (k) = Cx' k + Gv s (k) (4) x' k = a x' k-1 + b Bv s (k-1) (5)

[0125] wherein v p (k) is the primary voltage of the voltage transformer; v s (k) is the secondary output voltage; x' k is the defined state variable, x' k = a x k-1 + b Bv s (k-1).

[0126] Example 3:

[0127] A wide frequency voltage on-line measurement device based on FPGA+ARM architecture, the technical content is the same as that of example 2, further, the power supply system comprises a power supply, a synchronous step-down rectifier;

[0128] The power supply outputs a voltage with an amplitude of V FB .

[0129] The synchronous step-down rectifier performs step-down processing on the voltage output by the power supply, thereby meeting the voltage supply requirements of different levels;

[0130] The synchronous step-down rectifier realizes voltage output of different levels by changing the resistance value of the grounding resistor;

[0131] The relationship between the resistance value of the grounding resistor and the output voltage of the synchronous step-down rectifier is as follows:

[0132] wherein R2 is the resistance value of the grounding resistor; V outV is the output voltage of the synchronous buck rectifier; V FB V is the output voltage of the power supply; R1 is the resistance value of the synchronous buck rectifier other than the ground resistance.

[0133] Embodiment 4:

[0134] A wide-frequency voltage online measurement device based on an FPGA+ARM architecture, the technical content of which is the same as any one of embodiments 2-3, further, the secondary-side voltage monitoring module comprises a voltage reduction module and a full-differential amplifier;

[0135] The voltage reduction module performs voltage reduction processing on the secondary-side output voltage, and the voltage reduction ratio is V o is the ground resistance of the voltage reduction module, V all is the sum of the total resistance of the voltage reduction module.

[0136] The full-differential amplifier performs differential amplification on the voltage reduction secondary-side output voltage, and realizes the differential tracking function.

[0137] Embodiment 5:

[0138] A wide-frequency voltage online measurement device based on an FPGA+ARM architecture, the technical content of which is the same as any one of embodiments 2-4, further, the high-speed data transmission module selects a gigabit Ethernet chip.

[0139] Embodiment 6:

[0140] A wide-frequency voltage online measurement device based on an FPGA+ARM architecture, the technical content of which is the same as any one of embodiments 2-5, further, the secondary-side voltage monitoring module stores a voltage signal threshold range, and if the received voltage signal exceeds the voltage signal threshold range, an error signal is generated.

[0141] Embodiment 7:

[0142] A wide-frequency voltage online measurement device based on an FPGA+ARM architecture, the technical content of which is the same as any one of embodiments 2-6, further, the high-speed data transmission module integrates a Bar2Stream IP core and a FIFO module.

[0143] After the secondary-side voltage monitoring module generates and processes the secondary-side output voltage, the start signal of the Bar2Stream IP core is activated;

[0144] Under the control of the start signal, the high-speed data transmission module inputs and receives the preprocessed voltage signal through the DATA0 to DATA3 interface and writes it into the data_back array;

[0145] Subsequently, the Bar2Stream IP core and the FIFO module successfully handshake, and the data in the data_back array is transmitted to the broadband voltage inversion module through the stream_data_out interface;

[0146] The FIFO module is used to adjust the transmission rate, so that the transmission rate of the high-speed data transmission module matches the data generation rate of the secondary side voltage monitoring module.

[0147] Embodiment 8:

[0148] A broadband voltage online measurement device based on FPGA+ARM architecture, the technical content of any one of embodiments 2-7, further, the secondary side voltage monitoring module calls the uart_rx_over function to monitor the state of the two serial port receiving buffers, to determine whether there is a new data packet arrives;

[0149] When the data reception is detected to be completed, the rx_flag flag bit of the corresponding buffer is cleared to 0, and the message state is set to 1, and the data length in the ART receiving buffer of the secondary side voltage monitoring module is recorded;

[0150] When the AD_Trigger_on of the secondary side voltage monitoring module is 0, the secondary side voltage monitoring module is in a buffer state;

[0151] When AD_Trigger_on=1, the secondary side voltage monitoring module is in a waiting trigger state, at this time, the state of the key is detected to identify whether there is a manual trigger event, if yes, it immediately enters the trigger state, if not, it automatically enters the trigger state after t time;

[0152] When AD_Trigger_on=2, the secondary side voltage monitoring module is in a trigger state, and the voltage monitoring is performed, and the accurate time of triggering is recorded.

[0153] Embodiment 9:

[0154] A broadband voltage online measurement device based on FPGA+ARM architecture, the technical content of any one of embodiments 2-8, further, when monitoring the secondary side output voltage, the secondary side voltage monitoring module also calibrates the secondary side output voltage through zero point calibration and full bias calibration to eliminate bias error and gain error;

[0155] The zero point calibration step is: when there is no input signal, a plurality of sampling data are sampled, an average value is calculated, and the data is stored, to ensure that the output of the AD chip is 0 when there is no input signal;

[0156] The full-scale calibration step is: at 10% and 90% of the full-scale of the secondary side voltage monitoring module chip, test input is carried out, the ADC offset and gain error are obtained, the transfer function slope is calculated and saved, so as to eliminate the gain error.

[0157] The transfer function slope k is as follows:

[0158] Wherein V 90％real is the actual voltage value under 90% full-scale output, V 10％real is the actual voltage value under 10% full-scale output, V 90％ideal is the ideal voltage value under 90% full-scale output, V 10％ideal is the ideal voltage value under 10% full-scale output.

[0159] Embodiment 10:

[0160] A wide frequency voltage online measurement device based on FPGA+ARM architecture, the technical content is the same as any one of embodiments 2-9, further comprising a control module;

[0161] The control module generates a control command KEYWORD = value1, value2,..., valueN, and issues it to the secondary side voltage monitoring module in the form of a string;

[0162] The control command KEYWORD includes sampling frequency, sampling time, real-time time, model parameters, and voltage signal threshold range. The model parameters include the matrix A, B, C in the discrete state space equation, and the constant D.

[0163] Embodiment 11:

[0164] A wide frequency voltage online measurement device based on FPGA+ARM architecture, the technical content is the same as any one of embodiments 2-10, further comprising a visualization module;

[0165] The visualization module includes a trigger interface, a real-time monitoring interface, and a parameter configuration interface;

[0166] The trigger interface is used to start the wide frequency voltage online measurement;

[0167] The real-time monitoring interface is used to display the secondary side output voltage and the primary side voltage;

[0168] The parameter configuration interface is used to configure the parameters of the control command.

[0169] Embodiment 12:

[0170] A design method of a wide frequency voltage online measurement device based on FPGA+ARM architecture, the steps are as follows:

[0171] S1: design high-precision, high-speed hardware acquisition circuit, can meet the maximum 25MHz sampling rate,

[0172] S2: design can meet the dual-channel isolated output power system, meet the different levels of voltage supply demand in the system,

[0173] S3: design high-speed data transmission module, realize the high-speed transmission of data between the device and the host computer,

[0174] S4: design FPGA end high-speed sampling timing, realize the accurate transmission of data in the hardware,

[0175] S5: design FPGA end high-speed data transmission timing, realize the accurate transmission of data in the hardware,

[0176] S6: design ARM end main program control logic, complete the logic control of ARM to hardware,

[0177] S7: using zero point calibration and full bias calibration to calibrate the signal collected by the data acquisition module, to eliminate the bias error and gain error,

[0178] S8: design wide frequency voltage inversion program, through program call to complete the inversion calculation of secondary voltage,

[0179] S9: design the data communication protocol between the host computer and the lower computer, complete the data transmission from the lower computer to the host computer, and the instruction control from the host computer to the lower computer,

[0180] S10: develop powerful host computer interface, complete the real-time display of voltage waveform calculation results, and realize the function control of host computer to lower computer.

[0181] Step S1 is, using ANALOG DEVICES company's AD9251-80 as analog to digital conversion device. First, the collected voltage signal needs to be reduced pressure processing, the voltage reduction module used in the device is shown in figure 3. The figure VIN1~3 is after the voltage reduction circuit to supply AD chip signal. According to the resistance division principle, the voltage reduction ratio k of the circuit is:

[0182] where V o is the ground resistance, V all is the sum of the total resistance. In the device, k = 1 / 1001.

[0183] After the voltage signal collected is processed by the voltage reduction circuit, a full differential amplifier with model THS4521IDR is selected to process the signal, and the circuit design diagram is shown in FIG. 4. Among them, VIN1 is the original voltage input end, IN0_P and IN0_N are the analog voltage outputs after the differential amplifier, which are also the analog voltage inputs of the AD9251 chip, realizing the differential tracking function.

[0184] Step S2 is specifically to use TAS10-5-WH power supply that can meet the double-way isolated output, to stabilize the output of 5V voltage for the use of circuit board. At the same time, STI3472 synchronous step-down rectifier is used to convert 5V voltage into 1.8V and 3.3V voltage respectively, to ensure the different voltage level requirements of other modules in the circuit. The schematic diagram of the step-down rectifier is shown in FIG. 5, and by changing the resistance value of the grounding resistor, different levels of voltage output are realized. Through formula (2), the values of the resistors R2 corresponding to 1.8V and 3.3V are calculated as 15kΩ and 56.2kΩ.

[0185] Step S3 is specifically to select RTL8211E-VB-CGT gigabit Ethernet chip to build Ethernet circuit, to select 3.3V external circuit power supply, and to use Realtek RTL8211E physical layer chip, HR911130C network port device and 25MHz crystal oscillator in the hardware circuit. The hardware connection block diagram is shown in FIG. 6. 125MHz clock frequency is selected

[0186] Step S4 is specifically to design an IP core named AD_Control in VIVADO software, as shown in FIG. 7, to process the analog signal and generate the corresponding trigger signal. In addition, the AD_Control module also integrates the data monitoring function. The high 16 bits of the three limit signals are defined as the high threshold, and the low 16 bits are defined as the low threshold. If the collected voltage signal exceeds these thresholds, the module will generate an error signal, so as to realize real-time monitoring and abnormal processing.

[0187] Step S5 is specifically integrating a Bar2Stream IP core in the Vivado development environment, as shown in FIG. 8, to optimize data processing. The IP core receives a four-way 16-bit wide data stream through the DATA0 to DATA3 interface input. The start signal serves as a trigger mechanism to indicate the start of data acquisition. M00_AXIS is a 64-bit wide parallel output interface, and the data block size for each transmission is set to 2 bytes. When AD data acquisition is complete, the output signal done is pulled high, and at the same time, the start signal of the Bar2Stream IP core is activated. Under the control of the start signal, the data input through DATA0-DATA3 is written into the data_back array. Subsequently, when the Bar2Stream successfully communicates with the FIFO module, the data in the data_back array is efficiently transmitted to the next module through the stream_data_out interface.

[0188] Considering that the data rate generated by the AD module may not completely match the transmission rate of the direct memory access (DMA) module (as shown in FIG. 9), a FIFO (First In First Out) module (as shown in FIG. 10) is introduced to ensure the continuity and integrity of data transmission. The use of the FIFO module significantly reduces the risk of data transmission errors and data loss due to rate mismatch. To the maximum extent allowed by the resources of the FPGA, the depth of the FIFO is increased as much as possible in this article. In this design, the depth of the FIFO is set to 16384, and the width of the data signal TDATA is configured to 8 bits.

[0189] Step S6 is specifically as follows: the design idea of the engineering main program is shown in FIG. 11. First, the system is started, including serial communication initialization, message analysis initialization, TCP / IP protocol stack initialization, and AD module initialization. After entering the main loop, the system calls the uart_rx_over function to monitor the status of the two serial port receive buffers to determine whether new data packets have arrived. Once data reception is detected, the system clears the rx_flag flag bit of the corresponding buffer to 0 and sets the message status to 1, indicating that the data is ready and ready for subsequent processing. At the same time, the system records the data length in the UART receive buffer to prepare for message analysis.

[0190] Next, the system decides different trigger logic by switch statement according to the value of AD_Trigger_on. When AD_Trigger_on=0, the system is in the buffer state; when its value is 1, the system enters the waiting trigger state and detects the state of the key to identify whether there is a manual trigger event. Regardless of whether the key is pressed, the system will perform a timing trigger operation, and calculate the RMS value of the recorded waveform; when AD_Trigger_on is 2, it indicates that the system has triggered and data recording is performed, at which time the buzzer beeps and the accurate time of triggering is recorded.

[0191] Step S7 is specifically: bias calibration is performed on the three A / D sampling channels, 60 sampling data are sampled and the average value is calculated when there is no input signal, and the data is stored, so as to ensure that the output of the AD chip is 0 when there is no input signal, thereby performing zero point calibration.

[0192] At 10% and 90% of the full range of the AD chip, test inputs are performed to obtain ADC offset and gain error, the transfer function slope is calculated and saved, so as to eliminate the gain error.

[0193] Step S8 is specifically: the inversion calculation of the voltage is completed by the state space equation, and the formula is shown. A three-dimensional empty array x of size 2×n×2 is defined, where n is the dimension of the state space parameter matrix, and idx is a state switching parameter. Considering that A and C are complex matrices, the imaginary part and the real part of the matrix are split for operation in the calculation process, so as to simplify the operation process. The idx parameter defined in the array x alternately changes between 0 and 1 according to the index i of the current sample, so that only half of the state variables need to be updated each iteration, thereby effectively reducing the memory access frequency and the amount of calculation. k = αx′ k-1 + B′v s (k-1) (3) v p (k) = Cx′ k + Gv s (k) (4)

[0194] wherein

[0195] Step S9 is specifically: the control command is issued to the ARM end in the form of a string, where KEYWORD is a specific keyword indicating the sampling frequency, sampling time, real-time time, model parameter, threshold value, AD calibration value, and other parameters issued from the upper computer, value1, value2,..., valueN are user-set parameter values. The lower computer parses the format string by calling a function, extracts the corresponding system values according to KEYWORD, sets them, and formats a new string as a response. KEYWORD = value1, value2,..., valueN (6)

[0196] The upper computer reads the lower computer parameters also in the form of a string, where AT+GET is a fixed command prefix, indicating that it is a GET command, ID is a device identifier, and KEYWORD is a specific keyword indicating the sampling frequency, sampling time, real-time time, model parameter, threshold value, AD calibration value, and other parameters from the hardware part. AT+GET ID = xx, KEYWORD = value1, value2,..., valueN (7)

[0197] Step S10 is specifically: the upper computer visualization software is developed based on the NET Framework platform using WPF (Windows Presentation Foundation) language. WPF technology separates interface display and logic control, with XAML language used in the foreground to develop the interface and C# language used in the background as the control language. The development platform used in this paper is.NET, the programming language is C#, and the integrated development environment is Visual Studio 2022. The final designed upper computer system interface layout is shown in Figures 12-14. The system consists of three core interfaces, namely: event triggering interface, real-time monitoring interface, and parameter configuration interface.

[0198] The method proposed above can realize the design of the wideband voltage online monitoring device of the power grid.

Claims

1. A wide frequency voltage on-line measuring device based on FPGA+ARM architecture, characterized in that: The power supply system, the secondary side voltage monitoring module, the high-speed data transmission module, and the wideband voltage inversion module are included. The power supply system supplies power for the secondary side output voltage monitoring module, the high-speed data transmission module, and the wideband voltage inversion module. The secondary side voltage monitoring module monitors the secondary side output voltage of the voltage transformer, pre-processes the secondary side output voltage, and then transmits the pre-processed secondary side output voltage to the wideband voltage inversion module through the high-speed data transmission module. The wideband voltage inversion module inverts the secondary side output voltage to obtain the primary side voltage of the voltage transformer, and the steps include: 1) The measured discrete complex frequency domain data is fitted into the transfer function form of the sum of rational fractions by the vector matching method, i.e. where H CVT -1 (s) is a transfer function; s is a complex frequency domain parameter; r k , p k , d is H CVT -1 the residue, pole and constant term of H NF is the number of discrete complex frequency domain data 2) the transmission characteristic curve inverse function H of the voltage transformer is expressed by a discrete state space equation 1 cvt(s), i.e.: H CVT -1 (s) = C(sI - A) -1 B + D (2) where A is N F a diagonal matrix whose diagonal elements are the coefficients in equation (1); B is N F a 1 x 1 column vector whose elements are all 1; C is a 1 x N F a row vector whose elements are the poles in equation (1); D = d, and is a linear term; I is an identity matrix; 3) defining the parameters a and β, i.e.: In the formula, Δt is the time interval. 4) Calculate the primary side voltage of the voltage transformer, i.e. v p (k) = Cx' + Gv k + Gv s (k) (4) x′ k = ax′ k-1 + B'v s (k-1) (5) where v p (k) is the primary side voltage of the voltage transformer; v s (k) is the secondary side output voltage; x′ k , x′ k-1 is the state variable; G is the matrix; B′ is the matrix; v s (k-1) is the k-1th monitoring The secondary side output voltage of the voltage transformer.

2. The wideband voltage on-line measuring device based on F7PGA+ARM architecture according to claim 1, characterized in that: The power supply system includes a power supply and a synchronous step-down rectifier. The power supply outputs a voltage of V FB V. The synchronous step-down rectifier reduces the voltage output by the power supply to meet the voltage supply requirements of different levels. The synchronous step-down rectifier realizes different levels of voltage output by changing the resistance value of the grounding resistor. In the formula, the relationship between the resistance value of the grounding resistor and the output voltage of the synchronous voltage-reducing rectifier is shown as follows: In the formula, R2 is the resistance value of the grounding resistor; V out is the output voltage of the synchronous buck rectifier; V FB is the output voltage of the power supply; and R1 is the resistance value of the other resistor of the synchronous buck rectifier except the grounding resistor. 3.The wideband voltage on-line measuring device based on FPGA+ARM architecture according to claim 1, characterized in that: The secondary side voltage monitoring module includes a step-down module and a fully differential amplifier. The voltage reduction module reduces the output voltage on the secondary side, and the voltage reduction ratio is V o is the ground resistance of the voltage reduction module, V all is the sum of the total resistance of the voltage reduction module; The fully differential amplifier differentially amplifies the stepped-down secondary side output voltage to realize differential tracking.

4. The wideband voltage on-line measuring device based on FPGA+ARM architecture according to claim 1, characterized in that: The high-speed data transmission module selects a gigabit Ethernet chip.

5. The wideband voltage on-line measuring device based on FPGA+ARM architecture according to claim 1, characterized in that: The secondary side voltage monitoring module stores a voltage signal threshold range, and generates an error signal if the received voltage signal exceeds the voltage signal threshold range.

6. The wideband voltage on-line measuring device based on FPGA+ARM architecture according to claim 1, characterized in that: The high-speed data transmission module integrates a Bar2Stream IP core and a FIFO module. After the secondary side voltage monitoring module generates and processes the secondary side output voltage, the start signal of the Bar2Stream IP core is activated. Under the control of the start signal, the high-speed data transmission module inputs and receives the pre-processed voltage signal through the DATA0 to DATA3 interface and writes it into the data_back array. Subsequently, the Bar2Stream IP core and the FIFO module successfully handshake, and the data in the data_back array is transmitted to the wideband voltage inversion module through the stream_data_out interface. The FIFO module is used to adjust the transmission rate to match the transmission rate of the high-speed data transmission module with the data generation rate of the secondary side voltage monitoring module.

7. The wideband voltage on-line measuring device based on FPGA+ARM architecture according to claim 1, characterized in that: The secondary side voltage monitoring module calls the uart_rx_over function to monitor the status of the two serial port receive buffers to determine whether new data packets have arrived. After detecting that the data reception is complete, the rx_flag flag bit of the corresponding buffer is cleared to 0, the message state is set to 1, and the data length in the U secondary side voltage monitoring module ART receive buffer is recorded. When the AD_Trigger_on of the secondary side voltage monitoring module is 0, the secondary side voltage monitoring module is in a buffer state. When AD_Trigger_on is 1, the secondary side voltage monitoring module is in a waiting trigger state, at which time the state of the key is detected to identify whether there is a manual trigger event; if so, it immediately enters the trigger state, and if not, it automatically enters the trigger state after t time. When AD_Trigger_on = 2, the secondary side voltage monitoring module is in the trigger state, voltage monitoring is carried out, and the accurate time of triggering is recorded.

8. The wideband voltage on-line measuring device based on FPGA+ARM architecture according to claim 1, characterized in that: When monitoring the secondary side output voltage, the secondary side voltage monitoring module also calibrates the secondary side output voltage through zero calibration and full bias calibration to eliminate bias error and gain error. The zero calibration step is: when there is no input signal, a plurality of sampling data are sampled, an average value is obtained, and the data are stored to ensure that the output of the AD chip is 0 when there is no input signal. The full bias calibration step is: at 10% and 90% of the full scale of the secondary side voltage monitoring module chip, test input is carried out, ADC offset and gain error are obtained, a transfer function slope is calculated and saved, and thus the gain error is eliminated. The transfer function slope k is given by: where V 90％real is the actual voltage value at 90% full scale output, V 10％real is the actual voltage value at 10% full scale output, V 90％ideal is the ideal voltage value at 90% full scale output, V 10％ideal is the ideal voltage value at 10% full scale output.

9. The wideband voltage on-line measuring device based on FPGA+ARM architecture according to claim 1, characterized in that: The control module is also included. The control module generates a control command KEYWORD = value1, value2,..., valueN and issues it to the secondary side voltage monitoring module in the form of a string. The control command KEYWORD includes sampling frequency, sampling time, real-time time, model parameters, and voltage signal threshold range; the model parameters include matrix A, B, C in the discrete state space equation and constant D.

10. The wideband voltage on-line measuring device based on FPGA+ARM architecture according to claim 9, characterized in that: The visualization module is also included. The visualization module includes a trigger interface, a real-time monitoring interface and a parameter configuration interface. The trigger interface is used to start wideband voltage online measurement. The real-time monitoring interface is used to display the secondary side output voltage and the primary side voltage. The parameter configuration interface is used to configure the parameters of the control command.

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