Memory error correction method, memory controller, memory module, and processor

Abstract

A memory error correction method, a memory controller, a memory module, and a processor. The method comprises: in response to a read operation on a memory module, a memory controller acquires data from the memory module; the memory controller performs error correction on the data; if the error correction fails, the memory controller reads error correction indication information from buffers of a plurality of memory chips in the memory module, and determines, on the basis of the error correction indication information, a memory chip in which an error occurs; and the memory controller performs error correction on the data on the basis of the memory chip in which the error occurs. In this way, when the error correction fails, the memory controller performs error correction again on the data on the basis of the memory chip in which the error occurs; and when the memory controller performs error correction for the second time, the known information used for the error correction comprises the memory chip in which the error occurs, in addition to the data acquired from the memory module, thereby improving the error correction capability of the memory controller, and thus improving the error correction capability of a memory system and the reliability of the data in the memory module.

Description

Memory correction method, memory controller, memory module and processor

[0001] The present application claims priority from the Chinese patent application No. 202411074537.2 filed on August 6, 2024, and entitled "Memory correction method, memory controller, memory module and processor", the content of which is incorporated herein by reference in its entirety. TECHNICAL FIELD

[0002] The present application relates to the field of computer technology, and in particular to a memory correction method, a memory controller, a memory module and a processor. BACKGROUND

[0003] In storage technology, a memory system includes a memory controller and a double data rate synchronous dynamic random access memory (DDR SDRAM). The DDR SDRAM, also known as a memory module, can be referred to as a memory module or a memory. The memory module includes a plurality of memory particles, also known as dynamic random access memory (DRAM), wherein a part of the memory particles are used to store data, referred to as data particles (data device), and another part of the memory particles are used to store error correcting codes (ECC) of the data, also known as redundant information, referred to as ECC particles (ECC device), which are used to check whether the data stored in the memory particles has an error; the memory controller can correct errors in a code word based on the ECC, that is, the memory controller can implement system-level error correction. The memory particles also include an on-die ECC (OD ECC) engine, which can detect errors in data belonging to the same code word as the check code based on the check code, and correct a single-bit error in the data if the error occurs. If multiple bits in the data have errors, they may be corrected as single-bit errors by the on-die ECC engine, or the on-die ECC engine may not detect the error, resulting in a silent error, that is, the on-die ECC engine in the memory particles can implement particle-level error correction.

[0004] In the related art, when reading data, the on-chip error correction engine first detects errors of the memory particles, and once the on-chip error correction engine detects errors, the on-chip error correction engine immediately reports to the memory controller to assist the memory controller to locate the memory particles with errors, and then the memory controller recovers data of the memory particles with errors based on the redundant information in the ECC device, and re-reads the data. However, in the above method, for the case that multiple bits have errors, the on-chip error correction engine has a high probability of failing to detect errors, so that the memory controller cannot correct errors of the memory particles, resulting in a risk of silent data errors and affecting the reliability of memory data. SUMMARY

[0005] Embodiments of the present application provide a memory error correction method, a memory controller, a memory bank and a processor, which can reduce the risk of silent data errors, improve the error correction capability of the memory system, and improve the reliability of data in the memory bank.

[0006] Embodiments of the present application provide the following technical solutions:

[0007] In a first aspect, embodiments of the present application provide a memory error correction method applied to a memory controller, the method comprising: in response to a read operation on a memory bank, the memory controller acquiring data from the memory bank; the memory controller correcting errors of the data; if the error correction fails, the memory controller reading error correction indication information from the cache of a plurality of memory particles in the memory bank, and determining a memory particle with errors according to the error correction indication information; and the memory controller correcting errors of the data based on the memory particle with errors.

[0008] The result of the memory controller detecting data in a plurality of memory particles and the subsequent steps include three cases. The first case is that no error is detected, and the memory controller directly returns the data to the processor. The second case is that the number of detected errors is within the error correction capability of the error correction algorithm used by the memory controller, that is, the error correction is successful, and the memory controller corrects the data by using the error correction algorithm and returns the corrected data to the processor. The third case is that the number of detected errors exceeds the error correction capability of the error correction algorithm, that is, the error correction fails, and the memory controller determines the memory particle with errors in the memory bank based on the error correction indication information stored in the cache of the memory particle, and corrects the data.

[0009] In the method, the on-chip error correction engine-based granular error correction and the memory controller-based system-level error correction are coupled, the data is corrected by the memory controller, compared with the error correction only relying on the on-chip error correction engine, the silent error and the mis-corrected error of the on-chip error correction engine that are not detected can be corrected, so that the data silent error risk and the data mis-corrected risk in the memory granule can be reduced; in addition, in the case that the first error correction fails, the error correction result of the on-chip error correction engine is used to determine the memory granule in which the error occurs, and then the data is corrected again based on the memory granule in which the error occurs; since the known information used for error correction of the memory controller in the second error correction includes the information of the memory granule in which the error occurs in addition to the data obtained from the memory bank, compared with the error correction only relying on the memory controller, the error correction capability of the memory controller can be improved, so that the error correction capability of the memory system and the reliability of the data in the memory bank can be improved.

[0010] In a possible implementation of the first aspect, the depth of the buffer is greater than a preset threshold.

[0011] The memory granule in the memory bank is provided with a buffer, and the buffer has a certain data storage depth. Specifically, the depth of the buffer is greater than a preset threshold. In the embodiment of the application, the error correction indication information generated by the on-chip error correction engine after performing error correction is stored in the buffer provided in the memory granule, and the buffer has a depth greater than a preset threshold, which can effectively prevent the error correction indication information stored in the buffer from being covered by subsequent access when the data is corrected by using the error correction code (EC) algorithm, thereby ensuring the effectiveness and reliability of the memory error correction scheme.

[0012] In a possible implementation of the first aspect, the memory granule includes an on-chip error correction engine, and the method further includes: in response to a read operation on the memory bank, the on-chip error correction engine acquires data in the memory granule; the on-chip error correction engine corrects the acquired data, and if the error correction fails, stores the error correction indication information of the memory granule in which the error correction fails in the buffer.

[0013] The on-chip error correction engine writes the error correction indication information of the memory granule into the buffer of the memory granule, so that the memory controller can locate the memory granule in which the error occurs by reading the error correction indication information in the buffer, thereby enabling the granular error correction and the system-level error correction to cooperate with each other, achieving full utilization of the redundant resources, and being conducive to improving the error correction capability of the memory system under a fixed redundant configuration.

[0014] In a possible implementation of the first aspect, the memory controller reads the error correction indication information from the buffer of the plurality of memory particles in the memory bank, and determines the memory particle with the error according to the error correction indication information, including: if the error correction indication information indicates that any memory particle has an error, the memory controller determines the memory particle as the memory particle with the error; and / or, if the error correction indication information includes a data access address of any memory particle, the memory controller determines the memory particle as the memory particle with the error.

[0015] In the embodiments of the present application, the memory controller can read the error correction indication information in the buffer of the memory particle, and locate the memory particle with the error through the error correction indication information. If the error correction indication information indicates that a certain memory particle has an error, the memory controller determines the memory particle as the memory particle with the error; and / or, if the error correction indication information includes a data access address in a certain memory particle, the memory controller determines the memory particle as the memory particle with the error.

[0016] It can be understood that the error correction indication information can be used to indicate the memory particle with the error in the plurality of memory particles in the memory bank. In the present implementation, the error correction indication information is not specifically limited. For example, the error correction indication information can indicate the error correction state of the on-chip error correction engine through a preset identification field, for example, the values of the identification field are 00B, 01B and 10B, which respectively represent that the error correction state of the memory particle is no error, correctable error and uncorrectable error. The error correction indication information can also store the data access address corresponding to the data with the uncorrectable error in the memory particle, and indicate the memory particle with the error when the data access address is stored in the buffer.

[0017] In a possible implementation of the first aspect, the preset threshold is determined according to the frequency of occurrence of uncorrectable errors of the on-chip error correction engine in a first time length; wherein the first time length is the time length between a first time and a second time, the first time is the time when the on-chip error correction engine stores the error correction indication information in the buffer, and the second time is the time when the memory controller reads the error correction indication information from the buffer of the plurality of memory particles in the memory bank.

[0018] The preset threshold is determined according to the frequency of the on-chip error correction engine failing to correct errors in the first time length. The first time length is the time length between the time when the on-chip error correction engine stores the error correction indication information in the buffer and the time when the memory controller reads the error correction indication information from the buffer of the plurality of memory particles in the memory bank. Since the back pressure operation of the memory controller on the read-write process of the memory bank may not take effect immediately, the system write command to the memory bank is still being executed. Therefore, in the embodiment of the application, the buffer is set to a depth greater than the preset threshold, and the preset threshold is determined according to the frequency of the on-chip error correction engine failing to correct errors in the first time length. The error correction indication information stored in the buffer can be guaranteed not to be covered by other accesses before the EC error correction reading is executed, thereby guaranteeing the accuracy of the memory controller in determining the memory particle with errors according to the error correction indication information. Thus, the in-system particle with uncorrectable errors can be corrected when the system has uncorrectable errors, and the memory system error correction capability is improved.

[0019] It should be noted that the depth of the buffer should meet the depth corresponding to the frequency of the on-chip error correction engine failing to correct errors in the first time length. The depth of the buffer can also be greater than the depth corresponding to the frequency of the on-chip error correction engine failing to correct errors in the first time length. Those skilled in the art can set the depth of the buffer according to actual needs.

[0020] In a possible implementation of the first aspect, the method further includes: performing error correction on the data by the memory controller, and if the error correction fails, the method further includes: reporting a synchronous external abort (SEA).

[0021] In the above method, the system ECC engine of the memory controller determines that the error correction fails after performing error detection on the data, that is, the number of detected errors exceeds the error correction capability of the error correction algorithm adopted by the memory controller. The memory controller reports a synchronous external abort (SEA) and performs subsequent error correction processes.

[0022] In a possible implementation of the first aspect, the memory controller performs error correction on the data based on the memory particle with errors, including: the memory controller confirming that the data access address does not belong to a direct memory access (DMA) address, and performing error correction on the data based on the memory particle with errors.

[0023] The memory controller needs to determine the type of data access of the data before correcting the data based on the memory particle where the error occurs. If the storage address of the data is not a direct memory access (DMA) address, the data is corrected. Since the direct memory access (DMA) address cannot resist the memory access request, that is, the service access request of the memory cannot be limited, if the data access address of the data is a DMA address, the first error information is generated, and the first error information is used to indicate that the subsequent error correction cannot be performed.

[0024] In the above method, the type of data access address of the data is determined, and if the data access address is not a direct memory access (DMA) address, the data is corrected. If the data access address is a DMA address, the corresponding error indication is generated.

[0025] In a possible implementation of the first aspect, if the error correction fails, the memory controller reads error correction indication information from the cache of the plurality of memory particles in the memory bank, and determines the memory particle where the error occurs according to the error correction indication information, comprising: if the error correction fails, the memory controller resists the read-write process of the memory bank; the memory controller obtains the data in the memory bank again, if the data obtained twice is consistent, the error correction indication information of the plurality of memory particles is read from the cache of the plurality of memory particles, and the memory particle where the error occurs is determined according to the error correction indication information.

[0026] The resistance refers to the generation of memory access from the central processing unit (CPU) source or memory access path. The memory controller determines whether the memory address corresponding to the read operation is a direct memory access address. Only when the memory address is a memory address other than a direct memory access (DMA) address, the memory controller can resist the read process of the memory bank, thereby preventing other read-write processes from rewriting the data to be corrected, and further avoiding data inconsistency.

[0027] In the above method, the memory controller resists the read process of the memory bank, thereby preventing other read-write processes from rewriting the data to be corrected, and further avoiding data inconsistency. In addition, by obtaining the data from the memory bank again to determine whether the data is rewritten before the resistance takes effect, in the case where the data is not rewritten, the subsequent data error correction process is continued, which can ensure the effectiveness of the data error correction process and further ensure the consistency of the data.

[0028] In a possible implementation manner of the first aspect, the memory controller performs error correction on the data based on the memory particles having errors, including: if the number of the memory particles having errors is less than or equal to the number of the ECC particles in the memory bank, performing error correction on the data based on the memory particles having errors.

[0029] In the case that the number of the memory particles having errors is less than or equal to the number of the ECC particles in the memory bank, the memory controller can perform error correction on the data based on the memory particles having errors.

[0030] In the case that the number of the memory particles having errors is determined, the error correction capability of the memory controller can meet the error correction on the target number of the memory particles having errors, where the target number is the number of the ECC particles in the memory bank. The number of the memory particles having errors being less than or equal to the number of the ECC particles in the memory bank indicates that the number of the redundant memory particles in the memory bank is greater than or equal to the number of the memory particles having errors, that is, the number of the memory particles having errors is within the error correction capability of the memory controller, and the memory controller can perform error correction on the data in the memory particles having errors based on the data in the memory particles not having errors in the memory bank.

[0031] In a possible implementation manner of the first aspect, the data access address includes a bank group Bank Group, a bank Bank, a row Row and a column Col of the data.

[0032] The data access address includes bank group Bank Group, bank Bank, row Row and column Col information corresponding to the data, and the data access address is used to indicate storage location information of the data in the memory particles.

[0033] In a possible implementation manner of the first aspect, the buffer has a data storage width, and the data storage width is determined according to the data access address.

[0034] The buffer has a data storage width, and the data storage width is determined according to the data access address. The data storage width needs to be able to meet the address information of the bank group Bank Group, the bank Bank, the row Row and the column Col of the data.

[0035] In a possible implementation manner of the first aspect, the buffer includes a first in first out (FIFO) buffer.

[0036] Specifically, the buffer can be a first-in first-out (FIFO) buffer. It can be understood that the buffer in the embodiments of the present application can also use other buffers with a data storage depth, and the present application does not limit the data storage structure of the buffer.

[0037] The memory controller can read the buffer through a read command in an in-band mode or read the buffer through an out-of-band mode, and the embodiments of the present application do not limit this.

[0038] In a possible implementation of the first aspect, the back pressure on the read-write processes of the memory bank includes suspending, based on a software generated interrupt (SGI) request, a central processing unit (CPU) access to the memory.

[0039] The processor includes a plurality of cores, and the process of back pressure on the read-write processes of the memory bank includes: if the number of errors of data accessed by a memory read operation of any processor core exceeds a target threshold, the core initiates a halt core broadcast through an SGI; other cores in the processor set a halt core flag after receiving the halt core broadcast to stop memory access and wait to be woken up; the core that initiates the halt core broadcast detects whether the halt core of other cores is completed after a preset time, and if all the cores are halted, the memory controller enters a subsequent data recovery process; if any core is not halted, the memory controller records a halt core failure and wakes up other cores to return an error state.

[0040] In the above method, the read process of the memory bank is limited by halting the cores of the processor, which can prevent other read-write processes from rewriting the data to be corrected from the access source, thereby effectively ensuring the consistency of the data.

[0041] In a possible implementation of the first aspect, the back pressure on the read-write processes of the memory bank includes shutting down a path between a scheduling queue of the memory controller and a memory port.

[0042] The memory controller includes a dynamic memory controller (DMC) and a physical layer (PHY), and the DMC includes a scheduler configured to schedule read-write commands of the memory bank. The memory controller shuts down a path between the scheduler and the PHY by back pressure on a command scheduling queue in the memory controller, thereby preventing other read-write processes from rewriting the data to be corrected from the scheduling queue. The back pressure is more refined, the cores of the processor do not stop working, and the impact on the upper-layer service is small.

[0043] In the method, the consistency of the data is effectively ensured by preventing other read-write processes from overwriting the data to be corrected by shutting down the passage between the scheduling queue of the memory controller and the memory port.

[0044] In a possible implementation of the first aspect, if the error correction fails, the method further includes: storing the data into an error content register of the memory controller; and storing a data access address of the data into an uncorrectable error (UCE) address register of the memory controller.

[0045] The memory controller acquires the data in the memory again, and if the data acquired twice is consistent, includes: acquiring the data to be verified based on the data access address stored in the UCE address register; and if the data to be verified is consistent with the data in the error content register, determining that the data acquired twice is consistent.

[0046] The memory controller includes an error content register and an uncorrectable error (UCE) address register. After the memory controller performs error correction on the data and the error correction fails, the memory controller stores the data corresponding to the error correction failure into the error content register of the memory controller, and stores a data access address of the data corresponding to the error correction failure into the UCE address register of the memory controller. Before performing subsequent EC error correction, the memory controller acquires the data to be verified based on the data access address stored in the UCE address register, and compares the data to be verified with the data in the error content register. If the two are consistent, it indicates that the data has not been overwritten, and the memory controller can perform subsequent EC error correction.

[0047] In a possible implementation of the first aspect, if the data to be verified is inconsistent with the data in the error content register, a second error information is generated.

[0048] If the data to be verified is inconsistent with the data in the error content register, it indicates that the data has been overwritten, and a second error information is generated. The second error information indicates that the error correction fails, the memory controller ends the data error correction process, returns to an error state, and does not perform subsequent EC error correction.

[0049] In a possible implementation of the first aspect, after performing error correction on the data, the memory controller writes back the data after error correction to the memory grain.

[0050] The memory controller writes back the data after error correction to the memory address corresponding to the read operation, that is, replaces all the data in the position corresponding to the memory address in each memory grain.

[0051] In the method, the memory controller writes the corrected data back to the memory grain, so that correct data can be read when the same memory address is read next time, and the reliability of data in the memory bank is improved.

[0052] In a possible implementation of the first aspect, the method further includes: after the memory controller writes the corrected data back to the memory grain, releasing the back pressure on the read-write process of the memory bank.

[0053] In the method, after the error correction processing is completed, the restriction on the service access request of the memory is released, if the memory controller restricts the read-write process of the memory bank by stopping the processor core, the memory controller releases the restriction by waking up the processor core; if the memory controller restricts the read-write process of the memory bank by back pressure command scheduling queue, the memory controller releases the restriction on the command scheduling queue, so that the channel between the scheduler and the physical interface protocol is connected, thereby releasing the restriction on the read-write process of the memory bank.

[0054] In the second aspect, the embodiments of the present application further provide a memory error correction method, which is executed by a memory bank including a plurality of memory grains, each of the memory grains including a cache, the method including: in response to a read operation on the memory bank, performing error correction on data in the memory grain by an on-chip error correction engine; and if the error correction fails, storing error correction indication information of the memory grain with error correction failure in the cache by the on-chip error correction engine.

[0055] The result of the detection of the data in the memory grain by the on-chip error correction engine and the subsequent steps include three cases, the first case: no error is detected, the on-chip error correction engine directly returns the data to the processor; the second case: the number of detected errors is within the error correction capability of the on-chip error correction engine, that is, a single-bit error of the data is detected, the on-chip error correction engine can correct the single-bit error and return the corrected data to the processor; the third case: the number of detected errors exceeds the error correction capability of the on-chip error correction engine, that is, two or more errors of the data are detected, in which case, the on-chip error correction engine stores error correction indication information of the memory grain with error correction failure in the cache, so that the memory controller can obtain the error correction indication information from the cache when performing memory error correction processing, and determine the memory grain with error based on the error correction indication information, thereby correcting the data.

[0056] In a possible implementation of the second aspect, the depth of the cache is greater than a preset threshold.

[0057] The memory grain in the memory bank is provided with a cache, and the cache has a certain data storage depth. Specifically, the depth of the cache is greater than a preset threshold. In the embodiment of the application, the cache provided in the memory grain stores the error correction indication information generated by the on-chip error correction engine after performing error correction, and the cache has a depth greater than the preset threshold, which can effectively avoid the error correction indication information stored in the cache being covered by subsequent access when the data is corrected by using the error correction code (EC) algorithm, thereby ensuring the effectiveness and reliability of the memory error correction scheme.

[0058] In a possible implementation of the second aspect, the on-chip error correction engine stores the error correction indication information of the memory grain that fails in error correction in the cache, including that the on-chip error correction engine stores the data access address of the memory grain that fails in error correction in the cache of the memory grain that fails in error correction.

[0059] The on-chip error correction engine stores the data access address of the memory grain that fails in error correction in the cache of the memory grain that fails in error correction, so that the memory controller can locate the memory grain that fails in error correction by reading the error correction indication information in the cache, thereby enabling the grain-level error correction and the system-level error correction to cooperate with each other, achieving full use of the redundant resources, and being conducive to improving the error correction capability of the memory system under a fixed redundant configuration.

[0060] In a possible implementation of the second aspect, the data access address includes a bank group (Bank Group) of the data, a bank (Bank) of the data, a row (Row) of the data, and a column (Col) of the data.

[0061] The data access address includes bank group (Bank Group) information, bank (Bank) information, row (Row) information, and column (Col) information of the data, and the data access address is used to indicate the storage location information of the data in the memory grain.

[0062] In a possible implementation of the second aspect, the cache has a data storage width, and the data storage width is determined according to the data access address.

[0063] The cache has a data storage width, and the data storage width is determined according to the data access address. The data storage width needs to be able to store the address information of the bank group (Bank Group), the bank (Bank), the row (Row), and the column (Col) of the data.

[0064] In a possible implementation of the second aspect, the cache includes a first in first out (FIFO) cache.

[0065] Specifically, the buffer can be a first-in first-out (FIFO) buffer. It can be understood that other buffers with a data storage depth can also be used in the embodiments of the present application, and the present application does not limit the data storage structure of the buffer.

[0066] The memory controller can read the buffer through a read command in an in-band mode or through an out-of-band mode, and the embodiments of the present application do not limit this.

[0067] In a third aspect, the embodiments of the present application provide a memory controller, which comprises:

[0068] a data acquisition module configured to acquire data from the memory bank in response to a read operation on the memory bank;

[0069] a data error correction module configured to correct the data. If the correction fails, the data error correction module reads error correction state indication information from the buffers of the plurality of memory grains in the memory bank, determines a memory grain in which an error occurs according to the error correction state indication information, and corrects the data based on the memory grain in which the error occurs.

[0070] The constituent modules of the memory controller provided in the third aspect of the present application can also perform the steps described in the first aspect and various possible implementation manners, and details are described above in the first aspect and various possible implementation manners.

[0071] The third aspect and any one of the implementation manners of the third aspect correspond to the first aspect and any one of the implementation manners of the first aspect, respectively. The technical effects corresponding to the third aspect and any one of the implementation manners of the third aspect can be found in the technical effects corresponding to the first aspect and any one of the implementation manners of the first aspect, which will not be described herein again.

[0072] In a fourth aspect, the embodiments of the present application provide a memory bank, which comprises a plurality of memory grains, each of which comprises a buffer, and the memory bank is configured to execute the memory error correction method provided in the second aspect.

[0073] The constituent modules of the memory bank provided in the fourth aspect of the present application can also perform the steps described in the second aspect and various possible implementation manners, and details are described above in the second aspect and various possible implementation manners.

[0074] The fourth aspect and any one of the implementation manners of the fourth aspect correspond to the second aspect and any one of the implementation manners of the second aspect, respectively. The technical effects corresponding to the fourth aspect and any one of the implementation manners of the fourth aspect can be found in the technical effects corresponding to the second aspect and any one of the implementation manners of the second aspect, which will not be described herein again.

[0075] In a fifth aspect, a memory controller is provided, comprising: a memory for storing computer instructions; and a processor for executing the computer instructions stored in the memory, so that the memory controller performs the memory correction method provided in the first aspect or any possible implementation manner of the first aspect.

[0076] In a sixth aspect, a computing device is provided, comprising a memory controller and a memory bank for temporarily storing data, wherein the memory controller is configured to perform the memory correction method provided in the first aspect or any possible implementation manner of the first aspect.

[0077] In a seventh aspect, a computer readable storage medium is provided, which is configured to store at least one piece of program code for performing the memory correction method provided in the first aspect or any possible implementation manner of the first aspect and the second aspect and any implementation manner of the second aspect.

[0078] In an eighth aspect, a computer program product comprising at least one piece of program code is provided, which, when executed by a computing device, causes the computing device to perform the memory correction method provided in the first aspect or any possible implementation manner of the first aspect and the second aspect and any implementation manner of the second aspect. BRIEF DESCRIPTION OF DRAWINGS

[0079] FIG. 1 is a schematic diagram of a memory bank according to an embodiment of the present application;

[0080] FIG. 2 is a schematic diagram of a memory grain comprising an on-chip correction engine according to an embodiment of the present application;

[0081] FIG. 3 is a schematic diagram of a memory system according to an embodiment of the present application;

[0082] FIG. 4 is a flowchart of a memory correction method according to an embodiment of the present application;

[0083] FIG. 5 is a flowchart of a memory correction method according to an embodiment of the present application;

[0084] FIG. 6 is a structural block diagram of a memory correction apparatus according to an embodiment of the present application. DETAILED DESCRIPTION

[0085] In order to make the purpose, technical scheme and advantages of the present application clearer, the embodiments of the present application will be described in further detail below with reference to the drawings.

[0086] In order to facilitate understanding of the technical scheme of the present application, the following will first introduce several technical terms involved in the embodiments of the present application.

[0087] 1. Memory stick: A Von Neumann computer system includes five major components: arithmetic, control, storage, input, and output, among which storage includes main memory (memory) and secondary storage (solid state disk, mechanical hard disk, etc.). Among them, the memory stick mainly acts as a working memory (working memory) for storing instructions and data required for computer operation, and is an indispensable part of the Von Neumann computer system. Among them, double data rate synchronous dynamic random access memory (DDR SDRAM) is a kind of memory stick, and the application form of the memory stick includes particle surface and dual in-line memory module (DIMM). The memory sticks connected to the same chip select signal in the memory module are also called a memory column (rank), and Figure 1 is a schematic diagram of a memory stick provided by an embodiment of the present application, as shown in Figure 1, the memory stick includes dynamic random access memory (DRAM), registering clock driver (RCD), serial presence detect with hub (SPD Hub), power management ic (PMIC), temperature sensor (TS), printed circuit board (PCB) and other resistance and capacitance components. The memory module includes two channels (channel A and channel B), in the enterprise-level memory facing the high-reliability application scenario, the bit width of each channel is 40 bits (bit), among which the data bit width is 32 bits, and the error correcting code (ECC) bit width is 8 bits. The memory stick is also called a memory module, and the memory stick can be random access memory (RAM) and resistive random access memory (RRAM) in addition to DRAM.

[0088] 2. Device: A DRAM in memory is a device, and a device is a storage medium in a memory stick, as shown in FIG. 1, a memory stick includes multiple devices. According to the content stored in the device, the device is divided into a data device and an error correction code device. According to the number of data lanes of each device, the device is divided into an x4 device and an x8 device, x4 and x8 represent the number of data lanes of each device.

[0089] In the x8 memory stick of the 5th generation double data rate synchronous dynamic random access memory (DDR5 SDRAM), one rank in each channel of the memory module includes 4 data devices and 1 error correction code device. In response to a memory read operation, each device outputs 128 bits of data to the memory controller, and the 128 bits of data are distributed in two codewords, and each device contributes 64 bits of data to one codeword. Since each device has 8 external data lanes, the data output by each device to the memory controller is a 8x8 data block.

[0090] In the x4 memory stick of the 5th generation double data rate synchronous dynamic random access memory (DDR5 SDRAM), one rank in each channel of the memory module includes 8 data devices and 2 error correction code devices. In response to a memory read operation, each device outputs 64 bits of data to the memory controller, and the 64 bits of data are distributed in two codewords, and each device contributes 32 bits of data to one codeword. Since each device has 4 external data lanes, the data output by each device to the memory controller is a 4x8 data block.

[0091] 3. Memory array: An array in a device for storing data, which is composed of multiple memory cells. The memory array includes multiple bank groups, and each bank group includes multiple banks.

[0092] 4. On-die ECC (OD ECC) engine: also known as in-DRAM ECC engine, is an error correction engine implemented inside the memory die, which can correct the data read from the memory die, thereby improving the memory die yield. The on-die ECC engine can exist on the input-output (IO) pin or global input-output (GIO) in the internal data path of the memory die, or on the local input-output (LIO) in the internal data path of the memory die. FIG. 2 is a schematic diagram of a memory die including an on-die ECC engine according to an embodiment of the present application. As shown in FIG. 2, the memory die includes 8 bank groups (bank group 0-7) and an on-die ECC engine. Each bank group includes 4 banks (bank 0-3). As shown in (a) of FIG. 2, the on-die ECC engine exists on the GIO of the memory die. When the read operation on the memory bank corresponds to the memory address in bank 3 of bank group 7, the on-die ECC engine reads the data in the memory address, corrects the read data, and returns the corrected data to the memory controller. As shown in (b) of FIG. 2, the on-die ECC engine exists on the LIO of the memory die, i.e., the data in each bank is corrected by an on-die ECC engine.

[0093] The result of the detection of the read data by the on-die ECC engine includes three cases: the first case is that no error is detected, and correspondingly, the error correction state of the memory die is no error; the second case is that a single-bit error is detected, and the on-die ECC engine can correct the single-bit error, and correspondingly, the error correction state of the memory die is correctable error; the third case is that multiple-bit errors are detected, and the on-die ECC engine cannot correct the multiple-bit errors, and correspondingly, the error correction state of the memory die is uncorrectable error.

[0094] 5. Memory controller: The memory controller is located in the CPU, which is an important component of the computer system to control the memory and is responsible for the data exchange between the memory bank and the CPU. Taking the double data rate controller (DDRC) as an example, the memory controller includes a memory controller error correction engine (DDRC ECC engine), a dynamic memory controller (DMC), a micro controller unit (MCU), a bit pattern generator (BPG), and a physical layer (PHY).

[0095] 6. Reed-Solomon code (RS code) algorithm: The RS code algorithm includes k data elements (symbols) and 2t error correction code elements (ECC symbols) in the code word, where k and t are positive integers greater than 0. A symbol is data output through two pins. The RS code algorithm can correct 100% of errors within t symbols, and errors exceeding t symbols exceed the error correction capability of the RS code algorithm. For example, a DDR5 SDRAM x8 memory bank includes 4 data particles and 1 error correction code particle, where the data line outside each memory particle is 8, and the data input by each memory particle can be divided into 4 symbols. The data output by 5 memory particles to the memory controller is divided into 4x4=16 data symbols and 1x4=4 error correction code symbols, that is, k=16 and t=2. The RS code algorithm can correct 2 symbol errors in the DDR5 SDRAM x8 memory bank, and errors exceeding 2 symbols exceed the error correction capability of the RS code algorithm.

[0096] The implementation environment of the embodiments of the present application is introduced below.

[0097] FIG. 3 is a schematic diagram of a memory system provided by an embodiment of the present application. As shown in FIG. 3, the memory system includes a memory bank 301 and a memory controller 302. The memory bank 301 includes a plurality of memory particles. The memory bank 301 and the memory controller 302 communicate through a DDR bus.

[0098] The memory bank 301 can be any memory bank with an on-chip error correction engine, such as DDR5, DDR6, or Low Power Double Data Rate SDRAM (LPDDR), etc. The form of the memory bank 301 can be a dual in-line memory module or a particle surface mount. The memory particles in the memory 301 can be x4 memory particles or x8 memory particles, which are not limited in the embodiments of the present application. The memory particles in the memory 301 include data particles and error correction code particles. Each memory particle stores a plurality of code words, and each code word includes data and check code. The on-chip error correction engine in the memory particle corrects the data belonging to the same code word as the check code based on the check code, writes error correction indication information of the memory particle into the buffer, and outputs the corrected data to the memory controller 302.

[0099] The buffer is configured to have a certain data storage depth and a certain data storage width. The specific data storage depth and data storage width of the buffer are described below.

[0100] The memory controller 302 can be any memory controller with a system-level error correction function, such as a DDRC using RS code for error correction, which is not limited in the embodiments of the present application. The memory controller 302 can obtain data in the memory bank 301 and correct the obtained data, and then write the corrected data back to the memory bank 301.

[0101] The memory controller can read the buffer through an in-band mode read command or an out-of-band mode, which is not limited in the embodiments of the present application.

[0102] The embodiments of the present application provide a memory error correction method. The method can be applied to DDR5 SDRAM x8 memory banks and DDR5 SDRAM x4 memory banks, which are described below. It should be noted that the two types of memory banks are exemplary, and the method can also be applied to other types of memory banks, which are not limited in the embodiments of the present application.

[0103] The DDR5 SDRAM x8 memory bank is taken as an example. FIG. 4 is a flowchart of a memory error correction method according to an embodiment of the present application. As shown in FIG. 4, the method includes the following steps 401 to 407.

[0104] 401、in response to the read operation on the memory bank, the on-chip error correction engine in the memory grain obtains data in the memory grain, corrects the obtained data, writes error correction indication information into the buffer of the memory grain, and outputs the corrected data to the memory controller.

[0105] The memory grain stores data and a check code, and the check code is used to check whether the data has an error. The process in which the on-chip error correction engine obtains data in the memory grain and corrects the obtained data includes: in response to a read operation on the memory bank, reading a code word from a memory address corresponding to the read operation, the read code word including data and a check code of the data; and based on the read check code, correcting the read code word.

[0106] The result of the detection of the data by the on-chip error correction engine includes three cases: a first case in which no error is detected; a second case in which a single-bit error of the data is detected and the on-chip error correction engine corrects the single-bit error; and a third case in which an error of two bits or more of the data is detected and the on-chip error correction engine cannot correct the error. Corresponding to the error correction result, the error correction result of the memory grain includes no error, a correctable error (CE) and an uncorrectable error (UCE).

[0107] It can be understood that the error correction indication information can be used to indicate a memory grain in which an error occurs in the plurality of memory grains in the memory bank. In the present implementation, the error correction indication information is not specifically limited.

[0108] Optionally, the error correction indication information can indicate the error correction state of the on-chip error correction engine through a preset identification field. For example, the values of the identification field are 00B, 01B and 10B, respectively, which are used to represent that the error correction state of the memory grain is no error, a correctable error and an uncorrectable error. In this case, the memory controller can determine the specific error correction state of each memory grain, i.e., determine the memory grain in which an error occurs, based on the value corresponding to the error correction indication information.

[0109] Optionally, the error correction indication information can include a data access address corresponding to the data with uncorrectable errors in the memory grain, and the memory grain with errors can be indicated when the data access address is stored in the buffer. In this case, the memory controller can determine the specific error correction condition of each memory grain, i.e., determine the memory grain with errors, based on the data access address corresponding to the error correction indication information and the data address with uncorrectable errors determined by the memory controller in the subsequent steps. Optionally, the data access address includes a bank group (BG), a bank (BA), a row (R), and a column (C) corresponding to the data with uncorrectable errors. For example, the data access address includes BG1 (BG Address), BA1 (Bank Address in a BG), R3 (Row Address), and C4 (Col Address).

[0110] It should be noted that how the memory controller determines the memory grain with errors based on the data access address corresponding to the data with uncorrectable errors is described in detail in step 405.

[0111] In the above method, the on-chip error correction engine writes the error correction indication information of the memory grain into the buffer of the memory grain, so that the memory controller can locate the memory grain with errors by reading the error correction indication information in the buffer, thereby enabling the grain-level error correction and the system-level error correction to cooperate with each other, achieving full utilization of the redundant resources, and facilitating improvement of the error correction capability of the memory system under fixed redundant configuration.

[0112] In the above method, the on-chip error correction engine writes the error correction indication information of the memory grain into the buffer of the memory grain, so that the memory controller can locate the memory grain with errors by reading the error correction indication information in the buffer, thereby enabling the grain-level error correction and the system-level error correction to cooperate with each other, achieving full utilization of the redundant resources, and facilitating improvement of the error correction capability of the memory system under fixed redundant configuration.

[0113] It should be noted that in response to the read operation on the memory stick, the plurality of memory grains in the memory stick write the error correction indication information into the respective buffers, and simultaneously output the error-corrected data to the memory controller. The data output by the memory grain is the superposition of the data in the storage array (i.e., the read data) and the error correction result of the data by the on-chip error correction engine.

[0114] It should be noted that the step of acquiring, by the on-chip error correction engine, data in the memory particle, correcting the acquired data, and writing the error correction indication information into the buffer of the memory particle in the step 401 is an optional step. In some embodiments, if an error occurs in the memory particle, the memory particle directly reports the error to the memory controller, and then the memory controller can determine the memory particle that has an error based on the memory particle that reports the error when the error correction fails. The memory particle does not need to write the error correction indication information into the buffer, and the memory controller does not need to read the error correction indication information from the buffer to determine the memory particle that has an error, thereby saving the time cost of error correction and the buffer resource.

[0115] In an optional implementation, the depth of the buffer is greater than a preset threshold.

[0116] In the embodiments of the present application, the error correction indication information generated by the on-chip error correction engine after performing error correction is stored in the buffer arranged in the memory particle, and the depth of the buffer is greater than the preset threshold. The depth of the buffer greater than the preset threshold can effectively prevent the error correction indication information stored in the buffer from being covered by subsequent access when the data is corrected by using the error correction code (ECC) algorithm, thereby ensuring the effectiveness and reliability of the memory error correction scheme.

[0117] In an optional implementation, the preset threshold is determined according to the frequency of the on-chip error correction engine failing to correct errors within a first time length. The first time length is the time length between a first time and a second time. The first time is the time when the on-chip error correction engine stores the error correction indication information in the buffer. The second time is the time when the memory controller reads the error correction indication information from the buffers of the plurality of memory particles in the memory bank.

[0118] In the embodiments of the present application, the error correction indication information generated by the on-chip error correction engine after performing error correction is stored in the buffer arranged in the memory particle, and the depth of the buffer is greater than the preset threshold. The depth of the buffer greater than the preset threshold can effectively prevent the error correction indication information stored in the buffer from being covered by subsequent access when the data is corrected by using the error correction code (ECC) algorithm, thereby ensuring the effectiveness and reliability of the memory error correction scheme.

[0119] Since the back pressure operation of the memory controller on the read and write processes of the memory bank in the first time length may not take effect immediately, the system write command to the memory bank is still being executed, therefore, in the embodiment of the application, the cache is set to a depth greater than the preset threshold, and the preset threshold is determined according to the frequency of the occurrence of the on-chip error correction engine that cannot be corrected in the first time length, which can ensure that the error correction indication information stored in the cache is not covered by other accesses before the EC error correction reading is executed, and thus the accuracy of the memory controller in determining the memory particle that has an error according to the error correction indication information can be ensured, so that the error correction of the particle that has an uncorrectable error in the system can be performed, and the memory system error correction capability is improved.

[0120] It should be noted that the depth of the cache should meet the depth corresponding to the frequency of the occurrence of the on-chip error correction engine that cannot be corrected in the first time length, and the depth of the cache can also be greater than the depth corresponding to the frequency of the occurrence of the on-chip error correction engine that cannot be corrected in the first time length. Those skilled in the art can set the depth of the cache according to actual needs.

[0121] In an optional implementation, the step 401 specifically includes: in response to a read operation on the memory bank, the on-chip error correction engine acquires data in the memory particle, the on-chip error correction engine performs error correction on the acquired data, and if the error correction fails, the error correction indication information of the memory particle that fails in error correction is stored in the cache.

[0122] Specifically, when the on-chip error correction engine detects that two or more bits of data have errors and the on-chip error correction engine cannot correct the errors, i.e., determines that the error correction fails, the error correction indication information of the memory particle is written into the cache of the memory particle, so that the memory controller can locate the memory particle that has errors by reading the error correction indication information in the cache, thereby enabling the particle-level error correction and the system-level error correction to cooperate with each other, achieving full use of redundant resources, and being conducive to improving the error correction capability of the memory system under a fixed redundant configuration.

[0123] In an optional implementation, the cache includes a first in first out (FIFO) cache.

[0124] Specifically, the cache can be a first in first out (FIFO) cache. It can be understood that the cache in the embodiment of the application can also use other caches with a data storage depth, and the application does not limit the data storage structure of the cache.

[0125] In an optional implementation, the data access address includes a bank group (Bank Group), a bank (Bank), a row (Row), and a column (Col) of the data.

[0126] The data access address includes bank group, bank, row, and column information corresponding to the data, and is used to indicate the storage position information of the data in the memory particle.

[0127] In an optional implementation, the buffer has a data storage width, and the data storage width is determined according to the data access address.

[0128] The buffer has a data storage width, and the data storage width is determined according to the data access address of the data. The data storage width needs to be able to meet the address information of the bank group, the bank, the row, and the column of the data.

[0129] In an optional implementation, if the detection result of the on-chip error correction engine for the data is no error detected, the data is sent.

[0130] The on-chip error correction engine determines that the detection result is no error detected after detecting the obtained data, and directly sends the data without error correction processing.

[0131] In an optional implementation, if the detection result of the on-chip error correction engine for the data is correctable error, the on-chip error correction engine corrects the data and sends the corrected data.

[0132] The on-chip error correction engine determines that the detection result is correctable error after detecting the obtained data, that is, detects a single-bit error of the data, corrects the single-bit error, and returns the corrected data to the processor.

[0133] It can be understood that in some embodiments of the present application, the memory error correction method can only include the above step 401, that is, only step 401 is executed, and subsequent steps 402 to 407 are not executed.

[0134] 402: The memory controller obtains the data output by the plurality of memory particles and corrects the data in the plurality of memory particles.

[0135] Specifically, the memory controller detects the data in the plurality of memory particles, and if the number of errors detected by the memory controller is greater than a target threshold, it indicates that the memory controller fails to correct errors.

[0136] In some embodiments, the memory controller detects the data in the plurality of memory grains by a Reed-Solomon code (RS code) algorithm. The target threshold is the maximum number of errors that can be corrected by the error correction algorithm employed by the memory controller. For example, a DDR5 SDRAM x8 memory stick includes 4 data grains and 1 error correction code grain, wherein the data line outside each memory grain is 8, the data input by each memory grain can be divided into 4 symbols, and the data output by 5 memory grains to the memory controller is divided into 4x4=16 data symbols and 1x4=4 error correction code symbols, i.e., k=16 and t=2. The RS code algorithm can correct 2 symbols of errors in the DDR5 SDRAM x8 memory, and more than 2 symbols of errors exceeds the error correction capability of the RS code algorithm.

[0137] The result of the detection of the data in the plurality of memory grains by the memory controller and the subsequent steps include three cases. The first case is that no error is detected, and the memory controller directly returns the data to the processor. The second case is that the number of detected errors is within the error correction capability of the error correction algorithm employed by the memory controller, i.e., the error correction is successful, and the memory controller corrects the data by the error correction algorithm and returns the corrected data to the processor. The third case is that the number of detected errors exceeds the error correction capability of the error correction algorithm, i.e., the error correction fails, and the memory controller determines the memory grain in the memory stick in which the error occurs based on the error correction indication information stored in the buffer of the memory grain, and corrects the data.

[0138] It can be understood that in some embodiments of the present application, the memory controller can also directly execute the above step 402 without interacting with the on-chip error correction engine, i.e., the memory controller can execute the step 402 without obtaining the corrected data from the on-chip error correction engine.

[0139] The process of correcting the data by the memory controller based on the memory grain in which the error occurs in the third case is described below, which includes the following steps 403 to 406.

[0140] 403: If the error correction fails, the memory controller reverses the read / write process of the memory stick.

[0141] The back pressure refers to suppressing generation of memory access from a CPU source or a memory access path. The memory controller determines whether the memory address corresponding to the read operation is a direct memory access address. When the memory address is a memory address other than a direct memory access (DMA) address, the memory controller can back pressure the read process of the memory bank, thereby preventing other read / write processes from rewriting the data to be corrected, and avoiding data inconsistency.

[0142] In an optional implementation, the processor includes a plurality of cores, and the process of back pressure of the memory controller on the read / write process of the memory bank includes: if the number of errors of data accessed by a memory read operation of any processor core exceeds a target threshold, the core initiates a stop core broadcast through a software generated interrupt (SGI); other cores in the processor set a stop core flag after receiving the stop core broadcast, to stop memory access and wait to be woken up; the core that initiates the stop core broadcast detects whether the other cores have completed stopping cores after a preset time, and if all the cores have completed stopping cores, the memory controller enters a subsequent data recovery process; if any core has not completed stopping cores, the memory controller records a stop core failure, wakes up the other cores, and returns an error state. In the above method, the read process of the memory bank is back pressured by stopping the cores of the processor, which can prevent other read / write processes from rewriting the data to be corrected from the access source, thereby effectively ensuring data consistency.

[0143] In an optional implementation, the memory controller includes a dynamic memory controller and a physical layer (PHY), and the dynamic memory controller includes a scheduler configured to schedule read / write commands of the memory bank. The memory controller back pressures a command scheduling queue in the memory controller to cut off a path between the scheduler and the PHY, thereby preventing other read / write processes from rewriting the data to be corrected from the scheduling queue, and the back pressure is more refined, the processor cores do not stop working, and the impact on upper-layer services is small.

[0144] In an optional implementation, the memory controller reports a synchronous external abort (SEA) after error correction fails.

[0145] The memory controller determines that error correction fails after the system ECC engine of the memory controller detects errors in the data, that is, the number of detected errors exceeds the error correction capability of an error correction algorithm adopted by the memory controller, the memory controller reports a synchronous external abort (SEA), and performs a subsequent error correction process.

[0146] It should be noted that the step 403 is described by taking the memory address corresponding to the read operation as the memory address other than the DMA address as an example. In some embodiments, the memory address corresponding to the read operation is the DMA address, and the memory controller discards the current error correction, generates first error information, and the first error information is used to indicate that the subsequent error correction cannot be performed.

[0147] It should be noted that the process of back pressure on the read and write process of the memory bank in the step 403 is an optional step. In some embodiments, the process of back pressure on the read and write process of the memory bank in the step 403 is not performed, and the embodiments of the present application do not limit this.

[0148] 404: The memory controller obtains the data in the memory bank again. If the data obtained twice is consistent, the memory controller reads the error correction indication information of the plurality of memory particles from the buffer of the plurality of memory particles.

[0149] In the above method, the data in the memory bank is obtained again to determine whether the data is rewritten before the back pressure takes effect. If the data is not rewritten before the back pressure takes effect, the subsequent data error correction process is continued, which can ensure the effectiveness of the data error correction process and the consistency of the data.

[0150] In the above method, the data in the memory bank is obtained again to determine whether the data is rewritten before the back pressure takes effect. If the data is not rewritten before the back pressure takes effect, the subsequent data error correction process is continued, which can ensure the effectiveness of the data error correction process and the consistency of the data.

[0151] In the above method, the data in the memory bank is obtained again to determine whether the data is rewritten before the back pressure takes effect. If the data is not rewritten before the back pressure takes effect, the subsequent data error correction process is continued, which can ensure the effectiveness of the data error correction process and the consistency of the data.

[0152] It should be noted that the step 404 is an optional step. In some embodiments, if the process of back pressure on the read and write process of the memory bank in the step 403 is not performed, the step 404 is not performed, and the embodiments of the present application do not limit this.

[0153] In an optional implementation, if the error correction fails, the memory controller stores the data into an error content register and stores the data access address of the data into an uncorrectable error (UCE) address register.

[0154] The memory controller is provided with an error content register and an uncorrectable error (UCE) address register. The error content register is used to store the data that fails to be corrected by the memory controller. The UCE address register is used to store the data access address of the data that fails to be corrected by the memory controller.

[0155] Specifically, the memory controller corrects the data. When it is determined that the correction fails, the memory controller stores the data that fails to be corrected in the error content register of the memory controller and stores the data access address corresponding to the data that fails to be corrected in the UCE address register of the memory controller. The data that fails to be corrected and the data access address corresponding to the data that fails to be corrected are stored, which is used for subsequent consistency verification of the memory controller on the data.

[0156] In an optional implementation, in the step 404, the memory controller acquires the data in the memory again. If the data acquired twice is consistent, the method comprises the following steps: acquiring the to-be-verified data based on the data access address stored in the UCE address register; and if the to-be-verified data is consistent with the data in the error content register, it is determined that the data acquired twice is consistent.

[0157] Specifically, before the memory controller performs the EC correction, the memory controller acquires the to-be-verified data based on the data access address stored in the UCE address register and compares the to-be-verified data with the data in the error content register. If the to-be-verified data is consistent with the data in the error content register, it is indicated that the data is not rewritten, and the memory controller can perform subsequent EC correction.

[0158] In an optional implementation, if the to-be-verified data is inconsistent with the data in the error content register, a second error information is generated.

[0159] Specifically, if the to-be-verified data is inconsistent with the data in the error content register, it is indicated that the data is rewritten, and the second error information is generated. The second error information indicates that the correction fails, the memory controller ends the data correction process, returns to an error state, and the memory controller does not perform subsequent EC correction.

[0160] 405: If the number of memory particles that occur errors is less than or equal to the number of error correction code particles in the memory, the memory controller corrects the data based on the memory particles that occur errors.

[0161] The memory controller determines the memory particle with error based on the error correction indication information of the plurality of memory particles read from the buffer. If the error correction state information of any memory particle indicates that the memory particle has error, the memory controller determines that the memory particle is the memory particle with error. In the embodiment of the present application, the memory controller determines the memory particle with error based on the error correction indication information in the buffer, and then corrects the data based on the memory particle with error. The error correction at the particle level provided by the on-chip error correction engine and the error correction at the system level provided by the memory controller can cooperate with each other, thereby achieving full utilization of the redundant resources and improving the error correction capability of the memory system under the fixed redundancy configuration.

[0162] Specifically, the error correction capability of the memory controller can satisfy the error correction of a preset number of memory particles with error, wherein the preset number is the number of error correction code particles in the memory bank. The number of memory particles with error is less than or equal to the number of error correction code particles in the memory bank, which means that the number of redundant memory particles in the memory is greater than or equal to the number of memory particles with error. That is, the number of memory particles with error is within the error correction capability of the memory controller, and the memory controller can correct the data in the memory particles with error based on the data in the memory particles without error in the memory. For example, a DDR5 SDRAM x8 memory bank includes 4 data particles and 1 error correction code particle, that is, the number of redundant memory particles in the memory is 1. The memory controller can correct the data in the memory particles with error only when and if the number of memory particles with error is less than or equal to 1. When the number of memory particles with error is greater than 1, the memory controller ends the data error correction process and returns the uncorrectable error to the CPU.

[0163] In an optional implementation, if the error correction indication information indicates that any memory particle has error, the memory controller determines that the memory particle is the memory particle with error; and / or, if the error correction indication information stored in the buffer of any memory particle includes the data access address of any memory particle, the memory controller determines that the memory particle is the memory particle with error.

[0164] The error correction indication information can be used to indicate the memory particles with error in the plurality of memory particles in the memory bank. In the implementation, the error correction indication information is not specifically limited. Optionally, the error correction indication information can indicate the error correction state of the on-chip error correction engine through a preset identification field. For example, the values of the identification field are 00B, 01B and 10B, which are respectively used to represent that the error correction state of the memory particle is no error, correctable error and uncorrectable error. Optionally, the error correction indication information can include the data access address of the data with uncorrectable error in the memory particle. When the data access address is stored in the buffer, it indicates the memory particle with error.

[0165] For example, when the error correction indication information includes a preset identification field, the memory controller reads the error correction indication information in the cache, and determines that the read error correction indication information includes a specific identification field, and then determines that the memory particle corresponding to the cache is the error-occurring memory particle.

[0166] For example, when the error correction indication information includes a data access address corresponding to the data in the memory particle that has the uncorrectable error, the memory controller reads the error correction indication information in the cache, and determines that the read error correction indication information includes the data access address of the memory particle, and then determines that the memory particle corresponding to the cache is the error-occurring memory particle.

[0167] It can be understood that the expression "any memory particle has an error" in the embodiment can be understood as "a certain memory particle has an error" or "any memory particle has an error", and is not interpreted as "all memory particles have errors".

[0168] In an optional implementation, when the error correction indication information includes a data access address corresponding to the data in the memory particle that has the uncorrectable error, the memory controller determines the number of error-occurring memory particles, including: the memory controller compares the data access address stored in the cache with the data access address stored in the UCE address register, and through the comparison of the two data addresses, the number of error-occurring memory particles can be determined.

[0169] Specifically, the memory controller reads the data access address stored in the cache of the memory particle, and further compares and matches the data access address stored in the UCE address register with the data access address stored in the cache of each memory particle. The data access address stored in the cache is stored by the on-chip error correction engine when it is determined that the error correction fails, and the data access address stored in the UCE address register is stored by the memory controller when it is determined that the error correction fails based on the system ECC engine. Through the comparison and matching of the two data addresses, when the matching is successful, it can be determined that the memory particle corresponding to the cache has an error. After the same comparison and matching are performed on all caches, the number of error-occurring memory particles can be determined.

[0170] It can be understood that, in the embodiment of the application, the on-chip error correction engine will store the data access address corresponding to the data with errors in the buffer when the error correction fails, as a kind of error correction indication information, and the memory controller will also store the data access address corresponding to the data with errors in the UCE address register of the memory controller when the error correction fails once, so that the memory controller can compare and match the data access address stored in the buffer (indicating the data corresponding to the error correction failure of the on-chip error correction engine) and the data access address in the UCE address register (indicating the data corresponding to the error correction failure of the memory controller) based on the error correction in the previous two rounds, to determine the memory particle with errors again, thereby ensuring the accuracy and reliability of the number of memory particles with errors determined, so as to improve the error correction capability of the memory system and the reliability of the data in the memory bank.

[0171] In addition, in the embodiment of the application, the data access address is stored in the buffer, and the buffer provides a data storage depth greater than a preset threshold, which is determined according to the frequency of the on-chip error correction engine failing to correct errors within a first time period, so that the error correction indication information stored in the buffer will not be covered by other accesses before the memory controller performs EC error correction reading, thereby ensuring the accuracy of the memory controller in determining the memory particle with errors based on the error correction indication information, and thus ensuring the effectiveness and reliability of the memory error correction scheme.

[0172] In some embodiments, the memory controller uses an erasure code (EC) algorithm to correct errors in the data of the memory particle with errors.

[0173] The following takes the DDR5 SDRAM x8 memory bank as an example, and the data error correction process includes the following steps 405A to 405C:

[0174] 405A: The data in the four data particles are denoted as D1, D2, D3 and D4 respectively, and the data in the one error correction code particle (redundancy particle) is denoted as C1, wherein D1, D2, D3, D4 and C1 are all 8x8 data blocks. According to the properties of RS code algorithm, that is, EC code, there is a matrix H for generating code words, wherein the visible elements of H are all 8x8 block matrices, and this process can be represented by the following formula (1).

[0175] 405B: For the case that any memory particle has errors, the matrix row corresponding to the memory particle is removed from the matrix H, and the matrix is still a full rank matrix H', and the full rank matrix has an inverse matrix H' -1 For example, the memory particle D1 has errors, and the matrix row corresponding to the D1 is removed from the matrix H, and this process can be represented by the following formula (2).

[0176] 405C: left-multiply the data after removing D1 by the inverse matrix H' -1 to obtain the corrected data, which can be represented by the following formula (3).

[0177] 406: the memory controller writes the corrected data back to the memory grain.

[0178] In some embodiments, the memory controller writes the data corresponding to the memory grain in which the error occurs in the corrected data to the position corresponding to the memory address in the memory grain, that is, only replaces the data in the position corresponding to the memory address in the memory grain in which the error occurs. The embodiments of the present application do not limit this.

[0179] In the above method, the memory controller writes the corrected data back to the memory grain, so that the correct data can be read when the same memory address is read next time, which is beneficial to improve the reliability of the data in the memory bank.

[0180] It should be noted that the step 406 is an optional step. In some embodiments, the step 406 is not performed, and the memory controller directly returns the corrected data to the CPU to shorten the response time of the read operation on the memory bank and improve the response efficiency. The embodiments of the present application do not limit this.

[0181] 407: the memory controller releases the pressure on the read-write process of the memory bank.

[0182] In the step 407, the memory controller releases the pressure on the read-write process of the memory bank. The step 407 corresponds to the step 403. If the memory controller limits the service access request of the memory by triggering the software interrupt SGI to request the central processing unit to suspend the access to the memory, the memory controller releases the limitation by waking up the central processing unit core, so as to release the limitation on the service access request of the memory. If the memory controller limits the service access request of the memory by shutting down the path between the command scheduling queue of the memory controller and the memory port, the memory controller releases the shutdown of the command scheduling queue, so that the path between the scheduler and the physical interface protocol is connected, thereby releasing the limitation on the service access request of the memory.

[0183] It should be noted that the step 407 is an optional step. In some embodiments, if the step 403 is not performed, the step 407 is not performed. The embodiments of the present application do not limit this.

[0184] The memory correction method provided by the embodiment of the present application is described below in combination with a flowchart of a memory correction method shown in FIG. 5.

[0185] Step 1 in FIG. 5 (corresponding to step 401 described above): in response to a read operation on the memory bank, the on-chip correction engine reads data from the storage array of the memory particle and performs a check, and based on the check result, writes correction indication information into the buffer of the memory particle. The buffer is a buffer with a data storage depth (for example, a first-in-first-out (FIFO) buffer in FIG. 5).

[0186] Step 2 in FIG. 5 (corresponding to step 402 described above): the data in each memory particle is returned to the DDRC ECC engine in the memory controller through the data bus, the DDRC ECC engine detects the data using the RS code algorithm, if the RS code DDRC ECC engine does not detect an error, the memory controller directly returns the data to the CPU, and the flow ends in advance; if the number of symbols with errors detected by the RS code DDRC ECC engine is within t, the memory controller corrects the data through the RS code DDRC ECC engine and returns the data to the CPU, and the flow ends in advance; if the number of symbols with errors detected by the RS code DDRC ECC engine is greater than t, the RS code DDRC ECC engine exceeds the upper limit of the correction capability.

[0187] Step 3 in FIG. 5 (corresponding to step 403 described above): if the error of the memory data accessed by any CPU core exceeds the upper limit of the correction capability of the RS code DDRC ECC engine, the RS code DDRC ECC engine triggers a synchronous external abort (SEA), and the MCU enters a basic input output system (BIOS) processing flow. The MCU first determines whether the address belongs to a DMA address, and performs corresponding operations: if it belongs to a DMA address, the current correction is abandoned, an error state is returned, and the original processing flow is executed; if it does not belong to a DMA address, the subsequent correction flow is continued.

[0188] Step 4 in FIG. 5 (corresponding to step 403 described above): the DMC memory controller limits the service access request of the memory, to prevent the data from being overwritten by other read-write processes and causing data inconsistency.

[0189] Step 5 in FIG. 5 (corresponding to step 404 described above): the MCU initiates reading of the memory particles (DRAM) through the BPG, reads the first to-be-verified data based on the data access address stored in the UCE address register, judges the consistency of the first to-be-verified data and the data in the error content register, if the two are inconsistent, it indicates that the data has been overwritten before the request for the service access to the memory is restricted, the process is ended in advance, and the second error information is generated; if the two are consistent, the MCU reads the cache of each memory particle to obtain the error correction indication information generated by the on-chip error correction engine of each memory particle.

[0190] Step 6 in FIG. 5 (corresponding to step 405 and step 406 described above): the data access address stored in the cache is compared with the data access address stored in the UCE address register to determine the number of particles that have occurred errors. When the number of particles that have occurred errors is a preset number, the MCU performs data error correction using the EC algorithm; in the remaining scenarios, the process is ended in advance and the return of the uncorrectable error is returned. After the EC algorithm completes the error correction, the MCU writes the corrected data back to the memory particles through the BPG, modifies the interrupt return vector, and triggers the system to re-read the memory address corresponding to the read operation, that is, to re-read the cacheline.

[0191] Step 7 in FIG. 5 (corresponding to step 407 described above): the MCU removes the restriction on the request for the service access to the memory, and the memory controller initiates re-reading of the data in the memory particles that have occurred errors.

[0192] It should be noted that the steps 401 to 407 described above are explained by taking the DDR5 SDRAM x8 memory stick as an example, the memory error correction method provided by the embodiments of the present application can also be applied to the DDR5 SDRAM x4 memory stick, and the memory error correction method in the DDR5 SDRAM x4 memory stick is the same as the process shown in steps 401 to 407 described above, except that: in the DDR5 SDRAM x4 memory stick, in response to a memory read operation, each memory particle outputs 64-bit data to the memory controller, and the 64-bit data is distributed in two codewords, each memory particle contributes 32-bit data to one codeword, and since each memory particle has four external data lines, the data output by each memory particle to the memory controller is a 4x8 data block; in addition, the DDR5 SDRAM x4 memory stick includes 8 data particles and 2 error correction code particles, that is, the number of redundant memory particles in the memory stick is 2, when the number of particles that have occurred multi-bit errors is 2, the memory controller corrects the first data based on the error correction code EC algorithm to obtain the first data after error correction; when the number of memory particles that have occurred errors is greater than 2, the memory controller ends the data correction process and returns the uncorrectable error to the CPU.

[0193] The following is for DDR5 SDRAM x4 memory stick, the memory controller based on the error correction code EC algorithm for the first data correction process includes the following steps A to step C.

[0194] Step A, the data in the 8 data particles are respectively recorded as D1, D2…, D8, and the data in the 2 error correction code particles (redundant particles) are recorded as C1 and C2, wherein D1-D8, C1 and C2 are all 4x8 data blocks. According to the properties of RS code algorithm, that is, EC code, there is a matrix H for generating code words, wherein the visible elements of H are all 4x4 block matrices, and the process can be represented by the following (4).

[0195] Step B, for the case that errors occur in any two memory particles, the matrix row corresponding to the two memory particles is removed from the matrix H, and the matrix is still a full rank matrix H', and the full rank matrix H' has an inverse matrix H' -1 For example, memory particles D1 and C1 have errors, and the matrix row corresponding to D1 and C1 is removed from the matrix H, which can be represented by the following formula (5).

[0196] Step C, left multiply the read data by the inverse matrix H' -1 , the corrected data is obtained, which can be represented by the following formula (6).

[0197] The other steps of the memory error correction method in the DDR5 SDRAM x4 memory stick are the same as the steps in the memory error correction method in the DDR5 SDRAM x8 memory stick, and the same parts are not repeated.

[0198] In the above embodiment, the on-chip error correction engine performs first-time error correction on the data and writes error correction indication information of the memory grain into the buffer, so that the memory controller can locate the grain with errors by reading the error correction indication information in the buffer, the grain-level error correction and the system-level error correction can cooperate with each other, the redundant resources are fully utilized, and the error correction capability of the memory system is improved under the fixed redundant configuration; after the memory controller obtains the data, the second-time error correction is performed on the data, compared with the error correction relying only on the on-chip error correction engine, the silent errors and the mis-corrected errors that are not detected by the on-chip error correction engine can be corrected, so as to reduce the risk of silent errors and the risk of mis-corrected data in the memory grain; if the memory controller fails to correct the error, the memory controller reads the error correction indication information of the memory grain from the buffer in the memory grain, determines the memory grain with errors based on the error correction indication information, and then performs third-time error correction on the data, since the result of the grain-level error correction is utilized, compared with the error correction relying only on the memory controller, the error correction capability of the memory controller is improved, and thus the error correction capability of the memory system and the reliability of the data in the memory bank are improved; the buffer provides a data storage depth greater than a preset threshold, and the preset threshold is determined according to the frequency of the occurrence of the error that cannot be corrected by the on-chip error correction engine in the first time length, so that the error correction indication information stored in the buffer will not be covered by other accesses when the memory controller performs the third-time error correction, and thus the accuracy of the memory controller in determining the memory grain with errors based on the error correction indication information is ensured, and the effectiveness and reliability of the memory error correction scheme are ensured. For x4 memory, the present embodiment can implement dual-chipkill error correction on two memory grains, and for x8 memory bank, the present embodiment can implement chipkill error correction on a single memory grain.

[0199] It should be noted that the above embodiment is described by taking the module form in the application form of the memory bank as an example, in some embodiments, the memory error correction method provided in the present embodiment can be applied to the memory in the grain surface paste form. In other embodiments, the memory error correction method provided in the present embodiment is also applicable to the scene in which the memory grain includes the on-chip error correction engine and the memory controller uses the RS code for error correction, for example, the scene of DDR6 or LPDDR4 with sideband ECC, and the present embodiment is not limited to the specific scene shown above.

[0200] FIG. 6 is a memory controller provided by an embodiment of the present application, which includes a data acquisition module 601 and a data error correction module 602.

[0201] The data acquisition module 601 is configured to acquire data from the memory bank in response to a read operation on the memory bank.

[0202] The data correction module 602 is configured to correct the data. If the correction fails, the data correction state indication information is read from the buffer of the plurality of memory particles in the memory bank, the memory particle with the error is determined according to the data correction state indication information, and the data is corrected based on the memory particle with the error.

[0203] In an optional implementation, the depth of the buffer is greater than a preset threshold.

[0204] In an optional implementation, the data correction module includes:

[0205] The reading unit is configured to correct the data. If the correction fails, the data correction indication information of the plurality of memory particles is read from the buffer of the plurality of memory particles.

[0206] The determining unit is configured to determine that the memory particle is the memory particle with the error if the data correction state information of any memory particle indicates that the memory particle has the error, and / or the memory controller determines that the memory particle is the memory particle with the error if the data access address of the memory particle is stored in the buffer of any memory particle.

[0207] In an optional implementation, the data correction module is specifically configured to correct the data based on the memory particle with the error when it is confirmed that the data access address does not belong to a direct memory access (DMA) address.

[0208] In an optional implementation, the reading unit is configured to:

[0209] The data is corrected. If the correction fails, the memory controller reverses the read-write process of the memory bank.

[0210] The data in the memory is acquired again. If the data acquired twice is consistent, the data correction indication information of the plurality of memory particles is read from the buffer of the plurality of memory particles.

[0211] In an optional implementation, the data correction module includes:

[0212] The correction unit is configured to correct the data based on the memory particle with the error if the number of the memory particles with the error is less than or equal to the number of the error correction code particles in the memory bank.

[0213] In an optional implementation, the buffer includes a first-in-first-out (FIFO) buffer.

[0214] In an optional implementation, the data access address includes a bank group, a bank, a row, and a column of the data.

[0215] In an alternative implementation, the reading unit is specifically configured to: perform error correction on the data, and if the error correction fails, request to suspend the access of the central processing unit (CPU) to the memory based on a software triggered interrupt (SGI), or, shut down the passage between the scheduling queue of the memory controller and the memory port.

[0216] In an alternative implementation, the memory controller further comprises:

[0217] a write-back module configured to write back the error-corrected data to the memory grain;

[0218] a re-reading module configured to re-read the memory address corresponding to the reading operation.

[0219] The data acquisition module 601 and the data error correction module 602 can be implemented by software or by hardware. For example, the implementation of the data acquisition module 601 is described as follows. The implementation of the data error correction module 602 can be similar to that of the data acquisition module 601.

[0220] As an example of a software functional unit, the data acquisition module 601 can include code running on a computing instance. The computing instance can include at least one of a physical host (computing device), a virtual machine, and a container. Further, the computing instance can be one or more. For example, the data acquisition module 601 can include code running on multiple hosts / virtual machines / containers. It should be noted that the multiple hosts / virtual machines / containers running the code can be distributed in the same region, or in different regions. Further, the multiple hosts / virtual machines / containers running the code can be distributed in the same availability zone (AZ), or in different AZs, each of which includes one data center or multiple data centers in close geographical proximity. Generally, one region can include multiple AZs.

[0221] Similarly, the multiple hosts / virtual machines / containers running the code can be distributed in the same virtual private cloud (VPC), or in multiple VPCs. Generally, one VPC is set in one region, and communication between two VPCs in the same region or between VPCs in different regions needs to be set through a communication gateway in each VPC to realize the interconnection between VPCs.

[0222] As an example of a hardware functional unit, the data acquisition module 601 can include at least one computing device, such as a server or the like. Alternatively, the data acquisition module 601 can also be a device implemented by an application-specific integrated circuit (ASIC) or a programmable logic device (PLD), and the like. The PLD can be a complex programmable logical device (CPLD), a field-programmable gate array (FPGA), a generic array logic (GAL), or any combination thereof.

[0223] The plurality of computing devices included in the data acquisition module 601 can be distributed in the same region or in different regions. The plurality of computing devices included in the data acquisition module 601 can be distributed in the same AZ or in different AZs. Similarly, the plurality of computing devices included in the data correction module 602 can be distributed in the same VPC or in multiple VPCs. The plurality of computing devices can be any combination of servers, ASICs, PLDs, CPLDs, FPGAs, and GALs.

[0224] It should be noted that in other embodiments, the steps implemented by the above modules can be specified as needed, and the entire function of the device can be implemented by the above modules implementing different steps in the memory correction method. That is, the memory controller provided in the above embodiments is only an example of the division of the above functional modules when implementing the memory correction method, and in actual application, the above functions can be distributed to different functional modules according to the needs, that is, the internal structure of the device is divided into different functional modules to complete all or part of the functions described above. In addition, the device and the corresponding method embodiments provided in the above embodiments belong to the same concept, and the specific implementation process is described in the method embodiments, which will not be described here.

[0225] The present application also provides a computing device including a memory controller and a memory bank for temporarily storing data, and the memory controller is used to execute the memory correction method provided in the above method embodiments. The computing device can be a server or a terminal device. The description of the memory controller and the memory bank can refer to the description of the memory controller 302 and the memory bank 301 in FIG. 3, which will not be described here.

[0226] The computing device can include a bus and a communication interface in addition to the memory controller and the memory bank, and the memory controller, the memory bank and the communication interface communicate with each other through the bus.

[0227] The bus can be a peripheral component interconnect (PCI) bus, an extended industry standard architecture (EISA) bus or the like. The bus can be divided into an address bus, a data bus, a control bus and the like. The bus can include a path for transmitting information between various components (e.g., the memory bank, the memory controller, the communication interface) of the computing device.

[0228] In a possible implementation, the computing device can further include a processor connected with the memory controller, and the specific connection manner between the processor and the memory controller is not limited here. For example, the memory controller can be built in the processor, or can be connected with the processor through a line. The memory processor can include any one or more of a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, a discrete gate or transistor logic device, a discrete hardware component, an artificial intelligence chip, a chip on chip, and the like.

[0229] The memory bank can include a volatile memory (VM), such as a random access memory (RAM) or a double data rate SDRAM (DDR SDRAM).

[0230] The memory bank stores executable program code, and the memory controller executes the executable program code to respectively implement the functions of the foregoing data acquisition module 601 and the data error correction module 602, thereby implementing the memory error correction method. That is, the memory bank stores instructions for executing the memory error correction method.

[0231] The communication interface uses a transceiver module such as but not limited to a network interface card and a transceiver to implement communication between the computing device and other devices or communication networks.

[0232] The embodiments of the present application provide a computer program product containing instructions, which can be software or program product containing instructions capable of running on a computing device or stored in any available medium. When the computer program product runs on at least one computing device, the at least one computing device is caused to perform the memory error correction method provided in the above embodiments.

[0233] The embodiments of the present application provide a computer readable storage medium, which can be any available medium capable of being stored by a computing device or a data storage device such as a data center containing one or more available media. The available medium can be a magnetic medium (for example, a floppy disk, a hard disk, a magnetic tape), an optical medium (for example, a DVD), or a semiconductor medium (for example, a solid state disk), etc. The computer readable storage medium contains instructions, when the instructions are executed by a computing device cluster, the computing device cluster performs the memory error correction method provided in the above embodiments.

[0234] It should be noted that the information (including but not limited to user device information, user personal information, etc.), data (including but not limited to data for analysis, stored data, displayed data, etc.) and signals involved in the present application are all authorized by the user or fully authorized by all parties, and the collection, use and processing of related data need to comply with relevant laws, regulations and standards of relevant countries and regions. For example, the data involved in the present application are obtained under sufficient authorization.

[0235] Those skilled in the art can realize that, in combination with the method steps and units described in the embodiments disclosed in the present application, the methods can be realized by electronic hardware, computer software or a combination of both. In order to clearly illustrate the interchangeability of hardware and software, the steps and components of the embodiments have been described in the above description. Whether the functions are executed in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of the present application.

[0236] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working process of the above-described system, device and unit can refer to the corresponding process in the foregoing method embodiments, which will not be described here.

[0237] In several embodiments provided in the present application, it should be understood that the disclosed system, device and method can be implemented in other manners. For example, the described device embodiments are merely schematic. The division of the units is merely a logical function division. There can be another division manner for the actual implementation, for example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the displayed or discussed coupling or direct coupling or communication connection between the units can be indirect coupling or communication connection through some interfaces, devices or units, and can be electrical, mechanical or other forms of connection.

[0238] The units described as separated components can or can not be physically separated, and the components displayed as units can or can not be physical units, i.e., can be located in one place, or can be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purposes of the embodiments of the present application.

[0239] In addition, each unit in the various embodiments of the present application can be integrated in one processing unit, or each unit can be a physically separate unit, or two or more units can be integrated in one unit. The integrated unit can be realized in the form of hardware, or in the form of a software unit.

[0240] When the integrated unit is realized in the form of a software function unit and sold or used as an independent product, it can be stored in a computer readable storage medium. Based on such understanding, the technical solutions of the present application essentially or substantially, or all or part of the technical solutions can be embodied in the form of a software product. The computer software product is stored in a storage medium, and includes a plurality of instructions for causing a computing device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the methods in the various embodiments of the present application. The foregoing storage medium includes: U disk, mobile hard disk, read-only memory (ROM), random access memory (RAM), magnetic disk or optical disk, and various other media that can store program codes.

[0241] The terms "first", "second", and the like, used in the present application, are used to distinguish between similar or identical items or items having substantially the same function, and it should be understood that there is no logical or chronological dependency between "first", "second", and "n-th", nor does it limit the number and execution order. It should also be understood that although the following description uses the terms first, second, and the like to describe various elements, these elements should not be limited by the terms. These terms are only used to distinguish one element from another. For example, without departing from the scope of various examples, a first memory particle can be called a second memory particle, and similarly, a second memory particle can be called a first memory particle. The first memory particle and the second memory particle can both be memory particles, and in some cases, can be separate and distinct memory particles.

[0242] In the present application, the term "at least one" means one or more, and the term "a plurality of" means two or more, for example, a plurality of first memory particles means two or more first memory particles. The terms "system" and "network" are often used interchangeably herein.

[0243] It should also be understood that the term "if" can be interpreted to mean "when" or "upon" or "in response to determining" or "in response to detecting". Similarly, the phrase "if it is determined" or "if [a stated condition or event] is detected" can be interpreted to mean "upon determining" or "in response to determining" or "upon detecting [the stated condition or event]" or "in response to detecting [the stated condition or event]".

[0244] The above description is merely a specific implementation of the present application, but the scope of protection of the present application is not limited thereto. Any person skilled in the art can easily think of various equivalent modifications or replacements within the scope of the technology disclosed in the present application, and these modifications or replacements should be encompassed within the scope of protection of the present application. Therefore, the scope of protection of the present application should be subject to the scope of protection of the claims.

[0245] In the above-described embodiments, all or part can be implemented by software, hardware, firmware, or any combination thereof. When implemented by software, it can be implemented in the form of a computer program product in whole or in part. The computer program product includes one or more computer program instructions. When loaded and executed on a computer, the computer program instructions produce the processes or functions in whole or in part according to the embodiments of the present application. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable devices.

[0246] The computer instructions can be stored in or transferred from one computer-readable storage medium to another computer-readable storage medium, for example, the computer program instructions can be transmitted from one website site, computer, server or data center to another website site, computer, server or data center through wired or wireless manner. The computer-readable storage medium can be any available medium accessible by a computer or a data storage device such as a server, data center, etc. integrated with one or more available medium sets. The available medium can be a magnetic medium (such as a floppy disk, a hard disk, a magnetic tape), an optical medium (such as a digital video disc (DVD)), or a semiconductor medium (such as a solid state disk), etc.

[0247] Those of ordinary skill in the art can understand that all or part of the steps of the above-mentioned embodiments can be completed by hardware, or by programs instructing relevant hardware, and the programs can be stored in a computer-readable storage medium. The storage medium mentioned above can be a read-only memory, a magnetic disk or an optical disk, etc.

[0248] The above embodiments are only used to illustrate the technical solutions of the present application, but not to limit them; although the present application has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions recorded in the foregoing embodiments, or make equivalent replacements for part of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A memory error correction method, characterized by, The method comprises: In response to a read operation on a memory bank, a memory controller obtains data from the memory bank; The memory controller corrects errors of the data; If the error correction fails, the memory controller reads error correction indication information from the cache of the plurality of memory particles in the memory bank, and determines the memory particle with errors according to the error correction indication information; The memory controller corrects errors of the data based on the memory particle with errors.

2. The method of claim 1, wherein, The depth of the cache is greater than a preset threshold.

3. The method according to claim 1 or 2, characterized in that, The memory controller reads error correction indication information from the cache of the plurality of memory particles in the memory bank, and determines the memory particle with errors according to the error correction indication information, comprising: If the error correction indication information indicates that any memory particle has errors, the memory controller determines that the memory particle is the memory particle with errors; and / or, if the error correction indication information includes the data access address of any memory particle, the memory controller determines that the memory particle is the memory particle with errors.

4. The method according to any one of claims 1 to 3, characterized in that, If the error correction fails, the memory controller reads error correction indication information from the cache of the plurality of memory particles in the memory bank, and determines the memory particle with errors according to the error correction indication information, comprising: If the error correction fails, the memory controller reverses the read-write process of the memory bank; The memory controller obtains the data in the memory bank again, if the data obtained twice is consistent, reads the error correction indication information of the plurality of memory particles from the cache of the plurality of memory particles, and determines the memory particle with errors according to the error correction indication information.

5. The method according to any one of claims 1 to 4, characterized in that, The memory controller corrects errors of the data based on the memory particle with errors, comprising: If the number of memory particles with errors is less than or equal to the number of error correction code particles in the memory bank, the memory controller corrects errors of the data based on the memory particles with errors.

6. The method according to any one of claims 1 to 5, characterized in that, The error correction indication information is the data access address of the memory particle with errors, and the memory controller corrects errors of the data based on the memory particle with errors, comprising: The memory controller confirms that the data access address does not belong to a direct memory access (DMA) address, and corrects errors of the data based on the memory particle with errors.

7. The method according to any one of claims 1 to 6, characterized in that, The memory particle comprises an on-chip error correction engine, and the method further comprises: In response to a read operation on the memory bank, the on-chip error correction engine obtains data in the memory particle; The on-chip error correction engine corrects errors of the obtained data, and if the error correction fails, stores the error correction indication information of the memory particle with errors to the cache.

8. The method according to claim 3 or 6, characterized in that, The data access address comprises a bank group, a bank, a row, and a column of the data.

9. A memory error correction method, comprising: The memory bank is executed, the memory bank comprises a plurality of memory particles, the memory particle comprises an on-chip error correction engine, each memory particle comprises a cache, and the method comprises: In response to a read operation on a memory bank, the on-chip error correction engine corrects errors of the data in the memory particle; If the error correction fails, the on-chip error correction engine stores error correction indication information of the memory particle that fails in error correction in the buffer.

10. The method of claim 9, wherein, The depth of the buffer is greater than a preset threshold.

11. The method according to claim 9 or 10, characterized in that, The on-chip error correction engine stores error correction indication information of the memory particle that fails in error correction in the buffer, including: The on-chip error correction engine stores the data access address of the memory particle that fails in error correction in the buffer of the memory particle that fails in error correction.

12. A memory controller, comprising: The memory controller includes: a data acquisition module, configured to acquire data from the memory bank in response to a read operation on the memory bank; a data error correction module, configured to correct errors of the data, if the error correction fails, read error correction state indication information from the buffers of a plurality of memory particles in the memory bank, determine a memory particle that has errors according to the error correction state indication information, and correct errors of the data based on the memory particle that has errors.

13. A memory module, comprising: The memory bank includes a plurality of memory particles, each of the memory particles includes a buffer, and the memory bank is configured to perform the memory error correction method according to any one of claims 9-11.

14. A memory controller, comprising: comprising: a memory, configured to store computer instructions; a processor, configured to execute the computer instructions stored in the memory, so that the memory controller performs the memory error correction method according to any one of claims 1-8.

15. A computing device, comprising: comprising: a memory controller and a memory bank, the memory bank is configured to temporarily store data, and the memory controller is configured to perform the memory error correction method according to any one of claims 1-8.

16. A computer program product containing instructions which, when executed on a computer, cause the computer to perform the memory error correction method according to any one of claims 1-8 or 9-11.

Images