Vertically charge transferring pixel sensor and manufacturing method therefor

Abstract

The present invention relates to a vertically charge transferring pixel sensor and a manufacturing method therefor. In the vertically charge transferring pixel sensor, deep trench isolation (DTI) structures are used to divide a substrate to form a plurality of substrate pixel units, and the DTI structures pass through the substrate to physically isolate the substrate pixel units from each other, so that optoelectronic crosstalk between pixels corresponding to the substrate pixel units can be avoided, improving the device performance. In addition, a shallow trench isolation structure is used to divide each substrate pixel unit into a photosensitive region, a charge reading region, and a substrate lead-out region. In a pixel formed corresponding to a substrate pixel unit, the substrate pixel unit and a gate structure constitute a MOS capacitor, the substrate pixel unit is a substrate electrode of the MOS capacitor, and the substrate lead-out region is a connection terminal of the substrate pixel unit. The substrate lead-out region may be connected to a corresponding external signal from a front side of the substrate, so that a voltage is applied to the substrate electrode by means of the substrate lead-out region.

Description

Vertically charge transferring imaging sensor and manufacturing method thereof TECHNICAL FIELD

[0001] The present application relates to the field of photosensitive technology, and in particular to a vertically charge transferring imaging sensor and a manufacturing method thereof. BACKGROUND

[0002] A vertically charge transferring imaging sensor (Vertically charge transferring Pixel Sensors) uses a substrate and a floating gate transistor structure to realize imaging. Fig. 1 is a plan view of a pixel of the vertically charge transferring imaging sensor. Fig. 2 is a sectional view of the vertically charge transferring imaging sensor along the direction of XX' in Fig. 1. Referring to Figs. 1 and 2, the vertically charge transferring imaging sensor generally includes a plurality of pixels formed based on a substrate 10, each pixel having a photosensitive region 11 and a charge reading region 12 formed in the substrate 10 and separated by a shallow trench isolation structure (STI), a gate structure formed on the photosensitive region 11 and the charge reading region 12 and including a gate oxide GOX, a floating gate FG, an inter-gate dielectric layer 13 and a control gate CG stacked in sequence, and a source region S and a drain region D formed in the charge reading region 12 and located on the two sides of the control gate (CG) respectively, wherein the gate structure and the substrate 10 thereunder form a MOS capacitor, the control gate (CG) and the substrate 10 are two electrodes of the MOS capacitor respectively, and the gate structure and the source region S and the drain region D form a reading transistor having a floating gate transistor structure. When light is incident into the substrate 10 from the side of the substrate 10 away from the above-mentioned gate structure, the light collides with the lattice of the substrate 10 to generate photoelectrons. By applying a suitable bias voltage on the above-mentioned MOS capacitor, the photoelectrons can be moved towards the control gate CG and gathered on the surface of the photosensitive region 11 or enter the floating gate (FG) by overcoming the potential barrier, thereby causing the drain current and / or the threshold voltage of the reading transistor to change. By detecting the change, photoelectric sensing and imaging can be realized.

[0003] Compared with a conventional photodiode-based sensor device (such as a CMOS image sensor), the vertically charge transferring imaging sensor can realize a higher full-well capacity with the same area of pixels, thereby having a higher signal-to-noise ratio and being conducive to pixel miniaturization.

[0004] As shown in Fig. 2, the prior art forms deep trench isolation structures (DTI) between different pixels to reduce the crosstalk of photoelectrons between adjacent pixels, and keeps a substrate layer 14 of a proper thickness between the bottom surface of the deep trench isolation structure and the back surface of the substrate 10, which connects the substrate portions corresponding to the respective pixels, so that in operation, the substrate electrode of the MOS capacitor can be pressurized by applying a voltage to the substrate layer 14 from the back surface of the substrate 10. However, the photoelectrons formed in the substrate 10 by the incident light can generate mutual crosstalk through the substrate layer 14, affecting the performance of the device. In addition, in order to reduce the thickness of the substrate layer 14 to reduce the crosstalk, part of the bottom surface of the deep trench isolation structure can be exposed from the back surface of the substrate 10 while the other part is not exposed, resulting in unevenness on the back surface of the substrate 10, which is not conducive to the processes requiring flatness on the side of the back surface of the substrate 10. SUMMARY

[0005] In order to facilitate the application of voltage to the substrate corresponding to the pixel of the vertical charge transfer imaging sensor while improving the isolation performance between the pixels of the vertical charge transfer imaging sensor and avoiding the crosstalk of photoelectrons, the present application provides a vertical charge transfer imaging sensor and a manufacturing method of a vertical charge transfer imaging sensor.

[0006] In one aspect, the present application provides a vertical charge transfer imaging sensor, comprising:

[0007] a substrate having a first doping type and comprising a front surface and a back surface opposite to each other;

[0008] a deep trench isolation structure penetrating through the substrate, which separates the substrate to form a plurality of substrate pixel units;

[0009] a shallow trench isolation structure formed on the front surface of the substrate, which separates each of the substrate pixel units into a light sensing region, a charge reading region and a substrate leading-out region;

[0010] a reading transistor comprising a gate structure formed on the front surface of the charge reading region and a first source / drain region and a second source / drain region formed in the charge reading region on both sides of the gate structure respectively, wherein the gate structure spans from the charge reading region to the light sensing region; and

[0011] a MOS capacitor formed by the gate structure and the corresponding substrate pixel unit, the substrate pixel unit being a substrate electrode of the MOS capacitor, and the substrate leading-out region being a voltage application region of the substrate electrode.

[0012] Optionally, the vertical charge transfer imaging sensor further comprises:

[0013] an interlayer dielectric layer covering a plurality of the substrate pixel units, the deep trench isolation structure, the shallow trench isolation structure, the read transistor and the MOS capacitor from the front side;

[0014] a first source / drain plug penetrating through the interlayer dielectric layer to connect to the first source / drain region;

[0015] a second source / drain plug penetrating through the interlayer dielectric layer to connect to the second source / drain region; and

[0016] a substrate electrode plug penetrating through the interlayer dielectric layer to connect to the substrate lead-out region.

[0017] Optionally, the gate structure comprises a gate dielectric layer, a floating gate, an inter-gate dielectric layer and a control gate stacked on the surface of the photo- sensitive region and the charge reading region of the substrate pixel unit.

[0018] Optionally, the vertical charge transfer imaging sensor comprises:

[0019] at least one word line formed by the control gates in the gate structures on at least two of the substrate pixel units.

[0020] Optionally, the first doping type concentration of the surface of the substrate lead-out region is greater than the surrounding substrate, and the first source / drain region and the second source / drain region have a second doping type.

[0021] Optionally, the end surface of the deep trench isolation structure facing the same direction as the back surface of the substrate pixel unit is flush with the back surface of the substrate pixel unit.

[0022] Optionally, the vertical charge transfer imaging sensor further comprises:

[0023] a back surface dielectric layer comprising a high dielectric constant layer covering the deep trench isolation structure and the substrate pixel unit from the back surface of the substrate and an oxide layer covering the high dielectric constant layer.

[0024] In one aspect, the present application provides a manufacturing method of a vertical charge transfer imaging sensor, the manufacturing method comprising:

[0025] providing a substrate having a first doping type and comprising a front surface and a back surface opposite to each other;

[0026] forming a deep trench isolation structure and a shallow trench isolation structure on the front surface of the substrate, the deep trench isolation structure and the shallow trench isolation structure extending from the front surface side into the substrate, the deep trench isolation structure separating the substrate to form a plurality of substrate pixel units, and the shallow trench isolation structure separating each of the substrate pixel units into a photo-sensitive region, a charge reading region and a substrate lead-out region;

[0027] forming a gate structure on a surface of each of the substrate pixel units corresponding to the front surface of the substrate, and forming a first source / drain region and a second source / drain region on both sides of the gate structure in the charge reading region to form a reading transistor, wherein the gate structure spans from the charge reading region to the photosensitive region and forms a MOS capacitor with the corresponding substrate pixel unit; and

[0028] thinning the substrate from the back surface to expose the deep trench isolation structure and the plurality of substrate pixel units separated by the deep trench isolation structure.

[0029] Optionally, before thinning the substrate from the back surface, the manufacturing method further comprises:

[0030] forming a patterned mask layer on the substrate, an opening in the mask layer exposing the substrate lead-out region; and

[0031] performing a first doping type ion implantation on the surface of the substrate lead-out region, so that the first doping type concentration of the surface of the substrate lead-out region is greater than the surrounding substrate.

[0032] Optionally, before thinning the substrate from the back surface, the manufacturing method further comprises:

[0033] forming an interlayer dielectric layer on the front surface of the substrate; and

[0034] forming a first source / drain plug, a second source / drain plug and a substrate electrode plug through the interlayer dielectric layer, the first source / drain plug being connected to the first source / drain region, the second source / drain plug being connected to the second source / drain region, and the substrate electrode plug being connected to the substrate lead-out region.

[0035] Optionally, thinning the substrate from the back surface comprises:

[0036] polishing the back surface of the substrate by a CMP process to expose the deep trench isolation structure and the plurality of substrate pixel units from the back surface of the substrate; and

[0037] forming a back surface dielectric layer, the back surface dielectric layer comprising a high dielectric constant layer covering the deep trench isolation structure and the substrate pixel units from the back surface of the substrate and a low dielectric constant layer covering the high dielectric constant layer.

[0038] Optionally, after the CMP process is completed, wet etching is performed to remove damage on the surface of the substrate pixel units.

[0039] In the vertical charge transfer imaging sensor and its manufacturing method provided by the present invention, a plurality of substrate pixel units are formed by separating the substrate using the deep trench isolation structure (DTI). By allowing the deep trench isolation structure (DTI) to penetrate the substrate to physically isolate each substrate pixel unit, photoelectric crosstalk between corresponding pixels of each substrate pixel unit can be avoided, thereby improving device performance. Furthermore, each substrate pixel unit is divided into a photosensitive area, a charge readout area, and a substrate lead-out area using the shallow trench isolation structure. Corresponding to the pixel formed by the substrate pixel unit, the substrate pixel unit and the gate structure constitute a MOS capacitor. The substrate pixel unit is the substrate electrode of the MOS capacitor, and the substrate lead-out area is the connection terminal of the substrate pixel unit. The substrate lead-out area can be connected to a corresponding external signal from the front side of the substrate to apply a voltage to the substrate electrode through the substrate lead-out area. Attached Figure Description

[0040] Figure 1 is a planar schematic diagram of the pixels of the vertical charge transfer imaging sensor.

[0041] Figure 2 is a cross-sectional schematic diagram of the vertical charge transfer imaging sensor along the XX' direction in Figure 1.

[0042] Figure 3 is a planar schematic diagram of a vertical charge transfer imaging sensor according to an embodiment of the present invention.

[0043] Figures 4 and 5 are schematic cross-sectional views along lines A-A' and B-B' in Figure 3, respectively.

[0044] Figure 6 is a flowchart illustrating a method for manufacturing a vertical charge transfer imaging sensor according to an embodiment of the present invention.

[0045] Figures 7 to 28 are schematic cross-sectional views of a method for manufacturing a vertical charge transfer imaging sensor according to an embodiment of the present invention. Detailed Implementation

[0046] The vertical charge transfer imaging sensor and its manufacturing method of the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, only to facilitate and clarify the illustration of the embodiments of the present invention. The embodiments of the present invention should not be considered as limited to the specific shapes of the areas shown in the figures, but may include actual shapes, such as those caused by manufacturing deviations.

[0047] Referring to Figures 3, 4, and 5, according to an embodiment of the present invention, a vertical charge transfer imaging sensor includes a substrate 100, a deep trench isolation structure (DTI), a shallow trench isolation structure (STI), a readout transistor, and a MOS capacitor. Detailed description follows.

[0048] The substrate 100 can adopt various suitable substrates in the art, and the material thereof can include silicon, germanium, silicon germanium, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, or indium antimonide, etc. The substrate 100 has a first doping type, such as p-type or n-type, and the present embodiment takes p-type as an example. The substrate 100 is, for example, a silicon substrate doped with boron or boron difluoride. The substrate 100 has opposite front surface 100a and back surface 100b.

[0049] The deep trench isolation structure DTI penetrates the substrate 100 and separates the substrate 100 to form a plurality of substrate pixel units 110. The deep trench isolation structure DTI can include a deep trench penetrating the substrate 100 along the thickness direction of the substrate 100, and an isolation medium (such as silicon oxide or silicon nitride, etc.) filled in the deep trench. By making the deep trench isolation structure DTI penetrate the substrate 100, each substrate pixel unit 110 is physically isolated, and the formation of photoelectron crosstalk between the pixels corresponding to each substrate pixel unit 110 can be avoided, thereby improving the device performance.

[0050] As an example, the deep trench isolation structure DTI includes a deep trench penetrating the substrate 10, a linear medium layer 103 formed in the deep trench, a trench electrode 104a, and a cover layer 105, wherein the linear medium layer 103 covers the sidewall of the deep trench, the trench electrode 104a and the cover layer 105 are filled in the deep trench and are isolated from the substrate 100 by the linear medium layer 103, and the cover layer 105 is located on the side of the trench electrode 104a close to the front surface 100a of the substrate 10. The trench electrode 104a provides an operable electrode end for the vertical charge transfer imaging sensor, which cooperates with other electrode ends in the sensor to achieve diversified operation modes. For example, by applying a positive bias voltage between the substrate 100 and the trench electrode 104a, the barrier at the interface between the deep trench isolation structure DTI and the substrate 100 can be improved, the probability of photoelectrons being captured at the interface can be reduced, which helps to improve the photoelectric conversion efficiency and improve the dark current and white pixel problems. The trench electrode 104a can extend laterally along the deep trench to the peripheral region of the substrate 100 to connect with external electrical signals.

[0051] As an example, the end surface of the deep trench isolation structure DTI and the back surface 100b of the substrate pixel unit 110 are consistent, and the end surface is flush with the back surface 100b of the substrate pixel unit 110 (i.e., the height difference between the end surface and the back surface of the substrate pixel unit 110 is within a set requirement range), that is, the end surface and the back surface 100b of the substrate pixel unit 110 have better flatness, which is more convenient when performing a process based on the vertical charge transfer imaging sensor on the substrate 100 back surface 100b side which has a requirement for flatness.

[0052] A shallow trench isolation structure STI is formed on the front surface 100a of the substrate 100, which can include a shallow trench formed from the front surface 100a of the substrate 100 and an isolation medium (such as silicon oxide or silicon nitride) filled in the shallow trench. As shown in FIG. 3, according to an embodiment of the present application, the shallow trench isolation structure STI separates each substrate pixel unit 110 into a light sensing region 110a, a charge reading region 110b and a substrate leading-out region 110c. As an example, the substrate pixel unit 110, the light sensing region 110a, the charge reading region 110b and the substrate leading-out region 110c are all rectangular in cross-sectional shape, and a pair of parallel edges of each of the charge reading region 110b and the substrate leading-out region 110c are parallel to a pair of parallel edges of the substrate pixel unit 110.

[0053] Referring to FIG. 3, as an example, the substrate pixel unit 110 is square, and the length direction of the light sensing region 110a, the charge reading region 110b and the substrate leading-out region 110c is the same and the width direction is also the same. The length of the light sensing region 110a is equal to the side length of the substrate pixel unit 110, and the sum of the width of the light sensing region 110a, the width of the charge reading region 110b and the width of the shallow trench isolation structure STI is equal to the side length of the substrate pixel unit 110; the width of the charge reading region 110b and the substrate leading-out region 110c is equal, and the sum of the length of the charge reading region 110b, the length of the substrate leading-out region 110c and the length of the shallow trench isolation structure STI is equal to the side length of the substrate pixel unit 110. It can be understood that the present application is not limited thereto, and the cross-sectional shape of the substrate pixel unit 110, the light sensing region 110a, the charge reading region 110b and the substrate leading-out region 110c can also be other patterns or have other size relationships, and the position distribution of the light sensing region 110a, the charge reading region 110b and the substrate leading-out region 110c can be adjusted according to actual conditions. As an example, referring to FIG. 3, the substrate pixel units 110 are arranged in rows and columns, the row direction is parallel to the AA' line, for example, and the column direction is parallel to the BB' line, for example; in at least two adjacent substrate pixel units 110 in the same row, the charge reading region 110b and the substrate leading-out region 110c of one substrate pixel unit 110 are adjacent to the light sensing region 110a of the other substrate pixel unit 110; in at least two adjacent substrate pixel units 110 in the same column, the substrate leading-out region 110c of one substrate pixel unit 110 is adjacent to the substrate leading-out region 110c of the other substrate pixel unit 110, and the substrate leading-out region 110c and the charge reading region 110b in the substrate pixel unit 110 are aligned in the column direction. However, the present application is not limited thereto, and the arrangement of the light sensing region 110a, the charge reading region 110b and the substrate leading-out region 110c in different substrate pixel units 110 can be adjusted according to actual conditions.

[0054] The read transistor is formed on each substrate pixel unit 110. Referring to FIGS. 4 and 5, the read transistor includes a gate structure 120 formed on the front surface 100a of the charge read region 110b, and a first source / drain region and a second source / drain region (both denoted as S / D in the figures) formed on the charge read region 110b on both sides of the gate structure 120, respectively. In each substrate pixel unit 110, the gate structure 120 extends from the charge read region 110b to the photosensitive region 110a (see FIG. 3).

[0055] Referring to FIGS. 4 and 5, the gate structure 120 can include a gate dielectric layer 106, a floating gate FG, a gate interlayer dielectric layer 108, and a control gate CG stacked on the surface of the photosensitive region 110a and the charge read region 110b of the substrate pixel unit 110. In this embodiment, the floating gate FG, the gate interlayer dielectric layer 108, and the control gate CG in the gate structure 120 extend from the photosensitive region 110a to the charge read region 110b, and the first source / drain region and the second source / drain region can be exposed on both sides of the extension direction, respectively. The vertical charge transfer imaging sensor can include a plurality of word lines (e.g., WL1 and WL2 shown in FIG. 3), each of which is formed by the control gate CG in the gate structure 120 on at least two substrate pixel units 100.

[0056] The MOS capacitor is formed corresponding to each substrate pixel unit 110. Specifically, the MOS capacitor is formed by the gate structure 120 and the substrate pixel unit 110 below, in which the substrate pixel unit 110 is the substrate electrode of the MOS capacitor, and the control gate CG constitutes the other electrode of the MOS capacitor. The substrate extraction region 110c is the voltage application region of the substrate electrode. In order to reduce the contact resistance of the substrate extraction region 110c, the first doping type concentration of the top of the substrate extraction region 110c towards the front surface 100a is greater than the first doping type concentration of the surrounding substrate 100, for example, with p-type heavy doping (p+).

[0057] The substrate pixel unit 110 and the read transistor and the MOS capacitor formed on the substrate pixel unit 110 constitute a pixel of the vertical charge transfer imaging sensor. In operation, two electrodes in the MOS capacitor can be biased to form a depletion region in the substrate pixel unit 110 with the control gate CG being positively biased with respect to the substrate pixel unit 110. When light is incident from the back side 100b of the substrate 100, photoelectrons are generated by the light colliding with the substrate lattice. The photoelectrons are collected on the surface of the photosensitive region 110a or enter the floating gate FG by overcoming the potential barrier under the electric field in the depletion region. Since the floating gate FG of the photosensitive region 110a is connected to the charge reading region 110b, the collection of the photoelectrons changes the state of the floating gate FG of the charge reading region 110b, which in turn changes the threshold voltage and / or the drain current of the read transistor. The vertical charge transfer imaging sensor detects the changes to achieve photoelectric sensing and imaging. In this embodiment, the read transistor in the pixel of the vertical charge transfer imaging sensor is an N-type device, and the source region S and the drain region D are n-type doped. It should be understood that in the case of a P-type read transistor, the source region S and the drain region D are p-type doped.

[0058] Referring to FIGS. 4 and 5, on the front side 100a of the substrate 100, the vertical charge transfer imaging sensor further includes an interlayer dielectric layer 130, a first source / drain plug CT1, a second source / drain plug CT2, and a substrate electrode plug CT3. The interlayer dielectric layer 130 covers the plurality of substrate pixel units 110, the deep trench isolation structure DTI, the shallow trench isolation structure STI, the read transistor, and the MOS capacitor from the front side 100a. The first source / drain plug CT1 penetrates the interlayer dielectric layer 130 to connect to the first source / drain region. The second source / drain plug CT2 penetrates the interlayer dielectric layer 130 to connect to the second source / drain region. The substrate electrode plug CT3 penetrates the interlayer dielectric layer 130 to connect to the substrate lead-out region 110c. Metal interconnection structures and a plurality of metal pads (not shown) can be formed on the interlayer dielectric layer 130. The first source / drain region can be connected to the corresponding metal pad through the metal interconnection structures. As an example, the metal pads are connected to an external power supply during operation of the device to apply voltages to the first source / drain region, the second source / drain region, and the substrate lead-out region 110c. In this embodiment, since the substrate lead-out region 110c is formed in each substrate pixel unit 110, the voltages applied to each substrate pixel unit 110 are more uniform, which helps to improve the performance of the vertical charge transfer imaging sensor.

[0059] Referring to FIGS. 4 and 5, the vertical charge transfer imaging sensor can further include a backside dielectric layer 140 on the backside 100b of the substrate 100. The backside dielectric layer 140 can include a high-k layer 141 covering the deep trench isolation structure DTI and the substrate pixel units 110, and an oxide layer 142 (e.g., silicon oxide) covering the high-k layer 141. The high-k layer 141 is formed of a material with a high dielectric constant (e.g., greater than 3.9), such as Al2O3, Ta2O5, ZrO2, LaO, BaZrO, AlO, HfZrO, HfZrON, HfLaO, HfSiON, HfSiO, LaSiO, AlSiO, HfTaO, HfTiO, (Ba, Sr)TiO3(BST), or TiO2. The high-k layer 141 can increase the potential barrier of the backside 100b of the substrate 100, reduce the probability of photoelectrons being trapped near the backside 100b of the substrate 100, and improve photoelectric conversion efficiency.

[0060] Embodiments of the present application also relate to a method for manufacturing a vertical charge transfer imaging sensor. FIGS. 7-28 are cross-sectional views of a method for manufacturing a vertical charge transfer imaging sensor according to an embodiment of the present application. The method for manufacturing a vertical charge transfer imaging sensor will be described below with reference to FIGS. 3, 6, and 7-28.

[0061] FIGS. 7 and 8 are cross-sectional views along the lines A-A' and B-B' of FIG. 3 after forming the deep trench DT in the substrate 100. Referring to FIGS. 3, 6, 7, and 8, in step S1, a substrate 100 is provided. The substrate 100 has a first doping type and includes a front side 100a and a backside 100b opposite to each other. As an example, the substrate 100 is a silicon substrate and has a p-type doping. The surface of the substrate 100 for forming the floating gate transistor structure is the front side 100a, and the surface opposite to the front side 100a is the backside 100b.

[0062] Referring to FIG. 6, in step S2, a deep trench isolation structure DTI and a shallow trench isolation structure STI are formed on the front side 100a of the substrate 100. The deep trench isolation structure DTI and the shallow trench isolation structure STI extend from the front side 100a into the substrate 100. The deep trench isolation structure DTI separates the substrate 100 to form a plurality of substrate pixel units 110. The shallow trench isolation structure STI separates each substrate pixel unit 110 into a light sensing region 110a, a charge reading region 110b, and a substrate leading-out region 110c.

[0063] The shallow trench isolation structure STI can include a shallow trench formed from the front surface 100a side of the substrate 100 and an isolation medium filled in the shallow trench. The deep trench isolation structure DTI can include a deep trench formed from the front surface 100a side of the substrate 100 and an isolation medium filled in the deep trench. The isolation medium in the deep trench isolation structure DTI and the shallow trench isolation structure STI can include silicon oxide and / or silicon nitride, etc. The shallow trench isolation structure STI and the deep trench isolation structure DTI can be formed by using a conventional trench isolation fabrication process, and the present application does not specially limit the specific formation process of the shallow trench isolation structure STI and the deep trench isolation structure DTI. As an example, the deep trench isolation structure DTI includes a deep trench formed on the front surface 100a of the substrate 100, an isolation medium filled in the deep trench, and a trench electrode for providing an operable electrode terminal for the vertical charge transfer imaging sensor. As an example, the process of forming the shallow trench isolation structure STI and the deep trench isolation structure DTI including the trench electrode is described below, in which the same medium deposition process is used to fill the isolation medium in the shallow trench and fill the isolation medium on the top of the deep trench. The present application is not limited thereto, for example, in another embodiment, the shallow trench isolation structure STI is formed by first filling the shallow trench with the isolation medium, and then the deep trench and the deep trench isolation structure DTI are formed.

[0064] In step S2, as an example, referring to FIG. 3, FIG. 7 and FIG. 8, a pad oxide layer 101, at least one hard mask (such as a hard mask layer 102), an anti-reflective film (not shown in the figure) and a photoresist layer (not shown in the figure) can be formed on the surface of the substrate 100 in sequence, and a dry etching process is performed according to the pattern of the deep trench to form a deep trench DT extending from the front surface 100a side to the substrate 100. The pad oxide layer 101 can be made of silicon oxide, and the hard mask layer 102 can be made of silicon nitride. At this time, the bottom surface of the deep trench DT is located in the substrate 100, and a plurality of substrate pixel units 110 isolated by the deep trench DT are formed.

[0065] Figures 9 and 10 are cross-sectional views along the lines A-A' and B-B' of Figure 3 after filling the deep trenches DT. Referring to Figures 3, 9 and 10, a linear oxide layer 103 can then be formed on the surface of the deep trenches DT by thermal oxidation, chemical vapor deposition or atomic layer deposition, and a conductive material is deposited to fill the deep trenches DT and cover the hard mask layer 102. The upper surface of the conductive material is then planarized to expose the hard mask layer 102, and the remaining conductive material forms a trench conductive layer 104 in the deep trenches DT. The trench conductive layer 104 can be made of a conductive material with good light shielding performance. Optionally, the trench conductive layer 104 includes one or a combination of two or more of tungsten, tungsten silicide, titanium, titanium nitride and doped polysilicon. In the present embodiment, the trench conductive layer 104 is, for example, doped polysilicon, and annealing can be performed after the deposition of the conductive material to recrystallize the doped polysilicon to obtain a suitable grain size.

[0066] Figures 11 and 12 are cross-sectional views along the lines A-A' and B-B' of Figure 3 after forming the shallow trenches ST. Referring to Figures 3, 11 and 12, the hard mask layer 102, the pad oxide layer 101 and the substrate 100 are then etched to form the shallow trenches ST extending from the front surface 100a side into the substrate 100. The shallow trenches ST are formed in each of the substrate pixel units 110, and have a depth less than that of the deep trenches DT. In the present embodiment, the shallow trenches ST in each of the substrate pixel units 110 divide the substrate pixel unit 110 into a light sensing region 110a, a charge reading region 110b and a substrate lead-out region 110c.

[0067] Figures 13 and 14 are cross-sectional views along the lines A-A' and B-B' of Figure 3 after removing part of the trench conductive layer 105. Referring to Figures 3, 13 and 14, the trench conductive layer 104 in the deep trenches DT is then etched to be lower than the front surface 100a of the substrate 100, so that an unfilled space is formed in the upper part of the deep trenches DT, and the remaining trench conductive layer 104 forms a trench electrode 104a. At this time, the unfilled space is in communication with the shallow trenches ST at the top of the substrate 100 at a position where the shallow trenches ST and the deep trenches DT intersect.

[0068] Fig. 15 and Fig. 16 are cross sections along the lines A-A' and B-B' of Fig. 3, respectively, after forming the cap layer 105 in the un-filled space on top of the deep trench DT and in the shallow trench ST. Referring to Fig. 3, Fig. 15 and Fig. 16, an isolation medium, such as one or a combination of silicon oxide, silicon nitride, silicon oxynitride and nitrogen-doped silicon carbide, is deposited on the substrate 100 to fill the deep trench DT on top and the shallow trench ST and to cover the surface of the hard mask layer 102, and then a planarization process, such as CMP, is performed to expose the surface of the hard mask layer 102, leaving the isolation medium in the deep trench DT on top and the shallow trench ST to form the cap layer 105.

[0069] After the above processes, the deep trench isolation structure DTI and the shallow trench isolation structure STI are formed on the front surface 100a of the substrate 100 corresponding to the deep trench DT and the shallow trench ST, respectively, wherein the deep trench isolation structure DTI comprises the deep trench DT, the linear oxide layer 103, the trench electrode 104a and the cap layer 105 filling the deep trench DT, and the shallow trench isolation structure STI comprises the shallow trench ST and the cap layer 105 filling the shallow trench ST; and the deep trench isolation structure DTI separates the substrate 100 to form a plurality of substrate pixel units 110, and the shallow trench isolation structure STI separates each substrate pixel unit 110 into a photosensitive region 110a, a charge reading region 110b and a substrate lead-out region 110c, and the arrangement of the photosensitive region 110a, the charge reading region 110b and the substrate lead-out region 110c can refer to the vertical charge transfer imaging sensor described in the above embodiments.

[0070] Referring to Fig. 6, step S3 is performed to form a gate structure on the surface of each substrate pixel unit 110 corresponding to the front surface 100a of the substrate 100, and to form a first source / drain region and a second source / drain region on both sides of the gate structure in the charge reading region 110b to form a reading transistor, wherein the gate structure spans from the charge reading region 110b to the photosensitive region 110a and forms a MOS capacitor with the corresponding substrate pixel unit 110. The following describes the process of forming the gate structure in step S3 as an example.

[0071] Fig. 17 and Fig. 18 are cross sections along the lines A-A' and B-B' of Fig. 3, respectively, after removing part of the cap layer 105 in the shallow trench isolation structure DTI and the hard mask layer 102. Referring to Fig. 3, Fig. 17 and Fig. 18, the cap layer 105 in the shallow trench ST is etched first so that the top surface of the cap layer 105 is lower than the top surface of the hard mask layer 102 and not lower than the front surface 100a of the substrate 100, and then the hard mask layer 102 is removed. At this time, the side surface of part of the cap layer 105 in the deep trench isolation structure DTI is exposed. Then the pad oxide layer 101 on the surface of the substrate 100 can be removed, and a gate medium layer 106 is formed on the surface of the substrate 100 exposed by removing the pad oxide layer 101.

[0072] FIGS. 19 and 20 are cross-sectional views along the lines A-A' and B-B' of FIG. 3, respectively, after forming the floating gate material layer 107. Referring to FIGS. 3, 19 and 20, polysilicon is deposited on the substrate 100 to cover the gate dielectric layer 106, the shallow trench isolation structure STI and the deep trench isolation structure DTI, and then the top surface of the polysilicon is planarized to expose the top surface of the deep trench isolation structure DTI. The remaining polysilicon is stacked on the gate dielectric layer 106 to form the floating gate material layer 107.

[0073] FIGS. 21 and 22 are cross-sectional views along the lines A-A' and B-B' of FIG. 3, respectively, after etching the cover layer 105 in the deep trench isolation structure DTI and forming the inter-gate dielectric layer 108. Referring to FIGS. 3, 21 and 22, the cover layer 105 in the deep trench isolation structure DTI is etched to make the top surface of the cover layer 105 lower than the top surface of the floating gate material layer 107 and higher than the front surface 100a of the substrate 100, thereby forming a recess above the deep trench isolation structure DTI. Then, the inter-gate dielectric layer 108 is formed on the substrate 100 to cover the inner surface of the recess and the surface of the floating gate material layer 108. The inter-gate dielectric layer 108 has, for example, an ONO (oxide-nitride-oxide) structure.

[0074] FIGS. 23 and 24 are cross-sectional views along the lines A-A' and B-B' of FIG. 3, respectively, after depositing a control gate material layer and performing etching to form the gate structure. Referring to FIGS. 3, 23 and 24, a polysilicon material is first deposited on the substrate 100 as a control gate material layer, which fills the recess above the deep trench isolation structure DTI and covers each substrate pixel unit 110; then, the control gate material layer and the underlying inter-gate dielectric layer 108 and floating gate material layer 107 are etched to form the gate structure 120 including the gate dielectric layer 106, the floating gate FG (formed by the floating gate material layer 107), the inter-gate dielectric layer 108 and the control gate FG (formed by the control gate material layer) on each substrate pixel unit 110. As shown in FIG. 3, in the process of etching to form the gate structure 120, the control gates CG on the substrate pixel units 110 in the same row are connected to form at least one word line (e.g., WL1 and WL2 shown in FIG. 3) that spans at least two substrate pixel units 110. As shown in FIG. 3, after forming the gate structure 120, part of the charge reading region 110b in the substrate pixel unit 110 is exposed from both sides of the control gate CG.

[0075] Afterwards, a sidewall process can be performed to form sidewalls (not shown) on the sides of the gate structure 120; then, a source / drain ion implantation is performed on the exposed charge reading region 110b to form a first source / drain region and a second source / drain region (shown as S / D in FIGS. 25 and 26) on both sides of the gate structure 120, respectively, which is, for example, a second doping type (e.g., n-type) ion implantation, so that the source region S and the drain region D have n-type doping (e.g., n+).

[0076] Before the source / drain ion implantation is performed, a first mask layer can be formed on the substrate 100 to cover the substrate lead-out region 110c and expose the reading region 110a and the charge reading region 110b, so that the n-type ions can be prevented from being implanted into the substrate lead-out region 110c during the source / drain ion implantation. After the source / drain ion implantation is completed, the first mask layer can be removed, and a second mask layer is formed on the substrate 100 to cover the regions other than the substrate lead-out region 110c and expose only the substrate lead-out region 110c, and then a first doping type (e.g., p-type) ion implantation is performed on the substrate lead-out region 110c to make the first doping type concentration on the surface of the substrate lead-out region 110c greater than that of the surrounding substrate 100, which helps to reduce the contact resistance of the substrate lead-out region 110c. For example, a p-type heavily doped (p+) layer is formed on the top of the substrate lead-out region 110c.

[0077] FIGS. 25 and 26 are cross-sectional views along the lines A-A' and B-B', respectively, of FIG. 3 after the interlayer dielectric layer 130 and the plugs are formed. Referring to FIGS. 3, 25 and 26, after the gate structure is formed, further processes can be performed on the front surface 100a of the substrate 100 as follows: first, an interlayer dielectric layer 130 is formed on the front surface 100a of the substrate 100, which includes, for example, a contact hole etching stop layer (not shown) covering the front surface 100a of the substrate 100 and an oxide layer covering the contact hole etching stop layer; then, a first source / drain plug CT1, a second source / drain plug CT2 and a substrate electrode plug CT3 are formed through the interlayer dielectric layer 130, the first source / drain plug CT1 is connected to the first source / drain region, the second source / drain plug CT2 is connected to the second source / drain region, and the substrate electrode plug CT3 is connected to the substrate lead-out region 110c. The first source / drain plug CT1, the second source / drain plug CT2 and the substrate electrode plug CT3 can include a metal, such as copper, nickel, zinc, tin, silver, gold, tungsten, magnesium, tantalum, titanium, molybdenum, platinum, aluminum, hafnium, ruthenium, copper alloy or aluminum alloy, etc., formed in a contact hole through the interlayer dielectric layer 130.

[0078] Further, a metal interconnection structure and a metal pad (not shown) can be formed on the interlayer dielectric layer 130. The first source / drain plug CT1, the second source / drain plug CT2 and the substrate electrode plug CT3 can be connected to the corresponding metal pad through the metal interconnection structure, so that a voltage can be applied to the substrate drawing-out area 110c in each substrate pixel unit 110 from the front side 100a of the substrate 100 through the corresponding metal pad, i.e. the purpose of applying a voltage to the substrate electrode of the MOS capacitor is achieved. Alternatively, after the metal interconnection structure and the metal pad are formed, a circuit substrate (not shown) can be bonded to the front side 100a of the substrate 100, so that the metal pad is connected to a device in the circuit substrate.

[0079] FIG. 27 and FIG. 28 are cross-sectional views along the lines A-A' and B-B' in FIG. 3, respectively, after the deep trench isolation structure DTI and the substrate pixel units 110 are exposed from the back side 100b of the substrate 100. Referring to FIG. 3, FIG. 27 and FIG. 28, referring to FIG. 6, step S4 is performed to thin the substrate 100 from the back side 100b, so that the deep trench isolation structure DTI and the substrate pixel units 110 separated by the deep trench isolation structure DTI are exposed.

[0080] In performing step S4, the back side 100b can be ground by a CMP process, so that the deep trench isolation structure DTI and the substrate pixel units 110 separated by the deep trench isolation structure DTI are exposed. Alternatively, after the CMP process is completed, a wet etching process can be performed to remove the damage on the surface of the substrate pixel units 110 caused by the CMP process. By exposing the deep trench isolation structure DTI and the substrate pixel units 110 separated by the deep trench isolation structure DTI from the back side 100b of the substrate 100, the substrate pixel units 110 are completely physically isolated, so that the cross-talk of photoelectrons between pixels can be effectively reduced.

[0081] Referring to FIG. 4 and FIG. 5, after the above steps are completed, a back side dielectric layer 140 can be further formed on the back side 100a of the substrate 100. As an example, the back side dielectric layer 140 can include a high dielectric constant layer 141 covering the deep trench isolation structure DTI and the substrate pixel units 110 from the back side 100b of the substrate 100, and an oxide layer 142 (e.g. silicon oxide) covering the high dielectric constant layer 141.

[0082] In the vertical charge transfer imaging sensor and the manufacturing method of the vertical charge transfer imaging sensor described in the above embodiments, the plurality of substrate pixel units 110 are formed by separating the substrate 100 by the deep trench isolation structure DTI, and the physical isolation of each substrate pixel unit 110 is achieved by penetrating the substrate 100 with the deep trench isolation structure DTI, so that the photoelectron crosstalk between the pixels corresponding to each substrate pixel unit 110 is avoided, and the device performance is improved. Furthermore, each substrate pixel unit 110 is separated into a light sensing region 110a, a charge reading region 110b and a substrate lead-out region 110c by the shallow trench isolation structure STI. Among the pixels formed corresponding to the substrate pixel unit 110, the substrate pixel unit 110 and the gate structure 120 constitute a MOS capacitor, the substrate pixel unit 110 is the substrate electrode of the MOS capacitor, and the substrate lead-out region 110c is the connection end of the substrate pixel unit 110. The substrate lead-out region 110c can be connected to the corresponding external signal by connecting the source / drain region to the external signal from the front surface 100a side of the substrate 100, so as to apply a voltage to the substrate electrode through the substrate lead-out region 110c.

[0083] It should be noted that the embodiments in the specification are described in a progressive manner, and each part focuses on the differences from the previous part. The same and similar parts between the parts can be referred to.

[0084] The above description is only a description of the preferred embodiments of the present application, and is not any definition of the scope of the present application. Any person skilled in the art can make possible changes and modifications to the technical solutions of the present application without departing from the spirit and scope of the present application by using the disclosed methods and technical contents. Therefore, any simple modification, equivalent change and modification made according to the technical essence of the present application to the above embodiments, without departing from the technical solutions of the present application, all belong to the protection scope of the present application.

Claims

1. A vertical charge transfer imaging sensor, characterized by, comprising: a substrate having a first doping type and including opposite front and back surfaces; a deep trench isolation structure penetrating through the substrate, the deep trench isolation structure separating the substrate to form a plurality of substrate pixel units; a shallow trench isolation structure formed on the front surface of the substrate, the shallow trench isolation structure separating each of the substrate pixel units into a photosensitive region, a charge reading region, and a substrate lead-out region; a reading transistor including a gate structure formed on the front surface of the charge reading region and a first source / drain region and a second source / drain region formed on the charge reading region on both sides of the gate structure, respectively, wherein the gate structure spans from the charge reading region to the photosensitive region; and a MOS capacitor formed by the gate structure and the corresponding substrate pixel unit, the substrate pixel unit being a substrate electrode of the MOS capacitor, and the substrate lead-out region being a voltage application region of the substrate electrode.

2. The vertical charge-transfer imaging sensor of claim 1, wherein, further comprising: an interlayer dielectric layer covering a plurality of the substrate pixel units, the deep trench isolation structure, the shallow trench isolation structure, the reading transistor, and the MOS capacitor from the front surface; a first source / drain plug penetrating through the interlayer dielectric layer to connect to the first source / drain region; a second source / drain plug penetrating through the interlayer dielectric layer to connect to the second source / drain region; and a substrate electrode plug penetrating through the interlayer dielectric layer to connect to the substrate lead-out region. The gate structure includes a gate dielectric layer, a floating gate, an inter-gate dielectric layer, and a control gate stacked on the surface of the photosensitive region and the charge reading region of the substrate pixel unit.

3. The vertical charge-transfer imaging sensor of claim 1, wherein, comprising:

4. The vertical charge-transfer imaging sensor of claim 3, wherein, at least one word line formed by the control gates in the gate structures on at least two of the substrate pixel units. The first doping type concentration of the surface of the substrate lead-out region is greater than the surrounding substrate, and the first source / drain region and the second source / drain region have a second doping type.

5. The vertical charge transfer imaging sensor of claim 1, wherein, The end surface of the deep trench isolation structure facing the same direction as the back surface of the substrate pixel unit is flush with the back surface of the substrate pixel unit.

6. The vertical charge-transfer imaging sensor of claim 1, wherein, comprising:

7. The vertical charge-transfer imaging sensor of claim 1, wherein, a back surface dielectric layer including a high dielectric constant layer covering the deep trench isolation structure and the substrate pixel unit from the back surface of the substrate and an oxide layer covering the high dielectric constant layer. comprising:

8. A method of manufacturing a vertical charge transfer imaging sensor, characterized by, providing a substrate having a first doping type and including opposite front and back surfaces; forming a deep trench isolation structure and a shallow trench isolation structure on the front surface of the substrate, the deep trench isolation structure and the shallow trench isolation structure extending from one side of the front surface into the substrate, the deep trench isolation structure separating the substrate to form a plurality of substrate pixel units, and the shallow trench isolation structure separating each of the substrate pixel units into a photosensitive region, a charge reading region, and a substrate lead-out region; forming a gate structure on the surface of each of the substrate pixel units corresponding to the front surface of the substrate and forming a first source / drain region and a second source / drain region on the charge reading region on both sides of the gate structure to form a reading transistor, wherein the gate structure spans from the charge reading region to the photosensitive region and forms a MOS capacitor with the corresponding substrate pixel unit; and ​ ​ thinning the substrate from the back surface to expose the deep trench isolation structure and a plurality of substrate pixel units separated by the deep trench isolation structure.

9. The production method according to claim 8, wherein Before thinning the substrate from the back surface, the manufacturing method further comprises: forming a patterned mask layer on the substrate, an opening in the mask layer exposes the substrate lead-out region; and performing first-doping-type ion implantation on the surface of the substrate lead-out region, so that the first-doping-type concentration of the surface of the substrate lead-out region is greater than that of the surrounding substrate.

10. The production method according to claim 8, wherein Further comprising: forming an interlayer dielectric layer on the front surface of the substrate; and forming a first source / drain plug, a second source / drain plug and a substrate electrode plug through the interlayer dielectric layer, the first source / drain plug is connected to the first source / drain region, the second source / drain plug is connected to the second source / drain region, and the substrate electrode plug is connected to the substrate lead-out region. Thinning the substrate from the back surface comprises:

11. The production method according to claim 8, wherein polishing the back surface of the substrate by a CMP process to expose the deep trench isolation structure and a plurality of substrate pixel units from the back surface of the substrate; and forming a back surface dielectric layer, the back surface dielectric layer includes a high dielectric constant layer covering the deep trench isolation structure and the substrate pixel units from the back surface of the substrate, and a low dielectric constant layer covering the high dielectric constant layer. After the CMP process is completed, wet etching is performed to remove the damage on the surface of the substrate pixel units.

12. The production method according to claim 11, wherein ​

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