Semiconductor device

Abstract

The invention relates to a semiconductor device (20, 60) wherein a) for a semiconductor device (20) with a planar gate architecture a ratio of a peak doping concentration (52) in cm-3 in a channel region (32) to a length (54) of the channel region (32) in cm between a first pn-junction and a second pn-junction along a charge carrier axis (38) is more than 5.8 · 1021 cm-4 and / or for a semiconductor device (60) with a trench gate architecture a ratio of a peak doping concentration (52) in cm-3 in the channel region (32) to a length (54) of the channel region (32) in cm between the first pn-junction and the second pn-junction is more than 5 · 1020 cm-4, and wherein the semiconductor device (20, 60) comprises an enhancement region (56) in the drift region (30), the enhancement region (56) being arrange along the charge carrier axis (38) adjacent to the channel region (32) and wherein a ratio of a peak doping concentration (52) in the channel region (32) to a peak doping concentration (58) in the enhancement region (56) is more than 1.75 · 102. Furthermore, the invention relates to a method for manufacturing a semiconductor device (20, 60).

Description

[0001] 1 P230210W001

[0002] Description

[0003] Semiconductor device

[0004] Technical Field

[0005] The invention relates to a semiconductor device.

[0006] Furthermore, the invention relates to method for manufacturing a semiconductor device.

[0007] Additionally, the invention relates to a semiconductor device produced by the above method.

[0008] Furthermore, the invention relates to a method for increasing the short circuit withstand capability of a semiconductor device without negatively affecting the on-state conduction losses of the semiconductor device

[0009] Background Art

[0010] Semiconductor devices are used as switches controlling the current flow through various electronic systems. Many semiconductor devices make use of a metal-ox- ide-semiconductor (MOS) structure. Devices that comprise a MOS structure are for example a MOS field-effect transistor (MOSFET), an insulated-gate bipolar transistor (IGBT), or a bi-mode insulated gate transistor (BIGT) being able to operate in both freewheeling diode mode and IGBT transistor mode.

[0011] The safe operating area (SOA) is defined as the voltage and current conditions over which a semiconductor device such as the above-mentioned IGBTs or MOSFETs can be expected to operate without self-damage or degradation. In case the semiconductor device is operated outside the SOA a breakdown of the device for example caused by a thermal runaway can occur.

[0012] For an IGBT a short-circuit failure can be explained by the following mechanism: 2 P230210W001

[0013] Electric charges are induced between the insulation layer and the interface when the gate electrode is biased, which creates an inverted channel region. Once the inverted channel region has been formed, current starts flowing through the collector electrode to the emitter electrode of the IGBT. The gate voltage at this point corresponds to the gate-emitter threshold voltage Vth (also called gate-emitter cut off voltage VGE(OFF)), i.e. the minimum gate-to-emitter voltage that is needed to create a conducting path or channel between the emitter / source and drain / collector electrodes. The IGBT controls the collector current lc by the change of the electric charge induced between the insulation layer and the interface.

[0014] However, when a short-circuit failure occurs the high currents and voltages in the device lead to higher temperature which lowers Vth. This is because electric charge is generated more easily at high temperature. Short-circuit (SC) is thus a critical failure mode for semiconductor devices such as the above-mentioned IGBT, when large overcurrent levels are flowing in the electrical circuits. The time a semiconductor device such as an IGBT can withstand SC conditions, i.e. the short-circuit withstand time, is related to the gain and the thermal capacity of the semiconductor device. Higher gain leads to higher short-circuit current levels Isc within the IGBT. Hence, lower gain IGBTs will have lower short-circuit current levels Isc. However, the lower gain also results in higher on-state conduction losses, the on-state conduction losses being described by the collector current lc multiplied by the collectoremitter saturation voltage VcE(sat). The collector-emitter saturation voltage VcE(sat) is the collector-emitter voltage when a rated gate-emitter voltage VGE is applied and the collector current lc is at the rated collector current value lc. VcE(sat) is also called collector-emitter saturation voltage.

[0015] In other words, the trade-off relationship of an IGBT describes the relation between on-state conduction losses and short circuit withstand capability and an IGBT can either be optimized for one of those. For example, when increasing short circuit withstand capability (by decreasing short-circuit current levels Isc) the on-state conduction losses increase. Overcoming this trade-off relationship will massively open- up the IGBT design space for an overall enhanced performance of IGBTs and other semiconductor devices. 3 P230210W001

[0016] Summary of invention

[0017] It is an object of the invention to increase the performance of semiconductor devices. It is a further object of the invention to increase the short circuit withstand capability with less negative effect on the on-state conduction losses.

[0018] The object of the invention is at least solved in part by the features of the independent claims. Modified embodiments are detailed in the dependent claims.

[0019] Thus, the object is at least solved in part by a semiconductor device comprising:

[0020] - a base region of a first conductivity type provided in a substrate,

[0021] - a source region being of a second conductivity type different to the first conductivity type provided in the substrate adjacent to the base region for forming a first pn-junction, the source region being configured to be connected to an emitter electrode,

[0022] - a drift region being of the second conductivity type provided in the substrate adjacent to the base region for forming a second pn-junction, the drift region being arranged separate from the source region, such that a channel region in between the source region and the drift region is formed in the base region, the drift region being configured to be connected to a collector electrode,

[0023] - an insulation layer arranged next to the channel region for separating the channel region from a gate electrode, and a) wherein for a semiconductor device with a planar gate architecture a ratio of a peak doping concentration in cm-3in the channel region to a length of the channel region in cm between the first pn-junction and the second pn-junc- tion along a charge carrier axis is more than 5.8 ■ 1021cm-4; and / or for a semiconductor device with a trench gate architecture a ratio of a peak doping concentration in cm-3in the channel region to a length of the channel region in cm between the first pn-junction and the second pn-junction along a charge carrier axis is more than 5 ■ 102° cm^; and / or b) wherein a doping concentration of the channel region and a length of the channel region between the first pn-junction and the second pn-junction 4 P230210W001 along a charge carrier axis is such that a gate-emitter threshold voltage Vth at 25 °C is above 6 V, , and such that at 25 °C for i) a 6.5 kV semiconductor device a collector-emitter saturation voltage VcE(sat) is in between 2.8 V and 3.2 V, and / or ii) a 4.5 kV semiconductor device a collector-emitter saturation voltage VcE(sat) is in between 2.1 V and 2.5 V, and / or iii) a 3.3 kV semiconductor device a collector-emitter saturation voltage VcE(sat) is in between 2.0 V and 2.5 V, and / or iv) a 1 .7 kV semiconductor device a collector-emitter saturation voltage VcE(sat) is in between 1.6 V and 2.0 V, and / or v) a 1 .2 kV semiconductor device a collector-emitter saturation voltage VcE(sat) is in between 1.3 V and 1 .7 V, and wherein VcE(sat) is the collector-emitter voltage when a rated gate-emitter voltage VGE is applied and the collector current lc is at the rated collector current value.

[0024] In a first alternative of the invention one aspect is thus that the semiconductor device has a channel design where the ratio of the peak doping concentration in cm-3to the length of the channel region in cm is for a planar gate architecture more than 5.8 ■ 1021cm-4and for a trench gate architecture more than 5 ■ 102° cm-4. This channel design has the advantage that it breaks the trade-off relationship between the on- state conduction losses and short circuit withstand capability. Compared to channel designs known in prior art, the length of the channel is reduced while its peak doping concentration is increased. Preferably the channel length is reduced and the peak doping concentration is increased in such a way that the collector-emitter saturation voltage VcE(sat) remains unchanged, while the gate-emitter threshold voltage Vth is increased. The higher threshold voltage Vth thus results in lower short-circuit current levels Isc and thus increased short circuit withstand capabilities, while the shorter channel length prevents the collector-emitter saturation voltage VcE(sat) to increase. Thus, the on-state conduction losses do not increase. The gate-emitter threshold voltage Vth is also called gate threshold voltage and is the minimum gate-to-emitter voltage that is needed to create a conducting path or channel between the emit- ter / source and drain / collector terminals. Preferably, the gate-emitter threshold voltage Vth is the gate-emitter voltage at which 10 mA current flows between emitter 5 P230210W001 and collector while the gate electrode is shorted to the collector electrode.

[0025] In a second alternative of the invention one aspect is thus that the doping concentration and the length of the channel region is such that the gate-emitter threshold voltage Vth at 25 °C is above 6 V, and such that at 25 °C for i) a 6.5 kV semiconductor device the collector-emitter saturation voltage VcE(sat) is in between 2.8 V and 3.2 V, and / or ii) a 4.5 kV semiconductor device the collector-emitter saturation voltage VcE(sat) is in between 2.1 V and 2.5 V, and / or iii) a 3.3 kV semiconductor device the collector-emitter saturation voltage VcE(sat) is in between 2.0 V and 2.5 V, and / or iv) a 1 .7 kV semiconductor device the collector-emitter saturation voltage VcE(sat) is in between 1.6 V and 2.0 V, and / or v) a 1 .2 kV semiconductor device the collector-emitter saturation voltage VcE(sat) is in between 1 .3 V and 1 .7 V.

[0026] In other words, the semiconductor device has improved on-state and short-circuit characteristics which are otherwise limited by the conventional trade-off between short-circuit current levels Isc and gate-emitter threshold voltage Vth. It is thus possible to gain about > 200-300 mV in collector-emitter saturation voltage VcE(sat) without sacrificing the short circuit withstand capability for typical IGBTs.

[0027] In a third alternative of the invention, both above-described aspects are realized.

[0028] Preferably, the object is at least solved in part by a semiconductor device comprising:

[0029] - a base region of a first conductivity type provided in a substrate,

[0030] - a source region being of a second conductivity type different to the first conductivity type provided in the substrate adjacent to the base region for forming a first pn-junction, the source region being configured to be connected to an emitter electrode,

[0031] - a drift region being of the second conductivity type provided in the substrate adjacent to the base region for forming a second pn-junction, the drift region being arranged separate from the source region, such that a channel region 6 P230210W001 in between the source region and the drift region is formed in the base region, the drift region being configured to be connected to a collector electrode,

[0032] - an insulation layer arranged next to the channel region for separating the channel region from a gate electrode, and wherein for a semiconductor device with a planar gate architecture a ratio of a peak doping concentration in cm-3in the channel region to a length of the channel region in cm between the first pn-junction and the second pn-junction along a charge carrier axis is more than 5.8 ■ 1021cm-4; and / or for a semiconductor device with a trench gate architecture a ratio of a peak doping concentration in cm-3in the channel region to a length of the channel region in cm between the first pn-junction and the second pn-junction along a charge carrier axis is more than 5 ■ 1020cm-4, and wherein the semiconductor device comprises an enhancement region in the drift region, the enhancement region being arrange along the charge carrier axis adjacent to the channel region and wherein a ratio of a peak doping concentration in the channel region to a peak doping concentration in the enhancement region is more than 1.75 ■ 102.

[0033] The invention is based on the relationship of the collector emitter current ICE in an IGBT, or the drain source current IDS in a MOSFET when approaching saturation conditions. It is known that the device’s short-circuit current levels Isc is limited by the device’s gate-emitter threshold voltage Vth for an IGBT and gate-source threshold voltage Vth for a MOSFET, respectively: with W being the channel width, L being the channel length,nbeing the mobility of the electrons in the channel, Cox being the capacitance of the parallel-plate capacitor formed by the gate electrode and the channel, VDS being the drain-to-source voltage, VGS being the gate-to-source voltage, and m being a bulk-charge factor. 7 P230210W001

[0034] The higher the threshold voltage Vth the lower the device’s short-circuit current levels Isc. However, a higher threshold voltage Vth also increases the drain-source saturation voltage VDS(SAT) (i.e. the collector-emitter saturation voltage VcE(sat) in IGBT).

[0035] Figure 1 schematically shows the output characteristics of two IGBT devices according to prior art, and illustrates this trade-off relationship between gate-emitter threshold voltage Vth and collector-emitter saturation voltage VcE(sat). On the y-axis 10 of figure 1 the collector current lc is shown, the x-axis 12 shows the collectoremitter voltage VCE. Figure 1 shows the output characteristics of two IGBT devices according to prior art with different gate-emitter threshold voltages Vth. The collector current lc illustrated by curve 14 is for the device with higher gate-emitter threshold voltage Vth, while curve 16 illustrates the collector current lc for the device with lower gate-emitter threshold voltage Vth. Figure 1 shows that the higher the gate-emitter threshold voltage Vth of the device, the lower the saturation current and thus the short-circuit current levels Isc. It further shows that a higher gate-emitter threshold voltage Vth also means that the device has a higher collector-emitter saturation voltage VcE(sat) and thus higher on-state conduction losses, since the on-state conduction losses are described by the collector current lc when the collector-emitter saturation voltage VcE(sat) is applied multiplied by the collector-emitter saturation voltage VcE(sat).

[0036] The invention is based on the idea to accompanying the increase in gate-emitter threshold voltage Vth with a reduction in the channel length, such that the collectoremitter saturation voltage VcE(sat) remains unchanged. This design idea is illustrated in figure 2. On the y-axis 10 of figure 2 the collector current lc is shown, the x-axis 12 shows the collector-emitter voltage VCE. The output characteristic illustrated by curve 16 is the same as in figure 1 for a device according to prior art with low gateemitter threshold voltage Vth. Curve 18 in figure 2 however shows that the trade-off between on-state conduction losses and short circuit withstand capability can be broken. Even though for a device with a collector current lc according to curve 18 the gate-emitter threshold voltage Vth is increased compared to curve 16 resulting in lower short-circuit current levels Isc and thus higher short circuit withstand capability, the lower channel length for the device with curve 18 in figure 2 compared to 8 P230210W001 curve 16 in figure 2, compensates the negative effect on the collector-emitter saturation voltage VcE(sat). Thus, the on-state conduction losses are not increased.

[0037] Regarding the structure of the semiconductor device, the device comprises several regions provided in the substrate being adjacent to each other - i.e. the source region being provided adjacent to the base region and the drift region being provided adjacent to the base region. As the base region is of the first conductivity type, preferably p-type, and the source region and the drift region are of the second conductivity type, preferably n-type, two pn-junctions are formed within the substrate.

[0038] When a voltage VGE is applied to the gate electrode electric charges are induced between the insulation layer and the interface, which creates an inverted channel region, such that when the applied voltage VGE is above the gate-emitter threshold voltage Vth, charge carriers, preferably electrons, start flowing from the emitter electrode to the collector electrode via the channel region.

[0039] Preferably the semiconductor device can be configured with a planar gate architecture or with a trench gate architecture. In the planar gate architecture, the gate electrode is preferably arranged planarly on the semiconductor device, such that within the channel region the charge carrier axis is arranged perpendicularly to a connection axis that connects the emitter electrode with the collector electrode. In other words, the channel region is arranged horizontally, when the emitter electrode and the collector electrode are arranged vertically on top of each other.

[0040] In the trench gate architecture, the gate electrode is preferably carved into the semiconductor device, such that within the channel region the charge carrier axis is arranged parallel to a connection axis that connects the emitter electrode with the collector electrode. In other words, the channel region is arranged vertically, when the emitter electrode and the collector electrode are arranged vertically on top of each other.

[0041] According to a preferred embodiment of the invention, the semiconductor device comprises an enhancement region in the drift region, the enhancement region being arrange along the charge carrier axis adjacent to the channel region and wherein a 9 P230210W001 ratio of a peak doping concentration in the channel region to a peak doping concentration in the enhancement region is more than 1.75 ■ 102. This ensures a good blocking capability of the device.

[0042] According to another preferred embodiment of the invention, the channel length is below 2 pm. Having a channel length below 2 pm provides a semiconductor device having an even more increased short circuit withstand capability without negatively affecting the on-state conduction losses.

[0043] According to a first preferred alternative embodiment of the invention a semiconductor device is provided, wherein the channel region is uniformly doped along the charge carrier axis. This is a simple way to dope the channel region and provide a channel region where the ratio of the peak doping concentration to the length of the channel is more than 5.8 ■ 1021cm-4for planar gate architecture and more than 5 ■ 1O20cm-4for trench gate architecture.

[0044] According to a second preferred alternative embodiment of the invention a semiconductor device is provided, wherein the channel region is non-uniformly doped along the charge carrier axis. In other words, in this embodiment the channel region has a non-constant doping profile. This makes it possible to adapt the doping profile to the specific needs.

[0045] In connection to this and according to another preferred embodiment of the invention, the channel region comprises in a direction from the source region to the drift region along the charge carrier axis a high-low doping profile. The high-low doping profile makes the device particularly simple to manufacture.

[0046] According to another preferred embodiment of the invention, the source region is uniformly doped. Having a uniformly doped source region has the advantage that the manufacturing of the device is simplified.

[0047] According to another preferred embodiment of the invention, the features a) and b) are realized. In other words, according to this preferred embodiment a semiconduc- 10 P230210W001 tor device is provided wherein for a semiconductor device with a planar gate architecture the ratio of the peak doping concentration in cm-3in the channel region to the length of the channel region in cm between the first pn-junction and the second pn-junction along the charge carrier axis is more than 5.8 ■ 1021cm-4and / or for a semiconductor device with a trench gate architecture a ratio of a peak doping concentration in cm-3in the channel region to a length of the channel region in cm between the first pn-junction and the second pn-junction along a charge carrier axis is more than 5 ■ 102° cm-4and wherein the doping concentration of the channel region and the length of the channel region between the first pn-junction and the second pn-junction along the charge carrier axis is such that the gate-emitter threshold voltage Vth at 25 °C is above 6 V, and such that at 25 °C for i) a 6.5 kV semiconductor device the collector-emitter saturation voltage VcE(sat) is in between 2.8 V and 3.2 V, and / or ii) a 4.5 kV semiconductor device the collector-emitter saturation voltage VcE(sat) is in between 2.1 V and 2.5 V, and / or iii) a 3.3 kV semiconductor device the collector-emitter saturation voltage VcE(sat) is in between 2.0 V and 2.5 V, and / or iv) a 1 .7 kV semiconductor device the collector-emitter saturation voltage VcE(sat) is in between 1.6 V and 2.0 V, and / or v) a 1 .2 kV semiconductor device the collector-emitter saturation voltage VcE(sat) is in between 1 .3 V and 1 .7 V, and wherein VcE(sat) is the collector-emitter voltage when the rated gate-emitter voltage VGE is applied and the collector current lc is at the rated collector current value.

[0048] According to another preferred embodiment of the invention, a semiconductor device is provided wherein all of features i) to v) are realized. In other words, in this preferred embodiment the doping concentration of the channel region and the length of the channel region between the first pn-junction and the second pn-junction along the charge carrier axis is such that the gate-emitter threshold voltage Vth at 25 °C is above 6 V, and such that at 25 °C for i) a 6.5 kV semiconductor device with the collector-emitter saturation voltage VcE(sat) is in between 2.8 V and 3.2 V, and ii) a 4.5 kV semiconductor device with the collector-emitter saturation voltage VcE(sat) is in between 2.1 V and 2.5 V, and 11 P230210W001 iii) a 3.3 kV semiconductor device with the collector-emitter saturation voltage VcE(sat) is in between 2.0 V and 2.5 V, and iv) a 1.7 kV semiconductor device with the collector-emitter saturation voltage VcE(sat) is in between 1.6 V and 2.0 V, and v) a 1.2 kV semiconductor device with the collector-emitter saturation voltage VcE(sat) is in between 1.3 V and 1 .7 V.

[0049] According to another preferred embodiment of the invention, the semiconductor device comprises a planar gate architecture. According to an alternative embodiment of the invention, the semiconductor device comprises a trench gate architecture.

[0050] According to another preferred embodiment of the invention, the semiconductor device is a 6.5 kV semiconductor device preferably with a planar gate architecture. According to an alternative preferred embodiment of the invention, the semiconductor device is a 4.5 kV semiconductor device preferably with a planar gate architecture. According to further preferred alternative embodiment of the invention, the semiconductor device is a 3.3 kV semiconductor device preferably with a trench gate architecture. According to another preferred alternative embodiment of the invention, the semiconductor device is a 1 .7 kV semiconductor device preferably with a trench gate architecture. And according to further preferred alternative embodiment of the invention, the semiconductor device is a 1.2 kV semiconductor device preferably with a trench gate architecture.

[0051] According to another preferred embodiment of the invention, the source region is a n-type source region, and / or the base region is a p-type base region. In other words, in this preferred embodiment the semiconductor device is preferably of the n-type channel type, where upon inversion an n-type channel is formed in the channel region, with electrons being the majority charge carriers. As electrons have a higher mobility than holes, faster switching speeds are possible.

[0052] According to another preferred embodiment of the invention, the semiconductor device is configured as MOSFET (metal-oxide-semiconductor field-effect transistor), IGBT (insulated-gate bipolar transistor), or BIGT (bi-mode insulated gate transistor). Particularly preferably the semiconductor device is configured as MOSFET or IGBT 12 P230210W001 and further preferably as n-type MOSFET or n-type IGBT.

[0053] MOSFETs and IGBTs are different types of transistors having many common features, however the terminology is often different. While in an IGBT the electrode that provides the charge carriers is generally termed “emitter electrode” in a MOSFET this electrode is often termed “source electrode”. On the other hand, the “collector electrode” of the IGBT is in the MOSFET often termed “drain electrode”.

[0054] According to another preferred embodiment of the invention, the semiconductor device comprises a contact layer adjacent to the base region, the source region, and the emitter electrode, the contact layer being of the first conductivity type and having a higher carrier concentration than the base region. The contact region preferably provides immunity against parasitic thyristor latch-up in the semiconductor device, being potentially destructive in nature. In additional, the contact region preferably lowers the contact resistance for the emitter electrode.

[0055] According to another preferred embodiment of the invention, the semiconductor device comprises a collector layer being of the first conductivity type in between the collector electrode and the drift region. In this embodiment the semiconductor device is preferably configured as IGBT. The collector layer preferably provides together with the drift region and the base region a bipolar junction transistor arranged along the connection axis that connects the emitter electrode with the collector electrode.

[0056] According to a further preferred embodiment of the invention, the semiconductor device comprises a semiconductor material selected from the group consisting of silicon (Si), silicon carbide (SiC), gallium nitride (GaN), gallium(lll) oxide (Ga2Os), aluminium nitride (AIN), aluminium gallium nitride (AlxGai-xN), gallium arsenide (GaAs), and diamond. Preferably, the semiconductor material is silicon. Particularly preferably, the semiconductor device is a silicon IGBT.

[0057] Further embodiments and advantages of the semiconductor device are directly and unambiguously derived by the person skilled in the art from the description of the 13 P230210W001 method for manufacturing a semiconductor device, from the description of the semiconductor device manufactured by said method and from the description of the specific examples.

[0058] The object of the invention is also solved at least in part by a method for manufacturing a semiconductor device.

[0059] Thus, according to the invention, a method for manufacturing a semiconductor device by generating a channel region in a substrate through implantation of carriers into the substrate is provided, wherein a) implantation is performed with a ratio of a channel doping dose to a channel plateau driving time higher than 7.14 ■ 1011cm-2min-1and a thermal budget below 2.3 ■ 105°C- min, wherein the thermal budget denotes the product of the channel plateau driving time and a temperature at which the carriers are diffused into the substrate; or b) in a first step a channel precursor region in the substrate is formed through implantation of carriers of a first conductivity type into the substrate, followed by an implantation of carriers of a second conductivity type, being different to the first conductivity type to form the channel region.

[0060] Preferably a method for manufacturing a semiconductor device by generating a channel region in a substrate through implantation of carriers into the substrate is provided, wherein a) implantation is performed with a ratio of a channel doping dose to a channel plateau driving time higher than 7.14 ■ 1011cm-2min-1and a thermal budget below 2.3 ■ 105°C- min, wherein the thermal budget denotes the product of the channel plateau driving time and a temperature at which the carriers are diffused into the substrate; or b) in a first step a channel precursor region in the substrate is formed through implantation of carriers of a first conductivity type into the substrate, followed by an implantation of carriers of a second conductivity type, being different to the first conductivity type to form the channel region; and for alternative a) and alternative b) the method comprises the step of generating an enhancement region adjacent to 14 P230210W001 the channel region through implantation of carriers into the substrate wherein implantation is performed such that a ratio of the peak doping concentration in the channel region to the peak doping concentration in the enhancement region is more than 1.75 • 102; and wherein the semiconductor device comprises a planar gate architecture, and wherein implantation of the carriers into the substrate is performed such that a ratio of a peak doping concentration in cm-3in the channel region to a length of the channel region of more than 5.8 ■ 1021cm-4; or wherein the semiconductor device comprises a trench gate architecture, and wherein implantation of the carriers into the substrate is performed such that a ratio of a peak doping concentration in cm-3in the channel region to a length of the channel region of more than 5 ■ 102° cm-4.

[0061] In other words, a short channel region is generated either by a higher doping dose and a reduced thermal budget, or by reducing the length of the channel region with an additional step where carriers of the different conductivity type for compensating the effects of the previously implanted carriers are implanted.

[0062] According to a further preferred embodiment of the invention, the semiconductor device comprises a planar gate architecture, and the implantation of the carriers into the substrate is performed such that a ratio of a peak doping concentration in cm-3in the channel region to a length of the channel region is more than 5.8 ■ 1021cm-4.

[0063] According to an alternative preferred embodiment of the invention, the semiconductor device comprises a trench gate architecture, and the implantation of the carriers into the substrate is performed such that the ratio of a peak doping concentration in cm-3in the channel region to the length of the channel region is more than 5 ■ 1020cm-4.

[0064] According to another preferred embodiment of the invention, feature a) is realized and the channel doping dose is above 1 .5 ■ 1014cm-2. This is an easy way to ensure that a short channel with a high peak doping concentration is generated.

[0065] According to another preferred embodiment of the invention the channel region in 15 P230210W001 the substrate is generated through a dual doping of dopants having different diffusion rates.

[0066] According to a further preferred embodiment of the invention, the method comprises the step of generating an enhancement region adjacent to the channel region through implantation of carriers into the substrate wherein implantation is performed such that a ratio of the peak doping concentration in the channel region to the peak doping concentration in the enhancement region is more than 1.75 ■ 102. This is preferably achieved by reducing the enhancement drive plateau time.

[0067] The invention further relates to a semiconductor device manufactured according to the above-described method.

[0068] Furthermore, the invention also relates to a method for increasing the short circuit withstand capability of a semiconductor device without negatively affecting the on- state conduction losses of the semiconductor device by generating a channel region in a substrate through implantation of carriers into the substrate, such that in comparison to a reference semiconductor device with a predefined channel length and a predefined peak doping concentration in the channel region, the channel length is reduced and the peak doping concentration is increased in such a way that a col- lector-emitter saturation voltage VcE(sat) of the semiconductor device remains unchanged.

[0069] These and other aspects of the invention will be apparent from and elucidated with reference to the embodiments described hereinafter.

[0070] In the drawings:

[0071] Fig. 1 schematically shows output characteristics of two IGBT devices according to prior art,

[0072] Fig. 2 schematically illustrates the design principle by showing output characteristics of an IGBT devices according to prior art compared 16 P230210W001 to output characteristics of an IGBT according to a preferred embodiment of the invention,

[0073] Fig. 3 schematically shows a semiconductor device with a planar gate architecture according to a preferred embodiment of the invention,

[0074] Fig. 4 schematically shows a doping profile of the semiconductor device of figure 3,

[0075] Fig. 5 schematically shows a semiconductor device with a trench gate architecture according to another preferred embodiment of the invention,

[0076] Fig. 6 schematically shows a doping profile of the semiconductor device of figure 5,

[0077] Fig. 7 schematically shows simulation results for the semiconductor device of figure 5 with different channel length and varying peak doping concentration,

[0078] Fig. 8 schematically shows simulation results for the output characteristics

[0079] (a) and the transfer characteristics (b) of the semiconductor device of figure 5 with two different channel length and two different peak doping concentration,

[0080] Fig. 9 schematically shows in (a) a temperature-time-profile during channel drive, and in (b) a temperature-time-profile during enhancement drive for manufacturing a semiconductor device according to a preferred embodiment of the invention and as comparison for manufacturing a reference device according to prior art,

[0081] Fig. 10 schematically shows measured output characteristics for two semiconductor devices according to preferred embodiments of the invention compared to a semiconductor device according to prior art, 17 P230210W001

[0082] Fig. 11 schematically shows measured gate-emitter threshold voltage Vth vs. collector-emitter saturation voltage VcE(sat) for two semiconductor devices according to preferred embodiments of the invention compared to two semiconductor devices according to prior art, and

[0083] Fig. 12 schematically shows measured short circuit characteristics of two semiconductor devices according to preferred embodiments of the invention compared to two semiconductor devices according to prior art.

[0084] Description of embodiments

[0085] Fig. 3 schematically shows a semiconductor device 20 with a planar gate architecture according to a preferred embodiment of the invention.

[0086] The semiconductor device 20 comprises a base region 22 of a first conductivity type provided in a substrate 24. In this embodiment the base region 22 is of p-type. The semiconductor device 20 further comprises a source region 26 being of a second conductivity type - in this embodiment n-type - provided in the substrate 24 adjacent to the base region 22 for forming a first pn-junction. The source region 26 is configured to be connected to an emitter electrode 28. The semiconductor device 20 further comprises a drift region 30 being of the second conductivity type - in this embodiment n-type - provided in the substrate 24 adjacent to the base region 22 for forming a second pn-junction. The drift region 30 is arranged separate from the source region 26, such that a channel region 32 in between the source region 26 and the drift region 30 is formed in the base region 22. Furthermore, the drift region 30 is configured to be connected to a collector electrode (not shown on figure 3). Furthermore, the semiconductor device 20 comprises an insulation layer 34 arranged next to the channel region 32 for separating the channel region 32 from a gate electrode 36.

[0087] When a voltage VGE is applied to the gate electrode 36 electric charges are induced, 18 P230210W001 which generate the channel region 32, such that charge carriers can flow from the emitter electrode 28 to the collector electrode via the channel region 32. As in figure 3 the semiconductor device 20 is of planar gate architecture a charge carrier axis 38 along which the charges flow in the channel region 32 is arranged perpendicularly to a connection axis 40 that connects the emitter electrode 28 with the collector electrode.

[0088] As can further be seen in figure 3, in order to prevent that the gate electrode 36 is directly connected to the emitter electrode 28, a further insulation layer 42 is arranged on top of the gate electrode 36. Additionally, the semiconductor device 20 comprises a contact layer 43 adjacent to the base region 22, the source region 26, and the emitter electrode 28, the contact layer 43 being of the first conductivity type and having a higher carrier concentration than the base region 22.

[0089] Figure 4 schematically shows a profile of a doping concentration 44 of the semiconductor device 20 of figure 3 along a direction parallel to the charge carrier axis 38. The y-axis 46 of figure 3 shows the doping concentration in cm-3, while the x-axis 48 shows the location along the cutline 50 indicated in figure 3 parallel to the charge carrier axis 38.

[0090] As can be seen in figure 4, the doping concentration 44 for the semiconductor device 20 decreases from the source region 26 to the channel region 32. Furthermore, figure 4 shows that a ratio of a peak doping concentration 52 in cm-3in the channel region 32 to a length 54 of the channel region 32 in cm between the first pn-junction and the second pn-junction along the charge carrier axis 38 is more than 5.8 ■ 1021cm-4.

[0091] As can further be seen in figure 4, the semiconductor device 20 comprise an enhancement region 56 in the drift region 30, the enhancement region 56 being arrange along the charge carrier axis 38 adjacent to the channel region 56. For simplicity the enhancement region 56 is not shown in the schematic illustration of the semiconductor device 20 in figure 3. In this embodiment a ratio of the peak doping concentration 52 in the channel region 32 to a peak doping concentration 58 in the enhancement region 56 is more than 1.75 ■ 102. 19 P230210W001

[0092] For comparison, figure 4 schematically also shows a profile of a doping concentration 44’ of a semiconductor device according to prior art with planar gate architecture, where a ratio of a peak doping concentration 52’ in cm-3in the channel region 32 to a length 54’ of the channel region 32 in cm between the first pn-junction and the second pn-junction along the charge carrier axis 38 is not more than 5.8 ■ 1021cm-4.

[0093] Figure 5 schematically shows a semiconductor device 60 with a trench gate architecture according to another preferred embodiment of the invention. Similar to the device 20 shown in figure 3, the device 60 in figure 5 comprises a base region 22 of a first conductivity type provided in a substrate 24. The semiconductor device 60 further comprises a source region 26 being of a second conductivity type provided in the substrate 24 adjacent to the base region 22 for forming a first pn-junction. The source region 26 is configured to be connected to an emitter electrode 28. The semiconductor device 60 further comprises a drift region 30 being of the second conductivity type provided in the substrate 24 adjacent to the base region 22 for forming a second pn-junction. The drift region 30 is arranged separate from the source region 26, such that a channel region 32 in between the source region 26 and the drift region 30 is formed in the base region 22. Furthermore, the drift region 30 is configured to be connected to a collector electrode (not shown on figure 5). Furthermore, the semiconductor device 60 comprises an insulation layer 34 arranged next to the channel region 32 for separating the channel region 32 from a gate electrode 36. Additionally, the semiconductor device 60 comprises a contact layer 43 adjacent to the base region 22, the source region 26, and the emitter electrode 28, the contact layer 43 being of the first conductivity type and having a higher carrier concentration than the base region 22.

[0094] When a voltage VGE is applied to the gate electrode 36 electric charges are induced, which generate the channel region 32, such that charge carriers can flow from the emitter electrode 28 to the collector electrode via the channel region 32. As in figure 5 the semiconductor device 60 is of trench gate architecture a charge carrier axis 38 along which the charges flow in the channel region 32 is arranged parallel to a 20 P230210W001 connection axis 40 that connects the emitter electrode 28 with the collector electrode.

[0095] Figure 6 schematically shows a profile of a doping concentration 62 of the semiconductor device 60 of figure 5 along a direction parallel to the charge carrier axis 38 in the channel region 32. The y-axis 46 of figure 5 shows the doping concentration in cm-3, while the x-axis 48 shows the location along the device 60 along the cutline 50 indicated in figure 5 parallel to the charge carrier axis 38.

[0096] As can be seen in figure 6, the doping concentration 62 for the semiconductor device 60 in the channel region 32 for this specific embodiment is uniform. Furthermore, figure 6 shows that a ratio of a peak doping concentration 52 in cm-3in the channel region 32 to a length 54 of the channel region 32 in cm between the first pn-junction and the second pn-junction along the charge carrier axis 38 is more than 5 ■ 1020cm-4. Semiconductor devices 60 with trench gate architecture can in general also have different doping profiles such as high-low doping profiles from the source region 26 to the drift region 30.

[0097] For comparison, figure 6 schematically also shows a profile of a doping concentration 62’ of a semiconductor device according to prior art with trench gate architecture, where a ratio of a peak doping concentration 52’ in cm-3in the channel region 32 to a length 54’ of the channel region 32 in cm between the first pn-junction and the second pn-junction along the charge carrier axis 38 is not more than 5 ■ 102° cm-4.

[0098] Figure 7 schematically shows simulation results 64, 64’ for the semiconductor device 60 of figure 5 with different channel length 54 and varying peak doping concentration 52. The y-axis 66 of figure 7 denotes the short-circuit current levels Isc in Ampere, while the x-axis 68 denotes the collector-emitter saturation voltage VcE(sat) in Volt. The simulation results 64 are from a device 60 with a channel length 54 of 0.5 pm while the simulation results 64’ are from a device 60 with a channel length 54 of 2 pm. Figure 7 shows that a device with a shorter channel length 54 shows an improved trade-off with about 78 % lower short-circuit current levels Isc for the same 21 P230210W001 collector-emitter saturation voltage VcE(sat). The arrow 70 in figure 7 shows the direction of increasing gate-emitter threshold voltage Vth for the devices.

[0099] Figure 8 schematically shows in a) simulation results for the output characteristics 72 and in b) the transfer characteristics 74 of the semiconductor device 60 of figure 5 with two different channel length 54 and two different peak doping concentration 52. Curve 72 illustrates the simulated output characteristics for a device 60 with channel length 54 of 0.5 pm and a peak doping concentration 52 of 3-1017cm-3, curve 74 illustrates the simulated transfer characteristics for a device 60 with channel length 54 of 0.5 pm and a peak doping concentration 52 of 3- 1017cm-3. In other words, for curve 72 and curve 74, the ratio of the peak doping concentration 52 in cm-3in the channel region 32 to the length 54 of the channel region 32 in cm between the first pn-junction and the second pn-junction is more than 5 ■ 102° cm-4. For comparison curve 72’ illustrates the simulated output characteristics and curve 74’ the simulated transfer characteristics for a device with channel length 54 of 2 pm and a peak doping concentration 52’ of 1 -1016cm-3. In other words, for curve 72’ and curve 74’, the ratio of the peak doping concentration 52 in cm-3in the channel region 32 to the length 54 of the channel region 32 in cm between the first pn-junction and the second pn-junction is less than 5 ■ 1020cm-4. The y-axis 10 in figures 8a) and 8b) denotes the collector current lc. The x-axis 12 in figure 8a) denotes the collector-emitter voltage VCE. The x-axis 76 in figure 8b) denotes the gate emitter voltage VGE. Figure 8 shows that the device 60 with the short channel length 54 and a high peak doping concentration 52 shows higher gate-emitter threshold voltage Vth (and thus lower short-circuit current levels Isc) without an adverse effect on the collector-emitter saturation voltage VcE(sat) (and thus on-state conduction losses).

[0100] Figure 9 schematically shows in (a) a temperature-time-profile 78 during channel drive, and in (b) a temperature-time-profile 80 during enhancement drive for manufacturing a semiconductor device according to preferred embodiments of the method step 82 and as comparison a comparative method step 84 for manufacturing a reference device according to prior art. The y-axis 86 in figure 9 denotes the temperature, while the x-axis 88 denotes the time. For manufacturing the semiconductor device according to preferred embodiments of the invention, the channel doping dose is increased for raising the peak doping concentration 52 in the channel region 22 P230210W001

[0101] 32. Furthermore, as can be seen in figure 9a), the channel drive plateau time is reduced for reducing the length 54 of the channel region 32. In other words, the implantation is performed with a ratio of the channel doping dose to the channel plateau driving time higher than 7.14 ■ 1011cm-2min-1and a thermal budget below 2.3 ■ 105°C min, wherein the thermal budget denotes the product of the channel plateau driving time and the temperature at which the carriers are diffused into the substrate.

[0102] Additionally, as can be seen in figure 9b), the enhancement drive plateau time is reduced to keep the peak doping concentration 58 in the enhancement region 56 unchanged.

[0103] Figure 10 schematically shows measured output characteristics 90 for two semiconductor devices according to preferred embodiments of the invention compared to measured output characteristics 90’ for a semiconductor device according to prior art. The y-axis 10 of figure 10 denotes the collector current lc in Ampere, while the x-axis 12 denotes the collector-emitter voltage VCE in Volts. The temperature for the measurement was 25 °C and the applied gate emitter voltage VGE was 15 V. Figure 10 shows that semiconductor devices having a channel region 32 where the ratio of the peak doping concentration 52 to the length 54 of the channel region 32 is more than 5.8 ■ 1021cm-4have systematic reductions in the short-circuit current levels Isc without compromising their on-state characteristics. Lower short-circuit current levels Isc in the semiconductor devices is related to a higher gate-emitter threshold voltage Vth. In the devices according to the preferred embodiment compared to the prior art device, the channel length 54 is reduced and the peak doping concentration 52 is increased in such a way that the collector-emitter saturation voltage VcE(sat) of the semiconductor device remains unchanged.

[0104] Figure 11 schematically shows measured data 92 for two semiconductor devices according to preferred embodiments of the invention compared to measured data 92’, 92” for two semiconductor devices according to prior art at a temperature of 125 °C. Figure 11 plots on the y-axis 94 the gate-emitter threshold voltage Vth in Volt and on the x-axis 68 the collector-emitter saturation voltage VcE(sat) in Volt. Starting from the data 92‘ of the semiconductor devices according to prior, the short circuit 23 P230210W001 withstand capability is increased without negatively affecting the on-state conduction losses as shown by the data 92. When comparing the data 92’ to the data 92” the short circuit withstand capability is also increased, however as the collectoremitter saturation voltage VcE(sat) is also increased the on-state conduction losses are increased.

[0105] Figure 12 schematically shows measured short circuit characteristics 96 of the two semiconductor devices according to preferred embodiments of the invention compared to measured short circuit characteristics 96’, 96” of the two semiconductor devices according to prior art at a temperature of 125 °C and with a collector-emitter voltage VCE of 3400 V. The x-axis 88 in figure 12 represents the time in microseconds, the y-axis 98 on the top diagram denotes the collector-emitter voltage VCE in Volt, the y-axis 100 in the middle diagram denotes the gate emitter voltage VGE in Volt, and the y-axis 10 in the bottom diagram denotes the collector current lc in Ampere. The diagram shows that the two semiconductor devices according to the preferred embodiments have compared to the short circuit characteristics 96’ of the device according to prior art a lower collector current lc during short circuit conditions. The prior art device with the short circuit characteristics 96” has an even lower collector current lc, however for this device, as is shown in figure 11 , the on-state conduction losses are increased.

[0106] While the invention has been illustrated and described in detail in the drawings and foregoing description, such illustration and description are to be considered illustrative or exemplary and not restrictive; the invention is not limited to the disclosed embodiments. Other variations to the disclosed embodiments can be understood and effected by those skilled in the art in practicing the claimed invention, from a study of the drawings, the disclosed, and the appended claims. In the claims, the word “comprising” does not exclude other elements or steps, and the indefinite article “a” or “an” does not exclude a plurality. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage. Any reference signs in the claims should not be construed as limiting scope. 24 P230210W001

[0107] Reference signs list

[0108] 10 y-axis, collector current lc

[0109] 12 x-axis, collector-emitter voltage VCE

[0110] 14 collector current lc for prior art IGBT with high gate-emitter threshold voltage Vth

[0111] 16 collector current lc for prior art IGBT with low gate-emitter threshold voltage Vth

[0112] 18 collector current lc for IGBT with high gate-emitter threshold voltage Vth and short channel length

[0113] 20 semiconductor device with planar gate architecture

[0114] 22 base region

[0115] 24 substrate

[0116] 26 source region

[0117] 28 emitter electrode

[0118] 30 drift region

[0119] 32 channel region

[0120] 34 insulation layer

[0121] 36 gate electrode

[0122] 38 charge carrier axis

[0123] 40 connection axis

[0124] 42 further insulation layer

[0125] 43 contact layer

[0126] 44 doping concentration profile for device 20

[0127] 44’ doping concentration profile for prior art device with planar gate architecture

[0128] 46 y-axis, doping concentration

[0129] 48 x-axis, location

[0130] 50 cutline

[0131] 52 peak doping concentration in channel region

[0132] 54 length of channel region

[0133] 56 enhancement region

[0134] 58 peak doping concentration in enhancement region

[0135] 60 semiconductor device with trench gate architecture

[0136] 62 doping concentration profile for device 60 25 P230210W001

[0137] 62’ doping concentration profile for prior art device with trench gate architecture

[0138] 64 simulation results for device with channel length of 0.5 pm

[0139] 64’ simulation results for device with channel length of 2 pm

[0140] 66 y-axis, short-circuit current levels Isc

[0141] 68 x-axis, collector-emitter saturation voltage VcE(sat)

[0142] 70 Arrow, showing direction of increasing gate-emitter threshold voltage Vth

[0143] 72 simulated output characteristics for device 60 with channel length of 0.5 pm and peak doping concentration of 3 1017cm-3

[0144] 72’ simulated output characteristics for prior art device with channel length of 2 pm and peak doping concentration of 1 ■ 1016cm-3

[0145] 74 simulated transfer characteristics for device 60 with channel length of 0.5 pm and peak doping concentration of 3 1017cm-3

[0146] 74’ simulated transfer characteristics for prior art device with channel length of 2 pm and peak doping concentration of 1 ■ 1016cm-3

[0147] 76 x-axis, gate emitter voltage VGE

[0148] 78 Temperature-time-profile during channel drive

[0149] 80 Temperature-time-profile during enhancement drive

[0150] 82 preferred embodiment of method step

[0151] 84 comparative method step according to prior art

[0152] 86 y-axis, temperature

[0153] 88 x-axis, time

[0154] 90 measured output characteristics

[0155] 90’ measured output characteristics for prior art device

[0156] 92 measured data for device

[0157] 92’ measured data for prior art device

[0158] 92” measured data for prior art device

[0159] 94 y-axis, gate-emitter threshold voltage Vth

[0160] 96 measured short circuit characteristics

[0161] 96’ measured short circuit characteristics for prior art device

[0162] 96” measured short circuit characteristics for prior art device

[0163] 98 y-axis, collector-emitter voltage VCE

[0164] 100 y-axis, gate emitter voltage VGE

Claims

26 P230210W001Claims1 . Semiconductor device (20, 60) comprising:- a base region (22) of a first conductivity type provided in a substrate (24),- a source region (26) being of a second conductivity type different to the first conductivity type provided in the substrate (24) adjacent to the base region (22) for forming a first pn-junction, the source region (26) being configured to be connected to an emitter electrode (28),- a drift region (30) being of the second conductivity type provided in the substrate (24) adjacent to the base region (22) for forming a second pn-junction, the drift region (30) being arranged separate from the source region (26), such that a channel region (32) in between the source region (26) and the drift region (30) is formed in the base region (22), the drift region (30) being configured to be connected to a collector electrode,- an insulation layer (34) arranged next to the channel region (32) for separating the channel region (32) from a gate electrode (36), and wherein for a semiconductor device (20) with a planar gate architecture a ratio of a peak doping concentration (52) in cm-3in the channel region (32) to a length (54) of the channel region (32) in cm between the first pn-junction and the second pn-junction along a charge carrier axis (38) is more than 5.8 ■ 1021cm-4; and / or for a semiconductor device (60) with a trench gate architecture a ratio of a peak doping concentration (52) in cm-3in the channel region (32) to a length (54) of the channel region (32) in cm between the first pn- junction and the second pn-junction along a charge carrier axis (38) is more than 5 ■ 1020cm-4, and wherein the semiconductor device (20, 60) comprises an enhancement region (56) in the drift region (30), the enhancement region (56) being arrange along the charge carrier axis (38) adjacent to the channel region (32) and wherein a ratio of a peak doping concentration (52) in the channel region (32) to a peak doping concentration (58) in the enhancement region (56) is more than 1.75 ■ 102.

2. Semiconductor device (20, 60) according to claim 1 , wherein the channel length (54) is below 2 pm.27 P230210W0013. Semiconductor device (20, 60) according to any of the previous claims, wherein the channel region (32) is uniformly doped along the charge carrier axis (38).

4. Semiconductor device (20, 60) according to any of claims 1 to 2, wherein the channel region (32) is non-uniformly doped along the charge carrier axis (38).

5. Semiconductor device (20, 60) according to the previous claim, wherein the channel region (32) comprises in a direction from the source region (26) to the drift region (30) along the charge carrier axis (38) a high-low doping profile.

6. Semiconductor device (20, 60) according to any of the previous claims, wherein the source region (26) is uniformly doped.

7. Semiconductor device (20, 60) according to any of the previous claims, wherein the source region (26) is a n-type source region, and / or the base region (22) is a p-type base region.

8. Semiconductor device (20, 60) according to any of the previous claims, wherein the semiconductor device (20, 60) is configured as MOSFET, IGBT, or BIGT.

9. Semiconductor device (20, 60) according to any of the previous claims, wherein the semiconductor device (20, 60) comprises a contact layer (43) adjacent to the base region (22), the source region (26), and the emitter electrode (28), the contact layer (43) being of the first conductivity type and having a higher carrier concentration than the base region (22).

10. Semiconductor device (20, 60) according to any of the previous claims, wherein the semiconductor device (20, 60) comprises a collector layer being of the first conductivity type in between the collector electrode and the drift region (30).11 . Method for manufacturing a semiconductor device (20, 60) by generating a channel region (32) in a substrate (24) through implantation of carriers into the substrate (24), wherein a) implantation is performed with a ratio of a channel doping dose to a channel28 P230210W001 plateau driving time higher than 7.14 ■ 1011cm-2min-1and a thermal budget below 2.3 ■ 105°C- min, wherein the thermal budget denotes the product of the channel plateau driving time and a temperature at which the carriers are diffused into the substrate (24); or b) in a first step a channel precursor region in the substrate (24) is formed through implantation of carriers of a first conductivity type into the substrate (24), followed by an implantation of carriers of a second conductivity type, being different to the first conductivity type to form the channel region (32); and for alternative a) and alternative b) the method comprises the step of generating an enhancement region (56) adjacent to the channel region (32) through implantation of carriers into the substrate (24) wherein implantation is performed such that a ratio of the peak doping concentration in the channel region (32) to the peak doping concentration in the enhancement region (56) is more than 1.75 ■ 102; and wherein the semiconductor device (20) comprises a planar gate architecture, and wherein implantation of the carriers into the substrate (24) is performed such that a ratio of a peak doping concentration (52) in cm-3in the channel region (32) to a length (54) of the channel region (32) of more than 5.8 ■ 1021cm-4; or wherein the semiconductor device (60) comprises a trench gate architecture, and wherein implantation of the carriers into the substrate (24) is performed such that a ratio of a peak doping concentration (52) in cm-3in the channel region (32) to a length (54) of the channel region (32) of more than 5 ■ 102° cm-4.

12. Method according to the previous claim, wherein feature a) is realized and the channel doping dose is above 1.5 ■ 1014cm-2.

13. Method according to any of the previous method claims, wherein the channel region in the substrate is generated through a dual doping of dopants having different diffusion rates.

14. Semiconductor device (20, 60) manufactured according to any of the previous method claims.

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