A graphene-containing laminate

Abstract

There is provided a graphene-containing laminate (100) comprising: a substrate (105); a graphene layer structure (110) on the substrate (105); a conformal barrier layer (115) on the graphene layer structure (110), wherein the barrier layer (115) is a dielectric metal oxide or silicon nitride, and has a first thickness which is at least 3 nm; and a dopant layer (120) on the barrier layer (115), wherein the dopant layer (120) is formed of one or more of vanadium oxide, niobium oxide, tantalum oxide, chromium oxide, molybdenum oxide, tungsten oxide, and nickel oxide; wherein the dopant layer (120) has a second thickness, and a ratio of the first thickness to the second thickness is from 1:1 to 1:10.

Description

[0001] A graphene-containing laminate

[0002] The present invention relates to a graphene-containing laminate, and a method for the manufacture of a graphene-containing laminate, together with electronic devices comprising said laminate, in particular Hall-sensors. More particularly, the laminate comprises a dopant layer, the presence of which modulates the charge carrier concentration of the graphene layer structure of the laminate.

[0003] Graphene is a leading two-dimensional material that has been incorporated in numerous products for its extraordinary properties. The electronic properties of graphene are especially remarkable and has allowed for the production of electronic devices (particularly microelectronics) that demonstrate properties that are orders of magnitude better than those of their non-graphene counterparts. Most notable is the use of graphene in electronic devices and their constituent components and includes transistors, LEDs, photovoltaic cells, Hall-effect sensors, diodes, electro-optic modulators (EOMs) and the like.

[0004] Accordingly, there are a wide range of electronic devices known in the prior art which have integrated graphene layer structures (single layer or multi-layer graphene) for delivering improvements in such devices over earlier devices and electronic products. These include structural improvements through the use of thinner and lighter materials (which can give rise to flexible electronics) as well as performance improvements such as increased electrical and thermal conductance leading to greater operating efficiencies.

[0005] It is known to provide graphene layer structures with a range of different charge carrier concentrations and that low values are useful for certain applications. Through changing growth conditions it is possible to optimise the charge carrier concentrations. The present inventors have found that the most effective method for manufacturing high-quality graphene, especially directly on substrates providing non-metallic surfaces suitable for subsequent use in electronic devices, is that disclosed in WO 2017 / 029470 (the contents of which is incorporated herein by reference in its entirety).

[0006] One way to reduce the charge carrier concentration further is with doping, and this is known from WO 2017 / 029470. This method involves the intentional introduction of dopants to counter-dope the graphene material and reduce the charge carrier concentration (e.g. n-type doping a p-type graphene layer). The method of WO 2017 / 029470 involves directly doping the graphene during production, such as by using CHsBr as a precursor. However, the presence of dopant atoms can cause a reduction in carrier mobility due to scattering effects.

[0007] A further way to reduce the sheet carrier concentration is disclosed in WO 2021 / 008938 which relates to a method for the production of a polymer coated graphene layer structure. This publication discloses the formation of graphene on a substrate by CVD (preferably using a method as disclosed in WO 2017 / 029470), the graphene having a first charge carrier concentration, and coating the graphene layer structure with a polymer composition to form an impermeable coating, the coated graphene having a second charge carrier concentration that may be less than 1012cm-2. Such a low charge carrier concentration is achieved through the use of a dopant in the coating to counteract the intrinsic doping of graphene formed directly on substrates by CVD.

[0008] WO 2019 / 125267 relates to a method for assembling molecules on the surface of a two-dimensional material formed on a substrate, the molecules (such as F4TCNQ) having been allowed to diffuse through a spacer layer (such as PMMA) through an annealing step whereby the spacer layer provides for embedding the molecules which are assembled on the surface of the 2D material.

[0009] The Applicant’s WO 2023 / 237561 relates to a graphene-containing laminate in which a transition metal oxide with a high work function is formed directly on the graphene layer structure, the thickness of which ranges from 0.1 nm to 5 nm to control the extent of doping.

[0010] In the field of alternative low dimensional materials, 2023 International Electron Devices Meeting (IEDM), San Francisco, CA, USA, 2023, 1-4 “Barrier Booster for Remote Extension Doping and its DTCO for 1 D & 2D FETs” presents a “barrier booster” for remote extension doping in low-dimensional materials (LDMs), e.g., 1 D Carbon Nanotubes (CNTs) and 2D M0S2.

[0011] Nature Electronics 2021 , vol. 4, 664-670 “Remote modulation doping in van der Waals heterostructure transistors”, as well as EP 4386858 which shares the inventors as common authors, relates to a high-mobility atomic layer semiconductor device based on modulation doping and a method for fabricating the same, which prevents a charge scattering phenomenon caused by ionized impurities by modulation doping dopants such that the dopants are spatially separated from a channel layer of an atomic layer semiconductor device having an atomic layer semiconductor heterojunction structure band-aligned.

[0012] US 2024 / 178307 relates to a semiconductor device including a multi-layer gate dielectric layer and an electronic apparatus including the semiconductor device.

[0013] Adv. Mater. Interfaces 2017 , 4, 1700232 “Atomic Layer Deposition for Graphene Device Integration” provides a review of the different methods to achieve uniform deposition of ALD on graphene.

[0014] Appl. Phys. Lett. 2012, 100, 173113 “ Substrate-assisted nucleation of ultra-thin dielectric layers on graphene by atomic layer deposition” teaches a dramatic increase in the wetting ability of ALD AI2O3 films by the assistance of a metallic substrate (Cu, Ni-Au) beneath the graphene layer, compared to thicker graphite layers or inert SiC>2, which is said to be conveniently fulfilled by the metallic catalysts commonly used during the CVD growth of graphene. 2D Materials 2016, 3, 035027 “Physisorbed-precursor-assisted atomic layer deposition of reliable ultrathin dielectric films on inert graphene surfaces for low-power electronics” describes a process referred to as physisorbed-precursor-assisted atomic layer deposition (pALD) and investigates the mechanism through density functional theory.

[0015] The Applicant’s WO 2023 / 067309 (and GB 2613923) relates to a method of producing an electronic device precursor with ohmic contacts in contact with an edge portion of a dielectric-material-capped graphene layer structure. Such a precursor is suitable for a Hall-effect sensor.

[0016] Despite these developments in the prior art, there remains an ongoing need for improvements which allow for the integration of high quality graphene with the desired charge carrier concentration, consistently obtained from wafer to wafer and device to device. Moreover, in light of the pristine nature of graphene grown directly on substrates, there additionally remains a need for methods which allow for the formation of high quality dielectric layers thereon for device manufacture. The present invention seeks to provide improved graphene-containing laminates and associated electronic devices comprising the same which overcome, or substantially reduce, the various problems associated with the prior art, or at least provide a commercially useful alternative.

[0017] Thus, a first aspect of the present invention provides a graphene-containing laminate comprising: a substrate; a graphene layer structure on the substrate; a conformal barrier layer on the graphene layer structure, wherein the barrier layer is a dielectric metal oxide or silicon nitride, and has a first thickness which is at least 3 nm; and a dopant layer on the barrier layer, wherein the dopant layer is formed of one or more of vanadium oxide, niobium oxide, tantalum oxide, chromium oxide, molybdenum oxide, tungsten oxide, and nickel oxide; wherein the dopant layer has a second thickness, and a ratio of the first thickness to the second thickness is from 1 :1 to 1 :10.

[0018] The present disclosure will now be described further. In the following passages, different aspects / embodiments of the disclosure are defined in more detail. Each aspect / embodiment so defined may be combined with any other aspect / embodiment or aspects / embodiments unless clearly indicated to the contrary. In particular, any feature indicated as being preferred or advantageous may be combined with any other feature or features indicated as being preferred or advantageous.

[0019] A second aspect of the present invention provides a method for the manufacture of a graphenecontaining laminate, the method comprising: providing a substrate; forming a graphene layer structure on the substrate; forming a conformal barrier layer on the graphene layer structure by an evaporation deposition technique or ALD, wherein the barrier layer is a dielectric metal oxide or silicon nitride, and has a first thickness which is at least 3 nm; and forming a dopant layer on the barrier layer by an evaporation deposition technique or ALD, wherein the dopant layer is formed of one or more of vanadium oxide, niobium oxide, tantalum oxide, chromium oxide, molybdenum oxide, tungsten oxide, and nickel oxide; wherein the dopant layer has a second thickness, and a ratio of the first thickness to the second thickness is from 1 :1 to 1 :10.

[0020] There is also described herein another aspect which provides a method for the manufacture of a graphene-containing laminate, the method comprising: providing a sapphire substrate having a c-plane crystallographic growth surface; forming a graphene layer structure directly on the growth surface of the substrate by CVD; and forming a conformal barrier layer on the graphene layer structure by ALD, wherein the barrier layer is a dielectric metal oxide, and has a first thickness which is at least 3 nm; wherein the ALD is performed at a temperature of less than 80°C.

[0021] It is intended that the features disclosed in relation to either method may be combined with those disclosed in relation to the graphene-containing laminate and vice versa, unless the context clearly dictates otherwise. Accordingly, the graphene-containing laminate may be obtainable by the method and also the method may be one suitable for manufacturing the graphene-containing laminate described herein.

[0022] The present invention relates to a graphene-containing laminate and a method of forming a graphenecontaining laminate. As described in greater detail herein, the graphene-containing laminate comprises a substrate having thereon, a graphene layer structure, a first metal oxide (or silicon nitride) layer as a barrier layer, and a second metal oxide layer formed of one or more metal oxides with a high work function as a dopant layer. As such, there are no intervening layers between any given layer said to be “on” another layer.

[0023] Graphene is a very well-known two-dimensional material referring to an allotrope of carbon comprising a single layer of carbon atoms in a hexagonal lattice. Graphene, as used herein, refers to one or more layers of graphene. Accordingly, the present invention relates to the formation of a monolayer of graphene as well as multilayer graphene. Graphene, as used herein, refers to a graphene layer structure, preferably having from 1 to 10 monolayers of graphene. In many subsequent applications of a graphene-containing laminate, one monolayer of graphene is particularly preferred for its unique electronic properties (especially for Hall-sensors). Accordingly, a graphene layer structure is preferably a graphene monolayer. Nevertheless, multilayer graphene may be preferable for certain applications in which case 2 or 3 layers of graphene may be preferred.

[0024] The graphene layer structure is provided on a substrate, generally a non-metallic surface of a substrate. Preferably, the surface is an electrically insulative surface (for example, a substrate may be a silicon substrate having a silicon dioxide surface). The substrate may also be a CMOS wafer which may be silicon based and have associated circuitry embedded within the substrate. A substrate may also comprise one or more layers (for example, regions or channels of embedded waveguide materials such as silicon nitride suitable for EOMs).

[0025] Preferably, the non-metallic surface upon which the graphene layer structure is provided is silicon (Si), silicon carbide (SiC), silicon nitride (SisN4), silicon dioxide (SIOz), sapphire (AI2O3), aluminium gallium oxide (AGO), hafnium dioxide (HfOz), zirconium dioxide (ZrOz), yttria-stabilised hafnia (YSH), yttria-stabilised zirconia (YSZ), magnesium aluminate (MgAlzO^, yttrium orthoaluminate (YAIO3), strontium titanate (SrTiOs), cerium oxide (CezOs), scandium oxide (SC2O3), scandium aluminium oxide, scandium gallium oxide, erbium oxide (ErzOs), magnesium difluoride (MgFz), calcium difluoride (CaFz), strontium difluoride (SrFz), barium difluoride (BaFz), scandium trifluoride (ScFs), germanium (Ge), hexagonal boron nitride (h-BN), cubic boron nitride (c-BN) and / or a lll / V semiconductor such as aluminium nitride (AIN) and gallium nitride (GaN). Preferably, the non-metallic surface is silicon nitride, silicon dioxide, sapphire, aluminium nitride, YSZ, scandium oxide, scandium aluminium oxide, scandium gallium oxide, germanium, h-BN and / or calcium difluoride. More preferably, the non-metallic surface is sapphire or a rare-earth oxide (e.g. yttria-stabilised zirconia, scandium oxide, scandium aluminium oxide or scandium gallium oxide). In some embodiments, the non-metallic surface may have a specific crystallographic orientation, with <1 1 1 > cubic (e.g. for rare earth oxides YSZ or SC2O3, or CaFz) or <1 -102> hexagonal (i.e. r-plane, such as for sapphire) being preferred.

[0026] In accordance with some aspects of the invention, the inventors have found that c-plane sapphire (i.e. <0001 >) is ideal where the barrier layer is to be formed by low temperature ALD as described further herein.

[0027] In some preferred embodiments, the substrate comprises, or consists of, a first layer which provides the non-metallic surface and a support layer. In some embodiments, the substrate may consist of one such material. In some preferred embodiments, the substrate comprises, or consists of, a first (or upper) layer which provides the non-metallic surface and a support layer. Preferably, the support layer comprises silicon. A silicon support layer, includes a “pure” silicon wafer (essentially consisting of silicon, doped or undoped) or what may be referred to as a CMOS wafer which includes additional associated circuitry embedded therein. The first layer may preferably be formed of inorganic oxide or nitride such as those described herein and provides the non-metallic surface. Preferably, the substrate does not comprise the native silicon oxide which may be removed from the surface of the silicon support before forming the first layer.

[0028] The thickness of a silicon support layer is generally much thicker than the thickness of the layer thereon. When and where present, the support layer typically has a thickness of 250 pm to 1 .5 mm, for example from 400 pm to 1 mm. On the other hand, the thickness of a layer thereon is substantially thinner. Preferably, the thickness of such layer is at least 2 nm, preferably at least 5 nm and / or less than 500 nm, preferably less than 100 nm. Suitable ranges for the thickness of the layer are preferably 5 nm to 100 nm, preferably 10 to 50 nm. In some embodiments, very thin layers are preferred and the thickness of the layer may preferably be from 2 nm to 10 nm.

[0029] The graphene-containing laminate comprises a conformal barrier layer on the graphene layer structure. That is, the barrier layer provides uniform layer which completely covers the graphene layer structure. The barrier layer is formed of a dielectric metal oxide or silicon nitride and has a thickness of at least 3 nm in order to ensure that a fully coalesced and conformal layer is provided to physically isolate the graphene layer structure from further layers (as well as providing desirable protection from atmospheric contamination which may otherwise lead to a drift in electronic properties over time).

[0030] In preferred embodiments, the barrier layer is formed of aluminium oxide or hafnium oxide. These dielectric metal oxides are ubiquitous in microelectronic fabrication processes which have high dielectric constants (so-called high-k dielectrics). For the avoidance of doubt, at least where a dopant layer is included, the barrier layer is not formed of metal oxides suitable for the dopant layer and generally therefore have a lower work function and do not have as significant an influence on the charge carrier concentration when provided directly on the graphene surface.

[0031] Advantageously, both the barrier layer and the dopant layer (as described further below) can be deposited with the desired thickness by evaporation deposition techniques thereby simplifying the manufacturing process over other techniques, such a chemical deposition (e.g. ALD). Preferred evaporation techniques include thermal evaporation and e-beam evaporation.

[0032] In some embodiments, the barrier layer is dielectric metal oxide which is formed on the graphene layer structure by low temperature ALD, specifically at a temperature of less than 80°C.

[0033] ALD is technique known in the art. It comprises the reaction of at least two precursors in a sequential, self-limiting manner (a metal precursor and the non-metal, i.e. oxygen, precursor). Repeated cycles to the separate precursors allow the growth of a layer in a conformal manner (i.e. uniform thickness across the entire surface) due to the layer-by-layer growth mechanism. Suitable precursors which provide the required metal element, for example aluminium or hafnium atoms for alumina and hafnia, are well-known, commercially available and not particularly limited. Preferably, the second metal oxide layer is formed by ALD using a metal alkyl, metal alkoxide or metal halide as a metal precursor (i.e. metal alkyl is (R)nM, metal alkoxide is (RO)nM and metal halide is (X)nM). Metal halides such as metal chlorides (e.g. AlCh and HfCU) may be used. Alternatively, metal amides, metal alkoxides or organometallic precursors may be used. Hafnium precursors include, for example, tetrakis(dimethylamido)hafnium(IV), tetrakis(diethylamido)hafnium(IV), hafnium(IV) tert-butoxide and dimethylbis(cyclopentadienyl)hafnium(IV). Preferably, the barrier layer is alumina and preferably a further precursor for the ALD is a trialkyl aluminium or trialkoxide aluminium, such as trimethylaluminium, tris(dimethylamido)aluminium, aluminium tris(2,2,6,6-tetramethyl-3,5-heptanedionate) or aluminium tris(acetylacetonate).

[0034] Suitable oxygen precursors include one or more of water (H2O), O2 (e.g. O2 plasma), and ozone (O3), and preferably the oxygen precursor is water.

[0035] Typically the deposition temperature for ALD is from 100°C to 300°C. However, the inventors have found that temperatures below 80°C are preferable for growth on pristine graphene (i.e. substantially defect free having been grown directly on the substrate by CVD without transfer) and affords better quality barrier layers having improved dielectric properties. This is particularly relevant for the barrier layer described herein which is deposited directly on the graphene layer structure since the low temperature deposition facilitates the growth on a material which otherwise lacks nucleation sites (e.g. from defects or impurities).

[0036] Preferably, the ALD is performed at a temperature of at least 60°C, such as from 60°C to 70°C. Whilst a significant improvement has been observed at low temperatures, it has been observed that at 50°C, the surface roughness of the barrier layer begins to increase and the formation of pinholes in the layer becomes more prevalent. A range of 60°C to 70°C provides a particular window suited for metal oxide growth on CVD grown graphene. As a result, the barrier layer preferably has a root-mean-square (RMS) roughness of less than 0.5 nm, even at a thickness of less than 10 nm, such as less than 7 nm. The barrier layer may be characterised using AFM and / or ellipsometry which are conventional techniques in the art.

[0037] More specifically, such a low temperature ALD process on pristine graphene may be described as a physisorbed-precursor-assisted atomic layer deposition, and, without wishing to be bound by theory, it is believed that the use of c-plane sapphire specifically provides for a better polarisation-induced physisorption of the metal precursor when near the surface of the graphene layer structure. That is, the inventors believe that the crystallographic orientation may have a remote influence on the ALD deposition process and may be used to enhance the low temperature growth. The polarisation can lead to stronger dipole-induced-diploe interactions which in turn holds the adsorbate to the surface, even at the elevated temperatures inherently required for the formation of the dielectric material. Thus it is preferred that the first step of the ALD is a dosing of the metal precursor (i.e. before the dosing of the oxygen precursor). Such a process is therefore a seed-free process (which is an alternative to provide nucleation sites for the barrier layer formation, such as evaporated aluminium) and advantageously mitigates the risk of damage to the graphene layer structure.

[0038] In some preferred embodiments, the ALD comprises a purge step after each step of dosing the metal precursor and dosing the oxygen precursor, wherein the purge step has a purge duration of at least 15 seconds, such as from 20 to 60 seconds. This is significantly greater than the purge durations typically required for ALD growth a higher temperatures, which are typically less than 10 seconds, e.g. about 6 seconds. With low temperature ALD, the desorption rate of the excess reactants from the ALD chamber (reactor) significantly decreases, such that longer purge times are desired to effectively remove the unreacted precursors and by-products from the chamber to avoid CVD (gas phase) reactions and contamination of the layer in each alternating ALD step.

[0039] In view of the foregoing, one particular embodiment of the method of either aspect described herein comprises: providing a sapphire substrate having a c-plane crystallographic growth surface; forming a graphene layer structure directly on the growth surface of the substrate by CVD; and forming a conformal barrier layer on the graphene layer structure by ALD, wherein the barrier layer is a dielectric metal oxide, and has a first thickness which is at least 3 nm; wherein the ALD is performed at a temperature of greater than 60°C and less than 80°C, wherein the ALD is performed by dosing a metal precursor and H2O as an oxygen precursor (e.g. for forming aluminium oxide and / or hafnium oxide), and preferably wherein the ALD comprises a purge step after each step of dosing the metal precursor and dosing the oxygen precursor having a purge duration of at least 15 seconds.

[0040] The graphene-containing laminate of at least the first aspect described herein further comprises a dopant layer on the barrier layer, wherein the dopant layer is formed of one or more of vanadium oxide, niobium oxide, tantalum oxide, chromium oxide, molybdenum oxide, tungsten oxide, and nickel oxide. The inventors have found that these metal oxides have a high work function, sufficiently large enough in order to influence the observed charge carrier concentration of the graphene layer structure remotely through the barrier layer. Such remote doping may instead be referred to as a dielectric- induced field which, with a sufficiently thick dopant layer, and / or thin barrier layer, allows for the modulation of the charge carrier concentration of the graphene layer structure with respect to the laminate prior to the addition of the dopant layer. That is, the laminate product of the present invention advantageously has a consistent and stable charge carrier concentration. The thickness of the dopant layer is typically tailored to the thickness of the barrier layer. As described herein, a ratio of the thickness of the barrier layer (i.e. a first thickness) to the thickness of the dopant layer (i.e. a second thickness) is from 1 :1 to 1 :10. As such, the dopant layer has a corresponding thickness of at least 3 nm, and preferably, the ratio is from 1 :3 to 1 :5.

[0041] As the thickness of the barrier layer increases, it is preferred for the thickness of the dopant layer to increase in order to provide an equivalent doping effect on the graphene layer structure. However, without wishing to be bound by theory, there is a general limit to the thickness of the dopant layer beyond which the doping effect diminishes such that there is a careful balance required between the thickness of both the barrier and dopant layers. It is preferred that the barrier layer is thin, i.e. up to 15 nm, or even preferably up to 10 nm (such as from 5 nm to 10 nm). These thicknesses allow for the conformal deposition of a layer which physically isolates the doping layer from contacting the graphene layer structure, the conformal barrier being essential to ensure consistent doping across the whole area of the two-dimensional material (which is in turn essential for the mass manufacture of devices with consistent properties from device to device). Where the barrier layer is too thick, the field effect from the doping layer is diminished.

[0042] In the Applicant’s WO 2023 / 237561 , it was essential to deposit a transition metal oxide, such as molybdenum oxide, directly onto the surface of the graphene. The thickness of this layer ranges from 0.1 nm to 5 nm, with thicknesses on the order of 1 nm being preferred in the examples in order to provide the desired degree of doping. Such a nominal thickness is generally provided by islands without having a uniform layer. The inventors have found that it can be challenging to accurately deposit thinner layers with the desired nominal thickness and the present invention builds on this process by the inclusion of a barrier layer by allowing a thicker and more conformal and uniform doping layer of transition metal oxide to be deposited with greater process control.

[0043] By reducing the influence of the doping layer on the change in charge carrier concentration of the graphene layer structure, the present invention advantageously provides a marked increase in the control over the modulation of the charge carrier concentration for a given amount of dopant layer deposited. As such, the thickness of the dopant layer can be much greater than that contemplated in the prior art and may range from 5 to 40 nm, preferably from 10 to 30 nm. That is, with the presence of the barrier layer, the charge carrier concentration of the graphene layer structure is more finely tuned for an equivalent change in the thickness of the dopant layer. This process control provides the final device with a significantly reduced variability in the charge carrier concentration due to the weaker dielectric-induced field, both across the laminate (i.e. from device to device), but also from one manufacturing run to the next (i.e. from wafer to wafer) which is vital for commercial production of electronic devices. Thus, in preferred embodiments, the present invention allows for the first thickness, the second thickness, as well as the ratio therebetween, to be selected to provide the graphene layer structure of the final laminate with a charge carrier concentration of less than 5x1012cm-2(as measured at 0 V and 25°C), preferably less than 1 x1012cm-2. Such a carrier concentration close to the Dirac point permits electronic devices to benefit from the unique electronic properties of graphene which is particularly beneficial for sensors. As described further herein, such devices advantageously do not need to comprise a gate (contact) and may therefore be provided and used without a gate or application of a gate voltage.

[0044] In a further preferred embodiment, the laminate further comprises a passivation layer on and across the dopant layer. The passivation layer may comprise, or consist, of aluminium oxide or hafnium oxide. Such a layer be deposited by any conventional means (e.g. evaporation or ALD) and typically fully encapsulates the thin layers on the substrate from atmospheric contamination. This is beneficial in a device whereby the graphene, barrier and dopant layers have been patterned thereby exposing the edge of the graphene, the passivation layer encapsulates the edges having been deposited on the adjacent exposed substrate surface. The passivation layer typically is thicker than the barrier and / or dopant layers, and can have a thickness of 50 nm or more. There is no particular upper limit, though generally the capping layer is not thicker than 500 nm, preferably less than 250 nm.

[0045] It is particularly preferred that the graphene layer structure is formed directly on the substrate by CVD. The preparation of sufficiently large area graphene with high uniformity has been major problem in the art which has hindered the uptake of graphene in commercial processes and ultimately electronic devices. The standard in the art is to manufacture graphene by CVD on copper foils or other catalytic metal substrates. A significant proportion of research and development has since focussed on the need to optimise the process by which graphene is transferred from such substrates to those of interest for electronic devices (i.e. non-metallic substrates, for example semiconductors such as silicon and insulators such as sapphire).

[0046] However, the inventors found that graphene grown on copper is inevitably contaminated, if not with copper, at least with the additional materials which are essential to effect the transfer. These include transfer polymers such as PMMA, metal etchants and solvents to remove the polymer. Polymer residues are however never fully removed and graphene provided by such methods cannot be devoid of transfer polymers and / or copper. Additionally, the physical manipulation of the graphene during transfer leads to defects in the atomically thin material. Whilst the addition of a barrier layer and dopant as described herein may advantageously be used to counteract the change in charge carrier concentration resulting from the transfer, unintentional doping, particularly from the catalytic metal substrates together with the etching solutions, also results in the production of material which is not sufficiently consistent from sample to sample. This is required for commercial production of electronic devices such that the method of manufacture described herein is more consistent from wafer to wafer and device to device with graphene grown directly on the substrate by CVD.

[0047] The physical transfer of two-dimensional materials can introduce numerous defects which negatively impacts the physical and electronic properties. As such, a person skilled in the art can readily ascertain whether a graphene layer structure, and by extension a device, is one comprising a CVD- grown graphene layer structure that has been grown directly using conventional techniques in the art such as AFM and energy dispersive X-ray (EDX) spectroscopy.

[0048] Preferably, the graphene layer structure is formed by CVD directly on the substrate. Forming may be considered synonymous with synthesising, depositing, producing and growing. CVD refers generally to a range of chemical vapour deposition techniques, each of which involve deposition to produce thin film materials such as two-dimensional crystalline materials like graphene. Volatile precursors, those in the gas phase or suspended in a gas, are decomposed to liberate the necessary species to form the desired material, carbon in the case of graphene. CVD as described herein is intended to refer to thermal CVD such that the formation of graphene from the decomposition of a carbon-containing precursor is the result of the thermal decomposition of said carbon-containing precursor.

[0049] Preferably, the temperature of the growth surface during CVD is from 700°C to 1350°C, preferably from 800°C to 1250°C, more preferably from 1000°C to 1250°C. The inventors have found that such temperatures are particularly effective for providing graphene growth directly on the materials described herein by CVD. Preferably, the CVD reaction chamber used in the method disclosed herein is a cold-walled reaction chamber wherein a heater coupled to the substrate is the only source of heat to the chamber.

[0050] As will be appreciated by those skilled in the art, the temperature setting input to some CVD reactors (i.e. set temperature) will generally be greater than the actual wafer temperature (such as with MOCVD reactors available from Aixtron®). The set temperature may be 100°C (or more) greater than the wafer temperature, for example from 1 ,300°C to 1 ,400°C. The wafer temperature may be measured using conventional techniques, for example using an optical probe. Other apparatuses may have a temperature feedback control whereby the reactor achieves the same wafer temperature as the input temperature (such as with high rotation rate MOCVD reactors available from Veeco®).

[0051] In a particularly preferred embodiment, the CVD reaction chamber comprises a close-coupled showerhead having a plurality, or an array, of precursor entry points. Such CVD apparatus comprising a close-coupled showerhead may be known for use in MOCVD processes. Accordingly, the method may alternatively be said to be performed using an MOCVD reactor comprising a close-coupled showerhead. In either case, the showerhead is preferably configured to provide a minimum separation of less than 100 mm, more preferably less than 25 mm, even more preferably less than 10 mm, between the surface of the substrate and the plurality of precursor entry points. As will be appreciated, by a constant separation it is meant that the minimum separation between the surface of the substrate and each precursor entry point is substantially the same. The minimum separation refers to the smallest separation between a precursor entry point and the substrate surface. Accordingly, such an embodiment involves a “vertical” arrangement whereby the plane containing the precursor entry points is substantially parallel to the plane of the exposed substrate surface (i.e. the growth surface).

[0052] The precursor entry points into the reaction chamber are preferably cooled. The inlets, or when used, the showerhead, are preferably actively cooled by an external coolant, for example water, so as to maintain a relatively cool temperature of the precursor entry points such that the temperature of the precursor as it passes through the plurality of precursor entry points and into the reaction chamber is less than 100°C, preferably less than 50°C. For the avoidance of doubt, the addition of precursor at a temperature above ambient does not constitute heating the chamber, since it would be a drain on the temperature in the chamber and is responsible in part for establishing a temperature gradient in the chamber.

[0053] Preferably, a combination of a sufficiently small separation between the substrate surface and the plurality of precursor entry points and the cooling of the precursor entry points, coupled with the heating of the substrate to with a decomposition range of the precursor, generates a sufficiently steep thermal gradient extending from the substrate surface to the precursor entry points to allow graphene formation on the substrate surface. As disclosed in WO 2017 / 029470, very steep thermal gradients may be used to facilitate the formation of high-quality and uniform two-dimensional material layers directly on non-metallic substrates, preferably across the entire surface of the substrate. The substrate may have a diameter of at least 5 cm (2 inches), at least 15 cm (6 inches) or at least 30 cm (12 inches). Particularly suitable apparatus for the method described herein include an Aixtron® Close-Coupled Showerhead® reactor and a Veeco® TurboDisk reactor.

[0054] Consequently, in a particularly preferred embodiment wherein the method of the present invention involves using a method as disclosed in WO 2017 / 029470, forming the graphene layer structure by CVD comprises: providing the substrate on a heated susceptor in a close-coupled reaction chamber, the close- coupled reaction chamber having a plurality of cooled inlets arranged so that, in use, the inlets are distributed across the growth surface of the substrate and have constant separation from the substrate; cooling the inlets to less than 100°C; introducing a carbon-containing precursor in a gas phase and / or suspended in a gas through the inlets and into the close-coupled reaction chamber; and heating the susceptor to achieve a growth surface temperature of at least 50°C in excess of a decomposition temperature of the precursor, to provide a thermal gradient between the growth surface and inlets that is sufficiently steep to allow the formation of graphene from carbon released from the decomposed precursor; wherein the constant separation is less than 100 mm, preferably less than 25 mm, even more preferably less than 10 mm.

[0055] In another particularly preferred embodiment wherein the method involves using a method as disclosed in WO 2019 / 138231 , forming the graphene layer structure by CVD comprises: providing the substrate on a heated susceptor in a reaction chamber, the reaction chamber having a plurality of inlets arranged so that, in use, the inlets are distributed across the growth surface and have constant separation from the substrate; rotating the heated susceptor at a rotation rate of at least 600 rpm, preferably up to 3000 rpm; introducing a carbon-containing precursor in a gas phase and / or suspended in a gas through the inlets and into the reaction chamber; and heating the susceptor to achieve a growth surface temperature of at least 50°C in excess of a decomposition temperature of the precursor; wherein the constant separation is at least 12 cm, preferably up to 20 cm.

[0056] The most common carbon-containing precursor in the art for graphene growth is methane (CF ). The inventors have found that it is preferable that the carbon-containing precursor used to form graphene is an organic compound, that is, a chemical compound, or molecule, that contains a carbon-hydrogen covalent bond, which comprises two or more carbon atoms. The carbon-containing precursor is preferably a C3-C10 organic compound consisting of carbon and hydrogen and, optionally, oxygen, nitrogen, fluorine, chlorine and / or bromine, even more preferably a C6-C9 organic compound. In a preferred embodiment, the precursor does not comprise a heteroatom, such that the precursor consists of carbon and hydrogen. In other words, preferably the carbon-containing precursor is a hydrocarbon, preferably an alkane. It is also preferable that the organic compound comprise at least two methyl groups (-CH3). Particularly preferred organic compounds for use as carbon-containing precursors, and methods of forming graphene therefrom by CVD, are described in GB 2604377.

[0057] Graphene formed directly on the substrate by such a method generally has a desirable level of intrinsic n-doping which is very suitably counteracted by the doping from the doping layer as described herein having a high work function, the doping of which is directly correlated with the thickness of the layer. The “as-grown” doping level of the graphene can be fine-tuned through routine modifications of the growth process, such as through the choice of substrate, choice of precursor and growth / decomposition temperature. Ultimately, the first thickness, the second thickness and the ratio of the first thickness to the second thickness can be selected to provide the graphene layer structure with a charge carrier concentration of less than 5x1012cm-2. However, the graphene layer structure may be provided on a non-metallic surface of a substrate by known transfer techniques from, for example, copper foil, though this is less suitable for mass manufacture due to the possible variability in the electronic properties of the graphene layer structure as provided on the substrate. Moreover, such directly CVD-grown graphene is typically p-type which does not allow for the provision of a low charge carrier concentration close to the Dirac point.

[0058] In accordance with a further aspect of the present invention, there is provided an electronic device comprising the graphene-containing laminate (i.e. manufactured from the laminate) and having at least first and second electrical contacts in electrical communication via the graphene layer structure.

[0059] The graphene-containing laminate comprising the dopant layer is particularly suitable for the manufacture of sensors, utilising the desirably low charge carrier concentration that may be consistently provided by the combination of the barrier layer and the dopant layer thereon (e.g. less than 5x1012cm’2). Examples of sensors that can benefit through being formed from such graphenecontaining laminate include Hall-sensors, temperature sensors, and magneto-resistance sensors (as described in WO 2022 / 129606, for example). In preferred embodiments, the device is a Hall-sensor.

[0060] Contacts are standard components in electronic device fabrication that are well-known to those skilled in the art and may be deposited during fabrication of the graphene-containing laminate and / or after fabrication of said laminate. Contacts provide a point of connection into an electronic circuit (such as via metal wires bonded to the contacts or through soldering using “flip chip” style solder bumps). Thus an electronic device is a functioning device when installed in an electronic circuit and current is provided to the device.

[0061] Typically, contacts are metal contacts, such as those formed of chromium, titanium, aluminium, nickel, tungsten and / or gold. Generally, multiple contacts are provided in contact with the graphene layer structure of the graphene-containing laminate. Typically, at least two contacts are provided in electrical communication with the graphene layer structure, generally in direct contact with the graphene layer structure, and may be termed source and drain contacts. The contacts may have an edge and / or surface contact with the graphene layer structure, preferably edge only contact. It will be appreciated that the contact will be deposited on the adjacent exposed substrate in order to contact the edge of the graphene layer structure. Contacts may be deposited by PVD techniques such as e- beam evaporation.

[0062] Advantageously, the device does not need a gate contact (that is, for devices in which a gate contact is not in theory essential, e.g. sensors as opposed to transistors). Preferred devices therefore do not comprise a gate contact. The present disclosure therefore provides the use of a device comprising the graphene-containing laminate described herein without the application of a gate voltage. For example, a Hall-sensor may be used to detect a magnetic field without the application of a gate voltage. The inventors have found that the combination of the conformal barrier layer and dopant layer allow for the construction of devices without the need for a gate contact.

[0063] In other embodiments, the graphene-containing laminate produced by the methods described herein may preferably be used to manufacture devices which comprise a top gate contact, such as transistors, in view of the high quality dielectric layer properties achieved by the low temperature ALD deposition. That is, a gate contact may be provided directly on the barrier layer, particularly where formed thin, allowing for the scaling down of the gate oxide thereby reducing transistor size. In any event, other devices for which a gate contact is an essential component, such as transistors, may comprise the doping layer in order to adjust the charge carrier concentration of the graphene layer structure before forming a top gate contact on such further layers.

[0064] As will be appreciated, a large-area graphene-containing laminate (i.e. a wafer such as one having a diameter of greater than or equal to 5 cm (2 inches)) may be processed to manufacture an array of electronic devices on the common underlying substrate. This may then be diced into individual devices such that an electronic device comprises a portion of a larger graphene-containing laminate. As such, it will be appreciated that each of the layers of the graphene-containing laminate may extend substantially the full area of the of the underlying substrate. That is, each layer may be provided on and across the underling the layer with subsequent processing used to pattern the layers (e.g. by photolithography). Further layers such as a passivation layer as described herein may be deposited following patterning and deposition of contacts as a means to encapsulate the patterned layers, and the exposed edges of the graphene layer structure, as well as the contacts.

[0065] The present invention will now be described further with reference to the following exemplary non-limiting Figures, in which:

[0066] Figure 1 is a cross-section of a graphene-containing laminate according to the present invention.

[0067] Figure 2 is a cross-section of a sensor according to the present invention manufactured from the graphene-containing laminate shown in Figure 1 .

[0068] Figure 3 is a plot of the surface profile of a barrier layer grown at three different temperatures.

[0069] Figure 1 illustrates, in cross-section, a graphene-containing laminate 100 which consists of a substrate 105, a graphene monolayer 110 on and across the surface of the substrate 105, a barrier layer 115 on and across the graphene monolayer 110, and a dopant layer 120 on and across the barrier layer 115. In the embodiment illustrated by laminate 100, the barrier layer is formed of aluminium or hafnium oxide and has a thickness of about 5 nm, the barrier layer having a conformal and uniform thickness across the area of the substrate (wafer). This is typically a 5 cm (2 inch) diameter wafer or greater. The dopant layer is formed of molybdenum oxide (though other transition metal oxides with high work function as described herein may be used), the thickness of which is at least the same as the barrier layer and may be three times greater (e.g. about 15 nm thick).

[0070] It is preferred that the graphene monolayer 110 is grown directly on the surface of the substrate 105 by CVD, the substrate 105 preferably being a sapphire substrate, or comprise a silicon support layer with a rare-earth oxide (such as scandium oxide) thereon providing the growth surface.

[0071] Figure 2 illustrates, in cross-section, a sensor 200 manufactured from a portion of the graphenecontaining laminate 100. The sensor comprises the substrate 205, graphene monolayer 210 thereon, the barrier layer 215 thereon, and the dopant layer 220 thereon. The stack of the graphene monolayer 210, barrier layer 215 and dopant layer 220 have been co-patterned on the substrate 205 (so as to have the same cross shape when viewed perpendicular to the plane of the substrate). In the crosssection illustrated bisecting two arms of the cross shape, two metal contacts 225a, 225b have been deposited such that each contact is only in contact with an edge of the graphene monolayer 210 (i.e. not the surface of the graphene monolayer 210), the contacts 225a, 225b having been deposited on an adjacent exposed portion of the growth surface of the substrate 205.

[0072] The sensor further comprises a passivation layer 230, which may be formed from aluminium or hafnium oxide, which fully encapsulates the co-patterned stack of graphene monolayer 210, barrier layer 215 and dopant layer 220, as well as the metal contacts 225a, 225b. The shape of the stack may be designed as required for a given application as is well-known to those skilled in the art, with Hall bar geometries and crosses well-known for Hall-sensors, by way of example. The passivation layer 230 has a thickness of about 65 nm.

[0073] Figure 3 is a plot of the surface profile of three aluminium oxide barrier layers, about 6 to 7 nm in thickness, deposited in accordance with the methods described herein. The aluminium oxide was deposited on a graphene monolayer grown in an MOCVD reaction chamber on and across a c-plane surface of a 5 cm (2 inch) sapphire substrate. Each layer was deposited at different temperatures, namely 200°C, 50°C and 70°C. The plot measures the height of the barrier layer (normalised about 0 nm, in nm on the y-axis) across about 5 pm of the laminate surface (x-axis). The plots as measured at 200°C, 50°C and 70°C are shown by lines 305, 310 and 315, respectively. It can be seen by line 305 that the aluminium oxide grown at 200°C has considerable pin holes and a relatively large surface roughness with the height generally varying between about ±6 nm, whereas lines 310 and 315 are significantly smoother as a result of the low deposition temperature improving the ALD deposition process on CVD grown graphene. However, at a temperature of only 50°C, line 310 demonstrates that there is an increase in surface roughness at 50°C with the height generally varying between about ±1 nm (together with an observable pin hole of about -4 nm at about 1 .75 pm) when compared to line 315 for deposition at 70°C whose height profile is substantially constant having an RMS of less than 0.5 nm (about 0.25 nm).

[0074] As used herein, the singular form of “a”, “an” and “the” include plural references unless the context clearly dictates otherwise. The use of the term “comprising” is intended to be interpreted as including such features but not excluding other features and is also intended to include the option of the features necessarily being limited to those described. In other words, the term also includes the limitations of “consisting essentially of” (intended to mean that specific further components can be present provided they do not materially affect the essential characteristic of the described feature) and “consisting of” (intended to mean that no other feature may be included such that if the components were expressed as percentages by their proportions, these would add up to 100%, whilst accounting for any unavoidable impurities), unless the context clearly dictates otherwise.

[0075] It will be understood that, although the terms "first", "second", etc. may be used herein to describe, for example, various elements, layers and / or portions, the elements, layers and / or portions should not be limited by these terms. These terms are only used to distinguish one element, layer or portion from another, or a further, element, layer or portion. It will be understood that the term “on” is intended to mean “directly on” such that there are no intervening layers between one material being said to be “on” another material. Spatially relative terms, such as “under”, "below", "beneath", "lower", “over”, "above", "upper" and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s). It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if a device as described herein is turned over, elements described as "under” or “below" other elements or features would then be oriented “over” or "above" the other elements or features. Thus, the example term "under" can encompass both an orientation of over and under. The device may be otherwise oriented and the spatially relative descriptors used herein interpreted accordingly.

[0076] Numerical lower and upper limits of features described herein may preferably be combined to provide a closed range.

[0077] The foregoing detailed description has been provided by way of explanation and illustration, and is not intended to limit the scope of the appended claims. Many variations of the presently preferred embodiments illustrated herein will be apparent to one of ordinary skill in the art, and remain within the scope of the appended claims and their equivalents. For the avoidance of doubt, the entire contents of all documents acknowledged herein are incorporated herein by reference.

[0078] The present inventions will now be described further with reference to the following numbered clauses.

[0079] 1 . A graphene-containing laminate comprising: a substrate; a graphene layer structure on the substrate; a conformal barrier layer on the graphene layer structure, wherein the barrier layer is a dielectric metal oxide or silicon nitride, and has a first thickness which is at least 3 nm; and a dopant layer on the barrier layer, wherein the dopant layer is formed of one or more of vanadium oxide, niobium oxide, tantalum oxide, chromium oxide, molybdenum oxide, tungsten oxide, and nickel oxide; wherein the dopant layer has a second thickness, and a ratio of the first thickness to the second thickness is from 1 :1 to 1 :10.

[0080] 2. The graphene-containing laminate according to clause 1 , wherein the barrier layer is aluminium oxide or hafnium oxide.

[0081] 3. The graphene-containing laminate according to clause 1 or clause 2, wherein the ratio of the first thickness to the second thickness is from 1 :3 to 1 :5.

[0082] 4. The graphene-containing laminate according to any preceding clause, wherein the first thickness is from 3 to 15 nm.

[0083] 5. The graphene-containing laminate according to any preceding clause, wherein the second thickness is from 5 to 40 nm, preferably 10 to 30 nm.

[0084] 6. The graphene-containing laminate according to any preceding clause, wherein the dopant layer is conformal and has a uniform thickness.

[0085] 7. The graphene-containing laminate according to any preceding clause, wherein the substrate is sapphire or a rare-earth oxide on silicon.

[0086] 8. The graphene-containing laminate according to any preceding clause, wherein the graphene layer structure is a graphene monolayer. 9. The graphene-containing laminate according to any preceding clause, wherein the graphene layer structure has a charge carrier concentration of less than 5x1012cm-2.

[0087] 10. The graphene-containing laminate according to any preceding clause, wherein the laminate further comprises a passivation layer on the dopant layer, preferably wherein the passivation layer comprises aluminium oxide or hafnium oxide.

[0088] 11. An electronic device comprising the graphene-containing laminate and having at least first and second electrical contacts in electrical communication via the graphene layer structure.

[0089] 12. The electronic device according to clause 11 , wherein the device is a Hall-sensor.

[0090] 13. The electronic device according to clause 11 or clause 12, wherein the device does not comprise a gate contact.

[0091] 14. A method for the manufacture of a graphene-containing laminate, the method comprising: providing a substrate; forming a graphene layer structure on the substrate; forming a conformal barrier layer on the graphene layer structure by an evaporation deposition technique or ALD, wherein the barrier layer is a dielectric metal oxide or silicon nitride, and has a first thickness which is at least 3 nm; and forming a dopant layer on the barrier layer by an evaporation deposition technique or ALD, wherein the dopant layer is formed of one or more of vanadium oxide, niobium oxide, tantalum oxide, chromium oxide, molybdenum oxide, tungsten oxide, and nickel oxide; wherein the dopant layer has a second thickness, and a ratio of the first thickness to the second thickness is from 1 :1 to 1 :10.

[0092] 15. The method according to clause 14, wherein the graphene layer structure is formed directly on the substrate by CVD.

[0093] 16. The method according to clause 14 or clause 15, wherein the first thickness, the second thickness and the ratio of the first thickness to the second thickness are selected to provide the graphene layer structure with a charge carrier concentration of less than 5x1012cm-2.

[0094] 17. The method according to any one of clauses 14 to 16, wherein the substrate is sapphire having an r-plane or c-plane crystallographic growth surface upon which the graphene layer structure is formed. 18. The method according to any one of clauses 14 to 17, wherein the conformal barrier layer is formed on the graphene layer structure by ALD at a temperature of less than 80°C.

[0095] 19. A method for the manufacture of a graphene-containing laminate, the method comprising: providing a sapphire substrate having a c-plane crystallographic growth surface; forming a graphene layer structure directly on the growth surface of the substrate by CVD; and forming a conformal barrier layer on the graphene layer structure by ALD, wherein the barrier layer is a dielectric metal oxide, and has a first thickness which is at least 3 nm; wherein the ALD is performed at a temperature of less than 80°C.

[0096] 20. The method according to claim 19, further comprising: forming a dopant layer on the barrier layer by an evaporation deposition technique or ALD, wherein the dopant layer is formed of one or more of vanadium oxide, niobium oxide, tantalum oxide, chromium oxide, molybdenum oxide, tungsten oxide, and nickel oxide; wherein the dopant layer has a second thickness, and a ratio of the first thickness to the second thickness is from 1 :1 to 1 :10.

[0097] 21 . The method according to any one of clauses 18 to 20, wherein the conformal barrier layer is formed on the graphene layer structure by ALD at a temperature of at least 60°C, preferably from 60°C to 70°C.

[0098] 22. The method according to any one of clauses 14 to 21 , wherein the first thickness is from 3 to 15 nm, preferably less than 10 nm, preferably less than 7 nm.

[0099] 23. The method according to any one of clauses 18 to 22, wherein a first dosing step of the ALD is performed by dosing a metal precursor.

[0100] 24. The method according to any one of clauses 18 to 23, wherein the ALD is performed by dosing H2O as an oxygen precursor.

[0101] 25. The method according to any one of clauses 18 to 24, wherein the ALD comprises a purge step after each step of dosing the metal precursor and dosing the oxygen precursor, wherein the purge step has a purge duration of at least 15 seconds, preferably from 20 to 60 seconds.

[0102] 26. The method according to any one of clauses 14 to 25, wherein the dielectric metal oxide is aluminium oxide and / or hafnium oxide. 27. The method according to any one of clauses 18 to 26, wherein the barrier layer has a rootmean-square (RMS) roughness of less than 0.5 nm.

Claims

Claims:1 . A graphene-containing laminate comprising: a substrate; a graphene layer structure on the substrate; a conformal barrier layer on the graphene layer structure, wherein the barrier layer is a dielectric metal oxide or silicon nitride, and has a first thickness which is at least 3 nm; and a dopant layer on the barrier layer, wherein the dopant layer is formed of one or more of vanadium oxide, niobium oxide, tantalum oxide, chromium oxide, molybdenum oxide, tungsten oxide, and nickel oxide; wherein the dopant layer has a second thickness, and a ratio of the first thickness to the second thickness is from 1 :1 to 1 :10.

2. The graphene-containing laminate according to claim 1 , wherein the barrier layer is aluminium oxide or hafnium oxide.

3. The graphene-containing laminate according to claim 1 or claim 2, wherein the ratio of the first thickness to the second thickness is from 1 :3 to 1 :5.

4. The graphene-containing laminate according to any preceding claim, wherein the first thickness is from 3 to 15 nm.

5. The graphene-containing laminate according to any preceding claim, wherein the second thickness is from 5 to 40 nm, preferably 10 to 30 nm.

6. The graphene-containing laminate according to any preceding claim, wherein the dopant layer is conformal and has a uniform thickness.

7. The graphene-containing laminate according to any preceding claim, wherein the substrate is sapphire or a rare-earth oxide on silicon.

8. The graphene-containing laminate according to any preceding claim, wherein the graphene layer structure is a graphene monolayer.

9. The graphene-containing laminate according to any preceding claim, wherein the graphene layer structure has a charge carrier concentration of less than 5x1012cm-2.

10. The graphene-containing laminate according to any preceding claim, wherein the laminate further comprises a passivation layer on the dopant layer, preferably wherein the passivation layer comprises aluminium oxide or hafnium oxide.

11. An electronic device comprising the graphene-containing laminate and having at least first and second electrical contacts in electrical communication via the graphene layer structure.

12. The electronic device according to claim 11 , wherein the device is a Hall-sensor.

13. The electronic device according to claim 11 or claim 12, wherein the device does not comprise a gate contact.

14. A method for the manufacture of a graphene-containing laminate, the method comprising: providing a substrate; forming a graphene layer structure on the substrate; forming a conformal barrier layer on the graphene layer structure by an evaporation deposition technique or ALD, wherein the barrier layer is a dielectric metal oxide or silicon nitride, and has a first thickness which is at least 3 nm; and forming a dopant layer on the barrier layer by an evaporation deposition technique or ALD, wherein the dopant layer is formed of one or more of vanadium oxide, niobium oxide, tantalum oxide, chromium oxide, molybdenum oxide, tungsten oxide, and nickel oxide; wherein the dopant layer has a second thickness, and a ratio of the first thickness to the second thickness is from 1 :1 to 1 :10.

15. The method according to claim 14, wherein the graphene layer structure is formed directly on the substrate by CVD.

16. The method according to claim 14 or claim 15, wherein the first thickness, the second thickness and the ratio of the first thickness to the second thickness are selected to provide the graphene layer structure with a charge carrier concentration of less than 5x1012cm-2.

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