Display device

Abstract

The present invention provides a display device that achieves both high display quality and high reliability. The display device includes a circuit unit and a display unit. The circuit unit has a first transistor. The first transistor has a first semiconductor layer. The display unit has a display element and a pixel circuit. The pixel circuit has a second transistor. The second transistor has a second semiconductor layer. The first semiconductor layer contains indium oxide. The first semiconductor layer contains crystal grains. The grain size of the crystal grains is 0.3 μm or larger. The second semiconductor layer contains indium. The indium content in the first semiconductor layer is higher than the indium content in the second semiconductor layer.

Description

display device

[0001] BACKGROUND OF THE INVENTION 1. Field of the Invention One embodiment of the present invention relates to a display device and a manufacturing method thereof. 2. Description of the Related Art One embodiment of the present invention relates to a transistor and a manufacturing method thereof.

[0002] One embodiment of the present invention is not limited to the above technical field, and examples of the technical field of one embodiment of the present invention include a semiconductor device, a display device, a light-emitting device, a power storage device, a memory device, an electronic device, a lighting device, an input device (for example, a touch sensor), an input / output device (for example, a touch panel), a driving method thereof, or a manufacturing method thereof.

[0003] In this specification and the like, a semiconductor device is a device that utilizes semiconductor characteristics, and refers to a circuit including a semiconductor element (transistor, diode, photodiode, etc.), a device having such a circuit, etc. Also, it refers to any device that can function by utilizing semiconductor characteristics. For example, an integrated circuit, a chip including an integrated circuit, and an electronic component in which a chip is housed in a package are examples of semiconductor devices. Furthermore, a memory device, a display device, a light-emitting device, a lighting device, and an electronic device may themselves be semiconductor devices and each may have a semiconductor device.

[0004] In recent years, there has been a demand for high-definition display devices. Devices requiring high-definition display devices, such as devices for virtual reality (VR), augmented reality (AR), substitutional reality (SR), and mixed reality (MR), have been actively developed.

[0005] Examples of display devices include display devices having liquid crystal elements and display devices having light-emitting elements (also referred to as light-emitting devices). Examples of light-emitting elements include organic electroluminescence (EL) elements and light-emitting diodes (LEDs). Patent Document 1 discloses a high-definition display device using organic EL elements.

[0006] Technologies related to transistors using semiconductor thin films have been attracting attention. These transistors are widely used in electronic devices such as integrated circuits (ICs) and display devices. While silicon-based semiconductor materials are widely known as semiconductor materials applicable to transistors, oxide semiconductors have also attracted attention.

[0007] Examples of oxide semiconductors that can be used in transistors include indium oxide, indium gallium zinc oxide, etc. Non-Patent Documents 1 and 2 disclose thin film transistors using indium oxide.

[0008] International Publication No. 2016 / 038508

[0009] Dhananjay & Chu, C. W. Realization of In▲2▼O▲3▼ thin film transistors through reactive evaporation process. Appl. Phys. Lett. 91, 1-4 (2007). Y. Magari et al. , "High-mobility hydrogenated polycrystalline In 2 O 3 (In 2 O 3 : H) thin-film transistors", Nature Communications, 13, 1078 (2022) Takashi Koida, "High-mobility transparent conductive film", National Institute of Advanced Industrial Science and Technology, AIST Photovoltaic Power Generation Research Results Report 2019, Internet <URL: https: / / unit.aist.go.jp / rpd-envene / PV / ja / results / 2019 / oral / T13.pdf>

[0010] An object of one embodiment of the present invention is to provide a semiconductor device or a display device including a transistor with high field-effect mobility. Another object is to provide a semiconductor device or a display device including a transistor with high on-state current. Another object is to provide a semiconductor device or a display device including a micro-sized transistor. Another object is to provide a semiconductor device or a display device including a transistor with a short channel length. Another object is to provide a semiconductor device or a display device including a transistor with favorable electrical characteristics. Another object is to provide a semiconductor device or a display device that operates at high speed. Another object is to provide a semiconductor device with a small occupation area. Another object is to provide a semiconductor device or a display device with low wiring resistance. Another object is to provide a semiconductor device or a display device with low power consumption. Another object is to provide a highly reliable transistor, semiconductor device, or display device. Another object is to provide a display device with high display quality. Another object is to provide a high-resolution display device. Another object is to provide a manufacturing method of the above-described transistor, semiconductor device, or display device. Another object is to provide a manufacturing method of a transistor, semiconductor device, or display device with high productivity. Another object is to provide a novel transistor, semiconductor device, display device, or manufacturing method thereof.

[0011] Note that the description of these problems does not preclude the existence of other problems. One embodiment of the present invention does not necessarily have to solve all of these problems. Problems other than these can be extracted from the description in the specification, drawings, and claims.

[0012] One embodiment of the present invention is a display device including a circuit portion and a display portion. The circuit portion includes a first transistor. The first transistor includes a first semiconductor layer. The display portion includes a display element and a pixel circuit. The pixel circuit includes a second transistor. The second transistor includes a second semiconductor layer. The first semiconductor layer includes indium oxide. The first semiconductor layer includes crystal grains. The grain size of the crystal grains is 0.3 μm or more. The second semiconductor layer includes indium. The indium content in the first semiconductor layer is higher than the indium content in the second semiconductor layer.

[0013] In the above-described display device, the second semiconductor layer preferably contains one or more of gallium, tin, and zinc.

[0014] In the above-described display device, the second semiconductor layer is preferably thicker than the first semiconductor layer.

[0015] One embodiment of the present invention is a display device including a circuit portion and a display portion. The circuit portion includes a first transistor. The first transistor includes a first semiconductor layer, a first conductive layer, and a second conductive layer. The display portion includes a display element and a pixel circuit. The pixel circuit includes a second transistor. The second transistor includes a second semiconductor layer, a third conductive layer, and a fourth conductive layer. A first insulating layer is provided over the first conductive layer. A second conductive layer and a third conductive layer are provided over the first insulating layer. The second conductive layer and the first insulating layer have a first opening that reaches the first conductive layer. The first semiconductor layer has a region in contact with a top surface of the first conductive layer, a side surface of the first insulating layer, and a side surface of the second conductive layer in the first opening. A second insulating layer is provided over the second conductive layer, the third conductive layer, and the first insulating layer. A fourth conductive layer is provided on the second insulating layer. The fourth conductive layer and the second insulating layer have a second opening that reaches the third conductive layer. The second semiconductor layer has a region in the second opening that contacts an upper surface of the second conductive layer, a side surface of the second insulating layer, and a side surface of the fourth conductive layer. The first semiconductor layer contains indium oxide. The first semiconductor layer has crystal grains. The grain size of the crystal grains is 0.3 μm or more. The second semiconductor layer contains indium. The indium content in the first semiconductor layer is higher than the indium content in the second semiconductor layer.

[0016] In the above-described display device, the second semiconductor layer preferably contains one or more of gallium, tin, and zinc.

[0017] In the above-described display device, the second semiconductor layer is preferably thicker than the first semiconductor layer.

[0018] In the display device, the first transistor preferably has a first gate insulating layer and a first gate electrode. The second transistor preferably has a second gate insulating layer and a second gate electrode. The first gate electrode preferably has a region facing the first semiconductor layer through the first gate insulating layer in the first opening. The second gate electrode preferably has a region facing the second semiconductor layer through the second gate insulating layer in the second opening.

[0019] In the above-described display device, it is preferable that the first gate insulating layer does not have a region in contact with the second semiconductor layer.

[0020] In the display device described above, the first insulating layer preferably includes a third insulating layer and a fourth insulating layer on the third insulating layer, the second insulating layer preferably includes silicon and nitrogen, and the third insulating layer preferably includes silicon and oxygen.

[0021] In the display device described above, the second insulating layer preferably includes a fifth insulating layer and a sixth insulating layer on the fifth insulating layer. The fifth insulating layer preferably includes silicon and nitrogen. The sixth insulating layer preferably includes silicon and oxygen.

[0022] According to one embodiment of the present invention, a semiconductor device or display device including a transistor with high field-effect mobility can be provided. Alternatively, a semiconductor device or display device including a transistor with high on-state current can be provided. Alternatively, a semiconductor device or display device including a micro-sized transistor can be provided. Alternatively, a semiconductor device or display device including a transistor with a short channel length can be provided. Alternatively, a semiconductor device or display device including a transistor with favorable electrical characteristics can be provided. Alternatively, a semiconductor device or display device that operates at high speed can be provided. Alternatively, a semiconductor device with a small occupation area can be provided. Alternatively, a semiconductor device or display device with low wiring resistance can be provided. Alternatively, a semiconductor device or display device with low power consumption can be provided. Alternatively, a highly reliable transistor, semiconductor device, or display device can be provided. Alternatively, a display device with high display quality can be provided. Alternatively, a high-resolution display device can be provided. Alternatively, a manufacturing method for the above-described transistor, semiconductor device, or display device can be provided. Alternatively, a manufacturing method for a transistor, semiconductor device, or display device with high productivity can be provided. Alternatively, a novel transistor, semiconductor device, or display device, or a manufacturing method thereof can be provided.

[0023] Note that the description of these effects does not preclude the existence of other effects. One embodiment of the present invention does not necessarily have all of these effects. Effects other than these can be extracted from the description in the specification, drawings, and claims.

[0024] FIG. 1A is a perspective view showing an example of a display device. FIGS. 1B, 1C, 1D, and 1E are cross-sectional views showing an example of a display device. FIGS. 2A, 2B, 2C, 2D, 2E, 2F, and 2G are cross-sectional views showing an example of a display device. FIG. 3A is a top view showing an example of a semiconductor device. FIG. 3B is a cross-sectional view showing an example of a semiconductor device. FIGS. 4A and 4B are cross-sectional views showing an example of a semiconductor device. FIGS. 5A, 5B, 5C, and 5D are perspective views showing an example of a semiconductor device. FIG. 6 is a cross-sectional view showing an example of a semiconductor device. FIG. 7A is a top view showing an example of a semiconductor device. FIG. 7B is a cross-sectional view showing an example of a semiconductor device. FIGS. 8A and 8B are cross-sectional views showing an example of a semiconductor device. FIGS. 9A, 9B, and 9C are cross-sectional views showing an example of a semiconductor device. FIGS. 10A, 10B, and 10C are cross-sectional views showing an example of a semiconductor device. FIGS. 11A, 11B, and 11C are cross-sectional views showing an example of a semiconductor device. FIG. 12A is a top view showing an example of a semiconductor device. 12B and 12C are cross-sectional views showing an example of a semiconductor device. FIG. 13 is a cross-sectional view showing an example of a semiconductor device. FIGS. 14A and 14B are cross-sectional views showing an example of a semiconductor device. FIGS. 15A, 15B, 15C, 15D, and 15E are cross-sectional views showing an example of a method for manufacturing a semiconductor device. FIGS. 16A, 16B, 16C, and 16D are cross-sectional views showing an example of a method for manufacturing a semiconductor device. FIGS. 17A, 17B, and 17C are cross-sectional views showing an example of a method for manufacturing a semiconductor device. FIGS. 18A, 18B, and 18C are cross-sectional views showing an example of a method for manufacturing a semiconductor device. FIGS. 19A, 19B, 19C, and 19D are cross-sectional views showing an example of a method for manufacturing a semiconductor device. FIGS. 20A, 20B, 20C, and 20D are cross-sectional views showing an example of a method for manufacturing a semiconductor device. FIGS. 21A, 21B, 21C, and 21D are cross-sectional views showing an example of a method for manufacturing a semiconductor device. 22A, 22B, and 22C are cross-sectional views showing an example of a method for manufacturing a semiconductor device. FIGS. 23A and 23B are diagrams illustrating carrier concentration dependence of Hall mobility. FIG. 23C is a cross-sectional view illustrating an indium oxide film. FIGS. 24A and 24B are cross-sectional views showing an example of a display device. FIG. 25 is a cross-sectional view showing an example of a display device.26A, 26B, and 26C are cross-sectional views showing an example of a display device. FIGS. 27A and 27B are cross-sectional views showing an example of a display device. FIG. 28 is a cross-sectional view showing an example of a display device. FIG. 29 is a cross-sectional view showing an example of a display device. FIGS. 30A, 30B, 30C, and 30D are diagrams showing an example of an electronic device. FIGS. 31A, 31B, 31C, 31D, 31E, and 31F are diagrams showing an example of an electronic device. FIGS. 32A, 32B, 32C, 32D, 32E, 32F, and 32G are diagrams showing an example of an electronic device.

[0025] The embodiments will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it will be readily understood by those skilled in the art that various changes can be made in form and detail without departing from the spirit and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the description of the embodiments shown below.

[0026] In the configuration of the invention described below, the same parts or parts having similar functions are denoted by the same reference numerals in different drawings, and repeated explanations thereof will be omitted. Furthermore, when referring to similar functions, the same hatching pattern may be used and no particular reference numeral may be assigned.

[0027] For ease of understanding, the position, size, range, etc. of each component shown in the drawings may not represent the actual position, size, range, etc. Therefore, the disclosed invention is not necessarily limited to the position, size, range, etc. disclosed in the drawings.

[0028] In this specification, ordinal numbers such as "first" and "second" are used to avoid confusion between components and do not limit the number of components or the order of the components (for example, the order of processes or the order of stacking). Furthermore, even if a term does not have an ordinal number in this specification, an ordinal number may be added in the claims to avoid confusion between the components. Even if a term has an ordinal number in this specification, a different ordinal number may be added in the claims. Even if a term has an ordinal number in this specification, the ordinal number may be omitted in the claims.

[0029] In this specification and drawings, when the same reference numeral is used for multiple elements, and particularly when it is necessary to distinguish between them, an identification symbol such as "_1", "[n]", or "[m, n]" may be added to the reference numeral. Furthermore, when explaining matters common to multiple elements to which an identification numeral is added, or when it is not necessary to distinguish between them, the elements may be described without the identification numeral.

[0030] The words "film" and "layer" can be interchangeable in some cases or depending on the situation. For example, the term "conductive layer" can be changed to the term "conductive film." Or, for example, the term "insulating film" can be changed to the term "insulating layer."

[0031] A transistor is a type of semiconductor element that can perform functions such as amplifying current or voltage and performing switching operations to control conduction or non-conduction. The term "transistor" as used herein includes an insulated gate field effect transistor (IGFET) and a thin film transistor (TFT).

[0032] The functions of "source" and "drain" may be interchanged when transistors of different polarities are used or when the direction of current changes during circuit operation. For this reason, the terms "source" and "drain" may be used interchangeably in this specification. The source and drain of a transistor may be appropriately referred to as the source terminal and drain terminal, or the source electrode and drain electrode, depending on the situation.

[0033] The terms "gate" and "back gate" can be used interchangeably. Therefore, in this specification and the like, the terms "gate" and "back gate" can be used interchangeably. Note that the names of the gate and back gate of a transistor can be appropriately changed to gate electrode and back gate electrode, etc., depending on the situation.

[0034] In this specification, "connection" includes, as an example, "electrical connection." Note that the term "electrical connection" is sometimes used to define the connection relationship between circuit elements as an object. Furthermore, "electrical connection" includes "direct connection" and "indirect connection." "A and B are directly connected" means that A and B are connected without the intervention of a circuit element (e.g., a transistor, a switch, etc.; note that wiring is not a circuit element). On the other hand, "A and B are indirectly connected" means that A and B are connected via one or more circuit elements. Note that A and B represent objects such as elements, circuits, wiring, electrodes, terminals, semiconductor layers, and conductive layers.

[0035] For example, assuming that a circuit including A and B is operating, if there is a time during the operation of the circuit when an electrical signal is exchanged or an interaction of electrical potential occurs between A and B, then it can be defined that "A and B are indirectly connected" as objects. Note that even if there is a time during the operation of the circuit when no electrical signal is exchanged or an interaction of electrical potential occurs between A and B, it can still be defined that "A and B are indirectly connected" as long as there is a time during the operation of the circuit when an electrical signal is exchanged or an interaction of electrical potential occurs between A and B.

[0036] An example of a case where "A and B are indirectly connected" is when A and B are connected via the source and drain of one or more transistors. On the other hand, an example of a case where it cannot be said that "A and B are indirectly connected" is when an insulator is present in the path from A to B. Specifically, there are cases where a capacitive element is connected between A and B, and cases where a gate insulating film of a transistor is present between A and B. Therefore, it cannot be said that "the gate (A) of a transistor and the source or drain (B) of the transistor are indirectly connected."

[0037] Another example of a case where it cannot be said that "A and B are indirectly connected" is when multiple transistors are connected via their sources and drains to the path from A to B, and a constant potential V is supplied to a node between one transistor and another transistor from a power supply, GND, etc.

[0038] In this specification, unless otherwise specified, the on-state current refers to the drain current (also referred to as Id) when a transistor is in an on state (also referred to as a conductive state). Unless otherwise specified, the on state refers to a state in which the voltage between the gate and the source (also referred to as gate voltage, Vg or Vgs) is equal to or higher than a threshold voltage (also referred to as Vth) for an n-channel transistor, or a state in which the voltage is equal to or lower than the threshold voltage for a p-channel transistor.

[0039] In this specification and the like, unless otherwise specified, the off-state current refers to a leakage current between the source and drain when a transistor is in an off state (also referred to as a non-conducting state or a cut-off state). Unless otherwise specified, the off-state refers to a state in which the voltage between the gate and the source is lower than the threshold voltage in an n-channel transistor, and higher than the threshold voltage in a p-channel transistor.

[0040] In this specification, "parallel" refers to a state in which two straight lines are arranged at an angle of -10 degrees or more and 10 degrees or less. Therefore, it also includes cases in which the angle is -5 degrees or more and 5 degrees or less. Furthermore, "substantially parallel" refers to a state in which two straight lines are arranged at an angle of -30 degrees or more and 30 degrees or less. Furthermore, "perpendicular" refers to a state in which two straight lines are arranged at an angle of 80 degrees or more and 100 degrees or less. Therefore, it also includes cases in which the angle is 85 degrees or more and 95 degrees or less. Furthermore, "substantially perpendicular" refers to a state in which two straight lines are arranged at an angle of 60 degrees or more and 120 degrees or less.

[0041] In this specification, the top surface shape of a component refers to the contour shape of the component as viewed from above (also referred to as a plan view). The top surface view refers to a view from the normal direction of the surface on which the component is formed or the surface of a support (e.g., a substrate) on which the component is formed.

[0042] In this specification, the phrase "top surface shapes that match or approximately match" refers to at least a portion of the contours of stacked layers overlapping. For example, this includes cases where the upper and lower layers are processed using the same mask pattern or a portion of the same mask pattern. However, strictly speaking, the contours may not overlap, and the upper layer may be located inside the lower layer, or outside the lower layer. In these cases, the phrase "top surface shapes that match or approximately match" may also be used. Furthermore, when the top surface shapes match or approximately match, it can also be said that "edges match or approximately match" or "edges are aligned or approximately aligned."

[0043] In this specification, a tapered shape refers to a shape in which at least a part of a side surface of a structure is inclined with respect to a substrate surface or a surface to be formed. The angle formed between the inclined side surface and the substrate surface or the surface to be formed is sometimes referred to as a taper angle.

[0044] In this specification and the like, a step disconnection refers to a phenomenon in which a layer, a film, or an electrode is separated due to the shape of the surface on which it is formed (for example, a step or the like).

[0045] In this specification, the term "island-like" refers to a state in which two or more layers made of the same material and formed in the same process are physically separated. For example, an island-like metal oxide layer refers to a state in which the metal oxide layer is physically separated from the adjacent metal oxide layer.

[0046] In this specification, etc., a device fabricated using a metal mask or an FMM (fine metal mask, high-resolution metal mask) may be referred to as a device with an MM (metal mask) structure. Also, in this specification, etc., a device fabricated without using a metal mask or an FMM may be referred to as a device with an MML (metal maskless) structure.

[0047] In this specification and the like, holes or electrons may be referred to as "carriers." For example, in a light-emitting element, a hole injection layer or an electron injection layer may be referred to as a "carrier injection layer," a hole transport layer or an electron transport layer may be referred to as a "carrier transport layer," and a hole block layer or an electron block layer may be referred to as a "carrier block layer." Note that the above-mentioned carrier injection layer, carrier transport layer, and carrier block layer may not be clearly distinguishable. Furthermore, one layer may have two or three functions among the carrier injection layer, carrier transport layer, and carrier block layer.

[0048] In this specification and the like, a light-emitting element has an EL layer between a pair of electrodes (a first electrode and a second electrode). The light-emitting element has a first electrode, an EL layer on the first electrode, and a second electrode on the EL layer. The EL layer has at least a light-emitting layer. Here, examples of layers (also referred to as functional layers) included in the EL layer include a light-emitting layer, a carrier injection layer (a hole injection layer and an electron injection layer), a carrier transport layer (a hole transport layer and an electron transport layer), and a carrier block layer (a hole block layer and an electron block layer). In this specification and the like, a light-receiving element (also referred to as a light-receiving device) has at least an active layer functioning as a photoelectric conversion layer between a pair of electrodes. In this specification and the like, one of the first electrode and the second electrode may be referred to as a pixel electrode, and the other may be referred to as a common electrode.

[0049] In this specification and the like, flexibility refers to the property of an object being soft and bendable, i.e., the property of an object being able to deform in response to an external force applied to the object, regardless of whether or not the object has elasticity or the ability to return to its original shape before deformation.

[0050] For example, flexible electronic devices, flexible display devices (also referred to as flexible displays), flexible batteries (also referred to as flexible batteries), and flexible substrates (also referred to as flexible substrates) can each be deformed in response to an external force. The flexible electronic devices, flexible display devices, flexible batteries, and flexible substrates can each be fixed and used in a deformed state, repeatedly deformed, or used in an undeformed state. Note that the phrase "deforms in response to an external force" refers to deformation without requiring excessive force from the hand of an average adult. Flexibility can be evaluated using a testing machine (such as a tensile testing machine or a compression testing machine) capable of stress-strain measurement. In stress-strain measurement, an external force is applied to an object, and the resulting strain of the object is measured, thereby quantifying the flexibility of the object.

[0051] In this specification, when an object is described as having flexibility, it means that at least a part of the object has flexibility. In other words, a flexible object may have a non-flexible part.

[0052] In this specification, when two objects are deformed by the same external force, the object that deforms more is said to be the object with higher flexibility. Also, when a first part and a second part of an object are deformed by the same external force, the part that deforms more is said to be the part with higher flexibility.

[0053] In this embodiment, a display device and a semiconductor device according to one embodiment of the present invention will be described. The semiconductor device according to one embodiment of the present invention can be suitably used for, for example, one or both of a pixel circuit and a driver circuit of a display device.

[0054] One embodiment of the present invention is a display device including a circuit portion and a display portion including a plurality of pixels. Each pixel includes a display element and a pixel circuit. The circuit portion has a function of controlling the pixel circuit and includes a first transistor. The pixel circuit has a function of controlling driving of the display element and includes a second transistor.

[0055] It is preferable to use different materials for the first semiconductor layer of the first transistor and the second semiconductor layer of the second transistor. It is preferable to use different materials for the first semiconductor layer and the second semiconductor layer depending on the electrical characteristics and reliability required for the first transistor and the second transistor. This makes it possible to provide a display device that has both high display quality and high reliability.

[0056] The first semiconductor layer and the second semiconductor layer can each preferably be made of a metal oxide, and each preferably contains indium and oxygen.

[0057] The first transistor preferably has a large on-state current. The indium content of the first semiconductor layer is preferably higher than that of the second semiconductor layer. By using a metal oxide having a high indium content for the first semiconductor layer, the first transistor can have a large on-state current, and a circuit portion can operate at high speed. This allows the frame frequency during display to be increased, resulting in a display device with high display quality.

[0058] For example, indium oxide can be suitably used for the first semiconductor layer. Furthermore, a polycrystalline indium oxide film is preferably used as the first semiconductor layer, and a single-crystalline indium oxide film is more preferably used. When a polycrystalline film is used for the first semiconductor layer, the grain size of the crystal grains contained in the first semiconductor layer is preferably large. The grain size of the crystal grains in the first semiconductor layer is preferably 0.3 μm or more. By using a polycrystalline film with large grain sizes, the number of grain boundaries located in the channel formation region can be reduced, and the length of the grain boundaries located in the channel formation region can be shortened, resulting in a transistor with high field-effect mobility. Therefore, the first transistor can have a large on-current.

[0059] The second transistor preferably has high reliability against light, so that the electrical characteristics of the second transistor can be prevented from being changed by light incident on the display portion, and a highly reliable display device can be provided.

[0060] The second semiconductor layer preferably contains one or more of gallium, tin, and zinc in addition to indium. By containing one or more of gallium and tin, the band gap of the metal oxide can be increased. This allows oxygen vacancies (V) in the second semiconductor layer to be formed by light. Ｏ ) is suppressed from being formed in the second semiconductor layer, and a shift in the threshold voltage of the second transistor can be suppressed. Therefore, the second transistor can have high reliability against light. Furthermore, since the second semiconductor layer contains zinc, the crystallinity of the second semiconductor layer can be improved. This prevents oxygen vacancies (V Ｏ ) can be suppressed, and the second transistor can have high reliability against light. Therefore, a display device with high reliability can be provided.

[0061] A more specific example will be described below with reference to FIGS. 1A to 22C.

[0062] 1A is a perspective view of a display device 10 according to one embodiment of the present invention. The display device 10 includes a display portion 62 and a circuit portion 64.

[0063] The display device 10 has a configuration in which a substrate 51 and a substrate 52 are bonded together. In Fig. 1A, the substrate 52 is indicated by a dashed line. The display device 10 has a display unit 62 and a circuit unit 64 between the substrates 51 and 52.

[0064] The display unit 62 is an area for displaying an image and has a plurality of periodically arranged pixels 19. FIG. 1A shows an enlarged view of one pixel 19. The pixel 19 shown in FIG. 1A has pixels 11R, 11G, and 11B that function as sub-pixels. For example, pixel 11R emits red light, pixel 11G emits green light, and pixel 11B emits blue light. A full-color display can be achieved by combining a plurality of sub-pixels of different colors to function as a single pixel. Note that the number of sub-pixels included in a single pixel and the combination of colors of the sub-pixels are not particularly limited.

[0065] Each of the pixel 11R, pixel 11G, and pixel 11B includes a display element and a pixel circuit that controls the driving of the display element.

[0066] The pixel arrangement in the display device of this embodiment is not particularly limited, and various methods can be applied, such as a stripe arrangement, an S-stripe arrangement, a matrix arrangement, a delta arrangement, a Bayer arrangement, and a pentile arrangement.

[0067] The circuit portion 64 has a function of controlling the pixel circuits. The circuit portion 64 includes, for example, a scanning line driver circuit (also referred to as a gate driver). Alternatively, the circuit portion 64 may include both a scanning line driver circuit and a signal line driver circuit (also referred to as a source driver).

[0068] The circuit section 64 may include various circuits such as a shift register circuit, a level shifter circuit, an inverter circuit, a latch circuit, an analog switch circuit, a demultiplexer circuit, and a logic circuit. The circuit section 64 may include transistors, capacitance elements, and the like.

[0069] The display device of one embodiment of the present invention can be used for a display module. Examples of the display module include a display module in which a connector such as a flexible printed circuit (hereinafter referred to as FPC) or a tape carrier package (TCP) is attached to the display device, and a display module in which an integrated circuit (IC) is mounted by a chip-on-glass (COG) method, a chip-on-film (COF) method, or the like.

[0070] The display device 10 has a connection section 40 and a conductive layer 65 in addition to a display section 62 and a circuit section 64. Also, Fig. 1A shows an example in which an IC 73 and an FPC 72 are mounted on the display device 10. Therefore, the configuration shown in Fig. 1A can also be said to be a display module having the display device 10, an IC, and an FPC.

[0071] The connection portion 40 is provided on the outside of the display portion 62. The connection portion 40 can be provided along one or more sides of the display portion 62. There can be one or more connection portions 40. FIG. 1A shows an example in which the connection portion 40 is provided so as to surround the four sides of the display portion 62. The connection portion 40 connects the common electrode of the display element and the conductive layer, and can supply a potential to the common electrode.

[0072] The conductive layer 65 has a function of supplying signals and power to the display portion 62 and the circuit portion 64. The signals and power are input to the conductive layer 65 from the outside via the FPC 72 or are input to the conductive layer 65 from the IC 73.

[0073] 1A shows an example in which an IC 73 is provided on a substrate 51 by a COG method. For example, an IC having a scanning line driver circuit or a signal line driver circuit, or both, can be used as the IC 73. The display device 10A and the display module may also be configured without an IC. The IC may also be mounted on an FPC by a COF method or the like.

[0074] 1B is a cross-sectional view showing the configuration of the display unit 62 and the circuit unit 64. FIG. 1B shows a pixel 11 that can be applied to sub-pixels (for example, pixel 11R, pixel 11G, and pixel 11B) included in the display unit 62.

[0075] The pixel 11 includes a display element 13 and a pixel circuit 15. The pixel circuit 15 includes a transistor 30. The transistor 30 is connected to the display element 13. Note that the number of transistors included in the pixel circuit 15 is not particularly limited. The pixel circuit 15 may include a plurality of transistors 30.

[0076] The circuit portion 64 has a transistor 20. Note that the number of transistors included in the circuit portion 64 is not particularly limited. Furthermore, the connection relationship between the pixel circuit 15 and the transistors included in the circuit portion 64 is not particularly limited. The circuit portion 64 may have a configuration including a plurality of transistors 20.

[0077] The transistor 20 and the transistor 30 can be formed in different processes. FIG. 1B shows a layer 21 including the transistor 20 and a layer 31 including the transistor 30. The layer 21 including the transistor 20 is provided over a substrate 51, the layer 31 including the transistor 30 is provided over the layer 21, and the display element 13 is provided over the layer 31. Note that the layer 21 and the layer 31 may not be clearly distinguished from each other. Furthermore, a part of a transistor included in one layer may be included in the other layer. For example, a part of the transistor 20 may be included in the layer 31. The transistor 30 can be formed after the transistor 20 or a part of the transistor 20 is formed. A part of the transistor 20 and a part of the transistor 30 can be formed in a common process.

[0078] The structures of the transistor provided in the layer 21 (here, the transistor 20) and the transistor provided in the layer 31 (here, the transistor 30) are not particularly limited. The transistors provided in the layer 21 and the layer 31 can have the same structure. Alternatively, the transistors provided in the layer 21 and the layer 31 can have different structures.

[0079] The transistor 20 preferably has higher reliability against heat than the transistor 30. The transistor 20 preferably has small fluctuations in electrical characteristics due to heat. This can prevent fluctuations in the electrical characteristics of the transistor 20 due to heat applied during the formation of the transistor 30. Therefore, a transistor with favorable electrical characteristics can be obtained, and a display device with high reliability can be provided.

[0080] The transistor 20 preferably has a higher field-effect mobility than the transistor 30. The transistor 20 preferably has a higher on-state current than the transistor 30. This enables the circuit portion 64 to operate at high speed, thereby providing a display device with high display quality.

[0081] The transistor 30 preferably has higher reliability against light than the transistor 20. That is, the transistor 30 preferably has small fluctuations in electrical characteristics due to light. This can prevent the electrical characteristics of the transistor 30 from being changed by light incident on the display portion 62. Therefore, a highly reliable display device can be provided.

[0082] The semiconductor layer of the transistor 20 (hereinafter also referred to as a first semiconductor layer) and the semiconductor layer of the transistor 30 (hereinafter also referred to as a second semiconductor layer) can be formed in different processes. Therefore, different materials can be used for the first semiconductor layer and the second semiconductor layer, which can broaden the range of materials to be used for the first semiconductor layer and the second semiconductor layer.

[0083] In this specification and the like, different materials refer to materials in which some or all of the constituent elements are different, or materials in which the constituent elements are the same but the composition is different.

[0084] The electrical characteristics and reliability of a transistor vary depending on the material used for the semiconductor layer. It is preferable to use different materials for the first semiconductor layer and the second semiconductor layer depending on the electrical characteristics and reliability required for the transistor 20 and the transistor 30. This allows a display device to have both high display quality and high reliability.

[0085] Alternatively, the same material can be used for the first semiconductor layer and the second semiconductor layer, which allows a common device to be used for forming the first semiconductor layer and the second semiconductor layer, thereby reducing the manufacturing cost of the display device.

[0086] The semiconductor materials used for the first semiconductor layer and the second semiconductor layer are not particularly limited. For example, semiconductors made of simple elements or compound semiconductors can be used. Examples of semiconductors made of simple elements include silicon and germanium. Examples of compound semiconductors include gallium arsenide and silicon germanium. Other examples of compound semiconductors include organic semiconductors, nitride semiconductors, and oxide semiconductors (OS: Oxide Semiconductor). Note that these semiconductor materials may contain impurities as dopants.

[0087] The crystallinity of the semiconductor material is not particularly limited, and any of an amorphous semiconductor, a single-crystal semiconductor, and a semiconductor having crystallinity other than single crystal (a microcrystalline semiconductor, a polycrystalline semiconductor, or a semiconductor having a crystalline region in part) can be used. The use of a single-crystal semiconductor or a crystalline semiconductor is preferable because it can suppress deterioration of transistor characteristics.

[0088] One or both of the first semiconductor layer and the second semiconductor layer can be made of, for example, silicon. Examples of silicon include single crystal silicon, polycrystalline silicon, microcrystalline silicon, and amorphous silicon. Examples of polycrystalline silicon include low temperature polysilicon (LTPS). A transistor using amorphous silicon for its channel formation region can be fabricated on a large glass substrate at low cost. A transistor using polycrystalline silicon for its channel formation region has high field-effect mobility and can operate at high speed. A transistor using microcrystalline silicon for its channel formation region has higher field-effect mobility than a transistor using amorphous silicon and can operate at high speed. Note that a transistor using silicon for its channel formation region may be referred to as a Si transistor, and a transistor using LTPS for its channel formation region may be referred to as an LTPS transistor.

[0089] It is preferable to use a metal oxide (also referred to as an oxide semiconductor) exhibiting semiconductor characteristics for one or both of the first semiconductor layer and the second semiconductor layer. A transistor using an oxide semiconductor (hereinafter also referred to as an OS transistor) has extremely high field-effect mobility compared to a transistor using amorphous silicon. In addition, an OS transistor has a significantly low off-state current and can hold charge accumulated in a capacitor connected in series with the transistor for a long period of time. Furthermore, the use of an OS transistor can reduce the power consumption of a display device. Note that when a metal oxide is used for a semiconductor layer, the semiconductor layer can be referred to as a metal oxide layer or a metal oxide film.

[0090] One of the first semiconductor layer and the second semiconductor layer may be made of a metal oxide, and the other may be made of silicon. For example, one of the first semiconductor layer and the second semiconductor layer may be made of indium oxide, and the other may be made of LTPS. This makes it possible to provide a display device that has an OS transistor having both low off-state current and high field-effect mobility and an LTPS transistor having high field-effect mobility, and that achieves both high display quality and low power consumption.

[0091] It is particularly preferable to use a metal oxide for both the first semiconductor layer and the second semiconductor layer. That is, it is particularly preferable to use OS transistors for both the display portion 62 and the circuit portion 64. Furthermore, all the transistors included in the display device can be OS transistors. This allows the display device to have low power consumption and reduce manufacturing costs.

[0092] The electrical characteristics and reliability of a transistor vary depending on the composition of the metal oxide used in the semiconductor layer. When metal oxide is used for both the first semiconductor layer and the second semiconductor layer, it is preferable to make the composition of the metal oxide used in the first semiconductor layer different from the composition of the metal oxide used in the second semiconductor layer depending on the electrical characteristics and reliability required for the transistor 20 and the transistor 30. This makes it possible to provide a display device that achieves both high display quality and high reliability.

[0093] The metal oxide preferably contains at least indium. For example, indium oxide can be suitably used as the metal oxide. Alternatively, for example, gallium oxide or zinc oxide can be used as the metal oxide. Alternatively, the metal oxide preferably contains one or both of indium and zinc. Alternatively, the metal oxide preferably contains one or more elements selected from indium, element M, and zinc. The element M is a metal element or semimetal element having a high bond energy with oxygen, for example, a metal element or semimetal element having a bond energy with oxygen higher than that of indium. Specific examples of the element M include aluminum, gallium, tin, yttrium, titanium, vanadium, chromium, manganese, iron, cobalt, nickel, zirconium, molybdenum, hafnium, tantalum, tungsten, lanthanum, cerium, neodymium, magnesium, calcium, strontium, barium, boron, silicon, germanium, and antimony. The element M contained in the metal oxide is preferably one or more of the above elements, more preferably one or more selected from gallium, aluminum, tin, and yttrium, and even more preferably one or more of gallium, aluminum, and tin. These elements are more preferred because they have a high bond energy with oxygen and an ionic radius similar to that of indium or zinc. Furthermore, tin is more preferred because it is tetravalent and can increase carrier mobility. In this specification, metal elements and metalloid elements may be collectively referred to as "metal elements," and the "metal elements" described in this specification may also include metalloid elements.

[0094] Examples of metal oxides include indium zinc oxide (In-Zn oxide, also referred to as IZO (registered trademark)), indium tin oxide (In-Sn oxide, also referred to as ITO), indium titanium oxide (In-Ti oxide), indium gallium oxide (In-Ga oxide), indium tungsten oxide (In-W oxide, also referred to as IWO), indium gallium aluminum oxide (In-Ga-Al oxide), indium gallium tin oxide (In-Ga-Sn oxide, also referred to as IGTO), gallium zinc oxide (Ga-Zn oxide, also referred to as GZO), and aluminum zinc oxide (Al-Zn oxide). , AZO), indium aluminum zinc oxide (In-Al-Zn oxide, also referred to as IAZO), indium tin zinc oxide (In-Sn-Zn oxide, also referred to as ITZO (registered trademark)), indium titanium zinc oxide (In-Ti-Zn oxide), indium gallium zinc oxide (In-Ga-Zn oxide, also referred to as IGZO), indium gallium tin zinc oxide (In-Ga-Sn-Zn oxide, also referred to as IGZTO), indium gallium aluminum zinc oxide (In-Ga-Al-Zn oxide, also referred to as IGAZO, IGZAO, or IAGZO), etc. Alternatively, indium tin oxide containing silicon (In-Si-Sn oxide, also referred to as ITSO), gallium tin oxide (Ga-Sn oxide), aluminum tin oxide (Al-Sn oxide), etc. can be used.

[0095] Note that the metal oxide may contain one or more metal elements having a higher period number in the periodic table instead of or in addition to indium. The greater the overlap of the orbitals of metal elements, the greater the carrier conduction in the metal oxide. Therefore, the presence of a metal element having a higher period number may improve the field-effect mobility of a transistor. Examples of metal elements having a higher period number include metal elements belonging to the fifth period and the sixth period. Specific examples of such metal elements include yttrium, zirconium, silver, cadmium, tin, antimony, barium, lead, bismuth, lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium. Lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium are called light rare earth elements.

[0096] The metal oxide may contain one or more nonmetallic elements. The nonmetallic elements in the metal oxide may increase the carrier concentration or narrow the band gap, thereby increasing the field-effect mobility of the transistor. Examples of nonmetallic elements include carbon, nitrogen, phosphorus, sulfur, selenium, fluorine, chlorine, bromine, and hydrogen.

[0097] By increasing the ratio of the number of indium atoms to the sum of the numbers of atoms of all metal elements contained in the metal oxide, the field-effect mobility of the transistor can be increased, and the transistor can have a large on-state current and therefore operate at high speed.

[0098] In this specification and the like, the ratio of the number of indium atoms to the sum of the numbers of atoms of all contained metal elements may be referred to as the indium content. The same applies to other metal elements. When a plurality of elements are contained as the element M, the sum of the ratios of the number of atoms of the element M to the sum of the numbers of atoms of all contained metal elements can be referred to as the content of the element M.

[0099] By increasing the zinc content in the metal oxide, the metal oxide can be made highly crystalline, which can suppress the diffusion of impurities in the metal oxide, thereby suppressing fluctuations in the electrical characteristics of the transistor and improving its reliability.

[0100] By increasing the content of element M in the metal oxide, it is possible to obtain a metal oxide with a large band gap. Ｏ ) is suppressed from being formed, and oxygen vacancies (V Ｏ ) is suppressed. Therefore, a shift in the threshold voltage of the transistor is suppressed, and the drain current (hereinafter also referred to as cutoff current) that flows when the gate voltage (Vg) is 0 V can be reduced, resulting in a normally-off transistor. Furthermore, a transistor with a small off-state current can be obtained. Furthermore, fluctuations in the electrical characteristics of the transistor can be suppressed, resulting in improved reliability.

[0101] By using a metal oxide with a large band gap for the semiconductor layer, oxygen vacancies (V Ｏ The formation of an element M can be suppressed, and a shift in the threshold voltage of the transistor can be suppressed. Therefore, a transistor with high reliability against light can be obtained. A metal oxide containing the element M can be suitably used for a semiconductor layer of a transistor provided in a region where light can be incident (for example, a display portion).

[0102] It is preferable that the composition of the metal oxide used in the first semiconductor layer is different from the composition of the metal oxide used in the second semiconductor layer.

[0103] As described above, the transistor 20 preferably has a larger on-state current than the transistor 30. The indium content in the first semiconductor layer is preferably higher than the indium content in the second semiconductor layer. By using a metal oxide with a high indium content for the first semiconductor layer, the transistor 20 can have a large on-state current, and the circuit portion 64 can operate at high speed. This allows a display device with high display quality to be obtained. Furthermore, the transistor 20 can be suitably used in a signal line driver circuit that requires high-speed switching operation.

[0104] The first semiconductor layer preferably contains indium and oxygen, for example, indium oxide can be suitably used for the first semiconductor layer.

[0105] By using a metal oxide having a high indium content for the semiconductor layer, a transistor with a large on-state current can be obtained. Furthermore, a transistor using a metal oxide having a high indium content for the semiconductor layer has high field-effect mobility, so that a large on-state current can be obtained even with a small channel width. Therefore, the area occupied by the transistor can be reduced. By using a metal oxide having a high indium content for the first semiconductor layer, the area occupied by the circuit portion 64 can be reduced, and a display device with a narrow frame can be obtained.

[0106] The electrical characteristics of a transistor may fluctuate due to light incident thereon. A transistor used in an area where light may be incident (e.g., the display unit 62) preferably exhibits small fluctuations in electrical characteristics under light irradiation and has high reliability against light. As described above, the transistor 30 preferably has high reliability against light compared to the transistor 20.

[0107] The second semiconductor layer preferably contains indium, the element M, and oxygen. The content of the element M in the second semiconductor layer is preferably higher than the content of the element M in the first semiconductor layer. This prevents oxygen deficiency (V) in the second semiconductor layer. Ｏ ) is suppressed from being formed, and oxygen vacancies (V Ｏ) is suppressed. Therefore, the transistor 30 can have high reliability, and a display device can have high reliability.

[0108] The second semiconductor layer can be made of a metal oxide that does not contain element M. The second semiconductor layer preferably contains indium, zinc, and oxygen. The zinc content in the second semiconductor layer is preferably higher than the zinc content in the first semiconductor layer. This can increase the crystallinity of the second semiconductor layer. Therefore, a highly reliable transistor 30 can be obtained, and a highly reliable display device can be obtained.

[0109] The second semiconductor layer preferably contains indium, one or both of the element M and zinc, and oxygen. The second semiconductor layer preferably contains, for example, indium, gallium, and oxygen. Typically, indium gallium oxide (In—Ga oxide) can be suitably used for the second semiconductor layer. Alternatively, the second semiconductor layer preferably contains indium, the element M, zinc, and oxygen. For example, the second semiconductor layer preferably contains indium, tin, zinc, and oxygen. Typically, indium tin zinc oxide (In—Sn—Zn oxide) or indium gallium zinc oxide (In—Ga—Zn oxide) can be suitably used for the second semiconductor layer.

[0110] The indium content in the second semiconductor layer is also preferably high. The indium content in the second semiconductor layer is preferably higher than the content of element M (e.g., gallium and tin) in the second semiconductor layer. Furthermore, the indium content in the second semiconductor layer is preferably higher than the zinc content in the second semiconductor layer. This allows the transistor 30 to have both a large on-state current and high reliability. Therefore, a display device with high display quality and high reliability can be obtained. Furthermore, by applying a transistor having a metal oxide with a high indium content to the pixel circuit 15, the area occupied by the pixel circuit 15 can be reduced. This allows a high-definition display device to be obtained.

[0111] The first semiconductor layer and the second semiconductor layer preferably have crystallinity. Examples of the structure of a crystalline metal oxide include a single crystal structure, a polycrystalline structure, a c-axis aligned crystal (CAAC) structure, and a nanocrystalline (nc) structure. By using a crystalline metal oxide, the density of defect states in the semiconductor layer can be reduced, and a highly reliable semiconductor device can be realized.

[0112] The first semiconductor layer preferably has high crystallinity, and is preferably polycrystalline or single-crystalline. A polycrystalline indium oxide film is preferably used as the first semiconductor layer, and a single-crystalline indium oxide film is more preferably used.

[0113] The crystallinity of the first semiconductor layer and the second semiconductor layer can be analyzed by, for example, X-ray diffraction (XRD), transmission electron microscope (TEM), or electron diffraction (ED). Alternatively, the analysis can be performed by combining a plurality of these techniques.

[0114] A single-crystalline film is particularly preferable because it does not have grain boundaries, thereby suppressing carrier scattering at grain boundaries and enabling a transistor with high field-effect mobility. Compared to microcrystalline films and amorphous films, a polycrystalline film can reduce carrier scattering, enabling a transistor with high field-effect mobility. When a polycrystalline film is used for the first semiconductor layer, the grain size of the crystal grains contained in the first semiconductor layer is preferably large. Using a polycrystalline film with large grain sizes can reduce the number of grain boundaries located in the channel formation region and shorten the length of the grain boundaries located in the channel formation region, resulting in a transistor with high field-effect mobility. Furthermore, it is preferable that the number of grain boundaries intersecting the drain current flow direction (also referred to as the channel length direction) in the channel formation region is small. Even a polycrystalline film can achieve the same effects as a single-crystalline film if no grain boundaries are located in the channel formation region.

[0115] When a polycrystalline indium oxide film is used as the semiconductor layer, the grain size of the crystal grains contained in the semiconductor layer is preferably 0.1 μm or more, more preferably 0.2 μm or more, even more preferably 0.3 μm or more, even more preferably 0.4 μm or more, even more preferably 0.5 μm or more, even more preferably 0.6 μm or more, and even more preferably 0.7 μm or more. Since a large grain size of the crystal grains is preferable, no upper limit is particularly set for the grain size. Note that the grain size of the crystal grains is not limited to the above-mentioned range.

[0116] The grain size of the crystal grains contained in the semiconductor layer can be analyzed by, for example, a transmission electron microscope (TEM), a scanning transmission electron microscope (STEM), or an electron backscatter diffraction pattern (EBSD or EBSP). Alternatively, the analysis can be performed by combining a plurality of these techniques. For example, the average value of the grain sizes of a plurality of crystal grains can be used as the grain size. Furthermore, the grain size of a crystal grain can be, for example, the diameter of a circle having the same area as the area of ​​the crystal grain. Note that this diameter is sometimes called the circle equivalent diameter.

[0117] In this specification, the term "grain boundary" refers to, for example, a boundary between adjacent crystal grains with different crystal orientations. Therefore, in this specification, the term "grain boundary" does not include a boundary between adjacent crystal grains with the same crystal orientation. For example, even if a boundary between two crystal grains is observed in a TEM image, if the crystal orientations of the two crystal grains are identical or nearly identical, the boundary may not be called a grain boundary. Furthermore, in EBSD, if the difference in crystal orientation between adjacent measurement points is small (for example, if the difference in crystal orientation is less than 5 degrees), these measurement points can be considered to belong to the same crystal grain.

[0118] In this specification, space groups are expressed using short notation in international notation (or Hermann-Mauguin notation). In addition, space group numbers in the International Tables for Crystallography Volume A (hereinafter also referred to as ITA) may be assigned. Crystal planes and crystal directions are also expressed using Miller indices. In crystallography, space groups, crystal planes, and crystal directions are expressed with a bar above the number. However, due to formatting restrictions, in this specification, instead of a bar above the number, a minus sign (-) may be placed before the number. Individual orientations indicating directions within a crystal are expressed with [ ], collective orientations indicating all equivalent directions with < >, individual planes indicating crystal planes with ( ), and collective planes with equivalent symmetry with {}. Even if the space group number is the same, the space group notation may differ depending on how the crystal axes are arranged.

[0119] The crystal structure of cubic indium oxide belongs to space group Ia-3 (space group number 206).

[0120] The grain size of the crystal grains can also be confirmed using, for example, an optical microscope or a scanning electron microscope (SEM). Furthermore, by creating unevenness on the surface of the first semiconductor layer using an etchant whose etching rate varies depending on the crystal plane or crystallinity, the crystal grains can be easily observed even with an optical microscope or a scanning electron microscope (SEM). When an indium oxide film is used as the first semiconductor layer, the crystal grains of the indium oxide can be easily observed by using an etchant containing an acid. For example, one or more of phosphoric acid, oxalic acid, nitric acid, and hydrochloric acid can be used as the acid. Note that if the etching rate is too fast, part of the first semiconductor layer may be lost, making it difficult to observe the crystal grains. Therefore, it is preferable to adjust the etching rate by adjusting the concentration, temperature, and processing time of the etchant so that the thickness of the first semiconductor layer is reduced without being lost (also referred to as half etching). By performing half etching, the crystal grains can be easily observed.

[0121] When the thickness of the semiconductor layer is thin, it may be difficult to evaluate the crystallinity and the grain size of the crystal grains.

[0122] The impurity concentration in the channel formation region is preferably low. The channel formation region is preferably highly pure. In the channel formation region, impurities can act as a carrier scattering source, which can reduce the field-effect mobility. Furthermore, impurities can also hinder crystal growth.

[0123] Impurities in an indium oxide film include gallium, zinc, boron, aluminum, and silicon. In the channel formation region, the concentration of each of these impurities is preferably 1 atomic % or less, more preferably 0.1 atomic % or less, and even more preferably 0.01 atomic % (100 ppm) or less. Examples of elements that can be contained in an indium oxide film include carbon and hydrogen. Carbon and hydrogen are elements that can be contained in a film-forming gas (e.g., a precursor) for an indium oxide film, and may exist in the indium oxide film in greater amounts than the aforementioned impurities. Note that ppm is an abbreviation for "parts per million," and 1 ppm is 1×10 −６ is.

[0124] The concentration of impurities in a semiconductor layer can be analyzed using, for example, secondary ion mass spectrometry (SIMS) or X-ray photoelectron spectrometry (XPS). When using XPS analysis, the concentration distribution in the depth direction can be determined by combining ion sputtering from the front or back side of the sample with XPS analysis. Note that in low-concentration regions, quantification may be difficult or the concentration may be below the detection limit. XPS is also sometimes called ESCA (Electron Spectrometry for Chemical Analysis).

[0125] The concentrations of gallium, zinc, boron, aluminum, and silicon in the channel formation region are each 1×10 ２０atoms / cm ３ Preferably, it is less than 5×10 １９ atoms / cm ３ Preferably, it is less than 3×10 １９ atoms / cm ３ Preferably, it is equal to or less than 1×10 １９ atoms / cm ３ Preferably, it is less than 3×10 １８ atoms / cm ３ Preferably, it is equal to or less than 1×10 １８ atoms / cm ３ The following is preferred:

[0126] By using an indium oxide film with large crystal grains and a low impurity concentration in a transistor, the field effect mobility of the transistor can be increased to 50 cm ２ / (V·s) or more, even 100 cm ２ / (V·s) or more, and even 150 cm ２ / (V s) or more, even 200 cm ２ / (V s) or more, and even 250 cm ２ / (V·s) or more.

[0127] The second semiconductor layer is preferably formed using a CAAC-OS or an nc-OS. For example, an indium tin zinc oxide (In—Sn—Zn oxide) film or an indium gallium zinc oxide (In—Ga—Zn oxide) film having a CAAC structure or an nc structure can be suitably used as the second semiconductor layer.

[0128] The CAAC-OS has multiple layered crystals whose c-axes are oriented in the normal direction to the surface where the semiconductor layer is formed. The semiconductor layer preferably has layered crystals parallel or substantially parallel to the surface where the semiconductor layer is formed. With this structure, the layered crystals of the semiconductor layer are formed parallel or substantially parallel to the channel length direction of the transistor, thereby enabling the transistor to have a large on-state current.

[0129] Examples of configurations different from the configuration shown in FIG. 1B are shown in FIGS. 1C to 2G.

[0130] The configuration shown in FIG. 1C differs from the configuration shown in FIG. 1B mainly in that the circuit portion 64 includes a transistor 30A. The circuit portion 64 includes a transistor 20 and a transistor 30A. The layer 31 includes a transistor 30 and a transistor 30A. The same configuration as that of the transistor 30 can be applied to the transistor 30. The transistor 30A can be formed using the same material and in the same process as the transistor 30. In other words, some of the transistors included in the circuit portion 64 can be formed in the same process as the transistors included in the pixel circuit 15. For the transistor 30A, the description of the transistor 30 can be referred to.

[0131] By providing the transistors included in the circuit portion 64 in both the layer 21 and the layer 31, the area occupied by the circuit portion 64 can be reduced. This allows a display device with a narrow frame. Furthermore, the transistor 30A preferably has a region overlapping with the transistor 20. This allows the area occupied by the circuit portion 64 to be further reduced.

[0132] The semiconductor layer of the transistor 30A can be made of the same material as the semiconductor layer of the transistor 30. Furthermore, the semiconductor layer of the transistor 30A can be made of a different material from the semiconductor layer of the transistor 20. The indium content in the semiconductor layer of the transistor 20 is preferably higher than the indium content in the semiconductor layer of the transistor 30A. For example, in the circuit portion 64, the transistor 20 can be used as a transistor that requires high-speed operation, and the transistor 30A can be used as a transistor that requires high reliability. This allows for a display device with high display quality and high reliability. Furthermore, in the circuit portion 64, the transistor 20 or the transistor 30A can be appropriately selected depending on the magnitude of the required on-state current, thereby increasing the degree of freedom in circuit design.

[0133] For example, a metal oxide may be used for one of the semiconductor layers (first semiconductor layer) of the transistor 20 and the semiconductor layers (second semiconductor layers) of the transistors 30 and 30A, and silicon may be used for the other of the first semiconductor layer and the second semiconductor layer. Alternatively, the transistor 20 may be a p-channel LTPS transistor, and the transistor 30A may be an n-channel OS transistor. This allows a CMOS circuit to be applied to the circuit portion 64, thereby reducing the area occupied by the circuit portion 64.

[0134] The configuration shown in FIG. 1D differs from the configuration shown in FIG. 1B mainly in that the pixel circuit 15 includes a transistor 20A. The pixel circuit 15 includes a transistor 30 and a transistor 20A. The layer 21 includes a transistor 20 and a transistor 20A. The transistor 20A can have a similar configuration to the transistor 20. The transistor 20A can be formed using the same material and in the same process as the transistor 20. In other words, some of the transistors included in the pixel circuit 15 can be formed in the same process as the transistors included in the circuit portion 64. For the transistor 20A, the description of the transistor 20 can be referred to.

[0135] The semiconductor layer of the transistor 20A can be made of the same material as the semiconductor layer of the transistor 20. The indium content in the semiconductor layer of the transistor 20A is preferably higher than the indium content in the semiconductor layer of the transistor 30. This allows the transistor 20A to have a large on-state current. Furthermore, the transistor 30 can have high saturation properties. For example, in the pixel circuit 15, the transistor 20A can be used as a transistor that requires high-speed operation, and the transistor 30 can be used as a transistor that requires high saturation properties. When a light-emitting element is used as the display element 13, the pixel circuit 15 can have a configuration including a drive transistor for controlling a current flowing through the light-emitting element and a selection transistor that functions as a switch for selecting and deselecting the pixel. The transistor 30 can be suitably used as the drive transistor. The transistor 20A can be suitably used as the selection transistor. This allows a display device with high display quality.

[0136] In this specification and the like, a small change in current in the saturation region in the Id-Vd characteristics of a transistor may be expressed as "high saturation."

[0137] By using a metal oxide having a high indium content for the semiconductor layer of the transistor 20A, the area occupied by the transistor 20A can be reduced, which in turn reduces the area occupied by the pixel circuit 15. This allows a high-definition display device to be provided.

[0138] By providing the transistors included in the pixel circuit 15 in both the layer 21 and the layer 31, the area occupied by the pixel circuit 15 can be reduced. Furthermore, the transistor 20A preferably has a region overlapping with the transistor 30. This can further reduce the area occupied by the pixel circuit 15. Furthermore, in the pixel circuit 15, the transistor 20A or the transistor 30 can be selected as appropriate depending on the magnitude of the required on-state current, thereby increasing the degree of freedom in circuit design.

[0139] For example, a metal oxide may be used for one of the semiconductor layers (first semiconductor layer) of the transistor 20 and the transistor 20A and the semiconductor layer (second semiconductor layer) of the transistor 30, and silicon may be used for the other of the first semiconductor layer and the second semiconductor layer. Alternatively, the transistor 20A may be a p-channel LTPS transistor, and the transistor 30 may be an n-channel OS transistor. By using an n-channel transistor and a p-channel transistor in the pixel circuit 15, a CMOS circuit can be applied, thereby increasing the degree of freedom in circuit design.

[0140] 1D illustrates a structure in which the display element 13 is connected to the transistor 30; however, one embodiment of the present invention is not limited to this. The display element 13 can also be connected to the transistor 20A.

[0141] The configuration shown in FIG. 1E differs from the configuration shown in FIG. 1B mainly in that the circuit portion 64 includes a transistor 30A and the pixel circuit 15 includes a transistor 20A. The circuit portion 64 includes a transistor 20 and a transistor 30A. The pixel circuit 15 includes a transistor 30 and a transistor 20A. The layer 21 includes a transistor 20 and a transistor 20A. The layer 31 includes a transistor 30 and a transistor 30A. By providing the transistors included in the pixel circuit 15 and the transistors included in the circuit portion 64 in both the layer 21 and the layer 31, respectively, the areas occupied by the pixel circuit 15 and the circuit portion 64 can be reduced. This allows for a display device that achieves both high definition and a narrow frame. Furthermore, a display device with high display quality can be obtained.

[0142] The configuration shown in FIG. 2A differs from the configuration shown in FIG. 1B mainly in that the circuit portion 64 has a region overlapping with the pixel circuit 15. The circuit portion 64 includes a transistor 20 and a transistor 20A. The pixel circuit 15 includes a transistor 30. FIG. 2A shows a configuration in which the transistor 30 is provided over the transistor 20A, and the transistor 20A has a region overlapping with the transistor 30. The layer 21 includes the transistor 20 and the transistor 20A. The layer 31 includes the transistor 30. The circuit portion 64 has a region overlapping with the pixel circuit 15, thereby enabling a display device with a narrow frame.

[0143] 2B differs from the configuration shown in FIG. 2A mainly in that the circuit portion 64 includes a transistor 30A. The circuit portion 64 includes a transistor 20, a transistor 20A, and a transistor 30A. The pixel circuit 15 includes a transistor 30. The layer 21 includes a transistor 20 and a transistor 20A. The layer 31 includes a transistor 30 and a transistor 30A. By providing the transistors included in the circuit portion 64 in both the layer 21 and the layer 31 and further having a region where the circuit portion 64 overlaps with the pixel circuit 15, a display device with a narrow frame can be achieved.

[0144] 2C differs from the configuration shown in FIG. 1B in that the pixel circuit 15 includes a transistor 20 and the circuit portion 64 includes a transistor 30. By using the transistor 20 having a metal oxide with a high indium content in the pixel circuit 15, the area occupied by the pixel circuit 15 can be reduced. This allows for a high-resolution display device. By using the transistor 30 having a metal oxide with a high content of element M in the circuit portion 64, the reliability of circuits (e.g., a scanning line driver circuit and a signal line driver circuit) included in the circuit portion 64 can be improved.

[0145] 1B to 2C show a structure in which the layer 31 is provided over the layer 21, but one embodiment of the present invention is not limited thereto. As shown in FIG. 2D , the layer 21 can be provided over the layer 31. A display element 13 is provided over the layer 21. The layer 31 includes the transistor 30 and the transistor 30A, and the layer 21 includes the transistor 20 and the transistor 20A. When the layer 31 is provided over the layer 21, it is preferable that the transistors 30 and 30A have smaller fluctuations in electrical characteristics due to heat than the transistors 20 and 20A. This can prevent the electrical characteristics of the transistors 30 and 30A from fluctuating due to heat applied during the formation of the transistors 20 and 20A. Therefore, the transistors can have favorable electrical characteristics, resulting in a highly reliable display device.

[0146] 1B to 2D show a structure in which the layer in which the transistors 20 and 20A are provided (here, the layer 21) is different from the layer in which the transistors 30 and 30A are provided (here, the layer 31), but one embodiment of the present invention is not limited thereto. As shown in FIGS. 2E to 2G, the transistors 20 and 20A and the transistors 30 and 30A can be provided in the same layer.

[0147] 2E and 2F show a layer 41 including a transistor 20 and a transistor 30. The layer 41 including the transistor 20 and the transistor 30 is provided on a substrate 51, and a display element 13 is provided on the layer 41. The transistors 20 and 30 can be formed using some common processes. This can improve productivity of the display device and reduce manufacturing costs. For example, the first semiconductor layer and the second semiconductor layer can be formed in different processes, and components other than the first semiconductor layer and the second semiconductor layer can be formed in the same process. FIG. 2E shows a configuration in which a circuit portion 64 includes a transistor 20 and a pixel circuit 15 includes a transistor 30. FIG. 2F shows a configuration in which the circuit portion 64 includes a transistor 30 and a pixel circuit 15 includes a transistor 20.

[0148] Note that the transistors 20 and 30 can have the same structure. Alternatively, the transistors 20 and 30 can have different structures.

[0149] 2G, a layer 41 including transistors 20, 20A, 30, and 30A can be provided on a substrate 51. The circuit portion 64 includes the transistors 20 and 30A, and the pixel circuit 15 includes the transistors 30 and 20A.

[0150] [Semiconductor Layer] Metal oxides that can be used for the first semiconductor layer and the second semiconductor layer will be specifically described below. As described above, the metal oxide preferably contains at least indium.

[0151] When the metal oxide is an In-M-Zn oxide, the atomic ratio of In in the In-M-Zn oxide is preferably equal to or greater than the atomic ratio of the element M. Examples of atomic ratios of metal elements in such In-M-Zn oxides include In:M:Zn = 1:1:1, In:M:Zn = 1:1:1.2, In:M:Zn = 2:1:3, In:M:Zn = 3:1:1, In:M:Zn = 3:1:2, In:M:Zn = 4:2:3, In:M:Zn = 4:2:4.1, In:M:Zn = 5:1:3, In:M:Zn = 5:1:6, In:M:Zn = 5:1:7, In:M:Zn = 5:1:8, In:M Examples of suitable compositions include In:M:Zn = 5:1:9, In:M:Zn = 6:1:6, In:M:Zn = 10:1:1, In:M:Zn = 10:1:3, In:M:Zn = 10:1:4, In:M:Zn = 10:1:6, In:M:Zn = 10:1:7, In:M:Zn = 10:1:8, In:M:Zn = 5:2:5, In:M:Zn = 10:1:10, In:M:Zn = 20:1:10, In:M:Zn = 40:1:10, and compositions in the vicinity thereof. Note that a composition in the vicinity includes a range of ±30% of the desired atomic ratio. Increasing the atomic ratio of indium in the metal oxide can increase the on-state current or field-effect mobility of the transistor.

[0152] The atomic ratio of In in the In-M-Zn oxide can be less than the atomic ratio of the element M. Examples of atomic ratios of metal elements in such In-M-Zn oxide include In:M:Zn=1:3:2, In:M:Zn=1:3:3, In:M:Zn=1:3:4, In:M:Zn=1:3:6, and compositions close to these. By increasing the ratio of the number of M atoms in the metal oxide, oxygen deficiency (V Ｏ ) can be suppressed.

[0153] When the element M contains a plurality of elements, the atomic ratio of the element M can be the sum of the atomic ratios of these elements.

[0154] By using a material with a high indium content for the semiconductor layer, the on-state current or field-effect mobility of the transistor can be increased. Furthermore, by containing the element M, oxygen vacancies (V Ｏ The generation of ZnO can be suppressed. The content of element M is preferably 0.1% to 25%, more preferably 0.1% to 20%, even more preferably 0.1% to 10%, even more preferably 0.1% to 8%, even more preferably 0.1% to 6%, and even more preferably 0.1% to 4%. This allows for a transistor with excellent electrical characteristics. For example, it is preferable to use a metal oxide having a ratio of In:M:Zn=40:1:10 or thereabouts. The element M is preferably one or more of the above elements, and more preferably one or more selected from aluminum, gallium, tin, and yttrium. Specifically, a metal oxide having a ratio of In:Sn:Zn=40:1:10 or thereabouts can be suitably used. Alternatively, a metal oxide having a ratio of In:Al:Zn=40:1:10 or thereabouts can be suitably used.

[0155] A metal oxide that does not contain element M can be used for the semiconductor layer. When the metal oxide is an In-Zn oxide, the atomic ratio of the metal elements can be, for example, In:Zn = 1:1, In:Zn = 2:1, In:Zn = 1:2, In:Zn = 3:1, In:Zn = 3:2, In:Zn = 2:3, In:Zn = 4:1, In:Zn = 4:3, In:Zn = 5:1, In:Zn = 5:2, In:Zn = 5:3, In:Zn = 5:4, In:Zn = 5:6, In:Zn = 5:7, In:Zn = 5:8, In:Zn = 5:9, In:Zn = 7:1, In:Zn = 10:1, In:Zn = 10:3, In:Zn = 10:7, and compositions in the vicinity thereof. Furthermore, it is more preferable that the atomic ratio of In is equal to or greater than the atomic ratio of Zn. By increasing the atomic ratio of indium in the metal oxide, the on-state current or field-effect mobility of the transistor can be increased.

[0156] The composition of the semiconductor layer can be analyzed using, for example, energy dispersive X-ray spectrometry (EDX), X-ray photoelectron spectroscopy (XPS), inductively coupled plasma mass spectrometry (ICP-MS), or inductively coupled plasma atomic emission spectrometry (ICP-AES). Alternatively, a combination of these techniques can be used for analysis. It is preferable to separate the peaks of the spectrum obtained by the analysis and identify and quantify the elements. Note that for elements with low content, the actual content may differ from the content obtained by analysis due to the influence of analytical accuracy. For example, if the content of element M is low, the content of element M obtained by analysis may be lower than the actual content, it may be difficult to quantify element M, or element M may be below the detection limit.

[0157] When a metal oxide film is formed by sputtering, the composition of the formed metal oxide film may differ from the composition of the sputtering target. In particular, the zinc content in the formed metal oxide film may decrease to about 50% of the zinc content in the sputtering target.

[0158] Here, in the metal oxide, oxygen deficiency (V Ｏ ) into which hydrogen has entered (hereinafter referred to as V Ｏ When a metal oxide is used for the semiconductor layer, V in the channel formation region Ｏ It is preferable to reduce H as much as possible to obtain high-purity intrinsic or substantially high-purity intrinsic. Ｏ To obtain a metal oxide with a sufficiently reduced amount of H, impurities such as water and hydrogen in the metal oxide must be removed (sometimes referred to as dehydration or dehydrogenation treatment), and oxygen must be supplied to the metal oxide to eliminate oxygen deficiency (V Ｏ It is important to repair the Ｏ By using a metal oxide in which impurities such as H are sufficiently reduced for a channel formation region, a transistor with stable electrical characteristics can be obtained. Ｏ ) is sometimes referred to as oxygenation treatment.

[0159] OS transistors exhibit little change in electrical characteristics due to radiation exposure, i.e., have high radiation resistance, and therefore can be suitably used in environments where radiation may be incident. It can also be said that OS transistors have high reliability against radiation. For example, OS transistors can be suitably used in pixel circuits of X-ray flat panel detectors. Furthermore, OS transistors can be suitably used in semiconductor devices used in outer space. Examples of radiation include electromagnetic radiation (e.g., X-rays and gamma rays) and particle radiation (e.g., alpha rays, beta rays, proton rays, and neutron rays).

[0160] The semiconductor layer may have a layered material that functions as a semiconductor. A layered material is a general term for a group of materials that have a layered crystal structure. A layered crystal structure is a structure in which layers formed by covalent or ionic bonds are stacked via bonds weaker than covalent or ionic bonds, such as van der Waals bonds. A layered material has high electrical conductivity within a unit layer, that is, high two-dimensional electrical conductivity. By using a material that functions as a semiconductor and has high two-dimensional electrical conductivity in the channel formation region, a transistor with a large on-current can be provided.

[0161] Examples of the layered material include graphene, silicene, and chalcogenides. Chalcogenides are compounds containing chalcogen (an element belonging to Group 16). Examples of chalcogenides include transition metal chalcogenides and Group 13 chalcogenides. Specific examples of transition metal chalcogenides that can be used as the channel formation region of a transistor include molybdenum sulfide (typically MoS ２ ), molybdenum selenide (typically MoSe ２ ), molybdenum telluride (typically MoTe ２ ), tungsten sulfide (typically WS ２ ), tungsten selenide (typically WSe ２ ), tungsten tellurium (typically WTe ２ ), hafnium sulfide (typically HfS ２ ), hafnium selenide (typically HfSe ２ ), zirconium sulfide (typically ZrS ２ ), zirconium selenide (typically ZrSe ２ ) etc.

[0162] <Structural Example 1 of Semiconductor Device> A semiconductor device according to one embodiment of the present invention will be described. The semiconductor device according to one embodiment of the present invention can be suitably used for, for example, the pixel circuit 15 and the circuit portion 64 of a display device.

[0163] [Configuration Example 1-1 of Semiconductor Device] A top view (also referred to as a plan view) of a semiconductor device 80 is shown in FIG. 3A. A cross-sectional view of the cut surface taken along dashed dotted line A1-A2 shown in FIG. 3A is shown in FIG. 3B, a cross-sectional view of the cut surface taken along dashed dotted line B1-B2 is shown in FIG. 4A, and a cross-sectional view of the cut surface taken along dashed dotted line B3-B4 is shown in FIG. 3A. Note that some of the components of the semiconductor device 80 (such as a gate insulating layer) are omitted in FIG. 3A. As with FIG. 3A, some of the components are omitted in the top views of the semiconductor device in the following drawings.

[0164] The semiconductor device 80 includes a transistor 100, a transistor 200, an insulating layer 110, and an insulating layer 210. The semiconductor device 80 is provided on an insulating surface. In FIG. 3B and other drawings, the semiconductor device 80 is provided on a substrate 102 having an insulating surface. Note that an insulating film may be provided on the substrate 102, and the semiconductor device 80 may be provided on the insulating film.

[0165] The transistor 100 includes a conductive layer 104, an insulating layer 106, a semiconductor layer 108, a conductive layer 112a, and a conductive layer 112b. In the transistor 100, the conductive layer 104 functions as a gate electrode, and the insulating layer 106 functions as a gate insulating layer. The conductive layer 112a functions as one of a source electrode and a drain electrode, and the conductive layer 112b functions as the other. In the semiconductor layer 108, a region that overlaps with the gate electrode between the source electrode and the drain electrode via the gate insulating layer functions as a channel formation region. In the semiconductor layer 108, a region in contact with the source electrode functions as a source region, and a region in contact with the drain electrode functions as a drain region. In the semiconductor layer 108, the channel formation region is located between the source region and the drain region.

[0166] 5A to 5D show perspective views of the transistor 100 and the insulating layer 110. FIG. 5B shows a cross section taken along dashed line C1-C2 in FIG. 5A. FIG. 5C shows a transparent view of the insulating layer shown in FIG. 5A, with the outline indicated by a dashed line. Similarly, FIG. 5D shows a transparent view of the insulating layer shown in FIG. 5B, with the outline indicated by a dashed line.

[0167] A conductive layer 112a is provided over a substrate 102, an insulating layer 110 is provided over the conductive layer 112a, and a conductive layer 112b is provided over the insulating layer 110. The insulating layer 110 is in contact with the conductive layer 112a and the conductive layer 112b and has a region sandwiched between them. The conductive layer 112a has a region overlapping with the conductive layer 112b via the insulating layer 110. The conductive layer 112b and the insulating layer 110 have an opening 141 that reaches the conductive layer 112a. It can also be said that the conductive layer 112a is exposed in the opening 141. The opening 141 includes an opening in the insulating layer 110 and an opening in the conductive layer 112b. The opening in the insulating layer 110 is provided at a position overlapping with the opening in the conductive layer 112b.

[0168] The semiconductor layer 108 is provided to cover the opening 141. The semiconductor layer 108 has a region in contact with the top surface of the conductive layer 112a, the side surface of the insulating layer 110, and the side surface of the conductive layer 112b in the opening 141. Furthermore, the semiconductor layer 108 preferably has a region in contact with the top surface of the conductive layer 112b. The semiconductor layer 108 has a shape that follows the shapes of the top surface and side surface of the conductive layer 112b, the side surface of the insulating layer 110, and the top surface of the conductive layer 112a.

[0169] The insulating layer 106 is provided to cover the opening 141. The insulating layer 106 is provided over the semiconductor layer 108, the conductive layer 112b, and the insulating layer 110. The insulating layer 106 has a region in contact with the top surface and side surfaces of the semiconductor layer 108, the top surface and side surfaces of the conductive layer 112b, and the top surface of the insulating layer 110. The insulating layer 106 has a shape that follows the top surface and side surfaces of the semiconductor layer 108.

[0170] The conductive layer 104 is provided over the insulating layer 106 and has a region in contact with the top surface of the insulating layer 106. The conductive layer 104 has a region facing the semiconductor layer 108 with the insulating layer 106 interposed therebetween in the opening 141. The conductive layer 104 has a shape that follows the shapes of the top surface and side surfaces of the insulating layer 106.

[0171] 3B and the like show a configuration in which the end of the insulating layer 106 and the end of the conductive layer 104 are aligned or substantially aligned. It can also be said that the top surface shape of the insulating layer 106 is aligned or substantially aligned with the top surface shape of the conductive layer 104. For example, an insulating film to be the insulating layer 106 and a conductive film to be the conductive layer 204 are formed on the insulating film, and a resist mask is formed on the conductive film. Then, by processing the insulating film and the conductive film using the resist mask, the insulating layer 106 and the conductive layer 104 can be formed so that their end portions are aligned or substantially aligned. The insulating layer 106 and the conductive layer 104 can also be processed in different processes. Note that the end of the insulating layer 106 and the end of the conductive layer 104 may not be aligned.

[0172] The transistor 200 includes a conductive layer 204, an insulating layer 206, a semiconductor layer 208, a conductive layer 212a, and a conductive layer 212b. In the transistor 200, the conductive layer 204 functions as a gate electrode, and the insulating layer 206 functions as a gate insulating layer. The conductive layer 212a functions as one of a source electrode and a drain electrode, and the conductive layer 212b functions as the other. In the semiconductor layer 208, a region that overlaps with the gate electrode between the source electrode and the drain electrode via the gate insulating layer functions as a channel formation region. In the semiconductor layer 208, a region in contact with the source electrode functions as a source region, and a region in contact with the drain electrode functions as a drain region. In the semiconductor layer 208, the channel formation region is located between the source region and the drain region.

[0173] A conductive layer 212a is provided over the insulating layer 110, an insulating layer 210 is provided over the conductive layer 212a, and a conductive layer 212b is provided over the insulating layer 210. The insulating layer 210 is in contact with the conductive layer 212a and the conductive layer 212b and has a region sandwiched between them. The conductive layer 212a has a region overlapping with the conductive layer 212b via the insulating layer 210. The conductive layer 212b and the insulating layer 210 have an opening 241 that reaches the conductive layer 212a. It can also be said that the conductive layer 212a is exposed in the opening 241. The opening 241 includes an opening in the insulating layer 210 and an opening in the conductive layer 212b. The opening in the insulating layer 210 is provided at a position overlapping with the opening in the conductive layer 212b.

[0174] The semiconductor layer 208 is provided to cover the opening 241. The semiconductor layer 208 has regions in contact with the top surface of the conductive layer 212a, the side surface of the insulating layer 210, and the side surface of the conductive layer 212b in the opening 241. Furthermore, the semiconductor layer 208 preferably has a region in contact with the top surface of the conductive layer 212b. The semiconductor layer 208 has a shape that follows the shapes of the top surface and side surface of the conductive layer 212b, the side surface of the insulating layer 210, and the top surface of the conductive layer 212a.

[0175] The insulating layer 206 is provided to cover the opening 241. The insulating layer 206 is provided over the semiconductor layer 208, the conductive layer 212b, and the insulating layer 210. The insulating layer 206 has a region in contact with the top surface and side surfaces of the semiconductor layer 208, the top surface and side surfaces of the conductive layer 212b, and the top surface of the insulating layer 210. The insulating layer 206 has a shape that follows the shapes of the top surface of the insulating layer 210, the top surface and side surfaces of the conductive layer 212b, the top surface and side surfaces of the semiconductor layer 208, and the top surface of the conductive layer 212a.

[0176] The conductive layer 204 is provided over the insulating layer 206 and has a region in contact with the top surface of the insulating layer 206. The conductive layer 204 has a region facing the semiconductor layer 208 with the insulating layer 206 interposed therebetween in the opening 241. The conductive layer 204 has a shape that follows the shape of the top surface of the insulating layer 206.

[0177] 3B and the like show a structure in which the end portions of the insulating layer 206 and the conductive layer 204 do not coincide with each other, but one embodiment of the present invention is not limited to this. The end portions of the insulating layer 206 and the conductive layer 204 may coincide with each other or substantially coincide with each other (see the insulating layer 106 and the conductive layer 104).

[0178] 3B and other figures illustrate a structure in which the conductive layer 112b and the conductive layer 212a are provided in contact with the top surface of the insulating layer 110. The conductive layer 112b and the conductive layer 212a can be formed using the same material and in the same process. This simplifies the process and reduces manufacturing costs. For example, the conductive layer 112b and the conductive layer 212a can be formed by depositing a conductive film on the insulating layer 110 or an insulating film that will become the insulating layer 110 and processing the conductive film. Note that the conductive layer 112b and the conductive layer 212a can be formed in different processes. This allows different materials to be used for the conductive layer 112b and the conductive layer 212a, thereby broadening the range of materials to be used for the conductive layer 112b and the conductive layer 212a. The insulating layer 210 is provided to cover the conductive layer 112b, the conductive layer 212a, the semiconductor layer 108, the insulating layer 106, the conductive layer 104, and the insulating layer 110.

[0179] The transistor 200 has a structure similar to that of the transistor 100. The conductive layer 204, the insulating layer 206, the semiconductor layer 208, the conductive layer 212a, and the conductive layer 212b included in the transistor 200 correspond to the conductive layer 104, the insulating layer 106, the semiconductor layer 108, the conductive layer 112a, and the conductive layer 112b included in the transistor 100. The insulating layer 210 and the opening 241 correspond to the insulating layer 110 and the opening 141. For perspective views of the transistor 200 and the insulating layer 210, refer to the perspective views of the transistor 100 and the insulating layer 110 shown in FIGS. 5A to 5D .

[0180] An insulating layer 218 is provided over the transistor 200. The insulating layer 218 functions as a protective layer for the semiconductor device 80.

[0181] In the transistor 100, the source electrode and the drain electrode are located at different heights relative to the surface where the transistor 100 is formed (here, the surface of the substrate 102), and a drain current flows in a direction perpendicular or approximately perpendicular to the surface of the substrate 102. In the transistor 100, the drain current can also be said to flow vertically. Similarly, in the transistor 200, the drain current flows in a direction perpendicular or approximately perpendicular to the surface where the transistor 100 is formed (here, the surface of the insulating layer 110). Therefore, the transistors 100 and 200 can also be called VFETs (Vertical Field Effect Transistors), vertical transistors, vertical channel transistors, vertical channel transistors, etc. Furthermore, the conductive layer 112a can be called the lower electrode of the transistor 100, and the conductive layer 112b can be called the upper electrode. The conductive layer 212a can be called the lower electrode of the transistor 200, and the conductive layer 212b can be called the upper electrode. In a VFET, the source electrode, the semiconductor layer, and the drain electrode can be provided in an overlapping manner, and therefore the occupied area can be significantly reduced compared to a so-called planar type transistor in which the semiconductor layer is arranged in a plane.

[0182] The channel length of the transistor 100 can be controlled by the thickness of the insulating layer 110 provided between the conductive layer 112a and the conductive layer 112b. Similarly, the channel length of the transistor 200 can be controlled by the thickness of the insulating layer 210 provided between the conductive layer 212a and the conductive layer 212b. Therefore, a transistor having a channel length shorter than the minimum exposure dimension of an exposure apparatus used to manufacture the transistor can be manufactured with high precision. Furthermore, the characteristic variation among multiple transistors is also reduced. This stabilizes the operation of the semiconductor device 80, thereby improving its reliability. Furthermore, reduced characteristic variation of transistors increases the degree of freedom in circuit design, allowing the operating voltage of the semiconductor device to be lowered. This reduces the power consumption of the semiconductor device.

[0183] 1B to 2C, the transistor 100 can be applied to the transistor 20 and the transistor 20A, and the transistor 200 can be applied to the transistor 30 and the transistor 30A. Note that the layer 21 shown in FIGS. 1B to 2C includes the transistor 100 and the insulating layer 110, and the layer 31 includes the transistor 200, the insulating layer 210, and the insulating layer 218.

[0184] The semiconductor layer 108 and the semiconductor layer 208 are preferably made of a metal oxide. The semiconductor layer 108 and the semiconductor layer 208 are preferably made of a metal oxide having a high indium content. For the semiconductor layer 108, the above description of the first semiconductor layer can be referred to. For the semiconductor layer 208, the above description of the second semiconductor layer can be referred to. By using a metal oxide having a high indium content for the semiconductor layer of a transistor having a short channel length, the on-state current can be further increased. Therefore, a semiconductor device that operates at high speed can be obtained. Furthermore, since a large on-state current can be obtained even with a small channel width, the area occupied by the transistor can be further reduced. Therefore, the area occupied by the semiconductor device can be further reduced.

[0185] The indium content in the semiconductor layer 108 is preferably higher than the indium content in the semiconductor layer 208. For example, a polycrystalline indium oxide film or a single-crystalline indium oxide film is preferably used as the semiconductor layer 108. It is preferable to use an indium gallium zinc oxide (In—Ga—Zn oxide) film with a CAAC structure or an indium tin zinc oxide (In—Sn—Zn oxide) film with an nc structure as the semiconductor layer 208.

[0186] 2D , the transistor 100 can be applied to the transistor 30 and the transistor 30A, and the transistor 200 can be applied to the transistor 20 and the transistor 20A. The semiconductor layer 108 can be described in the second semiconductor layer. The semiconductor layer 208 can be described in the first semiconductor layer. The layer 31 shown in FIGS. 1B to 2C includes the transistor 100 and the insulating layer 110, and the layer 21 includes the transistor 200, the insulating layer 210, and the insulating layer 218.

[0187] The structure of the semiconductor device 80 will be described in detail. Note that the following description will be given taking the conductive layer 104, the insulating layer 106, the semiconductor layer 108, the conductive layer 112a, the conductive layer 112b, the insulating layer 110, and the opening 141 as examples, and descriptions of the conductive layer 204, the insulating layer 206, the semiconductor layer 208, the conductive layer 212a, the conductive layer 212b, the insulating layer 210, and the opening 241 may be omitted. For the conductive layer 204, the insulating layer 206, the semiconductor layer 208, the conductive layer 212a, the conductive layer 212b, the insulating layer 210, and the opening 241, the descriptions of the conductive layer 104, the insulating layer 106, the semiconductor layer 108, the conductive layer 112a, the conductive layer 112b, the insulating layer 110, and the opening 141 can be referred to.

[0188] The insulating layer 110 and the insulating layer 210 can each be an inorganic insulating layer or an organic insulating layer, or both. Examples of materials that can be used for the organic insulating layer include acrylic resin and polyimide resin. Preferably, the insulating layer 110 and the insulating layer 210 each have one or more inorganic insulating layers. Examples of materials that can be used for the inorganic insulating layer include oxides, nitrides, oxynitrides, and nitride oxides. Examples of oxides include silicon oxide, aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, tantalum oxide, cerium oxide, gallium zinc oxide, and hafnium aluminate. Examples of nitrides include silicon nitride and aluminum nitride. Examples of oxynitrides include silicon oxynitride, aluminum oxynitride, gallium oxynitride, yttrium oxynitride, and hafnium oxynitride. Examples of nitride oxides include silicon nitride oxide and aluminum nitride oxide.

[0189] In this specification and the like, an oxynitride refers to a material having a composition in which oxygen is contained in a larger amount than nitrogen, and a nitride oxide refers to a material having a composition in which nitrogen is contained in a larger amount than oxygen.

[0190] The insulating layer 110 has a region in contact with the semiconductor layer 108. When a metal oxide is used for the semiconductor layer 108, at least a part of the region of the insulating layer 110 in contact with the semiconductor layer 108 preferably contains oxygen in order to improve the interface characteristics between the semiconductor layer 108 and the insulating layer 110. Specifically, the region of the insulating layer 110 in contact with the channel formation region of the semiconductor layer 108 preferably contains oxygen. One or more of an oxide and an oxynitride can be suitably used for the region of the insulating layer 110 in contact with the channel formation region of the semiconductor layer 108.

[0191] When a metal oxide is used for the semiconductor layer 108, it is preferable that at least a part of the region of the insulating layer 110 in contact with the semiconductor layer 108 releases oxygen when heat is applied. As a result, oxygen is supplied from the insulating layer 110 to the semiconductor layer 108, and oxygen vacancies (V Ｏ ) and V Ｏ H can be reduced.

[0192] Since the transistor 200 is formed after the semiconductor layer 108 is formed, oxygen vacancies (V Ｏ However, oxygen vacancies (V Ｏ ) and V Ｏ The increase in H can be suppressed.

[0193] Here, since the indium oxide film has high oxygen diffusivity, oxygen supplied from the insulating layer 110 causes oxygen vacancies (V Ｏ ) and V Ｏ H can be reduced more efficiently. That is, by using indium oxide for the semiconductor layer 108, the transistor 100 can have high reliability against heat. In addition, indium oxide can be suitably used for the semiconductor layer 108 formed before the transistor 200 is formed.

[0194] By increasing the thickness of the channel formation region of the semiconductor layer, the on-state current of the transistor can be increased. However, if the thickness of the semiconductor layer is too thick, oxygen vacancies (V Ｏ ) and V ＯThe amount of H increases. This may result in a transistor having normally-on characteristics. Furthermore, reliability may also decrease. In FIG. 3B , the thickness T108 of the channel formation region of the semiconductor layer 108 is indicated by a solid arrow, and the thickness T208 of the channel formation region of the semiconductor layer 208 is indicated by a solid arrow. The thickness T108 may be the shortest distance between the side surface of the insulating layer 110 and the side surface of the semiconductor layer 108 in a cross-sectional view. Specifically, the thickness T108 may be the thickness of the semiconductor layer 108 at the midpoint between the height of the top surface and the height of the bottom surface of the insulating layer 110. The same applies to the thickness T208.

[0195] When a metal oxide with a high indium content is used for the semiconductor layer, if the thickness of the semiconductor layer is large, oxygen deficiency (V Ｏ ) and V Ｏ The amount of H increases, which may cause the transistor to have normally-on characteristics. In such a case, it is preferable to reduce the thickness of the semiconductor layer. When a metal oxide with a high indium content is used for the semiconductor layer 108 and the semiconductor layer 208, the thicknesses T108 and T208 are preferably 1 nm to 50 nm, more preferably 1 nm to 40 nm, even more preferably 1 nm to 30 nm, even more preferably 1 nm to 20 nm, and even more preferably 1 nm to 10 nm. By setting the thicknesses T108 and T208 within the above ranges, the transistor 100 and the transistor 200 can have favorable electrical characteristics and high reliability. Note that the thicknesses T108 and T208 are not limited to the above ranges. Note that although FIG. 3B and the like show a structure in which the thicknesses T108 and T208 are equal, one embodiment of the present invention is not limited thereto. The thicknesses T108 and T208 may be different from each other.

[0196] When a metal oxide having a low indium content is used for the semiconductor layer, the thickness of the semiconductor layer can be increased. Increasing the thickness of the semiconductor layer can increase the on-state current of the transistor. For example, when a metal oxide having a lower indium content than the semiconductor layer 108 is used for the semiconductor layer 208, as shown in FIG. 6, the thickness T208 is preferably thicker than the thickness T108. This allows the transistor 100 and the transistor 200 to have good electrical characteristics. The thickness T208 is preferably 1 nm to 50 nm, more preferably 5 nm to 50 nm, even more preferably 10 nm to 50 nm, even more preferably 10 nm to 40 nm, and even more preferably 20 nm to 40 nm. By setting the thickness T208 within the above range, the transistor 200 can have good electrical characteristics and high reliability. Note that the thickness T208 is not limited to the above range. The thickness T108 may be the same as or thicker than the thickness T208.

[0197] The conductive layers 112a, 112b, and 104 can each function as wirings, and the transistor 100 can be provided in a region where these wirings overlap. The same applies to the transistor 200. That is, in a circuit including the transistor 100, the transistor 200, and a wiring, the areas occupied by the transistor 100, the transistor 200, and the wiring can be reduced. Therefore, the area occupied by the circuit can be reduced, and a small-sized semiconductor device can be obtained. Furthermore, when the semiconductor device is applied to a pixel circuit of a display device, the area occupied by the pixel circuit can be reduced, and a high-resolution display device can be obtained. Furthermore, for example, when the semiconductor device of one embodiment of the present invention is applied to a driver circuit of a display device (e.g., one or both of a gate line driver circuit and a source line driver circuit), the area occupied by the driver circuit can be reduced, and a display device with a narrow frame can be obtained.

[0198] 3B and the like show an example in which the semiconductor layer 108, the insulating layer 106, and the conductive layer 104 cover the opening 141, and the semiconductor layer 208, the insulating layer 206, and the conductive layer 204 cover the opening 241; however, one embodiment of the present invention is not limited to this. A structure can be used in which a step is formed between the insulating layer 110 and the conductive layer 112b and the conductive layer 112a, and the semiconductor layer 108, the insulating layer 106, and the conductive layer 104 are provided along the step. Similarly, a structure can be used in which a step is formed between the insulating layer 210 and the conductive layer 212b and the conductive layer 212a, and the semiconductor layer 208, the insulating layer 206, and the conductive layer 204 are provided along the step.

[0199] [Insulating Layer 110, Insulating Layer 210] The insulating layer 110 and the insulating layer 210 each preferably have a stacked structure. Figure 3B and other figures show an example in which the insulating layer 110 includes an insulating layer 110a, an insulating layer 110b on the insulating layer 110a, and an insulating layer 110c on the insulating layer 110b, and the insulating layer 210 includes an insulating layer 210a, an insulating layer 210b on the insulating layer 210a, and an insulating layer 210c on the insulating layer 210b. The insulating layers 110a, 110b, 110c, 210a, 210b, and 210c can each be made of the materials listed for the insulating layer 110.

[0200] A region of the semiconductor layer 108 in contact with the insulating layer 110b functions as a channel formation region. The insulating layer 110b preferably contains oxygen and is preferably made of one or more of the above-described oxides and oxynitrides. Specifically, the insulating layer 110b can be made of silicon oxide, silicon oxynitride, or both.

[0201] It is more preferable to use a material that releases oxygen when heat is applied to the insulating layer 110b. When heat is applied during the manufacturing process of the semiconductor device 80, the insulating layer 110b releases oxygen, which allows oxygen to be supplied to the semiconductor layer 108. By supplying oxygen from the insulating layer 110b to the semiconductor layer 108, particularly to the channel formation region, oxygen vacancies (V Ｏ ) is repaired, and oxygen vacancies (V Ｏ ) can be reduced. ＯH can be reduced. Therefore, a highly reliable transistor can be obtained that exhibits favorable electrical characteristics.

[0202] For example, oxygen can be supplied to the insulating layer 110b by heat treatment in an oxygen-containing atmosphere or plasma treatment in an oxygen-containing atmosphere. Alternatively, oxygen can be supplied to the insulating layer 110b by forming a film on the top surface of the insulating layer 110b by a sputtering method in an oxygen-containing atmosphere. Then, the film can be removed.

[0203] The insulating layer 110b is preferably formed by a sputtering method or a PECVD method. In particular, when the insulating layer 110b is formed by a method that does not use a gas containing a hydrogen element (e.g., hydrogen gas or ammonia gas) as a deposition gas, the film can have an extremely low hydrogen content. The sputtering method is particularly suitable for forming the insulating layer 110b. This can suppress the supply of hydrogen to the channel formation region, thereby stabilizing the electrical characteristics of the transistor 100.

[0204] The insulating layer 110a is provided between the insulating layer 110b and the conductive layer 112a. The insulating layer 110c is provided between the insulating layer 110b and the conductive layer 112b. The insulating layer 110a and the insulating layer 110c preferably release small amounts of impurities (e.g., water and hydrogen) from themselves. Furthermore, the insulating layer 110a and the insulating layer 110c preferably are impermeable to substances (e.g., atoms, molecules, and ions). The insulating layer 110a and the insulating layer 110c can also be said to function as barrier films. Specifically, the insulating layer 110a and the insulating layer 110c preferably are impermeable to impurities. This can prevent impurities contained in the insulating layer 110a and the insulating layer 110c from diffusing into the channel formation region. Therefore, a highly reliable transistor can be obtained, exhibiting favorable electrical characteristics.

[0205] In this specification and the like, a barrier film refers to a film having barrier properties. The barrier properties refer to one or both of a function of making it difficult for a target substance to diffuse and thereby suppressing the substance from permeating the film (also referred to as low permeability) and a function of capturing or fixing the substance (also referred to as gettering). For example, an insulating layer having barrier properties can be referred to as a barrier insulating layer.

[0206] The barrier film can be formed using, for example, one or more of an oxide containing one or both of aluminum and hafnium, an oxide containing magnesium, an oxide containing gallium, a nitride containing silicon, and a nitride oxide containing silicon. Typically, the barrier film can be formed using, for example, one or more of aluminum oxide, hafnium oxide, hafnium aluminate, magnesium oxide, gallium oxide, gallium zinc oxide, silicon nitride, and silicon nitride oxide. The barrier film included in the insulating layer 106 can be formed using, for example, one or more of an oxide and an oxynitride, and aluminum oxide can be preferably used.

[0207] The insulating layer 110a and the insulating layer 110c are preferably made of a material that is difficult for oxygen to permeate. This can prevent oxygen contained in the insulating layer 110b from diffusing to the conductive layer 112a through the insulating layer 110a. Similarly, it can prevent oxygen contained in the insulating layer 110b from diffusing to the conductive layer 112b through the insulating layer 110c. This increases the amount of oxygen supplied from the insulating layer 110b to the channel formation region of the semiconductor layer 108, reducing oxygen vacancies (V Ｏ ) and V Ｏ H can be reduced. Therefore, a transistor exhibiting favorable electrical characteristics and high reliability can be obtained. Furthermore, the conductive layer 112a can be prevented from being oxidized by oxygen contained in the insulating layer 110b, which can prevent the electrical resistance of the conductive layer 112a from increasing. Similarly, the conductive layer 112b can be prevented from being oxidized by oxygen contained in the insulating layer 110b, which can prevent the electrical resistance of the conductive layer 112b from increasing. Therefore, a transistor with a large on-state current can be obtained.

[0208] The insulating layer 110a and the insulating layer 110c can each be preferably made of one or more of aluminum oxide, hafnium oxide, hafnium aluminate, magnesium oxide, gallium oxide, gallium zinc oxide, silicon nitride, and silicon nitride oxide. The insulating layer 110a and the insulating layer 110c can be made of the same material. Alternatively, the insulating layer 110a and the insulating layer 110c can be made of different materials.

[0209] By using an oxide or an oxynitride for the insulating layer 110c, oxygen can be supplied to the insulating layer 110b (or the insulating film that becomes the insulating layer 110b) when the insulating layer 110c (or the insulating film that becomes the insulating layer 110c) is formed.

[0210] One or more of the insulating layer 110a, the insulating layer 110b, and the insulating layer 110c can have a stacked structure.

[0211] When the insulating layer 110c has a stacked structure, the layers constituting the insulating layer 110c can be made of the materials listed for the insulating layer 110c. An oxide or an oxynitride can be preferably used for the layer provided on the insulating layer 110b side. More specifically, one or more of aluminum oxide, hafnium oxide, hafnium aluminate, magnesium oxide, gallium oxide, and gallium zinc oxide can be particularly preferably used for the layer provided on the insulating layer 110b side. By using an oxide or an oxynitride for the layer provided on the insulating layer 110b side, oxygen can be supplied to the insulating layer 110b (or the insulating film that will become the insulating layer 110b) during the formation of the layer (or the film that will become the layer), which is preferable. The insulating layer 110c can have a stacked structure, for example, of a first film containing an oxide or an oxynitride and a second film containing a nitride or a nitride oxide on the first film. More specifically, the insulating layer 110c can have a stacked structure of, for example, an aluminum oxide film and a silicon nitride film over the aluminum oxide film.

[0212] For the insulating layer 210a, the insulating layer 210b, and the insulating layer 210c, the description of the insulating layer 110a, the insulating layer 110b, and the insulating layer 110c can be referred to.

[0213] Here, the insulating layer 110 and the insulating layer 210 each have a stacked structure of three layers, but one embodiment of the present invention is not limited to this. The insulating layer 110 preferably includes at least the insulating layer 110b. A structure without one or more of the insulating layer 110a and the insulating layer 110c is also possible. For example, the insulating layer 110 can have a single layer structure or a stacked structure of two or four or more layers. The same applies to the insulating layer 210.

[0214] [Opening 141, Opening 241] The top surface shapes of openings 141 and 241 are not limited and may be, for example, a circle, ellipse, triangle, quadrangle (including rectangle, rhombus, and square), pentagon, or other polygonal shapes, or shapes with rounded corners. The polygon may be either a concave polygon (a polygon with at least one interior angle exceeding 180 degrees) or a convex polygon (a polygon with all interior angles less than 180 degrees). As shown in FIG. 3A and other figures, the top surface shapes of openings 141 and 241 are preferably circular. By making the top surface shapes of the openings circular, processing accuracy during formation of the openings can be improved, allowing for the formation of openings of finer sizes. Note that, in this specification, "circular" does not necessarily mean a perfect circle. Furthermore, the top surface shapes of openings 141 and opening 241 may be different.

[0215] In this specification and the like, the top surface shape of opening 141 refers to the shape of the top surface end portion of insulating layer 110 on the opening 141 side. Also, the top surface shape of opening 241 refers to the shape of the top surface end portion of insulating layer 210 on the opening 241 side.

[0216] The channel lengths and channel widths of the transistor 100 and the transistor 200 will be described with reference to FIGS. 7A and 7B. FIG. 7A is a top view of the semiconductor device 80, and FIG. 7B is a cross-sectional view. Here, the region of the semiconductor layer 108 in contact with the insulating layer 110b is the channel formation region of the transistor 100, and the region of the semiconductor layer 208 in contact with the insulating layer 210b is the channel formation region of the transistor 200.

[0217] 7B , the thickness T110 of the insulating layer 110b and the thickness T210 of the insulating layer 210b are indicated by double-headed arrows. The thickness T110 can be the shortest distance between the surface on which the insulating layer 110b is to be formed (here, the upper surface of the insulating layer 110a) and the upper surface of the insulating layer 110b in a cross-sectional view. The thickness T210 can be the shortest distance between the surface on which the insulating layer 210b is to be formed (here, the upper surface of the insulating layer 210a) and the upper surface of the insulating layer 210b in a cross-sectional view.

[0218] 7B , the channel length L100 of the transistor 100 and the channel length L200 of the transistor 200 are indicated by double-headed arrows. The channel length L100 corresponds to the length of the side surface of the insulating layer 110b on the opening 141 side in a cross-sectional view. That is, the channel length L100 is determined by the thickness T110 and the angle θ110 between the side surface of the insulating layer 110b on the opening 141 side and the surface on which the insulating layer 110b is to be formed (here, the upper surface of the insulating layer 110a). Similarly, the channel length L200 corresponds to the length of the side surface of the insulating layer 210b on the opening 241 side in a cross-sectional view and is determined by the thickness T210 and the angle θ210 between the side surface of the insulating layer 210b on the opening 241 side and the surface on which the insulating layer 210b is to be formed (here, the upper surface of the insulating layer 210a). Therefore, the channel lengths L100 and L200 can be set to values ​​smaller than the minimum exposure dimension of the exposure tool, thereby realizing a transistor with a very small size. Specifically, it is possible to realize a transistor with an extremely short channel length that could not be realized with conventional exposure tools used in the mass production of flat panel displays (e.g., minimum dimensions of approximately 2 μm or 1.5 μm). Furthermore, it is possible to realize a transistor with a channel length of less than 10 nm without using the extremely expensive exposure tools used in cutting-edge LSI technology.

[0219] The channel length L100 and the channel length L200 may each be, for example, 5 nm or more, 7 nm or more, or 10 nm or more, and may be less than 3 μm, 2.5 μm or less, 2 μm or less, 1.5 μm or less, 1.2 μm or less, 1 μm or less, 500 nm or less, 300 nm or less, 200 nm or less, 100 nm or less, 50 nm or less, 30 nm or less, or 20 nm or less. For example, the channel length L100 and the channel length L200 may each be 100 nm or more and 1 μm or less.

[0220] By shortening the channel length, the on-state current of the transistor can be increased. This allows a circuit capable of high-speed operation to be manufactured. Furthermore, the area occupied by the circuit can be reduced. Therefore, a small-sized semiconductor device can be obtained. For example, when the semiconductor device of one embodiment of the present invention is applied to a large display device or a high-resolution display device, even if the number of wirings is increased, signal delay in each wiring can be reduced, and display unevenness can be suppressed. Furthermore, since the area occupied by the circuit can be reduced, the frame of the display device can be narrowed.

[0221] The channel length L100 can be controlled by adjusting the thickness T110 and the angle θ110. Similarly, the channel length L200 can be controlled by adjusting the thickness T210 and the angle θ210.

[0222] The thickness T110 and the thickness T210 may each be, for example, 5 nm or more, 7 nm or more, or 10 nm or more, and may be less than 3 μm, 2.5 μm or less, 2 μm or less, 1.5 μm or less, 1.2 μm or less, 1 μm or less, 500 nm or less, 300 nm or less, 200 nm or less, 100 nm or less, 50 nm or less, 30 nm or less, or 20 nm or less. Note that, although FIG. 7B and other figures show a configuration in which the thickness T110 and the thickness T210 are equal, one embodiment of the present invention is not limited to this. The thickness T110 and the thickness T210 may be different.

[0223] Although the angles θ110 and θ210 are shown as being less than 90 degrees in FIG. 7B and other drawings, this is not a limitation of one embodiment of the present invention. The angles θ110 and θ210 can be set to 90 degrees or approximately 90 degrees. This allows the channel lengths L100 and L200 to be shortened. Furthermore, although FIG. 7B and other drawings show a configuration in which the angles θ110 and θ210 are equal, this is not a limitation of one embodiment of the present invention. The angles θ110 and θ210 can be set to be different from each other.

[0224] 7B and the like show a cross-sectional view in which the side surface of the insulating layer 110 on the opening 141 side and the side surface of the insulating layer 210 on the opening 241 side are linear, but one embodiment of the present invention is not limited to this. In the cross-sectional view, the side surfaces can be curved. Alternatively, the side surfaces can have both linear and curved regions.

[0225] Although FIG. 7B and other figures illustrate a configuration in which the channel length L100 and the channel length L200 are equal, one embodiment of the present invention is not limited thereto. The channel length L100 and the channel length L200 may be different. By differentiating one or both of the thickness T110 and the angle θ110 from the thickness T210 and the angle θ210, the channel length L100 and the channel length L200 can be different. The channel length L100 and the channel length L200 can be different depending on the on-state current and saturation required for the transistor 100 and the transistor 200. By shortening the channel length, the on-state current of the transistor can be increased. On the other hand, by increasing the channel length, the saturation of the transistor can be improved. For example, by making the thickness T210 thicker than the thickness T110, the channel length L200 can be longer than the channel length L100. This can improve the saturation of the transistor 200.

[0226] 7A and 7B , the width D141 of the opening 141, the channel width W100 of the transistor 100, the width D241 of the opening 241, and the channel width W200 of the transistor 200 are each indicated by a double-headed arrow. FIGS. 7A and 7B show an example in which the top surface shape of the opening 141 is circular. In this case, the width D141 corresponds to the diameter of the circle, and the channel width W100 is the length of the circumference of the circle. That is, the channel width W100 is π×D141. Thus, when the top surface shape of the opening 141 is circular, a transistor with a smaller channel width W100 can be realized compared to other shapes. Similarly, the channel width W200 is π×D241.

[0227] The width D141 of the opening 141 may vary in the depth direction. The width D141 of the opening 141 may be, for example, the average value of the diameter at the highest point, the diameter at the lowest point, and the diameter at the midpoint between these three values ​​of the insulating layer 110b (or the insulating layer 110) in a cross-sectional view. Alternatively, the diameter of the opening 141 may be, for example, any of the diameter at the highest point, the diameter at the lowest point, or the diameter at the midpoint between these three values ​​of the insulating layer 110b (or the insulating layer 110) in a cross-sectional view. The same applies to the width D241 and the insulating layer 210.

[0228] When the openings 141 and 241 are formed using lithography, the widths D141 and D241 are equal to or greater than the minimum exposure dimension of an exposure device. The widths D141 and D241 can be, for example, 20 nm or greater, 50 nm or greater, 100 nm or greater, 200 nm or greater, 300 nm or greater, 400 nm or greater, or 500 nm or greater, and less than 5 μm, 4.5 μm or less, 4 μm or less, 3.5 μm or less, 3 μm or less, 2.5 μm or less, 2 μm or less, 1.5 μm or less, or 1 μm or less. While FIG. 7B and other figures show a configuration in which the widths D141 and D241 are equal, one embodiment of the present invention is not limited to this. The widths D141 and D241 can be different from each other.

[0229] Note that although the example in which the region of the semiconductor layer 108 in contact with the insulating layer 110b functions as a channel formation region has been described here, one embodiment of the present invention is not limited to this. The region of the semiconductor layer 108 in contact with the insulating layer 110a may also function as a channel formation region. Similarly, the region of the semiconductor layer 108 in contact with the insulating layer 110c may also function as a channel formation region. The same applies to the semiconductor layer 208.

[0230] Although FIG. 7A and other drawings illustrate a configuration in which the channel width W100 and the channel width W200 are equal, one embodiment of the present invention is not limited to this. The channel width W100 and the channel width W200 can be different from each other. The channel width W100 and the channel width W200 can be different from each other by making one or both of the top surface shape and size of the opening 141 different from those of the opening 241. The channel width W100 and the channel width W200 can be different from each other depending on the on-state current required for the transistors 100 and 200. Increasing the channel width can increase the on-state current of the transistor. For example, by making the width D141 larger than the width D241, the channel width W100 can be longer than the channel width W200. This can increase the on-state current of the transistor 100.

[0231] [Insulating Layer 106, Insulating Layer 206] Each of the insulating layer 106 and the insulating layer 206 preferably includes one or more inorganic insulating layers. The materials listed for the insulating layer 110 can be used as materials that can be used for the inorganic insulating layer.

[0232] The insulating layer 106 has a region in contact with the semiconductor layer 108. When a metal oxide is used for the semiconductor layer 108, at least a part of the region of the insulating layer 106 in contact with the semiconductor layer 108 preferably contains oxygen in order to improve the interfacial characteristics between the semiconductor layer 108 and the insulating layer 106. Specifically, the region in contact with the channel formation region of the insulating layer 106 preferably contains oxygen. One or more of an oxide and an oxynitride can be preferably used for the region in contact with the channel formation region of the insulating layer 106. For example, the insulating layer 106 preferably contains silicon and oxygen. Silicon oxide or silicon oxynitride can be preferably used for the insulating layer 106.

[0233] Note that in a miniaturized transistor, a thin gate insulating layer may result in a large leakage current. By using a material with a high relative dielectric constant (also referred to as a high-k material) for the gate insulating layer, a low voltage can be achieved during transistor operation while maintaining the physical film thickness. Examples of high-k materials that can be used for the insulating layer 106 include gallium oxide, hafnium oxide, zirconium oxide, an oxide containing aluminum and hafnium, an oxynitride containing aluminum and hafnium, an oxide containing silicon and hafnium, an oxynitride containing silicon and hafnium, and a nitride containing silicon and hafnium.

[0234] 3B and the like, the insulating layer 106 has a single-layer structure; however, one embodiment of the present invention is not limited to this. The insulating layer 106 can have a stacked structure of two or more layers. When the insulating layer 106 has a stacked structure, the insulating layer on the semiconductor layer 108 side preferably contains oxide or oxynitride. The insulating layer on the semiconductor layer 108 side can preferably be made of, for example, one or more of silicon oxide, silicon oxynitride, and aluminum oxide.

[0235] It is preferable to provide a barrier film in one or more layers constituting the insulating layer 106. By providing the barrier film, it is possible to suppress the metal components contained in the conductive layer 104 from diffusing into the semiconductor layer 108 through the insulating layer 106. Furthermore, it is possible to suppress the oxygen contained in the semiconductor layer 108 from diffusing into the conductive layer 104 through the insulating layer 106. This prevents oxygen deficiency (V Ｏ In addition, it is possible to prevent the conductive layer 104 from being oxidized by oxygen contained in the semiconductor layer 108 and the electrical resistance of the conductive layer 104 from increasing. As a result, a highly reliable transistor with favorable electrical characteristics can be obtained.

[0236] The insulating layer 106 can have, for example, a stacked structure of a silicon oxynitride film and a silicon nitride film over the silicon oxynitride film. Alternatively, the insulating layer 106 can have a stacked structure of a silicon oxynitride film and an aluminum oxide film over the silicon oxynitride film. Alternatively, the insulating layer 106 can have a stacked structure of an aluminum oxide film and a silicon oxynitride film over the aluminum oxide film. Alternatively, the insulating layer 106 can have a stacked structure of an aluminum oxide film and a silicon nitride film over the aluminum oxide film. Although an example in which the insulating layer 106 has a two-layer structure is shown here, one embodiment of the present invention is not limited to this. The insulating layer 106 can also have a stacked structure of three or more layers.

[0237] As shown in FIG. 3B and other figures, it is preferable that the insulating layer 106 does not extend to the opening 241 and that the insulating layer 106 does not have a region in contact with the semiconductor layer 208. Here, if the insulating layer 106 has a region in contact with the semiconductor layer 208, oxygen contained in the insulating layer 106 may diffuse into that region, or oxygen contained in the semiconductor layer 108 may diffuse into that region via the insulating layer 106, thereby increasing the electrical resistance of that region. This may increase the electrical resistance of a portion of one of the source and drain regions of the semiconductor layer 208, potentially reducing the on-current. Therefore, it is preferable that the insulating layer 106 does not have a region in contact with the semiconductor layer 208.

[0238] As shown in Figures 8A and 8B, a configuration may be adopted in which the end of the insulating layer 106 does not coincide with the end of the conductive layer 104. Figure 8A is a cross-sectional view of the cut surface taken along dashed dotted line A1-A2 shown in Figure 3A, and Figure 8B is a cross-sectional view of the cut surface taken along dashed dotted line B1-B2. For a cross-sectional view of the cut surface taken along dashed dotted line B3-B4, see Figure 4B. As shown in Figures 8A and 8B, it is preferable that the insulating layer 106 have a region that protrudes beyond the end of the conductive layer 104.

[0239] Note that the insulating layer 106 may extend to the opening 241 and have a region in contact with the semiconductor layer 208 .

[0240] [Conductive Layer 112a, Conductive Layer 112b, Conductive Layer 104, Conductive Layer 212a, Conductive Layer 212b, Conductive Layer 204] The conductive layers 112a, 112b, 104, 212a, 212b, and 204 can each have a single-layer structure or a stacked structure of two or more layers. Materials that can be used for these conductive layers include, for example, one or more of chromium, copper, aluminum, gold, silver, zinc, tantalum, titanium, tungsten, manganese, nickel, iron, cobalt, molybdenum, and niobium, as well as alloys containing one or more of the aforementioned metals. For these conductive layers, conductive materials with low electrical resistivity, including one or more of copper, silver, gold, and aluminum, can be preferably used. Copper and aluminum are particularly preferred due to their excellent mass productivity.

[0241] The conductive layer 112a, the conductive layer 112b, the conductive layer 104, the conductive layer 212a, the conductive layer 212b, and the conductive layer 204 can each be formed using a conductive metal oxide (also referred to as an oxide conductor (OC)). Examples of oxide conductors include indium oxide, zinc oxide, ITO, In—Zn oxide, In—W oxide, In—W—Zn oxide, In—Ti oxide, In—Ti—Sn oxide, ITSO, zinc oxide to which gallium is added, and In—Ga—Zn oxide. In particular, an oxide conductor containing indium is preferable because of its high conductivity.

[0242] When oxygen vacancies are formed in a metal oxide having semiconductor properties and hydrogen is added to the oxygen vacancies, a donor level is formed near the conduction band. As a result, the metal oxide becomes electrically conductive, and the conductivity of the metal oxide increases. The metal oxide that has become electrically conductive can be called an oxide conductor.

[0243] The conductive layer 112a, the conductive layer 112b, the conductive layer 104, the conductive layer 212a, the conductive layer 212b, and the conductive layer 204 can each have a stacked structure of a conductive film containing the oxide conductor (metal oxide) and a conductive film containing a metal or an alloy. By using a conductive film containing a metal or an alloy, wiring resistance can be reduced.

[0244] A nitride conductor may also be used for each of the conductive layer 112a, the conductive layer 112b, the conductive layer 104, the conductive layer 212a, the conductive layer 212b, and the conductive layer 204. Examples of nitride conductors include tantalum nitride and titanium nitride.

[0245] A Cu-X alloy film (X is Mn, Ni, Cr, Fe, Co, Mo, Ta, or Ti) can also be applied to each of the conductive layer 112a, the conductive layer 112b, the conductive layer 104, the conductive layer 212a, the conductive layer 212b, and the conductive layer 204. By using a Cu-X alloy film, it can be processed by wet etching, thereby reducing manufacturing costs.

[0246] Note that the conductive layer 112a, the conductive layer 112b, the conductive layer 104, the conductive layer 212a, the conductive layer 212b, and the conductive layer 204 can be formed using the same material, or at least one of them can be formed using a different material.

[0247] The conductive layer 112a and the conductive layer 112b each have a region in contact with the semiconductor layer 108. When a metal oxide is used for the semiconductor layer 108, if a metal that is easily oxidized (e.g., aluminum) is used for the conductive layer 112a or the conductive layer 112b, an insulating oxide (e.g., aluminum oxide) may be formed between the conductive layer 112a or the conductive layer 112b and the semiconductor layer 108, preventing electrical conduction therebetween. Therefore, it is preferable to use a conductive material that is not easily oxidized or a conductive material that maintains low electrical resistance even when oxidized for the conductive layer 112a or the conductive layer 112b. The same applies to the semiconductor layer 208, the conductive layer 212a, and the conductive layer 212b. An oxide conductor or a nitride conductor can be used for the conductive layer 112a, the conductive layer 112b, the conductive layer 212a, and the conductive layer 212b, respectively. The above description can be referred to for the oxide conductor and the nitride conductor. For example, the conductive layers 112a, 112b, 212a, and 212b can be preferably formed using ITO or ITSO.

[0248] The conductive layer 112a, the conductive layer 112b, the conductive layer 212a, and the conductive layer 212b can each be made of, for example, titanium, tantalum nitride, titanium nitride, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, or an oxide containing lanthanum and nickel. These are preferable because they are conductive materials that are difficult to oxidize or materials that maintain low electrical resistance even when oxidized.

[0249] When the conductive layer 112a or the conductive layer 112b has a stacked-layer structure, a conductive material that is not easily oxidized or a conductive material that maintains low electrical resistance even when oxidized is preferably used for at least a layer in contact with the semiconductor layer 108. The same applies to the semiconductor layer 208, the conductive layer 212a, and the conductive layer 212b.

[0250] [Insulating Layer 218] The insulating layer 218 can be an inorganic insulating layer or an organic insulating layer, or both. The insulating layer 218 can be made of any of the materials listed for the insulating layer 110. The insulating layer 218 preferably includes one or more inorganic insulating layers.

[0251] The insulating layer 218 preferably functions as a barrier film. This effectively prevents impurities (e.g., water and hydrogen) from diffusing into the transistor from the outside, thereby improving the reliability of the semiconductor device. Furthermore, oxygen contained in the semiconductor layer 208 can be prevented from being desorbed above the insulating layer 218 through the insulating layer 206. For example, one or both of silicon nitride and silicon nitride oxide can be suitably used as the insulating layer 218. The above description of the barrier film can be referred to. Furthermore, by using an organic insulating layer for the insulating layer 218, unevenness due to the transistor 100 and the transistor 200 can be reduced. This improves the coverage of a layer (e.g., a layer included in a display element) provided over the insulating layer 218, thereby preventing defects such as discontinuities or voids in the layer.

[0252] [Substrate 102] The material of the substrate 102 is not particularly limited, but it must have at least heat resistance sufficient to withstand subsequent heat treatment. For example, a single crystal semiconductor substrate made of silicon or silicon carbide, a polycrystalline semiconductor substrate, a compound semiconductor substrate such as silicon germanium, an SOI substrate, a glass substrate, a quartz substrate, a sapphire substrate, a ceramic substrate, or a resin substrate can be used as the substrate 102. Alternatively, a substrate on which a semiconductor element is provided can be used as the substrate 102. Alternatively, a substrate on which an insulating film is formed on the surface can be used as the substrate 102. The shape of the substrate 102 is not particularly limited, and can be, for example, circular or rectangular.

[0253] A flexible substrate can be used as the substrate 102, and the transistor 200 and the like can be formed directly on the flexible substrate. Alternatively, a peeling layer can be provided between the substrate 102 and the transistor 200 and the like. By providing the peeling layer, after a semiconductor device is partially or entirely completed thereon, it can be separated from the substrate 102 and transferred to another substrate. In this case, the transistor 200 and the like can also be transferred to a substrate with low heat resistance or a flexible substrate.

[0254] The following describes a configuration example in which some of the configuration is different from the configuration example 1-1 of the semiconductor device described above. Note that, in the following, descriptions of parts that overlap with the configuration example 1-1 of the semiconductor device may be omitted. Furthermore, in the drawings shown below, parts that have the same function as the configuration example 1-1 of the semiconductor device described above may be hatched with the same pattern and may not be assigned reference numerals.

[0255] 9A to 9C show cross-sectional views of a semiconductor device 80A according to one embodiment of the present invention. For a top view of the semiconductor device 80A, see FIG. 3A. FIG. 9A is a cross-sectional view of the cut surface taken along dashed dotted line A1-A2 in FIG. 3A , FIG. 9B is a cross-sectional view of the cut surface taken along dashed dotted line B1-B2, and FIG. 9C is a cross-sectional view of the cut surface taken along dashed dotted line B3-B4.

[0256] The semiconductor device 80A includes a transistor 100, a transistor 200, an insulating layer 110, and an insulating layer 210. The semiconductor device 80A differs from the semiconductor device 80 shown in FIG. 3B and the like mainly in that a conductive layer 212a is provided in contact with the upper surface of the insulating layer 106.

[0257] The insulating layer 106 is provided over the semiconductor layer 108, the conductive layer 112b, and the insulating layer 110, the conductive layer 104 and the conductive layer 212a are provided over the insulating layer 106, and the insulating layer 210 is provided over the conductive layer 104 and the conductive layer 212a.

[0258] The conductive layer 104 and the conductive layer 212a are provided in contact with the top surface of the insulating layer 106. The conductive layer 104 and the conductive layer 212a can be formed using the same material and in the same process. This can simplify the process and reduce manufacturing costs. For example, the conductive layer 104 and the conductive layer 212a can be formed by forming a conductive film over the insulating layer 106 and processing the conductive film.

[0259] The insulating layer 106 is provided between the conductive layer 112b and the conductive layer 212a and the conductive layer 104. That is, the conductive layer 112b is formed in a different process from the conductive layer 212a and the conductive layer 104. This allows different materials to be used for the conductive layer 112b, the conductive layer 212a, and the conductive layer 104, thereby widening the range of materials that can be selected for the conductive layer 112b, the conductive layer 212a, and the conductive layer 104.

[0260] Note that the conductive layer 104 and the conductive layer 212a can be formed in different steps, which allows different materials to be used for the conductive layer 104 and the conductive layer 212a, thereby widening the range of materials that can be selected for the conductive layer 104 and the conductive layer 212a.

[0261] When the conductive layer 104 and the conductive layer 212a are formed in the same process, it is preferable to use a conductive material that is resistant to oxidation or a conductive material that maintains low electrical resistance even when oxidized for the conductive layer 104 and the conductive layer 212b. An oxide conductor or a nitride conductor can be used for each of the conductive layer 104 and the conductive layer 212b. The above description of oxide conductors and nitride conductors can be referred to. For example, ITO or ITSO can be preferably used for each of the conductive layer 104 and the conductive layer 212a.

[0262] 10A to 10C are cross-sectional views of a semiconductor device 80B according to one embodiment of the present invention. For a top view of the semiconductor device 80B, see FIG. 3A. FIG. 10A is a cross-sectional view of the cut surface taken along dashed dotted line A1-A2 in FIG. 3A , FIG. 10B is a cross-sectional view of the cut surface taken along dashed dotted line B1-B2, and FIG. 10C is a cross-sectional view of the cut surface taken along dashed dotted line B3-B4.

[0263] The semiconductor device 80B includes a transistor 100, a transistor 200, an insulating layer 110, an insulating layer 210, and an insulating layer 150. The semiconductor device 80B differs from the semiconductor device 80 shown in FIG. 3B etc. mainly in that the semiconductor device 80B includes the insulating layer 150.

[0264] The insulating layer 150 is provided between the transistor 100 and the transistor 200. The insulating layer 150 is provided over the conductive layer 104 and the insulating layer 106, the conductive layer 212a is provided over the insulating layer 150, and the insulating layer 210 is provided over the insulating layer 150 and the conductive layer 212a.

[0265] The insulating layer 150 can be an inorganic insulating layer or an organic insulating layer, or both. The insulating layer 150 can be made of the materials listed for the insulating layer 110. The insulating layer 150 preferably functions as, for example, a barrier film. When the insulating layer 150 functions as a barrier film, oxygen contained in the insulating layer 110 and oxygen contained in the semiconductor layer 108 can be prevented from being desorbed above the insulating layer 150. Furthermore, oxygen contained in the insulating layer 210 and oxygen contained in the semiconductor layer 208 can be prevented from being desorbed below the insulating layer 150. This prevents oxygen deficiency (V Ｏ ) and V Ｏ The insulating layer 150 can be formed by using, for example, one or both of silicon nitride and silicon nitride oxide. Furthermore, by using an organic insulating layer for the insulating layer 150, unevenness caused by the transistor 100 can be reduced. This can improve the coverage of layers (e.g., the conductive layer 212a and the insulating layer 210) provided on the insulating layer 150, and can prevent defects such as discontinuities or voids from occurring in the layers.

[0266] A conductive layer 212a is provided in contact with the upper surface of the insulating layer 150. The conductive layer 212a can be formed in a process different from that for the conductive layer 104 and the conductive layer 112b. This allows the conductive layer 212a, the conductive layer 104, and the conductive layer 112b to be formed using different materials, thereby broadening the range of materials to be used for the conductive layer 212a, the conductive layer 104, and the conductive layer 112b. Furthermore, the conductive layer 104 and the conductive layer 212a are insulated from each other by the insulating layer 150. Therefore, a structure can be adopted in which the conductive layer 212a has a region overlapping with the conductive layer 104. This increases the degree of freedom in layout and reduces the area occupied by the semiconductor device.

[0267] 11A to 11C are cross-sectional views of a semiconductor device 82 according to one embodiment of the present invention. For a top view of the semiconductor device 82, see FIG. 3A. FIG. 11A is a cross-sectional view taken along dashed dotted line A1-A2 in FIG. 3A , FIG. 11B is a cross-sectional view taken along dashed dotted line B1-B2, and FIG. 11C is a cross-sectional view taken along dashed dotted line B3-B4.

[0268] The semiconductor device 82 includes a transistor 100, a transistor 200, and an insulating layer 110. The semiconductor device 82 differs from the semiconductor device 80 shown in FIG.

[0269] 2E to 2G , the semiconductor device 82 can be used in the pixel circuit 15 and the circuit portion 64. The transistor 100 can be applied to, for example, the transistor 20 and the transistor 20A, and the transistor 200 can be applied to the transistor 30 and the transistor 30A. Note that the layer 41 shown in FIGS. 2E to 2G includes the transistor 100, the transistor 200, the insulating layer 110, and the insulating layer 218.

[0270] The transistor 100 and the transistor 200 can be formed over a substrate 102 by sharing some of the steps. A conductive layer 112a and a conductive layer 212a are provided over the substrate 102, an insulating layer 110 is provided over the conductive layer 112a and the conductive layer 212a, and a conductive layer 112b and a conductive layer 212b are provided over the insulating layer 110. The insulating layer 110 has an opening 141 that reaches the conductive layer 112a and an opening 241 that reaches the conductive layer 212a. The conductive layer 212a can be formed in the same step as the conductive layer 112a. The opening 241 can be formed in the same step as the opening 141. The conductive layer 212b can be formed in the same step as the conductive layer 112b.

[0271] The semiconductor layer 108 is provided so as to cover the opening 141, and the semiconductor layer 208 is provided so as to cover the opening 241. The semiconductor layer 208 is preferably made of a different material from the semiconductor layer 108. The semiconductor layer 208 can be formed in a different process from the semiconductor layer 108. For example, the semiconductor layer 208 can be formed after the semiconductor layer 108 is formed. A first metal oxide film is formed so as to cover the opening 141, and the first metal oxide film is processed to form the semiconductor layer 108. Then, a second metal oxide film is formed so as to cover the opening 241, and the second metal oxide film is processed to form the semiconductor layer 208. The order in which the semiconductor layer 108 and the semiconductor layer 208 are formed is not particularly limited, and the semiconductor layer 108 can be formed after the semiconductor layer 208 is formed. Alternatively, the semiconductor layer 108 and the semiconductor layer 208 can be formed using the same material in the same process.

[0272] An insulating layer 106 is provided over the semiconductor layer 108 and the semiconductor layer 208, and a conductive layer 104 and a conductive layer 204 are provided over the insulating layer 106. The conductive layer 104 has a region facing the semiconductor layer 108 with the insulating layer 106 interposed therebetween in an opening 141. The conductive layer 204 has a region facing the semiconductor layer 208 with the insulating layer 106 interposed therebetween in an opening 241. Part of the insulating layer 106 functions as a gate insulating layer for the transistor 100, and the other part functions as a gate insulating layer for the transistor 200.

[0273] By forming components other than the semiconductor layer 108 and the semiconductor layer 208 in the same process, productivity of the semiconductor device can be increased and manufacturing costs can be reduced.

[0274] 3A to 11C show examples in which a VFET is applied to a semiconductor device, but the structure of a transistor that can be applied to a semiconductor device of one embodiment of the present invention is not particularly limited. A planar transistor can be applied to a semiconductor device.

[0275] 12A shows a top view of a semiconductor device 90 according to one embodiment of the present invention. FIG. 12B shows a cross-sectional view of the cut surface taken along dashed dotted line A1-A2 in FIG. 12A , and FIG. 12C shows cross-sectional views of the cut surfaces taken along dashed dotted line B1-B2 and dashed dotted line B3-B4.

[0276] The semiconductor device 90 includes a transistor 300 and a transistor 400 .

[0277] The transistor 300 includes a conductive layer 303 over the substrate 102, an insulating layer 305 over the conductive layer 303, a semiconductor layer 308 over the insulating layer 305, an insulating layer 306 over the semiconductor layer 308, and a conductive layer 304 over the insulating layer 306. The conductive layer 304 has a region overlapping with the semiconductor layer 308 with the insulating layer 306 interposed therebetween. The conductive layer 304 functions as a gate electrode of the transistor 300, and the insulating layer 306 functions as a gate insulating layer. An insulating layer 405 is provided over the conductive layer 304 and the insulating layer 306, an insulating layer 406 is provided over the insulating layer 405, and an insulating layer 218 is provided over the insulating layer 406.

[0278] The semiconductor layer 308 has a region 308P and a region 308Q that do not overlap with the conductive layer 304. In the transistor 300, the region 308P functions as one of the source region and the drain region, and the region 308Q functions as the other of the source region and the drain region. In the semiconductor layer 308, a region that is located between the source region and the drain region and overlaps with the conductive layer 304 with the insulating layer 306 interposed therebetween functions as a channel formation region.

[0279] The insulating layer 306, the insulating layer 405, the insulating layer 406, and the insulating layer 218 have an opening 347a that reaches the region 308P and an opening 347b that reaches the region 308Q. A conductive layer 312a is provided to cover the opening 347a. In the opening 347a, the conductive layer 312a is in contact with the region 308P and connected to the region 308P. A conductive layer 312b is provided to cover the opening 347b. In the opening 347b, the conductive layer 312b is in contact with the region 308Q and connected to the region 308Q. The conductive layer 312a functions as one of the source and drain electrodes of the transistor 300, and the conductive layer 312b functions as the other of the source and drain electrodes.

[0280] The conductive layer 303 has a region facing the conductive layer 304 with the insulating layer 305, the semiconductor layer 308, and the insulating layer 306 interposed therebetween. In the transistor 300, the conductive layer 303 functions as a back gate electrode, and the insulating layer 305 functions as a back gate insulating layer.

[0281] By providing the back gate electrode, the potential on the back gate electrode side (also referred to as the back channel side) of the semiconductor layer 308 is fixed, and the saturation of the Id-Vd characteristics can be improved. Furthermore, by fixing the potential on the back channel side of the semiconductor layer 308, a shift in the threshold voltage can be suppressed. Therefore, a transistor with a small cutoff current can be obtained, and a semiconductor device with low power consumption can be provided.

[0282] The conductive layer 303 preferably has a region that protrudes beyond the end portion of the conductive layer 304. This can enhance the effect (also referred to as electric field shielding effect) that the conductive layer 303 shields an electric field generated outside the transistor and makes it difficult for the electric field generated outside to act on the channel formation region.

[0283] The conductive layer 303 can be connected to the conductive layer 312a or the conductive layer 312b. For example, openings reaching the conductive layer 303 can be formed in the insulating layers 218, 406, 405, 306, and 305, and the conductive layer 312a can be provided to cover the openings, thereby enabling a structure in which the conductive layer 303 and the conductive layer 312a are in contact with each other. The connection between the conductive layer 312a and the conductive layer 303 allows one of the source electrode and the drain electrode and the back gate electrode to have the same potential. For example, when the conductive layer 312a functions as a source electrode, a shift in the threshold voltage of the transistor 300 can be suppressed. Furthermore, the reliability of the transistor 300 can be improved.

[0284] The conductive layer 303 can be connected to the conductive layer 304. For example, openings reaching the conductive layer 303 are provided in the insulating layers 306 and 305, and the conductive layer 304 is provided to cover the openings, so that the conductive layers 303 and 304 are in contact with each other. By connecting the gate electrode and the back gate electrode, the back gate electrode and the gate electrode can have the same potential, and the on-state current of the transistor 300 can be increased.

[0285] Since the conductive layer 303 is formed before the semiconductor layer 308, it is preferable to use a material that can withstand the heat treatment for forming the semiconductor layer 308. The conductive layer 303 is preferably made of a high-melting-point material (for example, tungsten or molybdenum) that has both heat resistance and conductivity. For example, tungsten can be suitably used for the conductive layer 303.

[0286] The insulating layer 305 preferably has a stacked structure. The insulating layer 305 can have a stacked structure of a first insulating layer and a second insulating layer over the first insulating layer. The second insulating layer has a region in contact with the semiconductor layer 308. The second insulating layer in contact with the semiconductor layer 308 preferably contains oxygen. The first insulating layer located on the substrate 102 and conductive layer 303 side preferably functions as a barrier film. By providing a barrier film, it is possible to prevent components (e.g., metals) contained in the substrate 102 and conductive layer 303 from diffusing into the transistors 300 and 400, thereby achieving highly reliable semiconductor devices. For the barrier film, the above description can be referred to. The first insulating layer preferably contains nitrogen. The first insulating layer preferably contains silicon and nitrogen. The second insulating layer preferably contains silicon and nitrogen. For example, silicon nitride can be preferably used for the first insulating layer, and silicon oxynitride can be preferably used for the second insulating layer.

[0287] The transistor 400 includes a conductive layer 403 over the insulating layer 306, an insulating layer 405 over the conductive layer 403, a semiconductor layer 408 over the insulating layer 405, an insulating layer 406 over the semiconductor layer 408, and a conductive layer 404 over the insulating layer 406. The conductive layer 404 has a region overlapping with the semiconductor layer 408 with the insulating layer 406 interposed therebetween. The conductive layer 404 functions as a gate electrode of the transistor 400, and the insulating layer 406 functions as a gate insulating layer. An insulating layer 218 is provided over the conductive layer 404 and the insulating layer 406.

[0288] The semiconductor layer 408 has a region 408P and a region 408Q that do not overlap with the conductive layer 404. In the transistor 400, the region 408P functions as one of the source region and the drain region, and the region 408Q functions as the other of the source region and the drain region. In the semiconductor layer 408, a region that is located between the source region and the drain region and overlaps with the conductive layer 404 with the insulating layer 406 interposed therebetween functions as a channel formation region.

[0289] The insulating layer 406 and the insulating layer 218 have an opening 447a that reaches the region 408P and an opening 447b that reaches the region 408Q. A conductive layer 412a is provided to cover the opening 447a, and a conductive layer 412b is provided to cover the opening 447b. The conductive layer 412a functions as one of the source and drain electrodes of the transistor 400, and the conductive layer 412b functions as the other of the source and drain electrodes.

[0290] The conductive layer 403 has a region facing the conductive layer 404 with the insulating layer 405, the semiconductor layer 408, and the insulating layer 406 interposed therebetween. In the transistor 400, the conductive layer 403 functions as a back gate electrode, and the insulating layer 405 functions as a back gate insulating layer.

[0291] The transistor 400 has a structure similar to that of the transistor 300. The conductive layer 404, the insulating layer 406, the semiconductor layer 408, the insulating layer 405, the conductive layer 403, the conductive layer 412a, and the conductive layer 412b included in the transistor 400 correspond to the conductive layer 304, the insulating layer 306, the semiconductor layer 308, the insulating layer 305, the conductive layer 303, the conductive layer 312a, and the conductive layer 312b included in the transistor 300. The openings 447a and 447b correspond to the openings 347a and 347b.

[0292] The description of the semiconductor layer 108 can be referred to for the semiconductor layer 308, and the description of the semiconductor layer 208 can be referred to for the semiconductor layer 408. The indium content in the semiconductor layer 308 is preferably higher than the indium content in the semiconductor layer 408. For example, a polycrystalline indium oxide film or a single-crystalline indium oxide film is preferably used as the semiconductor layer 308. An indium tin zinc oxide film or an indium gallium zinc oxide film having a CAAC structure or an nc structure is preferably used as the semiconductor layer 408.

[0293] The thickness T308 of the channel formation region of the semiconductor layer 308 is preferably within the range of the thickness T108 described above. The thickness T408 of the channel formation region of the semiconductor layer 408 is preferably within the range of the thickness T208 described above. In FIG. 12B , the thicknesses T308 and T408 are indicated by solid arrows. The thickness T308 can be the shortest distance between the surface where the semiconductor layer 308 is to be formed (here, the top surface of the insulating layer 305) and the top surface of the semiconductor layer 308 in a cross-sectional view. The same applies to the thickness T408. Note that the thicknesses T308 and T408 are not limited to the ranges of the thicknesses T108 and T208 described above. Although FIG. 12B and other figures illustrate a configuration in which the thicknesses T308 and T408 are equal, one embodiment of the present invention is not limited thereto. The thicknesses T308 and T408 can also be different from each other.

[0294] 13, when a metal oxide having a higher indium content than the semiconductor layer 408 is used for the semiconductor layer 308, the thickness T408 is preferably larger than the thickness T308. This allows the transistor 300 and the transistor 400 to have favorable electrical characteristics. Note that the thickness T308 may also be larger than the thickness T408.

[0295] 12B and other figures show a structure in which the conductive layer 304 and the conductive layer 403 are provided in contact with the upper surface of the insulating layer 306. The conductive layer 304 and the conductive layer 403 can be formed using the same material and in the same process. This can simplify the process and reduce manufacturing costs. Note that the conductive layer 304 and the conductive layer 403 can be formed in different processes. This allows different materials to be used for the conductive layer 304 and the conductive layer 403, thereby broadening the range of materials to be selected for the conductive layer 304 and the conductive layer 403.

[0296] 12B and the like show a structure in which both the transistor 300 and the transistor 400 have a backgate electrode; however, one embodiment of the present invention is not limited to this. One or both of the transistor 300 and the transistor 400 may not have a backgate electrode.

[0297] The transistor 300 and the transistor 400 are so-called top-gate transistors having a gate electrode above the semiconductor layer. Furthermore, regions 308P and 308Q functioning as source and drain regions can be formed in a self-aligned manner by supplying impurities to the semiconductor layer 308 using the conductive layer 304 functioning as the gate electrode as a mask. Similarly, regions 408P and 408Q can be formed in a self-aligned manner using the conductive layer 404 as a mask. The transistor 300 and the transistor 400 can each be referred to as a TGSA (Top Gate Self-Aligned) transistor.

[0298] In a TGSA transistor, the physical distance between the source electrode and the drain electrode and the gate electrode can be increased, and therefore the parasitic capacitance between them can be reduced.

[0299] The regions 308P, 308Q, 408P, and 408Q each contain impurities. Supplying impurities to the semiconductor layer 308 can reduce the electrical resistance of the regions 308P and 308Q. The impurity concentrations in the regions 308P and 308Q are higher than the impurity concentration in the channel formation region of the semiconductor layer 308. The same applies to the semiconductor layer 408, the regions 408P, and 408Q. The elements contained in the impurities (hereinafter also referred to as first elements) can be one or more of hydrogen, boron, carbon, nitrogen, fluorine, phosphorus, sulfur, arsenic, aluminum, magnesium, silicon, and noble gases. Typical examples of noble gases include helium, neon, argon, krypton, and xenon. It is particularly preferable to use one or more of hydrogen, boron, phosphorus, aluminum, magnesium, and silicon as the first element.

[0300] Ion implantation can be suitably used to supply impurities. Ion implantation can control the concentration profile in the depth direction with high precision by adjusting the ion acceleration energy and dose. Furthermore, by using an ion implantation method in which a source gas is ionized and the ions are mass-separated before supply, ions of a specific mass can be supplied, thereby increasing the purity of the supplied impurities. Alternatively, by using an ion implantation method in which ions are supplied without mass separation, productivity can be increased. Unless otherwise specified in this specification, the presence or absence of mass separation is not limited. Note that a method in which ions are mass-separated before supplying them is sometimes called an ion implantation method, and a method in which ions are supplied without mass separation is sometimes called an ion doping method.

[0301] When an element that easily bonds with oxygen is used as the first element, the first element removes oxygen from the semiconductor layer 308 and exists in a state of being bonded to oxygen. Ｏ ) occurs. When an element that becomes stable when bonded with oxygen is used as the first element, the first element in the semiconductor layer 308 exists stably in an oxidized state and is therefore unlikely to be desorbed by heat or the like applied during the manufacturing process of the semiconductor device, and the electrical resistance of the regions 308P and 308Q can be kept low. For this reason, it is preferable to use an element whose oxide can exist in a solid state at least at the temperature during the manufacturing process as the first element. One or both of boron and phosphorus can be suitably used as the first element.

[0302] When boron is used as the first element, the boron contained in the region 308P and the region 308Q can exist in a state of being bonded to oxygen. ２ O ３ In XPS analysis, the spectral peak due to the existence of elemental boron may not be observed or may be so small as to be at the background level.

[0303] The supply of hydrogen causes oxygen vacancies (V Ｏ ) occurs, and oxygen deficiency (V Ｏ) by entering V Ｏ The generation of H can effectively reduce the electrical resistance of the regions 308P and 308Q. Therefore, hydrogen can be suitably used as the first element.

[0304] In supplying the impurity, it is preferable to adjust the supply conditions so that the impurity concentration is highest on the surface of the semiconductor layer 308 or in a region close to the surface.

[0305] The source material used to supply the impurity may be, for example, a gas containing the first element. When boron is supplied, a typical example is B ２ H ６ Gas, or BF ３ In addition, when phosphorus is supplied, one or more of the following gases can be used: PH ３ Furthermore, gases obtained by diluting these source gases with noble gases can also be used.

[0306] As a raw material used for supplying impurities, for example, CH ４ , N ２ , N.H. ３ , AlH ３ , AlCl ３ , SiH ４ , Si ２ H ６ , F ２ , H.F., H. ２ , (C ５ H ５ ) ２ Mg and noble gases can be used. Note that the raw material is not limited to gas, and a solid or liquid can also be heated and vaporized for use.

[0307] The supply of impurities can be controlled by setting conditions such as acceleration voltage and dose amount in consideration of the composition, density, thickness, and the like of the insulating layer 306 and the semiconductor layer 308. Note that when impurities are supplied to the semiconductor layer 308 through the insulating layer 306 using the conductive layer 304 as a mask, the region of the insulating layer 306 that does not overlap with the conductive layer 304 may also contain impurities when the impurities are supplied to the region. Furthermore, the region of the insulating layer 305 that does not overlap with the conductive layer 304 may also contain impurities when the impurities are supplied to the region.

[0308] The method of supplying the impurities is not limited to this, and for example, plasma treatment or treatment utilizing thermal diffusion by heating can also be used. In the case of plasma treatment, the impurities can be supplied by generating plasma in a gas atmosphere containing the impurities to be supplied and performing the plasma treatment. As an apparatus for generating the plasma, a dry etching apparatus, an ashing apparatus, a plasma CVD apparatus, a high-density plasma CVD apparatus, etc. can be used.

[0309] For example, by using a plasma CVD apparatus to perform plasma treatment in an atmosphere containing a gas containing a hydrogen element, hydrogen can be supplied as an impurity to a region of the semiconductor layer 308 that does not overlap with the conductive layer 304. Furthermore, by using a plasma CVD apparatus to supply the impurity and form the insulating layer 405, the supply of the impurity and the formation of the insulating layer 405 can be performed successively within the apparatus, thereby improving productivity.

[0310] The detailed description of the regions 408P and 408Q can be referred to in the description of the regions 308P and 308Q, and therefore will not be repeated. The first element contained in the regions 308P and 308Q can be different from the first element contained in the regions 408P and 408Q. Depending on the materials used for the semiconductor layers 308 and 408, the range of choices for the first element supplied to the semiconductor layer 308 and the first element supplied to the semiconductor layer 408 can be broadened. Alternatively, the first element contained in the regions 308P and 308Q can be the same as the first element contained in the regions 408P and 408Q. This allows a common device to be used for supplying the first element, thereby reducing the manufacturing cost of the semiconductor device.

[0311] 14A and 14B are cross-sectional views of a semiconductor device 92 according to one embodiment of the present invention. For a top view of the semiconductor device 92, refer to FIG. 12A. FIG. 14A is a cross-sectional view of the cut surface taken along dashed dotted line A1-A2 in FIG. 12A, and FIG. 14B is a cross-sectional view of the cut surfaces taken along dashed dotted line B1-B2 and dashed dotted line B3-B4.

[0312] The semiconductor device 92 includes a transistor 300 and a transistor 400. The semiconductor device 92 differs mainly from the semiconductor device 90 shown in FIG. 12B and the like in that a semiconductor layer 408 is provided in contact with the top surface of the insulating layer 305.

[0313] 2E to 2G. The transistor 300 can be applied to the transistor 20 and the transistor 20A, and the transistor 400 can be applied to the transistor 30 and the transistor 30A. The layer 41 shown in FIGS. 2E to 2G includes the transistor 100, the transistor 200, and the insulating layer 218.

[0314] The conductive layer 303 and the conductive layer 403 are provided over the substrate 102, and the insulating layer 305 is provided over the conductive layer 303 and the conductive layer 403. The semiconductor layer 308 and the semiconductor layer 408 are provided over the insulating layer 305, and the insulating layer 306 is provided over the semiconductor layer 308 and the semiconductor layer 408. The conductive layer 304 and the conductive layer 404 are provided over the insulating layer 306. The conductive layer 304 has a region overlapping with the semiconductor layer 308 with the insulating layer 306 interposed therebetween. The conductive layer 404 has a region overlapping with the semiconductor layer 408 with the insulating layer 306 interposed therebetween. Part of the insulating layer 306 functions as a gate insulating layer of the transistor 300, and the other part functions as a gate insulating layer of the transistor 400. Part of the insulating layer 305 functions as a back-gate insulating layer of the transistor 300, and the other part functions as a back-gate insulating layer of the transistor 400.

[0315] The insulating layer 218 is provided over the conductive layer 304, the conductive layer 404, and the insulating layer 306. The insulating layer 306 and the insulating layer 218 have an opening 347a, an opening 347b, an opening 447a, and an opening 447b.

[0316] The conductive layer 403 can be formed in the same process as the conductive layer 303. The conductive layer 304 can be formed in the same process as the conductive layer 404. The openings 447a and 447b can be formed in the same process as the openings 347a and 347b. The conductive layers 412a and 412b can be formed in the same process as the conductive layers 312a and 312b. By forming the semiconductor layer 308 and components other than the semiconductor layer 408 in the same process, productivity of the semiconductor device can be increased and manufacturing costs can be reduced.

[0317] <Example 1 of Manufacturing Method of Semiconductor Device> A manufacturing method of a semiconductor device according to one embodiment of the present invention will be described. Note that the description of the materials and formation methods of each element described above may be omitted.

[0318] Thin films (insulating films, semiconductor films, conductive films, etc.) constituting semiconductor devices can be formed using a sputtering method, a chemical vapor deposition (CVD) method, a vacuum evaporation method, a pulsed laser deposition (PLD) method, an atomic layer deposition (ALD) method, etc. CVD methods include a plasma enhanced chemical vapor deposition (PECVD) method and a thermal CVD method. One type of thermal CVD method is a metal organic chemical vapor deposition (MOCVD) method.

[0319] Thin films (insulating films, semiconductor films, conductive films, etc.) that constitute semiconductor devices can be formed by wet film formation methods such as spin coating, dipping, spray coating, inkjet, dispensing, screen printing, offset printing, doctor knife method, slit coating, roll coating, curtain coating, or knife coating.

[0320] When processing a thin film that constitutes a semiconductor device, a lithography method or the like can be used. Alternatively, the thin film can be processed by a nanoimprint method, a sandblasting method, a lift-off method, or the like. Furthermore, an island-shaped thin film can be directly formed by a film formation method using a shielding mask such as a metal mask.

[0321] There are two typical lithography methods: one is to form a resist mask on the thin film to be processed, process the thin film by etching or the like, and then remove the resist mask; the other is to form a photosensitive thin film, and then process the thin film into the desired shape by exposure and development.

[0322] In lithography, the light used for exposure can be, for example, i-line (wavelength 365 nm), g-line (wavelength 436 nm), h-line (wavelength 405 nm), or a mixture of these. Other examples include ultraviolet light, KrF laser light, and ArF laser light. Exposure can also be performed by immersion exposure technology. Extreme ultraviolet (EUV) light or X-rays can also be used as the light used for exposure. An electron beam can also be used instead of the light used for exposure. Extreme ultraviolet light, X-rays, or an electron beam are preferred because they enable extremely fine processing. When exposure is performed by scanning a beam such as an electron beam, a photomask is not required.

[0323] The thin film can be etched by one or more of dry etching, wet etching, and sandblasting.

[0324] Here, an example of a method for manufacturing the semiconductor device 80 shown in Fig. 8A and Fig. 8B will be described with reference to Fig. 15A to Fig. 18C, which show cross-sectional views taken along dashed line A1-A2 in Fig. 3A.

[0325] Here, a configuration example will be described in which indium oxide is used for the semiconductor layer 108 and a metal oxide (e.g., In—Ga—Zn oxide, In—Sn—Zn oxide) having a lower indium content than indium oxide is used for the semiconductor layer 208.

[0326] First, a conductive film is formed over the substrate 102 and then processed to form the conductive layer 112a. The conductive film can be formed by a sputtering method.

[0327] Subsequently, an insulating film 110af that will become the insulating layer 110a and an insulating film 110bf that will become the insulating layer 110b are formed on the conductive layer 112a (FIG. 15A).

[0328] The insulating films 110af and 110bf can be preferably formed by sputtering or PECVD. After forming the insulating film 110af, it is preferable to form the insulating film 110bf without exposing the surface of the insulating film 110af to the atmosphere. This can prevent impurities from the atmosphere from adhering to the surface of the insulating film 110af. Examples of such impurities include water and organic substances. For example, after forming the insulating film 110af, it is preferable to form the insulating film 110bf consecutively using the same device.

[0329] The substrate temperature during the deposition of the insulating film 110af and the insulating film 110bf is preferably 180° C. or higher and 450° C. or lower, more preferably 200° C. or higher and 450° C. or lower, further preferably 250° C. or higher and 450° C. or lower, further preferably 300° C. or higher and 450° C. or lower, further preferably 300° C. or higher and 400° C. or lower, further preferably 350° C. or higher and 400° C. or lower. By setting the substrate temperature during the deposition of the insulating film 110af and the insulating film 110bf within the above-mentioned range, the amount of impurities (e.g., water and hydrogen) released from the insulating film 110af and the insulating film 110bf can be reduced, and the diffusion of the impurities into the semiconductor layer 108 can be suppressed. Therefore, a transistor exhibiting good electrical characteristics and high reliability can be obtained.

[0330] After the insulating films 110af and 110bf are formed, heat treatment can be performed. By performing the heat treatment, impurities (for example, water and hydrogen) can be removed from the insulating films 110af and the insulating films 110bf and from their surfaces.

[0331] After the insulating film 110bf is formed, oxygen can be supplied to the insulating film 110bf. For example, ion implantation or plasma treatment can be used as a method for supplying oxygen. For the plasma treatment, an apparatus that converts gas into plasma using high-frequency power can be suitably used. Examples of the apparatus that converts gas into plasma using high-frequency power include a PECVD apparatus, a plasma etching apparatus, and a plasma ashing apparatus. The ion implantation or plasma treatment is preferably performed in an atmosphere containing oxygen. For example, the atmosphere may contain oxygen, nitrous oxide (N ２ O), nitrogen dioxide (NO ２ An atmosphere containing one or more of oxygen, carbon monoxide, and carbon dioxide can be suitably used. The amount of oxygen supplied can be adjusted, for example, by adjusting the power and processing time in the plasma treatment. Oxygen can also be supplied by irradiating high-frequency electromagnetic waves in an oxygen-containing atmosphere to generate oxygen plasma. For example, oxygen can be supplied by performing microwave treatment in an oxygen-containing atmosphere.

[0332] In this specification, microwaves refer to electromagnetic waves with a frequency of 300 MHz or more and 300 GHz or less. A typical example of microwaves is electromagnetic waves with a frequency of 2.45 GHz. Microwave processing refers to processing using a device with a power source that generates high-density plasma using microwaves. Microwave processing can also be called microwave-excited high-density plasma processing.

[0333] After the insulating film 110bf is formed, nitrogen can be supplied to the insulating film 110bf. The nitrogen supply method can be referred to the description of the oxygen supply method described above. As a nitrogen supply method, plasma treatment in an atmosphere containing nitrogen can be suitably used. For example, nitrogen, dinitrogen monoxide (N ２ O), and nitrogen dioxide (NO２ The amount of nitrogen supplied can be adjusted by, for example, the power and processing time in the plasma processing.

[0334] In the insulating layer (here, the insulating film 110bf or the later insulating layer 110b), nitrogen reacts with oxygen to form nitrogen oxide (NO Ｘ , X is a real number greater than 0). ２ O, NO and NO ２ In the insulating layer, the nitrogen oxide forms a level, which is located within the band gap of the metal oxide. ２ The transition level at which the charge of the indium oxide changes between a 0 state and a -1 state is located within the band gap of indium oxide. Therefore, when nitrogen oxide diffuses to the interface between the insulating layer and the semiconductor layer having the metal oxide or near the interface, the level traps electrons. As a result, the trapped electrons remain at the interface between the insulating layer and the semiconductor layer or near the interface, and the threshold voltage of the transistor can be increased in the positive direction. This allows a normally-off transistor to be obtained, resulting in a semiconductor device with low power consumption.

[0335] Increasing the amount of nitrogen oxide can increase the threshold voltage to the positive side. However, if the amount of nitrogen oxide is too large, the threshold voltage may fluctuate greatly when a positive potential (positive bias) is applied to the gate of the transistor, which may result in reduced reliability. Therefore, it is preferable to use a nitrogen oxide amount within a range that does not affect reliability.

[0336] The amount of nitrogen oxides can be evaluated, for example, by measuring the amount of desorption in thermal desorption spectroscopy (TDS) or the amount of electron spin in electron spin resonance (ESR). ２ O (m / z=44), and NO ２The amount of NO (m / z = 46) desorbed can be evaluated. ２ In some cases, it may be difficult to quantify the amount of NO and N released. ２ By evaluating the amount of O released, ２ In ESR, the amount of NO can be evaluated. ２ Since the N atom has 7 electrons and the O atom has 8 electrons, the ESR signal derived from NO ２ The molecule has an open-shell structure. Therefore, the neutral NO ２ The molecule has a lone electron, so it can be measured by ESR. １４ Since N has a nuclear spin of 1, １４ The peak of the ESR signal related to N is split into three. At this time, the split width of the ESR signal is the hyperfine coupling constant.

[0337] The order of the treatment for supplying oxygen and the treatment for supplying nitrogen is not particularly limited. Oxygen can be supplied after nitrogen is supplied. Nitrogen can also be supplied after oxygen is supplied. Alternatively, oxygen and nitrogen can be supplied in the same treatment. For example, oxygen and nitrogen can be supplied by performing a plasma treatment in an atmosphere containing nitrogen and oxygen. For example, dinitrogen monoxide (N ２ By carrying out a plasma treatment using nitrogen oxides, nitrogen oxides can be efficiently produced, which is preferable.

[0338] After the insulating film 110bf is formed, the plasma treatment can be performed without exposing the surface of the insulating film 110bf to the atmosphere. For example, when a PECVD apparatus is used to form the insulating film 110bf, it is preferable to perform the plasma treatment in the PECVD apparatus. This can improve productivity. Specifically, after the insulating film 110bf is formed in the PECVD apparatus, N ２ O plasma treatment can be performed.

[0339] Subsequently, a film 139 is preferably formed over the insulating film 110bf (FIG. 15B). The film 139 can be formed by a sputtering method. By forming the film 139 in an atmosphere containing oxygen, oxygen can be supplied to the insulating film 110bf.

[0340] The conductivity of the film 139 does not matter. At least one of an insulating film, a semiconductor film, and a conductive film can be used as the film 139. For example, aluminum oxide, hafnium oxide, hafnium aluminate, indium oxide, ITO, or ITSO can be used as the film 139.

[0341] The film 139 is preferably made of an oxide containing one or more of the same elements as those of the semiconductor layer 108 or the semiconductor layer 208. In particular, it is preferable to use an oxide semiconductor applicable to the semiconductor layer 108 or the semiconductor layer 208. This allows the film 139 to be formed using a common apparatus for forming the film that will become the semiconductor layer 108 or the semiconductor layer 208, thereby reducing the manufacturing cost of the semiconductor device.

[0342] The amount of oxygen supplied to the insulating film 110bf can be increased by increasing the ratio of the flow rate of oxygen gas to the total deposition gas when depositing the film 139 (hereinafter also referred to as the oxygen flow rate ratio) or the oxygen partial pressure in the processing chamber. The oxygen flow rate ratio is, for example, preferably 50% to 100%, more preferably 60% to 100%, further preferably 70% to 100%, further preferably 80% to 100%, and further preferably 90% to 100%. Typically, the oxygen flow rate ratio can be set to 100%. Note that the oxygen flow rate ratio can be interpreted as the ratio of the oxygen partial pressure to the pressure in the processing chamber.

[0343] By forming the film 139 by sputtering in an oxygen-containing atmosphere in this manner, oxygen can be supplied to the insulating film 110bf during the formation of the film 139, and oxygen can be prevented from being released from the insulating film 110bf. As a result, a large amount of oxygen can be trapped in the insulating film 110bf. Then, a large amount of oxygen can be supplied to the semiconductor layer 108 by subsequent heat treatment. As a result, oxygen vacancies and V in the semiconductor layer 108 can be reduced. Ｏ H can be reduced, and a highly reliable transistor can be obtained that exhibits favorable electrical characteristics.

[0344] Heat treatment is preferably performed after the film 139 is formed. By performing heat treatment after the film 139 is formed, oxygen can be effectively supplied from the film 139 to the insulating film 110bf.

[0345] The temperature of the heat treatment is preferably 150°C or higher and lower than the strain point of the substrate, more preferably 200°C or higher and 450°C or lower, even more preferably 250°C or higher and 450°C or lower, even more preferably 300°C or higher and 450°C or lower, even more preferably 300°C or higher and 400°C or lower, and even more preferably 350°C or higher and 400°C or lower. The heat treatment can be performed in an atmosphere containing one or more of a noble gas, nitrogen, or oxygen. As the nitrogen-containing atmosphere or the oxygen-containing atmosphere, dry air (CDA: Clean Dry Air) can be used. Note that the content of hydrogen, water, and the like in the atmosphere is preferably as low as possible. As the atmosphere, it is preferable to use a high-purity gas with a dew point of -60°C or lower, preferably -100°C or lower. Using an atmosphere with as low a content of hydrogen, water, and the like as possible can prevent hydrogen, water, and the like from being incorporated into the insulating film 110bf as much as possible. The heat treatment can be performed in an oven, an RTA apparatus, or the like.

[0346] After the film 139 is formed or after the heat treatment, oxygen can be further supplied to the insulating film 110bf through the film 139. For example, ion implantation or plasma treatment can be used as a method for supplying oxygen. The above description can be referred to for the method for supplying oxygen.

[0347] Next, the film 139 is removed. By removing the film 139, the insulating film 110bf is exposed. There is no particular limitation on the method for removing the film 139, but wet etching can be suitably used. By using wet etching, etching of the insulating film 110bf can be suppressed when removing the film 139. This can suppress the thickness of the insulating film 110bf from becoming thin, and can make the thickness of the insulating layer 110b uniform.

[0348] The process of supplying oxygen to the insulating film 110bf is not limited to the above-described method. For example, oxygen radicals, oxygen atoms, oxygen atomic ions, or oxygen molecular ions can be supplied to the insulating film 106f by ion implantation or plasma treatment. Alternatively, a film that suppresses oxygen desorption can be formed on the insulating film 106f, and then oxygen can be supplied to the insulating film 106f through the film. The film is preferably removed after oxygen is supplied. The film that suppresses oxygen desorption can be a conductive film or a semiconductor film containing one or more of indium, zinc, gallium, tin, aluminum, chromium, tantalum, titanium, molybdenum, nickel, iron, cobalt, and tungsten.

[0349] Next, an insulating film 110cf that will become the insulating layer 110c is formed on the insulating film 110bf (FIG. 15C). The description of the formation of the insulating film 110af can be referred to for the formation of the insulating film 110cf, and therefore a detailed description thereof will be omitted.

[0350] Next, a conductive film is formed on the insulating film 110cf and processed to form the conductive layer 112B and the conductive layer 212a ( FIG. 15D ). The conductive film can be formed by a sputtering method. The conductive layer 112B will later become the conductive layer 112b. The conductive layer 112B and the conductive layer 212a can be formed by, for example, a wet etching method.

[0351] Next, the conductive layer 112B, the insulating film 110af, the insulating film 110bf, and the insulating film 110cf are partially removed to form the conductive layer 112b and the insulating layer 110 having the opening 141 ( FIG. 15E ). The conductive layer 112a is exposed by forming the opening 141. The conductive layer 112b can be preferably formed by wet etching. The insulating layer 110 can be preferably formed by dry etching.

[0352] The opening in the insulating layer 110 can be formed, for example, using the resist mask used to form the opening in the conductive layer 112b. Specifically, a resist mask is formed over the conductive layer 112B, and the conductive layer 112b having an opening is formed by removing part of the conductive layer 112B using the resist mask. The insulating layer 110 having an opening can be formed by removing part of the insulating films 110af, 110bf, and 110cf using the resist mask. Alternatively, the opening in the insulating layer 110 and the opening in the conductive layer 112b can be formed using different resist masks.

[0353] Subsequently, a metal oxide film 108f that will become the semiconductor layer 108 is formed so as to cover the opening 141 (FIG. 16A).

[0354] The metal oxide film 108f is preferably formed by sputtering using a metal target (e.g., an indium target) or a metal oxide target (e.g., an indium oxide target). Alternatively, the metal oxide film 108f is preferably formed by ALD. The ALD method allows easy control of the film formation rate, and thus allows thin films to be formed with a high yield. Therefore, the ALD method is particularly suitable when the metal oxide film 108f is thin. Alternatively, the CVD method can be used to form the metal oxide film 108f.

[0355] When forming the metal oxide film 108f, an inert gas (for example, helium gas, argon gas, xenon gas, or the like) can be used.

[0356] The metal oxide film 108f is preferably formed under conditions that result in low crystallinity of the metal oxide film 108f. By performing heat treatment after forming the metal oxide film 108f with low crystallinity to crystallize it, the grain size of the crystal grains can be increased. Here, if the number of crystal grains contained in the metal oxide film 108f increases at the stage of forming the metal oxide film 108f, the grain size of the crystal grains after the heat treatment may become small. Therefore, it is preferable that the number of crystal grains contained in the metal oxide film 108f is small and the crystallinity of the metal oxide film 108f is low at the stage of forming the metal oxide film 108f.

[0357] When forming the metal oxide film 108f, a gas containing hydrogen elements (e.g., H ２ or H ２ It is preferable to use hydrogen gas (hydrogen fluoride gas) containing 1,000 sulphite (O). This can reduce the number of crystal grains generated during the formation of the metal oxide film 108f, thereby making the metal oxide film 108f low in crystallinity. When forming the metal oxide film 108f, a mixture of hydrogen gas and an inert gas can be used. For example, the ratio of the flow rate of hydrogen gas to the total film formation gas when forming the metal oxide film 108f (hereinafter also referred to as the hydrogen flow rate ratio) is preferably greater than 0% and less than 20%, more preferably greater than 0% and less than 15%, and even more preferably greater than 0% and less than 10%. Note that the hydrogen flow rate ratio during the formation of the metal oxide film 108f is not limited to the above-mentioned range.

[0358] When a reactive sputtering method using a metal target (for example, an indium target) is used to form the metal oxide film 108f, oxygen gas can be used as the film formation gas. Also, when a metal oxide target (for example, an indium oxide target) is used, it is preferable to use oxygen gas as the film formation gas. By using oxygen gas, oxygen deficiency (V Ｏ) can be suppressed. By using oxygen gas, the amount of oxygen contained in the metal oxide film 108f can be increased, which can promote crystallization in a later heat treatment. Furthermore, oxygen can be supplied into the insulating layer 110 when the metal oxide film 108f is formed. As a result, oxygen is supplied from the insulating layer 110 to the semiconductor layer 108 in a later step, and oxygen vacancies (V Ｏ ) and V Ｏ H can be reduced. When forming the metal oxide film 108f, a mixture of oxygen gas and an inert gas can be used. On the other hand, if the oxygen flow ratio when forming the metal oxide film 108f is high, the number of crystal grains contained in the metal oxide film 108f may increase at the stage when the metal oxide film 108f is formed. The oxygen flow ratio when forming the metal oxide film 108f is preferably higher than 0% and not higher than 10%, more preferably higher than 0% and not higher than 7%, and even more preferably higher than 0% and not higher than 5%. By setting the oxygen flow ratio within the above range, oxygen vacancies and V in the semiconductor layer 208 can be reduced. Ｏ This can reduce H and also lower the crystallinity of the metal oxide film 108f. Note that the oxygen flow rate ratio in the formation of the metal oxide film 108f is not limited to the above range.

[0359] A mixture of a gas containing hydrogen, oxygen gas, and an inert gas can be used as the deposition gas for the metal oxide film 108f. Typically, hydrogen gas, oxygen gas, and argon gas can be suitably used as the deposition gas for the metal oxide film 108f. The hydrogen flow rate ratio and the oxygen flow rate ratio are preferably set in the above-mentioned ranges. This can reduce the crystallinity of the metal oxide film 108f and increase the grain size of the crystal grains after the heat treatment. In addition, oxygen deficiency (V) in the semiconductor layer 208 can be reduced. Ｏ ) and V Ｏ H can be reduced.

[0360] The substrate temperature during deposition of the metal oxide film 108f is preferably low. This can reduce the crystallinity of the metal oxide film 108f. The substrate temperature during deposition of the metal oxide film 108f is preferably room temperature (e.g., 25°C) or higher and 150°C or lower, more preferably room temperature or higher and 100°C or lower, further preferably room temperature or higher and 80°C or lower, and further preferably room temperature or higher and 50°C or lower. In particular, it is preferable to deposit the metal oxide film 108f at room temperature or without heating the substrate. Note that the substrate temperature during deposition of the metal oxide film 108f is not limited to the above-mentioned range.

[0361] When the ALD method is used to form the metal oxide film 108f, it is preferable to use a film formation method such as a thermal ALD method or PEALD (Plasma Enhanced ALD). The thermal ALD method is preferable because it exhibits extremely high coverage. The PEALD method is preferable because it not only exhibits high coverage but also allows low-temperature film formation.

[0362] The metal oxide film 108f can be formed by, for example, an ALD method using a precursor containing a constituent metal element and an oxidizing agent.

[0363] For example, when forming an indium oxide film, a precursor containing indium can be used, such as triethylindium, trimethylindium, tris(2,2,6,6-tetramethyl-3,5-heptanedionate)indium, cyclopentadienylindium, indium(III) chloride, [3-(dimethylamino)propyl]dimethylindium, and [1,1,1-trimethyl-N-(trimethylsilyl)amido]indium.

[0364] Oxidizing agents include, for example, ozone, oxygen, hydrogen peroxide, and water.

[0365] The composition of the resulting film can be controlled by adjusting one or more of the types of source gases, the flow rate ratio of the source gases, the time for which the source gases are flowed, and the order in which the source gases are flowed. By adjusting these, the composition of the metal oxide film 108f can be controlled. Furthermore, by adjusting these, it is possible to form a metal oxide film 108f whose composition changes continuously.

[0366] Before forming the metal oxide film 108f, it is preferable to perform at least one of a treatment for removing water, hydrogen, organic substances, and the like adsorbed on the surface of the insulating layer 110 and a treatment for supplying oxygen into the insulating layer 110. For example, heat treatment can be performed at a temperature of 70° C. or higher and 200° C. or lower in a reduced pressure atmosphere. Alternatively, plasma treatment can be performed in an atmosphere containing oxygen. Alternatively, dinitrogen monoxide (N ２ By performing plasma treatment in an atmosphere containing an oxidizing gas such as nitrous oxide (NO), oxygen can be supplied to the insulating layer 110. When plasma treatment is performed in an atmosphere containing nitrous oxide gas, oxygen can be supplied while organic substances on the surface of the insulating layer 110 are suitably removed. After such treatment, it is preferable to form a metal oxide film 108f successively without exposing the surface of the insulating layer 110 to the air.

[0367] Next, the metal oxide film 108f is processed into an island shape to form a metal oxide layer 108F ( FIG. 16B ). A wet etching method can be suitably used to form the metal oxide layer 108F. At this time, a portion of the insulating layer 110 in a region that does not overlap with the metal oxide layer 108F may be etched and thinned. Note that, in the etching of the metal oxide film 108f, using a material with a high etching selectivity for the insulating layer 110 can prevent the thickness of the insulating layer 110 from becoming thin.

[0368] Next, heat treatment (hereinafter also referred to as first heat treatment) is performed. The first heat treatment crystallizes the metal oxide layer 108F, and the semiconductor layer 108 is formed ( FIG. 16C ). The heat treatment can reduce defects in the semiconductor layer 108. Furthermore, the first heat treatment can remove impurities contained in the semiconductor layer 108 or adsorbed on the surface thereof. Examples of impurities contained in the semiconductor layer 108 include impurities caused by hydrogen gas, oxygen gas, and argon gas used as deposition gases. Examples of impurities adsorbed on the surface of the semiconductor layer 108 include hydrogen and water.

[0369] The temperature of the first heat treatment is preferably high. Increasing the temperature of the first heat treatment can increase the crystallinity of the semiconductor layer 108. Here, regions with low crystallinity (e.g., amorphous regions) may exist between crystal grains in the semiconductor layer 108. In particular, if a region with low crystallinity exists in the channel formation region, carrier scattering may reduce the field-effect mobility of the transistor. Increasing the temperature of the first heat treatment increases the grain size of the crystal grains, thereby reducing the regions with low crystallinity between the crystal grains. This allows a transistor with high field-effect mobility to be obtained. Increasing the temperature of the first heat treatment may also increase the grain size of the crystal grains in the semiconductor layer 108. Furthermore, defects in the semiconductor layer 108 can be efficiently reduced, and impurities contained in or adsorbed on the surface of the semiconductor layer 108 can be efficiently removed.

[0370] The temperature of the first heat treatment is preferably 100° C. or higher and lower than the strain point of the substrate, more preferably 200° C. or higher and 670° C. or lower, further preferably 300° C. or higher and 670° C. or lower, further preferably 350° C. or higher and 670° C. or lower, further preferably 400° C. or higher and 670° C. or lower, and further preferably 450° C. or higher and 670° C. or lower. In the first heat treatment, the temperature of the substrate is preferably in the above-mentioned temperature range. Note that the temperature of the substrate in the first heat treatment is not limited to the above-mentioned range.

[0371] The first heat treatment can be performed in an atmosphere containing one or more of a noble gas, nitrogen, and oxygen. Dry air (CDA) can be used as the nitrogen-containing atmosphere or the oxygen-containing atmosphere. The first heat treatment is preferably performed in an atmosphere containing oxygen. Performing the first heat treatment in an oxygen-containing atmosphere may enhance the effects of reducing defects and increasing the grain size of crystal grains. CDA can be suitably used as the atmosphere for the first heat treatment. It is preferable that the content of hydrogen, water, and the like in the atmosphere be as low as possible. It is preferable to use a high-purity gas with a dew point of −60° C. or less, preferably −100° C. or less, as the atmosphere. Using an atmosphere with as low a content of hydrogen, water, and the like as possible can prevent hydrogen, water, and the like from being taken into the semiconductor layer 208 as much as possible.

[0372] The apparatus used for the first heat treatment is not particularly limited, and for example, an apparatus that heats by thermal conduction or thermal radiation from a heating element can be used. For example, an oven or a rapid thermal annealing (RTA) apparatus can be used for the first heat treatment. As the RTA apparatus, an LRTA (Lamp RTA) apparatus that heats the workpiece by radiating light (electromagnetic waves) emitted from a lamp can be used. Examples of such lamps include a halogen lamp, a metal halide lamp, a xenon arc lamp, a carbon arc lamp, a high-pressure sodium lamp, and a high-pressure mercury lamp. Furthermore, as the RTA apparatus, a GRTA (Gas RTA) apparatus that heats the workpiece using high-temperature gas can be used. Using an RTA apparatus can shorten the heat treatment time. The treatment time is preferably 1 minute to 10 minutes, more preferably 3 minutes to 10 minutes, and even more preferably 5 minutes to 10 minutes. The first heat treatment can typically be performed using a GRTA apparatus at 650° C. for 6 minutes. Note that when a short heat treatment time is performed using an RTA apparatus, the heating temperature can be set to a temperature equal to or higher than the strain point of the substrate, thereby further shortening the heat treatment time.

[0373] The higher the crystallinity of the semiconductor layer, the higher the film density may be. Increasing the film density of the semiconductor layer can suppress the diffusion of impurities into the semiconductor layer. The film density can be evaluated by, for example, Rutherford Backscattering Spectrometry (RBS) or X-ray Reflectivity (XRR).

[0374] The semiconductor layer 108 can be obtained by forming a metal oxide film 108f with low crystallinity, processing the metal oxide film 108f into an island-shaped metal oxide layer 108F, and then crystallizing the film by first heat treatment. This increases the grain size of crystal grains contained in the semiconductor layer 108. Furthermore, since the metal oxide film 108f can be processed into an island shape while still having low crystallinity, processing is facilitated, and productivity of the semiconductor device can be improved. Note that one embodiment of the present invention is not limited thereto. The semiconductor layer 108 can be formed by forming a metal oxide film 108f with low crystallinity, crystallizing the film by first heat treatment, and then processing the film into an island shape.

[0375] By the first heat treatment, oxygen can also be supplied from the insulating layer 110 to the metal oxide film 108f or the semiconductor layer 108.

[0376] The first heat treatment can be performed multiple times. By performing the first heat treatment multiple times, it may be possible to enhance the effect of increasing the crystallinity of the semiconductor layer 108 and the effect of reducing impurities adsorbed in or on the surface of the semiconductor layer 108. Note that the heat treatment is not performed here, and can serve as a heat treatment performed in a later step. Furthermore, a process in which heat is applied in a later step (for example, a film formation step) may also serve as the first heat treatment.

[0377] Subsequently, an insulating film 106f that will become the insulating layer 106 is formed to cover the semiconductor layer 108, the conductive layer 112b, the conductive layer 212a, and the insulating layer 110 (FIG. 16D). The insulating film 106f can be formed by, for example, a PECVD method, a sputtering method, or an ALD method.

[0378] When a metal oxide is used for the semiconductor layer 108, the insulating layer 106 preferably functions as a barrier film that suppresses oxygen diffusion. When the insulating layer 106 has a function of suppressing oxygen diffusion, oxygen is prevented from being released from the semiconductor layer 108, and oxygen vacancies (V Ｏ ) can be suppressed from increasing. Furthermore, oxygen contained in the semiconductor layer 108 is prevented from diffusing into the conductive layer 104 through the insulating layer 106, and the conductive layer 104 can be prevented from being oxidized. As a result, a transistor can be provided that exhibits favorable electrical characteristics and is highly reliable.

[0379] By increasing the temperature during the deposition of the insulating film 106f, it is possible to obtain a gate insulating layer with fewer defects. However, if the temperature during the deposition of the insulating film 106f is high, oxygen is released from the semiconductor layer 108, and oxygen vacancies and V in the semiconductor layer 108 occur. Ｏ H may increase. The substrate temperature during deposition of the insulating film 106f is preferably 180° C. or higher and 450° C. or lower, more preferably 200° C. or higher and 450° C. or lower, further preferably 250° C. or higher and 450° C. or lower, further preferably 300° C. or higher and 450° C. or lower, and further preferably 300° C. or higher and 400° C. or lower. By setting the substrate temperature during deposition of the insulating film 106f within the above range, defects in the insulating layer 106 can be reduced and oxygen can be prevented from being released from the semiconductor layer 108. Therefore, a transistor exhibiting good electrical characteristics and high reliability can be obtained.

[0380] Before forming the insulating film 106f, plasma treatment can be performed on the surface of the semiconductor layer 108. The plasma treatment can reduce impurities such as water adsorbed to the surface of the semiconductor layer 108. Therefore, impurities at the interface between the semiconductor layer 108 and the insulating layer 106 can be reduced, resulting in a highly reliable transistor. This is particularly suitable for the case where the surface of the semiconductor layer 108 is exposed to the air between the formation of the semiconductor layer 108 and the formation of the insulating film 106f. The plasma treatment can be performed in an atmosphere of oxygen, ozone, nitrogen, nitrous oxide, argon, or the like, for example. Furthermore, the plasma treatment and the formation of the insulating film 106f are preferably performed successively without exposure to the air.

[0381] After the insulating film 106f is formed, oxygen can be supplied to the insulating film 106f. The above description can be referred to for the method of supplying oxygen.

[0382] Subsequently, a conductive film is formed over the insulating film 106f and processed to form the conductive layer 104. The conductive film can be formed by, for example, a sputtering method, a thermal CVD method (including an MOCVD method), or an ALD method.

[0383] Next, the insulating film 106f is processed to form the insulating layer 106 ( FIG. 17A ). The insulating layer 106 can be formed by dry etching. As described above, it is preferable that the insulating layer 106 does not have a region that comes into contact with the semiconductor layer 208 to be formed later. In other words, it is preferable that the insulating layer 106 is not exposed in the opening 241.

[0384] Note that there is no particular limitation on the order in which the insulating layer 106 and the conductive layer 104 are formed. For example, the insulating film 106f can be formed on the insulating layer 106, a conductive film can be formed over the insulating layer 106, and the conductive film can be processed to form the conductive layer 104.

[0385] As a result, the transistor 100 is formed.

[0386] Subsequently, an insulating film 210af to become the insulating layer 210a, an insulating film 210bf to become the insulating layer 210b, and an insulating film 210cf to become the insulating layer 210c are formed on the conductive layer 104, the insulating layer 106, and the conductive layer 212a.

[0387] Subsequently, a conductive layer 212B that will become the conductive layer 212b is formed on the insulating film 210cf (FIG. 17B).

[0388] Subsequently, the conductive layer 212B, the insulating film 210af, the insulating film 210bf, and the insulating film 210cf are partially removed to form the conductive layer 212b and the insulating layer 210 having the opening 241 (FIG. 17C). The formation of the opening 241 exposes the conductive layer 212a.

[0389] For the process from the formation of the insulating film 210af to the formation of the opening 241, the description from the process from the formation of the insulating film 110af to the formation of the opening 141 can be referred to.

[0390] Subsequently, a metal oxide film 208f that will become the semiconductor layer 208 is formed so as to cover the opening 241 (FIG. 18A).

[0391] The metal oxide film 208f is preferably formed by a sputtering method using a metal target or a metal oxide target, or an ALD method.

[0392] The metal oxide film 208f is preferably a dense film with as few defects as possible. Furthermore, the metal oxide film 208f is preferably a high-purity film in which impurities including hydrogen elements are reduced as much as possible. In particular, it is preferable to use a crystalline metal oxide film as the metal oxide film 208f.

[0393] When the metal oxide film 208f is formed, oxygen gas is preferably used. By using oxygen gas, oxygen can be suitably supplied into the insulating layer 210. As a result, oxygen is supplied from the insulating layer 210 to the semiconductor layer 208 in a later step, and oxygen vacancies (V Ｏ ) and V Ｏ H can be reduced.

[0394] When forming the metal oxide film 208f, a mixture of oxygen gas and an inert gas can be used. Note that the higher the oxygen flow rate ratio or oxygen partial pressure of the deposition gas when forming the metal oxide film, the higher the crystallinity of the metal oxide film, and a highly reliable transistor can be realized. On the other hand, the lower the oxygen flow rate ratio or oxygen partial pressure, the lower the crystallinity and the higher the electrical conductivity of the metal oxide film, and the higher the on-state current of the transistor can be.

[0395] The higher the substrate temperature during deposition of the metal oxide film, the higher the crystallinity and density of the metal oxide film, which allows for a highly reliable transistor. On the other hand, the lower the substrate temperature, the lower the crystallinity and electrical conductivity of the metal oxide film, which allows for a high on-state current of the transistor.

[0396] The substrate temperature during deposition of the metal oxide film 208f is preferably from room temperature to 250° C., more preferably from room temperature to 200° C., and even more preferably from room temperature to 140° C. For example, a substrate temperature of from room temperature to 140° C. is preferable because it increases productivity. Furthermore, by depositing the metal oxide film 208f at room temperature or without heating the substrate, the crystallinity can be reduced.

[0397] For example, when an In—Sn—Zn oxide film is formed by ALD, three precursors, i.e., a precursor containing indium, a precursor containing tin, and a precursor containing zinc, can be used, or two precursors, i.e., a precursor containing indium and a precursor containing tin and zinc, can be used.

[0398] Tin-containing precursors include, for example, tin(IV) chloride and tetrakis(dimethylamido)tin.

[0399] Gallium-containing precursors include, for example, trimethylgallium, triethylgallium, gallium trichloride, tris(dimethylamido)gallium(III), gallium(III) acetylacetonate, tris(2,2,6,6-tetramethyl-3,5-heptanedionate)gallium, dimethylchlorogallium, and diethylchlorogallium.

[0400] Precursors containing aluminum include, for example, aluminum chloride and trimethylaluminum.

[0401] Precursors containing zinc include, for example, dimethylzinc, diethylzinc, zinc bis(2,2,6,6-tetramethyl-3,5-heptanedionate), and zinc chloride.

[0402] Before forming the metal oxide film 208f, it is preferable to perform at least one of a treatment for removing water, hydrogen, organic substances, and the like adsorbed on the surface of the insulating layer 210 and a treatment for supplying oxygen into the insulating layer 210. For these treatments, the above-described descriptions can be referred to.

[0403] Next, the metal oxide film 208f is processed into an island shape to form the semiconductor layer 208 (FIG. 18B). The semiconductor layer 208 can be preferably formed by wet etching.

[0404] After the metal oxide film 208f is formed or after the metal oxide film 208f is processed into the semiconductor layer 208, heat treatment (hereinafter also referred to as second heat treatment) is preferably performed. The second heat treatment can remove hydrogen and water contained in the metal oxide film 208f or the semiconductor layer 208 or adsorbed on the surface. The second heat treatment may improve the film quality of the metal oxide film 208f or the semiconductor layer 208 (for example, reduce defects or increase crystallinity). For the second heat treatment, refer to the description of the first heat treatment.

[0405] By the second heat treatment, oxygen can also be supplied from the insulating layer 210 to the metal oxide film 208 f or the semiconductor layer 208 .

[0406] When a crystal structure other than single crystal or polycrystal (e.g., a CAAC structure or an nc structure) is applied to the semiconductor layer 208, the second heat treatment is preferably performed at a temperature at which the metal oxide film 208f or the semiconductor layer 208 does not become single crystallized or polycrystallized. The temperature of the second heat treatment can be lower than the temperature of the first heat treatment. The temperature of the second heat treatment is preferably 100° C. or higher and lower than the strain point of the substrate, more preferably 100° C. or higher and 500° C. or lower, further preferably 150° C. or higher and 500° C. or lower, further preferably 250° C. or higher and 500° C. or lower, further preferably 350° C. or higher and 500° C. or lower, and further preferably 350° C. or higher and 450° C. or lower. In the second heat treatment, the temperature of the substrate is preferably in the above-mentioned temperature range. Note that the temperature of the substrate in the second heat treatment is not limited to the above-mentioned range.

[0407] Note that the heat treatment is not performed here, and can be performed in a subsequent step. In addition, a subsequent step in which heat is applied (for example, a film formation step) may also serve as the second heat treatment.

[0408] Subsequently, the insulating layer 206 is formed to cover the semiconductor layer 208, the conductive layer 212b, and the insulating layer 210. The conductive layer 204 is formed on the insulating layer 206 ( FIG. 18C ). For the formation of the insulating layer 206 to the conductive layer 204, the description regarding the formation of the insulating film 106f to the formation of the conductive layer 104 can be referred to.

[0409] As a result, the transistor 200 is formed.

[0410] Subsequently, an insulating layer 218 is formed on the insulating layer 206 and the conductive layer 204 (FIG. 8A).

[0411] Through the above steps, the semiconductor device 80 of one embodiment of the present invention can be manufactured.

[0412] 11A to 11C will be described with reference to FIGS. 19A to 20D. Cross-sectional views taken along dashed line A1-A2 in FIG. 3A are shown in FIGS. 19A to 20D. Note that descriptions of portions that overlap with the above-described <Example 1 of manufacturing method of semiconductor device> may be omitted.

[0413] First, a conductive film is formed over the substrate 102 and then processed to form the conductive layer 112a and the conductive layer 212a.

[0414] Subsequently, the insulating films 110af, 110bf, and 110cf are formed over the conductive layer 112a and the conductive layer 212a.

[0415] For the steps from the formation of the conductive layer 112a and the conductive layer 212a to the formation of the insulating film 110cf, the description from the formation of the conductive layer 112a to the formation of the insulating film 110cf in <Example 1 of manufacturing method of semiconductor device> can be referred to.

[0416] Next, a conductive film is formed on the insulating film 110cf and processed to form a conductive layer 112B and a conductive layer 212B (FIG. 19A). The conductive layer 212B will later become the conductive layer 212b.

[0417] Next, portions of the conductive layer 112B, the insulating film 110af, the insulating film 110bf, and the insulating film 110cf are removed to form an opening 141, and portions of the conductive layer 212B, the insulating film 110af, the insulating film 110bf, and the insulating film 110cf are removed to form an opening 241. This forms the conductive layer 112b, the conductive layer 212b, and the insulating layer 110 ( FIG. 19B ). The formation of the opening 141 exposes the conductive layer 112a, and the formation of the opening 241 exposes the conductive layer 212a.

[0418] Subsequently, a metal oxide film 108f that will become the semiconductor layer 108 is formed so as to cover at least the opening 141 (FIG. 19C).

[0419] Subsequently, the metal oxide film 108f is processed into an island shape to form a metal oxide layer 108F (FIG. 19D).

[0420] Next, a first heat treatment is performed. The first heat treatment crystallizes the metal oxide layer 108F, and the semiconductor layer 108 is formed ( FIG. 20A ). The above description can be referred to for the first heat treatment. Note that the first heat treatment may crystallize the conductive layer 112b and the conductive layer 212b or increase the crystallinity. For example, when an ITO film is used as the conductive layer 112b and the conductive layer 212b, the first heat treatment increases the crystallinity of the ITO film.

[0421] Subsequently, a metal oxide film 208f that will become the semiconductor layer 208 is formed so as to cover at least the opening 241 (FIG. 20B).

[0422] Next, the metal oxide film 208f is processed into an island shape to form the semiconductor layer 208 ( FIG. 20C ). The metal oxide film 208f is processed using an etchant that has a faster etching rate for the metal oxide film 208f than for the semiconductor layer 108, the conductive layer 112a, the conductive layer 212b, and the insulating layer 110. Here, the first heat treatment increases the crystallinity of the semiconductor layer 108, the conductive layer 112a, and the conductive layer 212b, slowing their etching rates. Therefore, thinning of the semiconductor layer 108, the conductive layer 112a, and the conductive layer 212b during processing of the metal oxide film 208f is suppressed. For example, the etching rate of highly crystalline indium oxide films and ITO films is extremely slow when oxalic acid is used. When indium oxide is used for the semiconductor layer 108, ITO is used for the conductive layer 112b and the conductive layer 212b, and In—Ga—Zn oxide or In—Sn—Zn oxide is used for the metal oxide film 208f, an etchant containing oxalic acid can be suitably used to process the metal oxide film 208f.

[0423] The second heat treatment is preferably performed after the metal oxide film 208f is formed or after the metal oxide film 208f is processed into the semiconductor layer 208. The above description can be referred to for the second heat treatment.

[0424] Subsequently, the insulating layer 106 is formed to cover the semiconductor layer 108 , the semiconductor layer 208 , the conductive layer 112 b , the conductive layer 212 b , and the insulating layer 110 .

[0425] Subsequently, a conductive film is formed on the insulating layer 106, and the conductive film is processed to form the conductive layer 104 and the conductive layer 204 (FIG. 20D).

[0426] As a result, the transistor 100 and the transistor 200 are formed.

[0427] Subsequently, an insulating layer 218 is formed on the insulating layer 106, the conductive layer 104, and the conductive layer 204 (FIG. 11A).

[0428] Through the above steps, the semiconductor device 82 of one embodiment of the present invention can be manufactured.

[0429] <Manufacturing Method Example 3 of Semiconductor Device> An example of a manufacturing method different from the above-described <Manufacturing Method Example 2 of Semiconductor Device> will be described with reference to Fig. 21A to Fig. 22C. Fig. 21A to Fig. 22C show cross-sectional views taken along dashed dotted line A1-A2 in Fig. 3A. Note that the process up to the formation of the metal oxide film 108f is the same as in <Manufacturing Method Example 2 of Semiconductor Device> (see Fig. 19A to Fig. 19C).

[0430] Next, a mask film 181f is formed on the metal oxide film 108f. The mask film 181f can be formed by, for example, sputtering or vacuum deposition. The mask film 181f is preferably formed immediately after the formation of the metal oxide film 108f without being exposed to the atmosphere.

[0431] The mask film 181f is preferably made of a material that does not easily diffuse into the metal oxide film 108f. Furthermore, the mask film 181f is preferably made of a material that has an etching rate different from that of the metal oxide film 108f. Specifically, the ratio of the etching rate of the mask film 181f to the etching rate of the metal oxide film 108f (hereinafter also referred to as the selectivity) is preferably large. Furthermore, the mask film 181f is preferably made of a material that can withstand subsequent heat treatment. For example, one or more of a tungsten film, a molybdenum film, and a titanium film can be suitably used as the mask film 181f.

[0432] Subsequently, a resist mask 183 is formed on the mask film 181f (FIG. 21A).

[0433] Next, the mask film 181f is processed using the resist mask 183 as a mask to expose a portion of the upper surface of the metal oxide film 108f, thereby forming an island-shaped mask layer 181. The mask layer 181 is preferably formed by dry etching.

[0434] Next, the metal oxide film 108f is processed using the resist mask 183 and the mask layer 181 as a mask to form a metal oxide layer 108F (FIG. 21B). The mask layer 181 can also be said to function as a hard mask. As a result, the metal oxide layer 108F and the mask layer 181 are formed with even or approximately even edges.

[0435] Subsequently, the resist mask 183 is removed (FIG. 21C).

[0436] Next, a first heat treatment is performed. The first heat treatment crystallizes the metal oxide layer 108F, and the semiconductor layer 108 is formed (FIG. 21D). The above description can be referred to for the first heat treatment. The first heat treatment may crystallize the mask layer 181 or increase its crystallinity.

[0437] Subsequently, a metal oxide film 208 f is formed so as to cover at least the opening 241 .

[0438] Next, a mask film 185f is formed on the metal oxide film 208f. For the mask film 185f, the description of the mask film 181f can be referred to. The mask film 185f is preferably made of the same material as the mask film 181f. Furthermore, the thickness of the mask film 185f is preferably the same as or approximately the same as the thickness of the mask film 181f.

[0439] Subsequently, a resist mask 187 is formed on the mask film 185f (FIG. 22A).

[0440] Subsequently, the mask film 185f is processed using the resist mask 187 as a mask to expose a part of the upper surface of the metal oxide film 208f, thereby forming an island-shaped mask layer 185.

[0441] Next, the metal oxide film 208f is processed using the resist mask 187 and the mask layer 185 as a mask to form the semiconductor layer 208 (FIG. 22B). The mask layer 185 can also be said to function as a hard mask. As a result, the semiconductor layer 208 and the mask layer 185 are formed with aligned or approximately aligned edges.

[0442] Subsequently, the resist mask 187 is removed (FIG. 22C).

[0443] Next, the mask layer 181 and the mask layer 185 are removed (FIG. 20C), thereby exposing the semiconductor layer 108 and the semiconductor layer 208.

[0444] By using the same material for mask layer 181 and mask layer 185, mask layer 181 and mask layer 185 can be removed in the same process. Furthermore, by making mask layer 181 and mask layer 185 the same or approximately the same thickness, it is not necessary to remove mask layer 181 and mask layer 185 separately, which simplifies the process.

[0445] It is preferable to use a wet etching method for removing the mask layer 181 and the mask layer 185. By using a wet etching method, it is possible to prevent damage to the semiconductor layer 108 and the semiconductor layer 208. For example, an etchant containing phosphoric acid, acetic acid, and nitric acid can be used for removing the mask layer 181 and the mask layer 185.

[0446] The second heat treatment is preferably performed after the metal oxide film 208f is formed or after the metal oxide film 208f is processed into the semiconductor layer 208. The above description can be referred to for the second heat treatment.

[0447] Subsequently, the insulating layer 106 is formed to cover the semiconductor layer 108, the semiconductor layer 208, the conductive layer 112b, the conductive layer 212b, and the insulating layer 110. For the process after the formation of the insulating layer 106, the above description can be referred to.

[0448] Through the above steps, the semiconductor device 82 of one embodiment of the present invention can be manufactured.

[0449] This embodiment mode can be combined with other embodiment modes as appropriate. In addition, in this specification, when a plurality of configuration examples are shown in one embodiment mode, the configuration examples can be combined as appropriate.

[0450] Embodiment 2 In this embodiment, an indium oxide film that can be used for a semiconductor layer of a transistor included in a display device or a semiconductor device according to one embodiment of the present invention will be described.

[0451] In this specification and the like, indium oxide having at least a crystalline portion or a crystalline region in a film is referred to as crystalline indium oxide (crystal IO) or crystalline indium oxide (crystalline IO). Examples of crystalline IO or crystalline IO include single-crystalline indium oxide, polycrystalline indium oxide, and microcrystalline indium oxide.

[0452] Indium oxide is a semiconductor material having physical properties that are completely different from those of oxide semiconductors such as In—Ga—Zn oxide (hereinafter also referred to as IGZO) and zinc oxide.

[0453] The carrier concentration dependence of the Hall mobility of indium oxide, silicon, and IGZO will be explained. Figure 23A shows the carrier concentration dependence of the Hall mobility of silicon (Si) and indium oxide (InO Ｘ ) and FIG. 23B is a schematic diagram showing the carrier concentration dependence of the hole mobility for IGZO.

[0454] First, IGZO tends to exhibit higher hole mobility as the carrier concentration increases, as shown by the arrows in Figure 23B. On the other hand, indium oxide tends to exhibit higher hole mobility as the carrier concentration decreases, as shown by the arrows in Figure 23A (see Non-Patent Document 3). This trend is similar to that of silicon; the lower the concentration of dopants (impurities) in the material, the less impurity scattering there is and the higher the hole mobility. In other words, the higher the purity and intrinsic indium oxide, the higher the hole mobility. From these results, it can be said that indium oxide, unlike IGZO, is a material with physical properties similar to those of silicon. Note that the characteristics of indium oxide shown in Figure 23A are assumed to be single crystal. Therefore, when indium oxide is non-single crystal (e.g., polycrystalline), the characteristics may differ from those shown in Figure 23A.

[0455] 23A, the range R1 of low carrier concentration has extremely high hole mobility, and therefore can be said to be a range of carrier concentration suitable for, for example, a channel formation region of a transistor. For example, in the case of indium oxide, the range R1 is a range where the carrier concentration value is 1×10 １５ cm −３ The range includes, for example, 1×10１４ cm −３ That's it, 1 x 10 １８ cm −３ By sufficiently reducing the carrier concentration, the Hall mobility value can be increased to 270 cm ２ It is expected that the resistance can be increased to about / (V·s).

[0456] In addition, in indium oxide, the region where the carrier concentration is in the range R1 may contain an element that lowers the carrier concentration. Examples of elements that lower the carrier concentration include magnesium, calcium, zinc, cadmium, and copper. By substituting these elements for indium, the carrier concentration can be lowered. Examples of elements that lower the carrier concentration include nitrogen, phosphorus, arsenic, and antimony. For example, by substituting nitrogen, phosphorus, arsenic, or antimony for oxygen, the carrier concentration can be lowered.

[0457] On the other hand, the range R2 with a high carrier concentration has a low electrical resistance, and can be said to be a range of carrier concentrations suitable for, for example, the source and drain regions of a transistor, a resistor, or a transparent conductive film. ２０ cm −３ The range includes, for example, 1×10 １９ cm −３ That's it, 1 x 10 ２２ cm −３ By increasing the carrier concentration sufficiently, the resistivity can be reduced to 1×10 −４ It is expected that the resistivity can be reduced to Ω·cm or less.

[0458] In addition, in indium oxide, the region where the carrier concentration is in the range R2 may contain an element that increases the carrier concentration. For example, it is preferable that the indium oxide contains an element that is common to the source electrode and drain electrode of the transistor. Examples of elements that increase the carrier concentration include titanium, zirconium, hafnium, tantalum, tungsten, molybdenum, tin, silicon, and boron. In particular, it is more preferable to use an element whose oxide has conductive or semiconducting properties. Note that, as a method for supplying an element that increases the carrier concentration, a method of forming a film containing the element and diffusing it, ion implantation, ion doping, plasma immersion ion implantation, or plasma treatment can be used. Note that, unless otherwise specified in this specification, the presence or absence of mass separation is not limited. For example, in this specification, a method of supplying ions after mass separation is referred to as an ion implantation method, and a method of supplying ions without mass separation is referred to as an ion doping method.

[0459] In this way, indium oxide uses a region with a low carrier concentration as the channel formation region of a transistor, and a region with a high carrier concentration as the source and drain regions of the transistor. In other words, indium oxide can be said to be an oxide capable of valence electron control. Note that IGZO may experience strain in the source and drain regions due to stress from electrodes in contact with the IGZO, resulting in the formation of n-type regions. On the other hand, unlike IGZO, indium oxide is capable of valence electron control, and therefore does not require strain to be formed in the film as with IGZO. Less strain in the film is expected to improve reliability. For example, by separately creating a region with a carrier concentration in the range R1 shown in FIG. 23A and a region with a carrier concentration in the range R2 in the indium oxide film, a so-called n-i-n junction (a junction between an n-type region, an i-type region, and an n-type region) can be created. Note that valence electron control in transistors using silicon is generally known. On the other hand, valence electron control in transistors using indium oxide is a novel technical concept that would not normally be conceived.

[0460] By using the above technical concept, the transistor having indium oxide in this specification and the like has two or more, preferably three or more, more preferably four or more, and most preferably five of the following characteristics (1) to (5): (1) high on-current (in other words, high mobility); (2) low off-current; (3) normally-off operation; (4) high reliability; and (5) high cutoff frequency (fT). For example, the transistor having indium oxide in this specification and the like has high mobility, low off-current, and is normally-off operation. The transistor has high mobility and is different from a normally-on transistor.

[0461] In addition, a semiconductor being i-type can be rephrased as having the same Fermi level (Ef) and intrinsic Fermi level (Ei) (Ef = Ei). As shown in FIG. 23B, in IGZO, the lower the carrier concentration, the smaller the hole mobility. Therefore, when Ef = Ei finally occurs, the carriers disappear (in other words, the physical properties become similar to those of an insulator), and there is a possibility that the transistor will no longer function. On the other hand, in indium oxide, as shown in FIG. 23A, the lower the carrier concentration, the larger the hole mobility. When Ef = Ei finally occurs, the hole mobility is maximized. In other words, a transistor including indium oxide can achieve high field-effect mobility by setting Ef = Ei. Note that a transistor including indium oxide is likely to be normally-off due to its low carrier concentration. Therefore, a transistor including indium oxide can be normally-off and achieve high field-effect mobility.

[0462] Note that normally-off refers to a state in which no current flows through a transistor when no potential is applied to the gate or when the gate-source voltage is 0 V. Furthermore, normally-off can be evaluated by the threshold voltage (Vth) or shift value (Vsh) of the transistor. Unless otherwise specified, Vth is calculated by a constant current method. More specifically, Vth refers to a state in which the value of drain current (Id) × channel length (L) ÷ channel width (W) in the Id-Vg characteristics of a transistor is 1 nA (1 × 10 −９ A). Vsh is the gate voltage (Vg) when the drain current (Id) in the Id-Vg characteristic of the transistor is expressed logarithmically and the tangent of the maximum slope is Id = 1 pA (1 × 10 −１２ The gate voltage (Vg) is the intersection point between the line of Id = 1 pA and the line extrapolated from two points where the slope of Id is maximum when Id is expressed logarithmically in the Id-Vg characteristics of the transistor. For example, if either or both of Vth and Vsh are zero or a positive value, the transistor can be considered to be normally-off.

[0463] In addition, in a transistor containing indium oxide, in order to make the semiconductor i-type, that is, to achieve Ef = Ei, the film structure in contact with the indium oxide film is important. For example, in a transistor containing indium oxide, a film structure in which a silicon oxide film in contact with the indium oxide film, a hafnium oxide film, and a silicon nitride film are stacked is exemplified. By using this film structure, a semiconductor device with high reliability and Ef = Ei can be obtained.

[0464] In the above film configuration, a film containing oxygen, such as a silicon oxynitride film, a silicon nitride oxide film, an aluminum oxide film, or a gallium oxide film, can be used instead of the silicon oxide film. Also, in the above film configuration, a silicon nitride oxide film, a silicon oxynitride film, or the like can be used instead of the silicon nitride film. The hafnium oxide film, which is located closer to the indium oxide film than the silicon nitride film, functions as a gettering site for hydrogen.

[0465] The above film configuration can also be considered as a stacked structure of a film (e.g., a silicon oxide film) capable of supplying oxygen to the indium oxide film from the indium oxide film side, a film (e.g., a hafnium oxide film) capable of gettering hydrogen, and a film (e.g., a silicon nitride film) that suppresses the penetration of oxygen and hydrogen. With this configuration, oxygen vacancies in the indium oxide film are filled with oxygen in the silicon oxide film. Hydrogen in the indium oxide film is captured by the hafnium oxide film by heat treatment or the like. Furthermore, the provision of the silicon nitride film results in a film configuration that reduces the penetration of oxygen and hydrogen from the outside. That is, with the above film configuration, the indium oxide film can be made closer to i-type. Therefore, a transistor having the above-described indium oxide film has high field-effect mobility and high reliability.

[0466] Next, an indium oxide film applied to a transistor will be described. The indium oxide film preferably has crystallinity (i.e., has crystal grains). Examples of films having crystal grains include single-crystal films, polycrystalline films, and amorphous films containing crystal grains (also called microcrystalline films). In particular, the indium oxide film is preferably a polycrystalline film, and more preferably a single-crystal film. A single-crystal film does not have grain boundaries. Impurities (typically, insulating impurities, insulating oxides, etc.) that hinder carrier flow tend to segregate at grain boundaries. The use of a single-crystal film can suppress carrier scattering at grain boundaries, thereby realizing a transistor exhibiting high field-effect mobility. Furthermore, the use of a single-crystal film has the excellent effect of suppressing variations in transistor characteristics due to the grain boundaries.

[0467] Furthermore, polycrystalline films are preferable because they can reduce carrier scattering and exhibit high field-effect mobility compared to microcrystalline or amorphous films. When using a polycrystalline film, it is preferable to use a film with as large a crystal grain size as possible and with few crystal grain boundaries. Note that in a transistor using an indium oxide polycrystalline film, if there is no crystal grain boundary in the channel formation region or no crystal grain boundary is observed, the channel formation region is located within a single crystal region included in the polycrystalline film, and therefore the transistor can be considered to be using single-crystal indium oxide.

[0468] The crystallinity of indium oxide can be analyzed by, for example, X-ray diffraction (XRD), transmission electron microscope (TEM), or electron diffraction (ED). Alternatively, a combination of these methods may be used for analysis.

[0469] In this specification and the like, a semiconductor layer in which no crystal grain boundary is observed in the channel formation region, a semiconductor layer in which the channel formation region is included in one crystal grain, or a semiconductor layer in which the crystal axis direction is the same in at least two regions in the channel formation region can be called a single crystal film. Also, a semiconductor layer in which, in the channel formation region, within one crystal grain, the direction of another crystal axis continuously changes around a certain crystal axis or a certain crystal orientation as the axis of rotation can be called a single crystal film.

[0470] The channel formation region refers to a region of the semiconductor layer that overlaps (or faces) the gate electrode via the gate insulating layer, and is located between the region in contact with the source electrode and the region in contact with the drain electrode. The current path in the channel formation region is the shortest distance between the source electrode and the drain electrode. Therefore, the crystal grains, crystal grain boundaries, crystal axes, crystal orientation, etc. in the channel formation region can be confirmed by observing a cross section including the semiconductor layer, the source electrode, and the drain electrode.

[0471] The indium oxide film in the channel formation region preferably has a lower impurity concentration. Impurities in the indium oxide film in the channel formation region can be a scattering source of carriers, which can lead to a decrease in field-effect mobility. These impurities can also hinder the crystal growth of the indium oxide film. Examples of impurities in the indium oxide film include boron and silicon. The indium oxide film preferably contains these impurities at concentrations of 0.1% or less, and more preferably 0.01% (100 ppm) or less. Carbon, hydrogen, and other elements may be contained in the film-forming gas or precursor during film formation, and may remain in the indium oxide film in greater amounts than the above-mentioned impurities.

[0472] The indium oxide film in the channel formation region may contain an element that can become the same trivalent cation as indium, as long as the crystal maintains a cubic crystal structure (bixbyite type). Examples of such an element include Group 13 elements of the periodic table, such as gallium and aluminum, and Group 3 elements of the periodic table. These elements exist mainly as trivalent cations in oxides, and therefore the carrier concentration of indium oxide can be maintained low.

[0473] In addition, the indium oxide film in this specification and the like has a high film density. ２ O ３ The film densities of the films are shown in Table 1.

[0474]

[0475] As shown in Table 1, the film density of the indium oxide film was evaluated at six levels, Sample 1 to Sample 6. In Table 1, Condition 1 is the condition of the base of the indium oxide film, Samples 1 to 3 are glass, Sample 4 is a SiOx film formed by sputtering, and Samples 5 and 6 are yttria-stabilized zirconia (YSZ). Condition 2 is the film formation condition of the indium oxide film, Samples 1 to 3 are film formation by sputtering (SP), and Samples 4 to 6 are film formation by ALD. Condition 3 is the heat treatment condition after the formation of the indium oxide film, with Sample 1, Sample 4, and Sample 5 being no heat treatment (as-deposited), Sample 2 being baked at 350°C in a CDA atmosphere, Sample 3 being baked at 650°C in a CDA atmosphere, and Sample 6 being baked at 250°C in a vacuum atmosphere.

[0476] In Table 1, CDA stands for clean dry air. It is preferable that the atmosphere used in the heat treatment (condition 3) after the formation of the indium oxide film contains as little hydrogen and water as possible. It is preferable to use a high-purity gas with a dew point of −60° C. or lower, preferably −100° C. or lower, as the atmosphere.

[0477] As shown in Table 1, the indium oxide film tends to have a higher film density when subjected to heat treatment compared to when not subjected to heat treatment (Sample 1, Sample 4, or Sample 5). This is because the heat treatment removes impurity elements (e.g., carbon, nitrogen, hydrogen, argon, etc.) from the film, thereby increasing the purity of the indium oxide film. Furthermore, as shown in Samples 5 and 6, the indium oxide film on YSZ has a film density of 7.00 g / cm. ３ The theoretical film density of an indium oxide film is 7.18 g / cm ３ In this specification, the range of the film density of the indium oxide film is 6.70 g / cm ３ 7.18g / cm or more ３ Preferably, it is 6.90 g / cm or less.３ 7.18g / cm or more ３ More preferably, it is 7.00 g / cm or less. ３ 7.18g / cm or more ３ The following is the result.

[0478] The film density can be evaluated by, for example, Rutherford backscattering spectroscopy (RBS) or X-ray reflectometry (XRR). Differences in film density can sometimes be evaluated by cross-sectional transmission electron microscope (TEM) images. In TEM observation, a high film density results in a dense (dark) transmission electron (TE) image, whereas a low film density results in a faint (bright) transmission electron (TE) image.

[0479] By using such an indium oxide film in a transistor, the field effect mobility of the transistor can be increased to 50 cm ２ / (V·s) or more, preferably 100 cm ２ / (V·s) or more, more preferably 150 cm ２ / (V·s) or more, more preferably 200 cm ２ / (V·s) or more, more preferably 250 cm ２ / (V·s) or more.

[0480] One of the features of an indium oxide film is that it has higher oxygen permeability (diffusibility) than an IGZO film. As shown in FIG. 23C, an indium oxide film (InO Ｘ Oxygen (O) diffusing into the indium oxide film passes through the indium oxide film and becomes oxygen molecules (O ２ ) and is released as water molecules (H ２ O) may be released in the film. Ｏ In the case where an indium oxide film is present, oxygen atoms diffuse to compensate for the oxygen vacancies. Since oxygen diffuses easily in the indium oxide film, it can be said that oxygen vacancies are more easily compensated for in the indium oxide film than in the IGZO film.

[0481] As described above, an indium oxide film can more easily reduce oxygen vacancies in the film than an IGZO film. Therefore, by using such an indium oxide film in a transistor, a transistor exhibiting extremely high reliability can be realized.

[0482] Furthermore, as shown in FIG. 23C, the indium oxide film diffuses hydrogen. Hydrogen that diffuses into the indium oxide film from the outside passes through the indium oxide film and becomes hydrogen molecules (H ２ ) or reacts with oxygen contained in the membrane and is released as water molecules.

[0483] A transistor using an indium oxide film is an accumulation-type transistor that uses electrons as majority carriers. Assuming that the carrier relaxation time is constant, the smaller the effective mass of the electrons (carriers), the higher the electron mobility. In other words, by using indium oxide, which has a small effective mass of electrons, for a transistor, the on-state current or field-effect mobility of the transistor can be increased.

[0484] Table 2 shows the results of single crystal indium oxide (here, In ２ O ３ ) and single-crystal silicon (Si). As shown in Table 2, indium oxide is characterized by a small effective mass of electrons and a large effective mass of holes. Indium oxide also has the characteristic that the effective mass of electrons is almost independent of the crystal orientation. Therefore, by using crystalline indium oxide in a transistor, a transistor with high field-effect mobility and high frequency characteristics (also called f characteristics) can be realized. Furthermore, since the effective mass of holes is large, a transistor with extremely small off-current can be realized. For example, by applying an indium oxide film to a vertical transistor, the off-current per 1 μm of channel width can be reduced to 1 fA (1×10) in an environment of 125° C. −１５ A) or less, or 1aA (1 x 10 −１８ A) or less, and under room temperature (25°C) conditions, −１８ A) or less, or 1zA (1 x 10 −２１Furthermore, as shown in Table 2, indium oxide has a smaller effective mass of electrons and a larger effective mass of holes than silicon, and therefore may be able to realize a transistor with higher field-effect mobility and lower off-state current than a Si transistor.

[0485]

[0486] It is preferable to provide a seed layer so as to be in contact with at least a portion of the crystalline indium oxide film. The seed layer is preferably made of a material containing crystals with a small difference in lattice constant (also called lattice mismatch) with indium oxide. This can improve the crystallinity of the indium oxide film. Note that a substrate (e.g., a single-crystal substrate) may be used as one of the layers in contact with at least a portion of the crystalline indium oxide film.

[0487] One method for evaluating the degree of lattice mismatch is to use the value of the lattice mismatch shown below. The lattice mismatch Δa [%] of the crystals of the formed film (here, the indium oxide film) with respect to the crystals of the seed layer is expressed as Δa = ((L １ -L ２ ) / L ２ ) × 100, where L １ is the length or lattice constant of the unit lattice vector of the crystal of the formed film, and L ２ is the length of the unit cell vector or the lattice constant of the crystal of the seed layer.

[0488] The smaller the absolute value of the lattice mismatch Δa between the seed layer and the indium oxide film, the more preferable, and it is most preferably 0. For example, Δa can be set to −5% or more and 5% or less, preferably −4% or more and 4% or less, more preferably −3% or more and 3% or less, and even more preferably −2% or more and 2% or less.

[0489] Here, the indium oxide crystal has a cubic crystal structure (bixbyite type). For example, the crystal of yttria-stabilized zirconia (YSZ) can have a cubic crystal structure (fluorite type). The lattice mismatch of the indium oxide crystal with the cubic YSZ crystal is in the range of −2% to 2%, and a single crystal film of indium oxide can be epitaxially grown on the YSZ substrate.

[0490] It should be noted that the crystal structure of the seed layer and the crystal structure of the indium oxide film may not necessarily have the same crystal system or crystal orientation. For example, a film having crystals of a hexagonal or trigonal structure may be used under an indium oxide film having crystals of a cubic structure. For example, by setting the crystal orientation of the surface of the seed layer to

[001] and the crystal orientation of the underside of the indium oxide film to

[111] , the requirements related to the crystal orientation necessary for epitaxial growth can be satisfied. Examples of hexagonal or trigonal crystals include wurtzite structure, YbFe ２ O ４ Type structure, Yb ２ Fe ３ O ７ YbFeFe alloys have the following structures: ２ O ４ Type structure or Yb ２ Fe ３ O ７ An example of a crystal having a crystalline structure is IGZO. It should be noted that a single crystal film of indium oxide can be formed not only on a YSZ substrate but also on an insulating film. On the other hand, it is difficult to form a single crystal film of silicon on an insulating film. Silicon crystals have a diamond structure. As such, indium oxide and silicon have similar properties in terms of single crystal. However, when comparing indium oxide and silicon in terms of whether they can be formed as single crystals on an insulating film, they have different properties.

[0491] This embodiment mode can be implemented by appropriately combining at least a part thereof with other embodiment modes described in this specification.

[0492] Embodiment 3 In this embodiment, a display device of one embodiment of the present invention will be described with reference to FIGS. 24A to 29. FIG.

[0493] The display device of this embodiment can be a high-resolution display device or a large-sized display device. Therefore, the display device of this embodiment can be used as a display unit for electronic devices having relatively large screens, such as television devices, desktop or notebook computers, computer monitors, digital signage, and large game machines such as pachinko machines, as well as digital cameras, digital video cameras, digital photo frames, mobile phones, portable game machines, personal digital assistants, and sound reproduction devices.

[0494] The display device of the present embodiment can be a high-definition display device, and can therefore be used, for example, as a display unit for a wristwatch-type or bracelet-type information terminal (wearable device), as well as a display unit for a wearable device that can be worn on the head, such as a head-mounted display (HMD) for VR, or a glasses-type AR device.

[0495] The display device of this embodiment may have a function as a touch panel. For example, various detection elements (also referred to as sensor elements) that can detect the proximity or contact of a detection target such as a finger can be applied to the display device.

[0496] Examples of sensor types include a capacitance type, a resistive film type, a surface acoustic wave type, an infrared type, an optical type, and a pressure-sensitive type.

[0497] The capacitance type includes, for example, a surface capacitance type and a projected capacitance type. The projected capacitance type includes, for example, a self-capacitance type and a mutual capacitance type. The mutual capacitance type is preferred because it enables simultaneous multi-point detection.

[0498] Examples of touch panels include out-cell, on-cell, and in-cell types. Note that an in-cell touch panel is a type in which electrodes constituting a detection element are provided on one or both of a substrate supporting a display element and an opposing substrate.

[0499] Various elements can be used as the display element, including, for example, a liquid crystal element and a light-emitting element. Other examples include shutter-type or optical interference-type MEMS (Micro Electro Mechanical Systems) elements, display elements using microcapsules, electrophoresis, electrowetting, or electronic liquid powder (registered trademark) methods, etc. Furthermore, a QLED (Quantum-dot LED) that uses a light source and color conversion technology using quantum dot materials can be used.

[0500] Examples of quantum dot materials used in the color conversion layer include Group 14 elements, Group 15 elements, Group 16 elements, compounds consisting of multiple Group 14 elements, compounds of an element belonging to Groups 4 to 14 and a Group 16 element, compounds of a Group 2 element and a Group 16 element, compounds of a Group 13 element and a Group 15 element, compounds of a Group 13 element and a Group 17 element, compounds of a Group 14 element and a Group 15 element, compounds of a Group 11 element and a Group 17 element, iron oxides, titanium oxides, chalcogenide spinels, and various semiconductor clusters.

[0501] Specifically, cadmium selenide, cadmium sulfide, cadmium telluride, zinc selenide, zinc oxide, zinc sulfide, zinc telluride, mercury sulfide, mercury selenide, mercury telluride, indium arsenide, indium phosphide, gallium arsenide, gallium phosphide, indium nitride, gallium nitride, indium antimonide, gallium antimonide, aluminum phosphide, aluminum arsenide, aluminum antimonide, lead selenide, lead telluride, lead sulfide, indium selenide, and tellurium Indium sulfide, indium sulfide, gallium selenide, arsenic sulfide, arsenic selenide, arsenic telluride, antimony sulfide, antimony selenide, antimony telluride, bismuth sulfide, bismuth selenide, bismuth telluride, silicon, silicon carbide, germanium, tin, selenium, tellurium, boron, carbon, phosphorus, boron nitride, boron phosphide, boron arsenide, aluminum nitride, aluminum sulfide, barium sulfide, barium selenide, barium telluride, calcium sulfide, calcium selenide Calcium, calcium telluride, beryllium sulfide, beryllium selenide, beryllium telluride, magnesium sulfide, magnesium selenide, germanium sulfide, germanium selenide, germanium telluride, tin sulfide, tin selenide, tin telluride, lead oxide, copper fluoride, copper chloride, copper bromide, copper iodide, copper oxide, copper selenide, nickel oxide, cobalt oxide, cobalt sulfide, iron oxide, iron sulfide, manganese oxide, molybdenum sulfide, vanadium oxide, tungsten oxide, tungsten oxide Examples of the quantum dots include tantalum, titanium oxide, zirconium oxide, silicon nitride, germanium nitride, aluminum oxide, barium titanate, a compound of selenium, zinc, and cadmium, a compound of indium, arsenic, and phosphorus, a compound of cadmium, selenium, and sulfur, a compound of cadmium, selenium, and tellurium, a compound of indium, gallium, and arsenic, a compound of indium, gallium, and selenium, a compound of indium, selenium, and sulfur, a compound of copper, indium, and sulfur, and combinations thereof. Also usable are so-called alloy-type quantum dots whose composition is expressed in any ratio.

[0502] Examples of quantum dot structures include core, core-shell, and core-multishell types. Quantum dots have a high proportion of surface atoms, making them highly reactive and prone to aggregation. Therefore, to prevent quantum dot aggregation and improve their dispersibility in a dispersion medium, it is preferable that a protective agent be attached to the surface of the quantum dots or that protective groups be provided. This can also reduce reactivity and make them electrically stable.

[0503] Since the band gap of quantum dots increases as their size decreases, their size can be adjusted appropriately to obtain light of the desired wavelength. As the size decreases, the emission of quantum dots shifts toward the blue side, i.e., toward higher energy, so by changing the size of the quantum dots, the emission wavelength can be adjusted across the wavelength ranges of the ultraviolet, visible, and infrared spectrums. The size (diameter) of the quantum dots is, for example, 0.5 nm or more and 20 nm or less, preferably 1 nm or more and 10 nm or less. Furthermore, the narrower the size distribution of the quantum dots, the narrower the emission spectrum, and the more excellent the color purity of the light emitted. Furthermore, the shape of the quantum dots is not particularly limited and can be spherical, rod-shaped, disc-shaped, or other shapes. Quantum rods, which are rod-shaped quantum dots, have the function of emitting directional light.

[0504] Examples of display devices using liquid crystal elements include transmissive liquid crystal display devices, reflective liquid crystal display devices, and semi-transmissive liquid crystal display devices.

[0505] Examples of modes that can be used in display devices using liquid crystal elements include vertical alignment (VA) mode, Fringe Field Switching (FFS) mode, In-Plane-Switching (IPS) mode, Twisted Nematic (TN) mode, Axially Symmetric Aligned Micro-cell (ASM) mode, Optically Compensated Birefringence (OCB) mode, Ferroelectric Liquid Crystal (FLC) mode, Anti-Ferroelectric Liquid Crystal (AFLC) mode, and Electrically Compensated Birefringence (ECB) mode. Examples of the VA mode include a Multi-Domain Vertical Alignment (MVA) mode, a Patterned Vertical Alignment (PVA) mode, and an Advanced Super View (ASV) mode.

[0506] Examples of liquid crystal materials that can be used in liquid crystal elements include thermotropic liquid crystals, low-molecular-weight liquid crystals, polymer liquid crystals, polymer-dispersed liquid crystals (PDLCs), polymer network liquid crystals (PNLCs), ferroelectric liquid crystals, and antiferroelectric liquid crystals. These liquid crystal materials exhibit cholesteric phases, smectic phases, cubic phases, chiral nematic phases, isotropic phases, blue phases, and the like, depending on the conditions. Furthermore, either positive-type or negative-type liquid crystals can be used as the liquid crystal material, and the type can be selected depending on the mode or design to be applied.

[0507] Examples of the light-emitting element include self-luminous light-emitting elements such as LEDs (Light Emitting Diodes), OLEDs (Organic LEDs), semiconductor lasers, etc. Examples of the LED that can be used include mini LEDs and micro LEDs.

[0508] The light-emitting element can emit light of infrared, red, green, blue, cyan, magenta, yellow, white, etc. Furthermore, the color purity can be improved by providing the light-emitting element with a microcavity structure.

[0509] One of a pair of electrodes included in the light-emitting element functions as an anode, and the other electrode functions as a cathode.

[0510] Note that the display device of one embodiment of the present invention can be a top-emission type in which light is emitted in a direction opposite to a substrate on which a light-emitting element is formed, a bottom-emission type in which light is emitted toward a substrate on which a light-emitting element is formed, or a dual-emission type in which light is emitted to both sides.

[0511] The above-described semiconductor device can be suitably used in a display device that is one embodiment of the present invention. The semiconductor device that is one embodiment of the present invention can be suitably used in one or both of the display portion 62 and the circuit portion 64. Furthermore, the semiconductor device that is one embodiment of the present invention can be used in both the display portion 62 and the circuit portion 64, that is, all of the transistors included in the display device can be OS transistors. By using OS transistors for all of the transistors included in the display device in this way, an effect of reducing manufacturing costs can be obtained.

[0512] The pixel size can be reduced and a high-resolution display device can be obtained by using the semiconductor device of one embodiment of the present invention for the display portion 62. Furthermore, the area occupied by the circuit portion 64 can be reduced and a display device with a narrow frame can be obtained by using the semiconductor device of one embodiment of the present invention for the circuit portion 64.

[0513] <Configuration example 1 of display device> Figure 24A shows an example of a cross section of the display device 10A when a portion of the area including the FPC 72, a portion of the circuit unit 64, a portion of the display unit 62, a portion of the connection unit 40, and a portion of the area including the end portion are cut away.

[0514] 24A includes transistors 207D, 205D, 205R, 207G, 205G, 207B, light-emitting elements 130R, 130G, and 130B between a substrate 51 and a substrate 52. The light-emitting element 130R is a display element included in the pixel 11R that emits red light, the light-emitting element 130G is a display element included in the pixel 11G that emits green light, and the light-emitting element 130B is a display element included in the pixel 11B that emits blue light.

[0515] The display device 10A employs a structure (also referred to as an SBS (Side By Side) structure) in which light-emitting layers are separately created for light-emitting elements (light-emitting devices) with different emission wavelengths. The SBS structure allows the materials and configuration to be optimized for each light-emitting element, increasing the degree of freedom in material and configuration selection and facilitating improvements in brightness and reliability.

[0516] The display device 10A is a top-emission type, which allows transistors and the like to be arranged so as to overlap the light-emitting region of the light-emitting element, thereby enabling a higher pixel aperture ratio than a bottom-emission type.

[0517] 24A shows a configuration example in which the display device shown in FIG. 1E is used in the display portion 62 and the circuit portion 64. Also, a configuration example in which the semiconductor device 80 shown in FIG. 3B is used in the display portion 62 and the circuit portion 64. Specifically, the configuration example shows a configuration in which the transistor 100 shown in FIG. 3B is used as the transistor 207D, the transistor 207G, and the transistor 207B, and the transistor 200 is used as the transistor 205D, the transistor 205R, and the transistor 205G.

[0518] The transistors 207D, 207G, and 207B each include a conductive layer 104 that functions as a gate, an insulating layer 106 that functions as a gate insulating layer, conductive layers 112a and 112b that function as a source and a drain, and a semiconductor layer 108. The transistors 205D, 205R, and 205G each include a conductive layer 204 that functions as a gate, an insulating layer 206 that functions as a gate insulating layer, conductive layers 212a and 212b that function as a source and a drain, and a semiconductor layer 208. The display device 10A also includes an insulating layer 110 and an insulating layer 210. Here, the same hatching pattern is applied to multiple layers obtained by processing the same conductive film.

[0519] Note that the structure of the transistor included in the display device of this embodiment is not particularly limited, and the display device can have a structure including at least one of a VFET, a planar transistor, a staggered transistor, and an inverted staggered transistor, for example.

[0520] The display device of this embodiment can have a structure including a Si transistor.

[0521] To increase the emission luminance of a light-emitting element included in a pixel circuit, it is necessary to increase the amount of current flowing through the light-emitting element. To achieve this, it is necessary to increase the source-drain voltage of a driving transistor included in the pixel circuit. Since an OS transistor has a higher withstand voltage between its source and drain than a Si transistor, a high voltage can be applied between the source and drain of the OS transistor. Therefore, by using an OS transistor as the driving transistor included in a pixel circuit, it is possible to increase the amount of current flowing through the light-emitting element and increase the emission luminance of the light-emitting element.

[0522] When a transistor operates in a saturation region, an OS transistor can reduce the change in source-drain current with respect to a change in gate-source voltage compared to a Si transistor. Therefore, by using an OS transistor as a driving transistor included in a pixel circuit, the current flowing between the source and drain can be precisely controlled by changing the gate-source voltage, thereby controlling the amount of current flowing to a light-emitting element. This allows a pixel circuit to have a larger number of gray levels.

[0523] In terms of the saturation of the current that flows when a transistor operates in a saturation region, an OS transistor can pass a more stable current (saturation current) than a Si transistor, even when the source-drain voltage gradually increases. Therefore, by using an OS transistor as a driving transistor, a stable current can be passed to a light-emitting element, even when the current-voltage characteristics of the light-emitting element vary. In other words, when an OS transistor operates in a saturation region, the change in the source-drain current is small even when the source-drain voltage is changed, and therefore the light-emitting luminance of the light-emitting element can be stabilized.

[0524] The transistors included in the circuit unit 64 and the transistors included in the display unit 62 may have the same structure or different structures. The transistors included in the circuit unit 64 may all have the same structure or may have two or more types. Similarly, the transistors included in the display unit 62 may all have the same structure or may have two or more types.

[0525] All the transistors included in the display portion 62 may be OS transistors, all the transistors included in the display portion 62 may be Si transistors, or some of the transistors included in the display portion 62 may be OS transistors and the rest may be Si transistors.

[0526] For example, by using both an LTPS transistor and an OS transistor in the display portion 62, a display device with low power consumption and high driving capability can be realized. A configuration in which an LTPS transistor and an OS transistor are combined is sometimes referred to as LTPO. A more preferable example is a configuration in which an OS transistor is used as a transistor that functions as a switch for controlling conduction / non-conduction between wirings, and an LTPS transistor is used as a transistor for controlling current.

[0527] For example, one of the transistors included in the display unit 62 functions as a transistor for controlling a current flowing to a light-emitting element and can also be called a driving transistor. One of the source and drain of the driving transistor is connected to a pixel electrode of the light-emitting element. It is preferable to use an LTPS transistor as the driving transistor. This allows a large current to flow to the light-emitting element in the pixel circuit.

[0528] On the other hand, another transistor included in the display unit 62 functions as a switch for controlling pixel selection / deselection and can also be called a selection transistor. The gate of the selection transistor is connected to a gate line, and one of the source and drain is connected to a source line (signal line). It is preferable to use an OS transistor as the selection transistor. This allows the gradation of pixels to be maintained even when the frame frequency is significantly low (for example, 1 fps or less), and therefore power consumption can be reduced by stopping the driver when displaying a still image.

[0529] An insulating layer 218 is provided to cover the transistor 205D, the transistor 205R, and the transistor 205G, and an insulating layer 235 is provided over the insulating layer 218. The above description of the insulating layer 218 can be referred to.

[0530] The insulating layer 235 preferably functions as a planarization layer, and is preferably an organic insulating film. Materials that can be used for the organic insulating film include acrylic resin, polyimide resin, epoxy resin, polyamide resin, polyimideamide resin, siloxane resin, benzocyclobutene-based resin, phenolic resin, and precursors of these resins. The insulating layer 235 may also have a laminated structure of an organic insulating film and an inorganic insulating film. The outermost layer of the insulating layer 235 preferably functions as an etching protection layer. This prevents recesses from being formed in the insulating layer 235 during processing of the pixel electrodes 111R, 111G, 111B, etc. Alternatively, recesses may be formed in the insulating layer 235 during processing of the pixel electrodes 111R, 111G, 111B, etc. Note that the pixel electrodes 111R, 111G, and 111B may be collectively referred to as pixel electrodes 111.

[0531] On the insulating layer 235, the light emitting elements 130R, 130G, and 130B are provided.

[0532] The light-emitting element 130R has a pixel electrode 111R on the insulating layer 235, an EL layer 113R on the pixel electrode 111R, and a common electrode 115 on the EL layer 113R. The light-emitting element 130R shown in Fig. 24A emits red light (R). The EL layer 113R has a light-emitting layer that emits red light.

[0533] The light-emitting element 130G has a pixel electrode 111G on the insulating layer 235, an EL layer 113G on the pixel electrode 111G, and a common electrode 115 on the EL layer 113G. The light-emitting element 130G shown in Fig. 24A emits green light (G). The EL layer 113G has a light-emitting layer that emits green light.

[0534] The light-emitting element 130B has a pixel electrode 111B on the insulating layer 235, an EL layer 113B on the pixel electrode 111B, and a common electrode 115 on the EL layer 113B. The light-emitting element 130B shown in Fig. 24A emits blue light (B). The EL layer 113B has a light-emitting layer that emits blue light.

[0535] 24A, the EL layers 113R, 113G, and 113B are all shown with the same thickness, but this is not limited to this. The thicknesses of the EL layers 113R, 113G, and 113B may be different. For example, it is preferable to set the thicknesses of the EL layers 113R, 113G, and 113B so that the optical path length increases the intensity of the light emitted by each layer. This allows for a microcavity structure to be realized, and the color purity of the light emitted from each light-emitting element to be increased.

[0536] The pixel electrode 111R is connected to the conductive layer 212b of the transistor 205R in an opening provided in the insulating layer 106, the insulating layer 218, and the insulating layer 235. Similarly, the pixel electrode 111G is connected to the conductive layer 212b of the transistor 205G, and the pixel electrode 111B is connected to the conductive layer 212b of the transistor 205B (not shown).

[0537] Ends of each of the pixel electrodes 111R, 111G, and 111B are covered with an insulating layer 237. The insulating layer 237 functions as a partition wall. The insulating layer 237 can be formed in a single layer structure or a stacked layer structure using one or both of an inorganic insulating material and an organic insulating material. For example, the materials that can be used for the insulating layer 218 and the insulating layer 235 can be used for the insulating layer 237. The insulating layer 237 can electrically insulate the pixel electrode and the common electrode. Furthermore, the insulating layer 237 can electrically insulate adjacent light-emitting elements from each other.

[0538] The insulating layer 237 is provided at least in the display unit 62. The insulating layer 237 may be provided not only in the display unit 62 but also in the connection unit 40 and the circuit unit 64. Furthermore, the insulating layer 237 may be provided up to the edge of the display device 10A.

[0539] The common electrode 115 is a continuous film provided in common to the light-emitting elements 130R, 130G, and 130B. The common electrode 115 shared by the plurality of light-emitting elements is connected to a conductive layer 123 provided in the connection portion 40. For the conductive layer 123, it is preferable to use a conductive layer formed from the same material and in the same process as the pixel electrodes 111R, 111G, and 111B.

[0540] In a display device according to one embodiment of the present invention, a conductive film that transmits visible light is preferably used for the pixel electrode and the common electrode, which are electrodes from which light is extracted, and a conductive film that reflects visible light is preferably used for the electrode from which light is not extracted.

[0541] A conductive film that transmits visible light may also be used for the electrode on the side from which light is not extracted. In this case, it is preferable to place the electrode between the reflective layer and the EL layer. In other words, the light emitted from the EL layer may be reflected by the reflective layer and extracted from the display device.

[0542] Materials for forming the pair of electrodes of the light-emitting element can include metals, alloys, electrically conductive compounds, and mixtures thereof, as appropriate. Specific examples of such materials include metals such as aluminum, magnesium, titanium, chromium, manganese, iron, cobalt, nickel, copper, gallium, zinc, indium, tin, molybdenum, tantalum, tungsten, palladium, gold, platinum, silver, yttrium, and neodymium, and alloys containing these metals in appropriate combination. Other examples of such materials include ITO, ITSO, In-Zn oxide, and In-W-Zn oxide. Other examples of such materials include aluminum alloys (aluminum alloys), such as an alloy of aluminum, nickel, and lanthanum (Al-Ni-La), as well as silver alloys, such as an alloy of silver and magnesium and an alloy of silver, palladium, and copper (Ag-Pd-Cu, also referred to as APC). Other examples of the material include elements belonging to Group 1 or 2 of the periodic table (e.g., lithium, cesium, calcium, and strontium) that are not exemplified above, rare earth metals such as europium and ytterbium, alloys containing appropriate combinations of these, and graphene.

[0543] The light-emitting element preferably has a micro-optical resonator (microcavity) structure. Therefore, one of the pair of electrodes of the light-emitting element is preferably an electrode that is transparent and reflective to visible light (semi-transmissive / semi-reflective electrode), and the other is preferably an electrode that is reflective to visible light (reflective electrode). By having the light-emitting element have a microcavity structure, the light emitted from the light-emitting layer can be resonated between both electrodes, thereby intensifying the light emitted from the light-emitting element.

[0544] The light transmittance of the transparent electrode is 40% or more. For example, it is preferable to use an electrode having a visible light (light with a wavelength of 400 nm or more and less than 750 nm) transmittance of 40% or more for the transparent electrode of the light-emitting element. The visible light reflectance of the semi-transmissive / semi-reflective electrode is 10% or more and 95% or less, preferably 30% or more and 80% or less. The visible light reflectance of the reflective electrode is 40% or more and 100% or less, preferably 70% or more and 100% or less. In addition, the electrical resistivity of these electrodes is 1×10 −２ Preferably, it is Ωcm or less.

[0545] The EL layers 113R, 113G, and 113B are each provided in an island shape. In FIG. 24A , the ends of adjacent EL layers 113R and 113G overlap, the ends of adjacent EL layers 113G and 113B overlap, and the ends of adjacent EL layers 113R and 113B overlap. When forming island-shaped EL layers using a fine metal mask, the ends of adjacent EL layers may overlap as shown in FIG. 24A , but this is not limited to this. In other words, adjacent EL layers may not overlap but may be spaced apart. Furthermore, the display device may have both regions where adjacent EL layers overlap and regions where adjacent EL layers do not overlap but are spaced apart.

[0546] Each of the EL layers 113R, 113G, and 113B includes at least a light-emitting layer. The light-emitting layer includes one or more light-emitting materials. As the light-emitting material, a material that emits light of a color such as blue, purple, blue-purple, green, yellow-green, yellow, orange, or red is appropriately used. Furthermore, a material that emits near-infrared light can also be used as the light-emitting material.

[0547] Examples of the light-emitting substance include a substance that emits fluorescence (fluorescent material), a substance that emits phosphorescence (phosphorescent material), a substance that exhibits thermally activated delayed fluorescence (thermally activated delayed fluorescence (TADF) material), and an inorganic compound (such as a quantum dot material).

[0548] Quantum dot materials include colloidal quantum dots, alloy quantum dots, core-shell quantum dots, and core quantum dots. Quantum dot materials containing elements from groups 2 and 16, 13 and 15, 13 and 17, 11 and 17, or 14 and 15 can also be used. Quantum dot materials containing elements such as cadmium (Cd), selenium (Se), zinc (Zn), sulfur (S), phosphorus (P), indium (In), tellurium (Te), lead (Pb), gallium (Ga), arsenic (As), and aluminum (Al) can also be used.

[0549] The light-emitting layer may contain one or more organic compounds (host materials, assist materials, etc.) in addition to a light-emitting substance (guest material). As the one or more organic compounds, one or both of a substance with high hole-transport properties (hole-transport material) and a substance with high electron-transport properties (electron-transport material) can be used. Furthermore, as the one or more organic compounds, a bipolar substance (a substance with high electron-transport properties and hole-transport properties) or a TADF material can be used.

[0550] The light-emitting layer preferably includes, for example, a phosphorescent material and a hole-transporting material and an electron-transporting material, which are a combination that easily forms an exciplex. This configuration allows efficient emission using Exciplex-Triple Energy Transfer (ExTET), which is energy transfer from the exciplex to the light-emitting material (phosphorescent material). By selecting a combination that forms an exciplex that emits light that overlaps with the wavelength of the lowest-energy absorption band of the light-emitting material, energy transfer becomes smooth, allowing efficient emission. This configuration simultaneously enables high efficiency, low-voltage operation, and long life of the light-emitting element.

[0551] In addition to the light-emitting layer, the EL layer may include one or more of a layer containing a substance with high hole-injecting properties (hole-injecting layer), a layer containing a hole-transporting material (hole-transporting layer), a layer containing a substance with high electron-blocking properties (electron-blocking layer), a layer containing a substance with high electron-injecting properties (electron-injecting layer), a layer containing an electron-transporting material (electron-transporting layer), and a layer containing a substance with high hole-blocking properties (hole-blocking layer).In addition, the EL layer may include one or both of a bipolar substance and a TADF material.

[0552] The light-emitting element can be made of either a low-molecular-weight compound or a high-molecular-weight compound, and may contain an inorganic compound. The layers constituting the light-emitting element can be formed by a method such as a vapor deposition method (including a vacuum vapor deposition method), a transfer method, a printing method, an inkjet method, or a coating method.

[0553] The light-emitting element may have a single structure (a structure having only one light-emitting unit) or a tandem structure (a structure having multiple light-emitting units). The light-emitting unit has at least one light-emitting layer. The tandem structure is a structure in which multiple light-emitting units are connected in series via a charge-generating layer. When a voltage is applied between a pair of electrodes, the charge-generating layer injects electrons into one of the two light-emitting units and holes into the other. The tandem structure allows the light-emitting element to emit light with high brightness. Furthermore, the tandem structure can reduce the current required to achieve the same brightness compared to a single structure, thereby improving reliability. The tandem structure can also be called a stack structure.

[0554] In Figure 24A, when light-emitting elements with a tandem structure are used, it is preferable that EL layer 113R has a structure having multiple light-emitting units that emit red light, EL layer 113G has a structure having multiple light-emitting units that emit green light, and EL layer 113B has a structure having multiple light-emitting units that emit blue light.

[0555] A protective layer 131 is provided on the light-emitting elements 130R, 130G, and 130B. The protective layer 131 and the substrate 52 are bonded via an adhesive layer 142. A light-shielding layer 117 is provided on the substrate 52. For example, a solid sealing structure or a hollow sealing structure can be applied to seal the light-emitting elements. In FIG. 24A , the space between the substrate 52 and the substrate 51 is filled with the adhesive layer 142, and a solid sealing structure is applied. Alternatively, the space may be filled with an inert gas (such as nitrogen or argon), and a hollow sealing structure may be applied. In this case, the adhesive layer 142 may be provided so as not to overlap with the light-emitting elements. Alternatively, the space may be filled with a resin different from the frame-shaped adhesive layer 142.

[0556] The protective layer 131 is preferably provided on at least the display unit 62, and is preferably provided so as to cover the entire display unit 62. The protective layer 131 is preferably provided so as to cover not only the display unit 62, but also the connection unit 40 and the circuit unit 64. The protective layer 131 is also preferably provided up to the edge of the display device 10A. Meanwhile, in the connection unit 197, an area where the protective layer 131 is not provided is generated in order to connect the FPC 72 and the conductive layer 166.

[0557] By providing the protective layer 131 on the light emitting elements 130R, 130G, and 130B, the reliability of the light emitting elements can be improved.

[0558] The protective layer 131 can have a single layer structure or a stacked structure of two or more layers. The conductivity of the protective layer 131 does not matter. The protective layer 131 can be formed using at least one of an insulating film, a semiconductor film, and a conductive film.

[0559] The protective layer 131 has an inorganic film, which can prevent the common electrode 115 from being oxidized, suppress impurities (moisture, oxygen, etc.) from entering the light-emitting element, and so on, thereby suppressing deterioration of the light-emitting element and improving the reliability of the display device.

[0560] The protective layer 131 preferably includes one or more inorganic insulating layers. The protective layer 131 can be made of a material that can be used for the insulating layer 110. In particular, the protective layer 131 is preferably made of a nitride or a nitride oxide, and more preferably made of a nitride.

[0561] The protective layer 131 may be an inorganic film containing ITO, In—Zn oxide, Ga—Zn oxide, Al—Zn oxide, IGZO, or the like. The inorganic film preferably has high resistance, specifically, preferably has higher resistance than the common electrode 115. The inorganic film may further contain nitrogen.

[0562] When light emitted from the light-emitting element is extracted through the protect...

Claims

1. A display device having a circuit unit and a display unit, wherein the circuit unit has a first transistor, the first transistor has a first semiconductor layer, the display unit has a display element and a pixel circuit, the pixel circuit has a second transistor, the second transistor has a second semiconductor layer, the first semiconductor layer has indium oxide, the first semiconductor layer has crystal grains, the grain size of the crystal grains is 0.3 μm or more, the second semiconductor layer contains indium, and the indium content in the first semiconductor layer is higher than the indium content in the second semiconductor layer.

2. A display device according to claim 1, wherein the second semiconductor layer contains one or more of gallium, tin, and zinc.

3. A display device according to claim 1 or claim 2, wherein the second semiconductor layer is thicker than the first semiconductor layer.

4. A semiconductor device comprising a circuit unit and a display unit, wherein the circuit unit comprises a first transistor, wherein the first transistor comprises a first semiconductor layer, a first conductive layer, and a second conductive layer, wherein the display unit comprises a display element and a pixel circuit, wherein the pixel circuit comprises a second transistor, wherein the second transistor comprises a second semiconductor layer, a third conductive layer, and a fourth conductive layer, wherein a first insulating layer is provided on the first conductive layer, wherein the second conductive layer and the third conductive layer are provided on the first insulating layer, wherein the second conductive layer and the first insulating layer have a first opening that reaches the first conductive layer, wherein the first semiconductor layer has a region in contact with an upper surface of the first conductive layer, a side surface of the first insulating layer, and a side surface of the second conductive layer in the first opening, and wherein a second insulating layer is provided on the second conductive layer, the third conductive layer, and the first insulating layer, a fourth conductive layer provided on the second insulating layer; the fourth conductive layer and the second insulating layer have a second opening reaching the third conductive layer; the second semiconductor layer has a region in the second opening that contacts an upper surface of the second conductive layer, a side surface of the second insulating layer, and a side surface of the fourth conductive layer; the first semiconductor layer contains indium oxide; the first semiconductor layer has crystal grains, the grain size of the crystal grains being 0.3 μm or more; the second semiconductor layer contains indium; and the indium content in the first semiconductor layer is higher than the indium content in the second semiconductor layer.

5. A display device according to claim 4, wherein the second semiconductor layer contains one or more of gallium, tin, and zinc.

6. A display device according to claim 4 or 5, wherein the thickness of the second semiconductor layer is greater than the thickness of the first semiconductor layer.

7. A display device according to claim 4 or claim 5, wherein the first transistor has a first gate insulating layer and a first gate electrode, the second transistor has a second gate insulating layer and a second gate electrode, the first gate electrode has a region in the first opening that faces the first semiconductor layer with the first gate insulating layer interposed therebetween, and the second gate electrode has a region in the second opening that faces the second semiconductor layer with the second gate insulating layer interposed therebetween.

8. A display device according to claim 7, wherein the first gate insulating layer does not have a region in contact with the second semiconductor layer.

9. A display device according to claim 4 or claim 5, wherein the first insulating layer has a third insulating layer and a fourth insulating layer on the third insulating layer, the second insulating layer has silicon and nitrogen, and the third insulating layer has silicon and oxygen.

10. A display device according to claim 9, wherein the second insulating layer comprises a fifth insulating layer and a sixth insulating layer on the fifth insulating layer, the fifth insulating layer comprises silicon and nitrogen, and the sixth insulating layer comprises silicon and oxygen.

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