Semiconductor device and method for producing semiconductor device

Abstract

A semiconductor device 10 includes: a semiconductor chip 12; a circuit element layer 14 comprising a circuit element 14A; and a redistribution wiring layer 13 comprising a redistribution wire 13A connected to the circuit element 14A and the semiconductor chip 12.

Description

Semiconductor device and manufacturing method thereof

[0001] The technology disclosed in this specification relates to a semiconductor device and a method for manufacturing the semiconductor device that allows for larger substrates and lower costs.

[0002] Conventionally, semiconductor devices disclosed in the following Patent Documents 1 and 2 are known. The semiconductor device disclosed in Patent Document 1 is a semiconductor device mounted with a semiconductor chip including an output transistor that converts an input voltage into a first voltage and outputs the first voltage, wherein the semiconductor chip includes a first electrode pad connected to an output terminal of the output transistor and a second electrode pad connected to the output terminal via an internal resistance, the semiconductor device includes a first through electrode and a rewiring that connects the first electrode pad to an external terminal of the semiconductor device, and a second through electrode that connects the second electrode pad to the rewiring, and the semiconductor chip includes an error amplifier that generates an error voltage between the first voltage and a negative feedback voltage and controls the output transistor to convert an input voltage inputted into the first voltage based on the error voltage, and a switching unit that selectively outputs either a second voltage at the first electrode pad or a third voltage at the second electrode pad to the error amplifier as a negative feedback voltage.

[0003] The modulation device (semiconductor device) described in Patent Document 2 includes a substrate, a modulation section arranged on the substrate, data lines arranged on the substrate and electrically connected to the modulation section, and scanning lines arranged on the substrate and having overlapping regions that overlap with the data lines and non-overlapping regions that do not overlap with the data lines, and in a first direction, the scanning lines have a first width in the overlapping regions and a second width in the non-overlapping regions, the first width being smaller than the second width.

[0004] JP 2016-111262 A

[0005] US Patent Application Publication No. 2023 / 0238390

[0006] (Problem to be Solved by the Invention) In the semiconductor device described in the above-mentioned Patent Document 1, a switch for inspecting whether or not there is a break in the rewiring is formed by utilizing the free space in the semiconductor chip. However, forming the switch on the semiconductor chip requires a design change of the existing semiconductor chip, and there are problems in that it cannot be implemented when there is no free space in the semiconductor chip.

[0007] In contrast, in the modulation device described in Patent Document 2, circuit elements such as a modulation section and transistors are provided on the first surface of a substrate, and a chip is provided on the second surface of the substrate. Therefore, compared to Patent Document 1, Patent Document 2 does not require chip design changes, and circuit elements can be provided on the first surface of the substrate even if there is no free space within the chip. However, Patent Document 2 requires vias to be formed through the substrate to connect the chip and the circuit elements. Therefore, if the substrate thermally expands or contracts due to changes in the thermal environment, the position of the vias will change. The amount of such via position change increases as the substrate becomes larger, which has been a problem when attempting to increase the size of the substrate. If the substrate cannot be made larger, it will be difficult to reduce manufacturing costs.

[0008] The technology described in this specification was developed based on the above circumstances, and aims to increase the size of the substrate while reducing costs.

[0009] (Means for solving the problem) (1) A semiconductor device related to the technology described in this specification includes a semiconductor chip, a circuit element layer including circuit elements, and a rewiring layer including rewiring connected to the circuit elements and the semiconductor chip.

[0010] (2) In addition to the above (1), the semiconductor device may be configured such that the rewiring layer is disposed above the circuit element layer and below the semiconductor chip.

[0011] (3) In addition to the above (2), the semiconductor device may further include a switching element in the circuit element.

[0012] (4) In addition to the above (3), the semiconductor device may be configured such that the switching element is connected to an external testing device and a testing signal is input by the testing device.

[0013] (5) In addition to the above (3), the semiconductor device may be configured such that the switching element is connected to an external power supply and receives a power supply voltage from the power supply.

[0014] (6) In addition to the above (3), the semiconductor device may be configured such that the switching element is connected to ground.

[0015] (7) In addition to any one of (4) to (6), the semiconductor device may further include a semiconductor portion made of an oxide semiconductor material.

[0016] (8) In addition to any one of (4) to (6), the semiconductor device may further include a semiconductor portion made of polysilicon material.

[0017] (9) In addition to any one of (3) to (8), the semiconductor device may further include a ground-connected diode in the circuit element.

[0018] (10) In addition to any one of (3) to (9), the semiconductor device may further include a capacitor connected to ground in the circuit element.

[0019] (11) In addition to any one of (1) to (10) above, the semiconductor device may further include a dummy circuit element in the circuit element layer that is not connected to the semiconductor chip and the rewiring.

[0020] (12) In addition to any one of (1) to (11), the semiconductor device may also include a substrate having a first main surface and a second main surface, and the semiconductor chip, the circuit element layer, and the rewiring layer may be provided on the first main surface of the substrate.

[0021] (13) A method for manufacturing a semiconductor device according to the technology described in this specification includes providing a circuit element layer including circuit elements, providing a rewiring layer including rewiring connected to the circuit elements, and providing a semiconductor chip connected to the rewiring.

[0022] (14) In addition to the above (13), the method for manufacturing a semiconductor device may further include providing the rewiring layer above the circuit element layer, and providing the semiconductor chip above the rewiring layer.

[0023] (15) In addition to the above (14), the manufacturing method of the semiconductor device may further include providing a switching element as the circuit element, connecting the switching element to an external inspection device before providing the semiconductor chip, and inputting an inspection signal from the inspection device to the switching element to inspect the rewiring.

[0024] (16) In addition to the above (15), the manufacturing method of the semiconductor device may further include connecting the switching element to an external inspection device after providing the semiconductor chip, and inputting an inspection signal from the inspection device to the switching element to inspect the rewiring.

[0025] (17) In addition to the above (15) or (16), the method for manufacturing the semiconductor device further includes the steps of: providing the circuit element layer on each of the first main surfaces of a plurality of substrates among a mother substrate including a plurality of substrates having a first main surface and a second main surface; providing the rewiring layer on each of the first main surfaces of the plurality of substrates among the mother substrate; providing the semiconductor chip on each of the first main surfaces of the plurality of substrates among the mother substrate; and manufacturing a plurality of semiconductor devices by dividing the mother substrate into each of the plurality of substrates, wherein when providing the circuit element layer on the mother substrate, the circuit element layer includes a plurality of first wirings extending along a first direction so as to straddle the plurality of substrates and arranged at intervals corresponding to the substrates in a second direction intersecting the first direction; and a first signal supply unit disposed at an end of the motherboard in the first direction and connected to the plurality of first wirings; and a second signal supply unit disposed at an end of the motherboard in the second direction and connected to the plurality of second wirings. A plurality of switching elements are provided at locations where the first wirings and the second wirings intersect, and the first wirings and the second wirings are connected to the switching elements. When inspecting the rewiring, the first signal supply unit and the second signal supply unit may be connected to the external inspection device, and scanning signals may be output from the first signal supply unit to the plurality of first wirings in sequence, and the switching elements connected to the first wirings may be driven in sequence, while the inspection signals may be output from the second signal supply unit to the plurality of second wirings, and the inspection signals may be input to the rewirings via the switching elements connected to the second wirings and in a driven state.

[0026] (18) In addition to any of (13) to (17), the method for manufacturing the semiconductor device may also include a step of providing the circuit element layer, the redistribution layer, and the semiconductor chip on a first main surface of a substrate having a first main surface and a second main surface, and then peeling off the substrate.

[0027] Effect of the Invention According to the technology described in this specification, it is possible to increase the size of the substrate and reduce costs.

[0028] FIG. 1 is a perspective view showing an outline of a semiconductor device according to a first embodiment; FIG. 1 is a cross-sectional view showing an outline of a semiconductor device according to a first embodiment; FIG. 1 is a cross-sectional view of a semiconductor device according to a first embodiment; 10 is a plan view showing a state where the semiconductor device has been mounted; FIG. 11 is a circuit diagram showing the relationship between the diode, rewiring, and semiconductor chip provided in the semiconductor device according to the fourth embodiment and the external DC power supply and ground; FIG. 12 is a cross-sectional view of the semiconductor device according to the fourth embodiment; FIG. 13 is a circuit diagram showing the relationship between the capacitor, rewiring, and semiconductor chip provided in the semiconductor device according to the fifth embodiment and the external DC power supply and ground; FIG. 14 is a cross-sectional view of the semiconductor device according to the fifth embodiment;

[0029] First Embodiment A first embodiment will be described with reference to Figures 1 to 8. In this embodiment, a semiconductor device 10 will be illustrated. Note that the description of the up-down direction is based on Figures 2, 3, 5, and 6.

[0030] 1, the semiconductor device 10 according to this embodiment uses chiplet technology and has multiple semiconductor chips 12 mounted on a single substrate 11. Examples of chiplet technology that can be used include "SiP (System in Package)," which is a method of combining multiple semiconductor chips 12 into a single package, "2.5-dimensional packaging," which is a method of connecting multiple semiconductor chips 12 via a connecting semiconductor chip, and "3-dimensional packaging," which is a method of stacking and connecting semiconductor chips 12 in a three-dimensional manner. The multiple semiconductor chips 12 include, for example, logic semiconductors, memories such as DRAMs (Dynamic Random Access Memory) and flash memories, analog ICs (Integrated Circuits), RFICs (Radio Frequency Integrated Circuits), and power semiconductors.

[0031] As shown in FIG. 2 , the substrate 11 included in the semiconductor device 10 has a first main surface 11A facing the front side (upper side in FIG. 2 ) and a second main surface 11B facing the back side (lower side in FIG. 2 ). A redistribution layer 13 to which the semiconductor chip 12 is connected is provided on the first main surface 11A of the substrate 11. A circuit element layer 14 is provided on the first main surface 11A of the substrate 11. In this embodiment, the circuit element layer 14 is disposed on the first main surface 11A of the substrate 11 as an underlying layer and is disposed below the redistribution layer 13. The redistribution layer 13 is located above the circuit element layer 14 and below the semiconductor chip 12. The semiconductor chip 12 is flip-chip mounted to the redistribution layer 13 on the first main surface 11A of the substrate 11. Electrodes (not shown) and solder balls (solder bumps) 12A connected to the electrodes are provided on the surface of the semiconductor chip 12 facing the redistribution layer 13, and the solder balls 12A are connected to the redistribution layer 13. A semiconductor device 10 including such a redistribution layer 13 can be efficiently manufactured using fan-out wafer level packaging (FOWLP) or fan-out panel level packaging (FOPLP). The semiconductor device 10 includes a molded portion 34 disposed on the first main surface 11A of the substrate 11 above the semiconductor chip 12. The molded portion 34 is made of a synthetic resin with excellent insulating properties and is molded to cover the semiconductor chip 12 mounted on the upper side of the redistribution layer 13 from above.

[0032] As shown in FIG. 3 , the rewiring layer 13 includes rewirings 13A and interlayer insulating material (build-up film) 13B. The rewiring layer 13 includes multiple rewirings 13A and multiple interlayer insulating material 13B, with the rewirings 13A and the interlayer insulating material 13B alternately stacked. The rewirings 13A are made of a metal material (e.g., copper) and are formed into a predetermined wiring pattern by, for example, plating the surface of the interlayer insulating material 13B. For this reason, the thickness of the rewirings 13A is, for example, approximately 10 μm. The multiple rewirings 13A are arranged in different layers above and below, with the interlayer insulating material 13B interposed between them. Multiple rewirings 13A may be provided on the same layer as different (electrically independent) wiring patterns. The rewirings 13A located in the uppermost layer of the multiple rewirings 13A are connected to solder balls 12A of the semiconductor chip 12. Among the multiple rewirings 13A, the rewirings 13A located in the lowest layer include those connected to circuit elements 14A included in the circuit element layer 14, which will be described later. The interlayer insulating material 13B is made of an insulating resin material and is in the form of a film. The interlayer insulating material 13B has multiple through holes (vias) 13B1 formed at predetermined positions. The multiple through holes 13B1 are arranged in positions overlapping the rewirings 13A within the main surface of the interlayer insulating material 13B. The rewirings 13A are also formed within the through holes 13B1. Therefore, the two rewirings 13A arranged above and below the interlayer insulating material 13B are connected to each other through the through holes 13B1. The through holes 13B1 are formed, for example, by laser processing the interlayer insulating material 13B.

[0033] The substrate 11 is made of, for example, a glass material, and has a plurality of through holes 11C formed at predetermined positions, as shown in FIG. 3 . A portion of the rewirings 13A located in the lowest layer among the plurality of rewirings 13A described above is formed within the through holes 11C. A plurality of solder balls 15 are provided on the second main surface 11B of the substrate 11 at positions overlapping the plurality of through holes 11C. The solder balls 15 are connected to the rewirings 13A within the through holes 11C. The solder balls 15 are arranged, for example, in a grid pattern on the second main surface 11B of the substrate 11. Thus, the semiconductor device 10 according to this embodiment is a package known as a "BGA (Ball Grid Array)."

[0034] The circuit element layer 14 is formed on the substrate 11 using a known photolithography method, using the first main surface 11A as a base, as shown in FIG. 3 , and includes circuit elements 14A. The circuit elements 14A according to this embodiment include thin film transistors (TFTs) 16. In this embodiment, the TFTs 16 are switching elements used for testing. The TFTs 16 are connected to the rewirings 13A and an external testing device IN (see FIG. 7 ), and testing signals are input from the testing device IN. The number of TFTs 16 is the same as the number of rewirings 13A to be tested, and in this embodiment, a plurality of TFTs 16 are provided. The plurality of TFTs 16 includes TFTs connected to the semiconductor chip 12 via the rewirings 13A. The TFTs 16 each have a gate electrode 16A, a source electrode 16B, a drain electrode 16C, and a semiconductor portion 16D. The circuit element layer 14 includes, in addition to the TFTs 16, a buffer insulating film 17, a gate insulating film 18, and a first interlayer insulating film 19. The buffer insulating film 17 is made of an inorganic resin material such as silicon nitride or silicon oxide and is disposed in contact with the first main surface 11A of the substrate 11. The gate electrode 16A of the TFT 16 is disposed above the buffer insulating film 17. The gate electrode 16A is formed by patterning a first metal film deposited on the buffer insulating film 17 using photolithography. The first metal film is a single-layer film made of one type of metal material selected from copper, titanium, aluminum, molybdenum, tungsten, etc., or a laminated film or alloy made of different types of metal materials, and its thickness is, for example, approximately tens to hundreds of nanometers. In other words, the thickness of the first metal film is much smaller than the thickness of the rewiring 13A. The gate insulating film 18 is made of an inorganic resin material such as silicon nitride or silicon oxide and is disposed above the gate electrode 16A. A semiconductor portion 16D of the TFT 16 is disposed on the upper layer side of the gate insulating film 18. The semiconductor portion 16D is disposed so as to overlap the gate electrode 16A in a plan view with the gate insulating film 18 interposed therebetween. The semiconductor portion 16D is formed by patterning a semiconductor film formed on the gate insulating film 18 by photolithography.

[0035] The semiconductor film constituting the semiconductor portion 16D of the TFT 16 is made of an oxide semiconductor material. The semiconductor film may contain at least one metal element selected from the group consisting of In, Ga, and Zn, and may be, for example, an In—Ga—Zn—O-based semiconductor (e.g., indium gallium zinc oxide). Here, the In—Ga—Zn—O-based semiconductor is a ternary oxide of In (indium), Ga (gallium), and Zn (zinc). The ratio (composition ratio) of In, Ga, and Zn is not particularly limited, and may include, for example, In:Ga:Zn=2:2:1, In:Ga:Zn=1:1:1, In:Ga:Zn=1:1:2, etc. The In—Ga—Zn—O-based semiconductor used in the semiconductor film may be amorphous or crystalline. The semiconductor film may contain other oxide semiconductors instead of the In—Ga—Zn—O-based semiconductor. For example, an In—Sn—Zn—O-based semiconductor (e.g., In ２ O ３ -SnO ２In—Sn—Zn—O based semiconductors may contain In (indium), Sn (tin), and Zn (zinc). Alternatively, the oxide semiconductor layer may include an In—W—Zn—O-based semiconductor containing W (tungsten), an In—W—Sn—Zn—O-based semiconductor, an In—Al—Zn—O-based semiconductor, an In—Al—Sn—Zn—O-based semiconductor, a Zn—O-based semiconductor, an In—Zn—O-based semiconductor, a Zn—Ti—O-based semiconductor, a Cd—Ge—O-based semiconductor, a Cd—Pb—O-based semiconductor, CdO (cadmium oxide), an Mg—Zn—O-based semiconductor, an In—Ga—Sn—O-based semiconductor, an In—Ga—O-based semiconductor, a Zr—In—Zn—O-based semiconductor, an Hf—In—Zn—O-based semiconductor, an Al—Ga—Zn—O-based semiconductor, a Ga—Zn—O-based semiconductor, or an In—Ga—Zn—Sn—O-based semiconductor. The oxide semiconductor material of the semiconductor film has a characteristic of having a higher resistance value when no voltage is applied (off state), i.e., a lower off-leakage current, compared to polysilicon semiconductor material. This sufficiently suppresses current leakage from the rewiring 13A, thereby minimizing defects caused by the TFT 16 remaining in the semiconductor device 10. Furthermore, the oxide semiconductor material of the semiconductor film has a higher electron mobility than amorphous silicon semiconductor material. The film thickness of the semiconductor film is, for example, approximately several tens to several hundreds of nanometers. In other words, the thickness of the semiconductor film is much smaller than the thickness of the rewiring 13A.

[0036] As shown in FIG. 3 , the TFT 16 according to this embodiment is a bottom-gate type in which the gate electrode 16A is located below the semiconductor portion 16D. A source electrode 16B and a drain electrode 16C are disposed above the semiconductor portion 16D. The source electrode 16B is connected to one end of the semiconductor portion 16D. The drain electrode 16C is connected to the other end of the semiconductor portion 16D (the side opposite the source electrode 16B). The source electrode 16B and the drain electrode 16C are disposed at a predetermined distance on the semiconductor portion 16D. The source electrode 16B and the drain electrode 16C are formed by patterning a second metal film formed on the semiconductor portion 16D using a photolithography method. The second metal film is a single-layer film made of one type of metal material selected from copper, titanium, aluminum, molybdenum, tungsten, etc., or a laminated film or alloy made of different types of metal materials, and its thickness is, for example, approximately several tens to several hundreds of nanometers. In other words, the thickness of the second metal film is much smaller than the thickness of the rewiring 13A. The TFT 16 configured as described above is driven by supplying a potential higher than the threshold voltage to the gate electrode 16A. When the TFT 16 is driven, a channel region is generated in the semiconductor portion 16D, allowing charges to move between the source electrode 16B and the drain electrode 16C via the channel region.

[0037] The first interlayer insulating film 19 is made of an inorganic resin material such as silicon nitride or silicon oxide, and is disposed above the source electrode 16B and the drain electrode 16C, as shown in FIG. 3 . A first contact hole H1 and a second contact hole H2 are formed in the first interlayer insulating film 19 at positions overlapping the source electrode 16B and the drain electrode 16C, respectively. The first contact hole H1 is disposed so as to overlap a portion of the source electrode 16B that does not overlap the semiconductor portion 16D. A portion of the rewiring 13A located in the lowest layer of the multiple rewirings 13A included in the rewiring layer 13 is formed within the first contact hole H1. The rewiring 13A disposed within the first contact hole H1 is connected to the source electrode 16B. The second contact hole H2 is disposed so as to overlap a portion of the drain electrode 16C that does not overlap the semiconductor portion 16D. A portion of the rewiring 13A located in the lowest layer of the multiple rewirings 13A included in the rewiring layer 13 is formed in the second contact hole H2. The rewiring 13A arranged in the second contact hole H2 is connected to the drain electrode 16C. The rewiring 13A connected to the drain electrode 16C is an object to be inspected by an inspection device IN, which will be described later. Although not shown, a gate contact hole is provided through the gate insulating film 18 and the first interlayer insulating film 19 at a position overlapping a portion of the gate electrode 16A. A portion of the rewiring 13A located in the lowest layer of the multiple rewirings 13A included in the rewiring layer 13 is formed in the gate contact hole, and the rewiring 13A arranged in the gate contact hole is connected to the gate electrode 16A.

[0038] As shown in FIG. 3 , the buffer insulating film 17, the gate insulating film 18, and the first interlayer insulating film 19 are provided with through-holes H3 that communicate with predetermined through-holes 11C in the substrate 11. A portion of the rewiring 13A located in the lowest layer among the plurality of rewirings 13A included in the rewiring layer 13 is formed in the through-hole H3 and in the through-hole 11C that communicates with the through-hole H3. The rewiring 13A formed across the through-hole H3 and the through-hole 11C that communicates with the through-hole H3 is connected to a solder ball 15 provided on the second main surface 11B of the substrate 11. A plurality of the through-holes H3 and the through-holes 11C that communicate with each other are provided, and a rewiring 13A is formed therein. The plurality of rewirings 13A formed in the through-holes H3 and the through-holes 11C that communicate with each other include a rewiring 13A that is connected to the source electrode 16B through the first contact hole H1. The rewirings 13A formed inside the communicating holes H3 and through holes 11C that are connected to each other include rewirings 13A connected to the gate electrode 16A through the gate contact hole. Of the rewirings 13A, the rewirings 13A connected to the gate electrode 16A, the rewirings 13A connected to the source electrode 16B, and the rewirings 13A connected to the drain electrode 16C are each configured to be connected to an external inspection device IN (see FIG. 7). The rewirings 13A connected to the drain electrode 16C may be connected to the semiconductor chip 12 (see FIG. 8).

[0039] According to this embodiment, as shown in FIG. 2 , the semiconductor device 10 includes a rewiring layer 13 including rewirings 13A connected to the circuit elements 14A and the semiconductor chip 12. Therefore, compared to the conventional case where the chip and the circuit elements are connected through vias provided in the substrate, where via positional fluctuations due to thermal expansion and contraction of the substrate become an issue, problems associated with increasing the size of the substrate 11 are less likely to occur. This makes it suitable for increasing the size of the substrate 11. Increasing the size of the substrate 11 is also suitable for reducing manufacturing costs. Furthermore, because the thickness of the metal film or semiconductor film formed by photolithography to form the circuit elements 14A is much smaller than the thickness of the rewirings 13A, warping of the substrate 11 is less likely to occur even when the substrate 11 is increased in size, which also makes it suitable for increasing the size of the substrate 11.

[0040] Furthermore, the rewiring layer 13 is disposed above the circuit element layer 14 and below the semiconductor chip 12. Because the circuit element layer 14 is disposed below the rewiring layer 13, the circuit elements 14A are connected to the rewiring 13A during fabrication, i.e., before the semiconductor chip 12 is disposed above the rewiring layer 13. In this embodiment, the circuit elements 14A are provided as test TFTs 16, enabling inspection of the rewiring 13A before the semiconductor chip 12 is disposed. Since the rewiring 13A can be inspected before the semiconductor chip 12 is disposed, the yield of the semiconductor device 10 can be improved. Improved yield is also advantageous for increasing the size of the substrate 11. Furthermore, the rewiring 13A and the semiconductor chip 12 can be inspected during and after the semiconductor chip 12 is disposed.

[0041] This embodiment has the above-described structure, and a method for manufacturing the semiconductor device 10 will now be described. As shown in FIG. 4 , the semiconductor device 10 is manufactured through a substrate formation process S1, a circuit element layer formation process S2, a rewiring layer formation process S3, a first inspection process S4, a semiconductor chip mounting process S5, a second inspection process S6, and a molding process S7. In the substrate formation process S1, a substrate 11 made of a glass material is formed by a known method. Through holes 11C are opened and formed at predetermined positions in the substrate 11.

[0042] The term "patterning" refers to film processing based on a general photolithography method. Specifically, the processing of the film to be processed, i.e., patterning, is performed by forming a photoresist film on the film to be processed, exposing the photoresist film using an exposure device through a photomask having a predetermined opening pattern, developing the photoresist film, and then etching the developed photoresist film.

[0043] In the circuit element layer formation process S2, a buffer insulating film 17 is first formed on the first main surface 11A of the substrate 11, a first metal film is formed on the upper side thereof, and the first metal film is then patterned by a typical photolithography method. This forms the gate electrode 16A. A gate insulating film 18 is then formed on the upper side of the gate electrode 16A, and a semiconductor film is then formed on the upper side thereof, and the semiconductor film is then patterned by a typical photolithography method. This forms the semiconductor portion 16D. A second metal film is then formed on the upper side of the semiconductor portion 16D, and the second metal film is then patterned by a typical photolithography method. This forms the source electrode 16B and the drain electrode 16C. A first interlayer insulating film 19 is then formed on the upper side of the source electrode 16B and the drain electrode 16C, and the first interlayer insulating film 19 is then patterned by a typical photolithography method. At this time, the buffer insulating film 17 and the gate insulating film 18 are also patterned by using the photoresist film for patterning the first interlayer insulating film 19 as a mask. As a result, a first contact hole H1 and a second contact hole H2 are formed in the first interlayer insulating film 19, as shown in Fig. 5, and a through hole H3 is formed in the buffer insulating film 17, the gate insulating film 18, and the first interlayer insulating film 19. In this way, the circuit element layer 14 including the TFTs 16, which are circuit elements 14A, is formed on the first main surface 11A of the substrate 11.

[0044] In the rewiring layer formation process S3, as shown in FIG. 6 , rewirings 13A located in the bottom layer are formed on the circuit element layer 14 by a plating process or other method. The multiple rewirings 13A formed at this time include rewirings 13A connected to the source electrode 16B through the first contact hole H1 and formed inside the communicating hole H3 and the through hole 11C that communicate with each other, and rewirings 13A connected to the drain electrode 16C through the second contact hole H2. An interlayer insulating material 13B is then formed on the bottom rewirings 13A. The formed interlayer insulating material 13B is laser processed to form through holes 13B1 at predetermined positions. The surface of the formed interlayer insulating material 13B is then plated or other method to form the rewirings 13A in the second layer from the bottom. The rewirings 13A formed at this time include rewirings 13A connected to the bottom rewirings 13A through the through holes 13B1. Thereafter, interlayer insulating material 13B and rewiring 13A are alternately formed, and the uppermost rewiring 13A is formed, thereby forming a rewiring layer 13 on the first main surface 11A of the substrate 11.

[0045] In the first inspection step S4, as shown in FIG. 7 , an external inspection device IN is connected to the TFT 16, which is a circuit element 14A of the circuit element layer 14. In FIG. 7 , the rewiring 13A to be inspected is illustrated with a circuit symbol of a "resistor." When the inspection device IN supplies a potential higher than the threshold voltage to the rewiring 13A connected to the gate electrode 16A of the TFT 16, the TFT 16 is driven, and a channel region is generated in the semiconductor portion 16D. Synchronously with this timing, the inspection device IN supplies an inspection signal to the rewiring 13A connected to the source electrode 16B of the TFT 16. The inspection signal is transmitted from the source electrode 16B to the drain electrode 16C via the channel region of the semiconductor portion 16D and is then supplied to the rewiring 13A to be inspected. At this time, if no open circuit has occurred in the rewiring 13A to be inspected, the inspection signal is detected by the inspection device IN. On the other hand, if an open circuit has occurred in the rewiring 13A to be inspected, the inspection signal is not detected by the inspection device IN. In this way, whether or not a break has occurred in the rewiring 13A being inspected can be determined based on whether or not the inspection signal is detected by the inspection device IN. In particular, in this embodiment, the first inspection process S4 is performed before the semiconductor chip mounting process S5, and the rewiring 13A is inspected using the TFT 16 (circuit element 14A) connected to the rewiring 13A before the semiconductor chip 12 is mounted. Therefore, if a break has occurred in the rewiring 13A being inspected, the rewiring 13A can be repaired or the work-in-progress can be discarded. This makes it less likely that a semiconductor chip 12 will be connected to a rewiring 13A with a break, thereby improving yield.

[0046] In the semiconductor chip mounting process S5, as shown in FIG. 3 , the semiconductor chip 12 is placed on the rewiring layer 13, and the solder balls 12A provided on the surface of the semiconductor chip 12 facing the rewiring layer 13 are brought into contact with the rewirings 13A located in the uppermost layer of the rewiring layer 13. In this state, the solder balls 12A are bonded to the rewirings 13A located in the uppermost layer. This connects the semiconductor chip 12 to the rewirings 13A. In this manner, the semiconductor chip 12 is provided on the first main surface 11A of the substrate 11. As described above, according to this embodiment, the circuit element layer 14, the rewiring layer 13, and the semiconductor chip 12 are provided, and the semiconductor chip 12 is connected to the TFTs 16, which are the circuit elements 14A, via the rewirings 13A. Therefore, when connecting the semiconductor chip 12 to the TFTs 16, which are the circuit elements 14A, there is no need to provide vias in the substrate as in the conventional method, and there is no need to consider via positional fluctuations due to thermal expansion and contraction of the substrate. This is advantageous for increasing the size of the substrate 11. If the substrate 11 can be made larger, it is also advantageous in terms of reducing manufacturing costs.

[0047] In the second inspection process S6, as shown in FIG. 8 , an external inspection device IN is connected to the TFT 16, which is a circuit element 14A of the circuit element layer 14. In FIG. 8 , the rewiring 13A and the semiconductor chip 12 to be inspected are each illustrated as a "resistor" circuit symbol. When the inspection device IN supplies a potential higher than the threshold voltage to the rewiring 13A connected to the gate electrode 16A of the TFT 16, the TFT 16 is driven, and a channel region is generated in the semiconductor portion 16D. In synchronization with this timing, the inspection device IN supplies an inspection signal to the rewiring 13A connected to the source electrode 16B of the TFT 16. The inspection signal is transmitted from the source electrode 16B to the drain electrode 16C via the channel region of the semiconductor portion 16D and then supplied to the semiconductor chip 12 to be inspected via the rewiring 13A connected to the drain electrode 16C. If no defects are present in the semiconductor chip 12 to be inspected, the inspection signal is detected by the inspection device IN. On the other hand, if a defect occurs in the semiconductor chip 12 being inspected, the inspection signal will not be detected by the inspection device IN. Thus, whether or not a defect occurs in the semiconductor chip 12 being inspected can be determined based on whether or not the inspection signal is detected by the inspection device IN. In particular, in this embodiment, the first inspection process S4 is performed before the semiconductor chip mounting process S5, and the rewiring 13A is inspected using the TFT 16 (circuit element 14A) connected to the rewiring 13A before the semiconductor chip 12 is mounted. Therefore, the inspection results of the semiconductor chip 12 in the second inspection process S6 are prevented from reflecting any defect in the rewiring 13A, making it possible to distinguish between defects in the semiconductor chip 12 and defects in the rewiring 13A. If a defect occurs in the semiconductor chip 12, the yield can be improved by replacing the semiconductor chip 12, for example.

[0048] In the molding process S7, as shown in FIG. 2, a molded portion 34 is formed by molding. The molded portion 34 is formed by disposing a molded resin material so as to cover the semiconductor chip 12 connected to the rewiring 13A from above and then hardening the molded resin material. This molding process S7 is performed after the first inspection process S4 and the second inspection process S6, so there are no defects in the rewiring 13A and the semiconductor chip 12 covered by the molded portion 34. Therefore, compared to the case where the second inspection process S6 is performed after the molding process S7, which requires removing the molded portion 34 to replace the semiconductor chip 12, this process not only eliminates the labor involved but also improves yield.

[0049] As described above, the semiconductor device 10 of this embodiment comprises a semiconductor chip 12, a circuit element layer 14 including circuit elements 14A, and a rewiring layer 13 including rewiring 13A connected to the circuit elements 14A and the semiconductor chip 12.

[0050] The circuit elements 14A included in the circuit element layer 14 are connected to the semiconductor chip 12 via rewiring 13A included in the rewiring layer 13. Therefore, compared to the conventional case where the chip and the circuit elements are connected through vias provided in the substrate, problems associated with increasing the size of the semiconductor device 10 are less likely to occur. This makes it suitable for increasing the size of the semiconductor device 10. By increasing the size of the semiconductor device 10, costs can be reduced.

[0051] Furthermore, the rewiring layer 13 is disposed above the circuit element layer 14 and below the semiconductor chip 12. Since the circuit element layer 14 is disposed below the rewiring layer 13, the circuit elements 14A are connected to the rewiring 13A during fabrication, i.e., before the semiconductor chip 12 is disposed above the rewiring layer 13. If, for example, a test TFT 16 is provided as the circuit element 14A, the rewiring 13A can be inspected before the semiconductor chip 12 is disposed. Since the rewiring 13A can be inspected before the semiconductor chip 12 is disposed, the yield of the semiconductor device 10 can be improved. Improved yield is also advantageous for increasing the size of the substrate 11. Furthermore, the rewiring 13A and the semiconductor chip 12 can be inspected during and after the semiconductor chip 12 is disposed.

[0052] The circuit elements 14A also include TFTs (switching elements) 16. In this way, the TFTs 16, which are the circuit elements 14A, are connected to the rewirings 13A at a stage before the semiconductor chip 12 is provided on the upper side of the rewiring layer 13. The TFTs 16 enable inspection of the rewirings 13A, etc.

[0053] Furthermore, the TFT 16 is connected to an external inspection device IN, and an inspection signal is input by the inspection device IN. At a stage before the semiconductor chip 12 is provided, the rewiring 13A can be inspected by connecting the TFT 16 to the external inspection device IN and inputting an inspection signal to the TFT 16 using the inspection device IN. If a break occurs in the rewiring 13A at this time, the rewiring 13A can be repaired or the work-in-progress can be discarded. This makes it less likely that the semiconductor chip 12 will be connected to a rewiring 13A in a broken state, thereby improving yield. Furthermore, even after the semiconductor chip 12 is provided, the semiconductor chip 12 can be inspected by connecting the TFT 16 to the external inspection device IN and inputting an inspection signal to the TFT 16 using the inspection device IN.

[0054] Furthermore, the TFT 16 has a semiconductor portion 16D made of an oxide semiconductor material. This reduces the off-leak current of the TFT 16 compared to when the semiconductor portion 16D is made of an amorphous silicon material or a polysilicon material. This sufficiently suppresses current leakage from the rewiring 13A, thereby minimizing problems caused by the TFT 16 remaining in the semiconductor device 10.

[0055] The semiconductor device also includes a substrate 11 having a first main surface 11A and a second main surface 11B, and the semiconductor chip 12, circuit element layer 14, and rewiring layer 13 are provided on the first main surface 11A of the substrate 11. The semiconductor chip 12, circuit element layer 14, and rewiring layer 13 are all provided on the first main surface 11A of the substrate 11. Therefore, when connecting the semiconductor chip 12 to the circuit element 14A, there is no need to provide vias in the substrate as in the past, and there is no need to consider fluctuations in the position of the vias due to thermal expansion and contraction of the substrate. This makes it suitable for increasing the size of the substrate 11.

[0056] The manufacturing method of the semiconductor device 10 according to this embodiment includes providing a circuit element layer 14 including circuit elements 14A, providing a rewiring layer 13 including rewiring 13A connected to the circuit elements 14A, and providing a semiconductor chip 12 connected to the rewiring 13A.

[0057] The circuit elements 14A included in the circuit element layer 14 are connected to the semiconductor chip 12 via rewiring 13A included in the rewiring layer 13. Therefore, compared to the conventional case where the chip and the circuit elements are connected through vias provided in the substrate, problems associated with increasing the size of the semiconductor device 10 are less likely to occur. This makes it suitable for increasing the size of the semiconductor device 10. By increasing the size of the semiconductor device 10, costs can be reduced.

[0058] Furthermore, a rewiring layer 13 is provided above the circuit element layer 14, and a semiconductor chip 12 is provided above the rewiring layer 13. When the rewiring layer 13 is provided above the circuit element layer 14, the semiconductor chip 12 is not provided. That is, before the semiconductor chip 12 is provided, the circuit element 14A is connected to the rewiring 13A. If, for example, a test TFT 16 is provided as the circuit element 14A, the rewiring 13A can be inspected before the semiconductor chip 12 is provided. In this way, since the rewiring 13A can be inspected before the semiconductor chip 12 is provided, the yield of the semiconductor device 10 can be improved. Improved yield is also advantageous for increasing the size of the semiconductor device 10. The rewiring 13A and the semiconductor chip 12 can be inspected when the semiconductor chip 12 is provided or after the semiconductor chip 12 is provided.

[0059] Furthermore, a TFT 16 is provided as the circuit element 14A, and before the semiconductor chip 12 is provided, the TFT 16 is connected to an external inspection device IN, and an inspection signal is input from the inspection device IN to the TFT 16 to inspect the rewiring 13A. At a stage before the semiconductor chip 12 is provided, the rewiring 13A can be inspected by connecting the TFT 16 to the external inspection device IN and inputting an inspection signal to the TFT 16 from the inspection device IN. If a break occurs in the rewiring 13A at this time, the rewiring 13A can be repaired or the work-in-progress can be discarded. This makes it less likely that a semiconductor chip 12 will be connected to a rewiring 13A that is in a broken state, thereby improving yield.

[0060] Furthermore, after the semiconductor chip 12 is provided, the TFT 16 is connected to an external inspection device IN, and an inspection signal is input from the inspection device IN to the TFT 16 to inspect the rewiring 13A. After the semiconductor chip 12 is provided, the semiconductor chip 12 can be inspected by connecting the TFT 16 to the external inspection device IN and inputting an inspection signal to the TFT 16 from the inspection device IN. Here, the rewiring 13A is inspected using the TFT 16 before the semiconductor chip 12 is provided. Therefore, defects in the rewiring 13A are prevented from being reflected in the inspection results of the semiconductor chip 12, and defects in the semiconductor chip 12 and the rewiring 13A can be distinguished from each other. If a defect occurs in the semiconductor chip 12, the yield can be improved by replacing the semiconductor chip 12, for example.

[0061] Second Embodiment A second embodiment will be described with reference to Fig. 9. In this second embodiment, a modified configuration of the TFT 116 is shown. Note that a redundant description of the structure, operation, and effects similar to those of the first embodiment will be omitted.

[0062] 9, the TFT 116 according to this embodiment is a top-gate type in which the gate electrode 116A is located above the semiconductor portion 116D. Specifically, the semiconductor portion 116D constituting the TFT 116 is disposed above the buffer insulating film 117 and below the gate insulating film 118. The semiconductor portion 116D is formed by patterning a semiconductor film made of polysilicon (polycrystalline) material using a photolithography method. Examples of semiconductor films made of polysilicon material include a thin film of continuous grain silicon (CG silicon).

[0063] The circuit element layer 114 according to this embodiment includes a second interlayer insulating film 20 in addition to the TFT 116, buffer insulating film 117, gate insulating film 118, and first interlayer insulating film 119. The second interlayer insulating film 20 is made of an inorganic resin material such as silicon nitride or silicon oxide, and is disposed above the gate electrode 116A (first metal film) and below the source electrode 116B and drain electrode 116C (second metal film). The gate electrode 116A constituting the TFT 116 is disposed above the gate insulating film 118 and below the second interlayer insulating film 20, overlapping the semiconductor portion 116D. The source electrode 116B and drain electrode 116C constituting the TFT 116 are disposed above the second interlayer insulating film 20 and below the first interlayer insulating film 119. The source electrode 116B and the drain electrode 116C are arranged at positions spaced apart from each other with the gate electrode 116A therebetween, and are also arranged at positions overlapping both end portions of the semiconductor portion 116D.

[0064] A third contact hole H4 and a fourth contact hole H5 are provided in communication with each other at positions of the gate insulating film 118 and the second interlayer insulating film 20 that overlap the source electrode 116B and the drain electrode 116C, respectively, but do not overlap the first contact hole H101 and the second contact hole H102. The third contact hole H4 is arranged to overlap a portion of the source electrode 116B that overlaps with the semiconductor portion 116D. The source electrode 116B is connected to the semiconductor portion 116D through the third contact hole H4. The fourth contact hole H5 is arranged to overlap a portion of the drain electrode 116C that overlaps with the semiconductor portion 116D. The drain electrode 116C is connected to the semiconductor portion 116D through the fourth contact hole H5. The communication hole H103 is provided to communicate with the second interlayer insulating film 20 in addition to the buffer insulating film 117, the gate insulating film 118, and the first interlayer insulating film 119.

[0065] As described above, according to this embodiment, the TFT 116 has the semiconductor portion 116D made of polysilicon material, and therefore the electron mobility of the semiconductor portion 116D is higher than when an oxide semiconductor material is used as the material for the semiconductor portion 16D as in the above-described embodiment 1. This allows the inspection-related processes in the first inspection step S1 and the second inspection step S2 (see FIG. 4 ) described in embodiment 1 to be performed at high speed.

[0066] As described above, according to this embodiment, the TFT 116 has a semiconductor portion 116D made of polysilicon material. In this way, the electron mobility in the semiconductor portion 116D made of polysilicon material is higher than when an amorphous silicon material or an oxide semiconductor material is used as the material for the semiconductor portion. This allows for high-speed processing related to testing.

[0067] 10 to 13, a third embodiment will be described. In this third embodiment, a manufacturing method of a semiconductor device 210 is modified from that of the second embodiment. Note that redundant descriptions of the structure, operation, and effects similar to those of the second embodiment will be omitted.

[0068] In the manufacturing method of the semiconductor device 210 according to this embodiment, as shown in FIGS. 10 and 11 , a mother substrate 21 including a plurality of substrates 211 is formed in a substrate formation step S201. The mother substrate 21 is larger than the individual substrates 211 in a plan view and includes the plurality of substrates 211 arranged in a matrix (rows and columns) in a plan view. In the following description, the left-right direction of the paper in FIGS. 11 to 13 is referred to as the "first direction" and the up-down direction of the paper is referred to as the "second direction." In addition, in FIGS. 11 and 12 , the outlines of the individual substrates 211 on the mother substrate 21 are illustrated with dashed lines. In addition, in FIGS. 11 to 13 , the rewirings 213A and semiconductor chips 212 to be inspected in the inspection steps S204 and S206 are illustrated with the circuit symbol "resistor."

[0069] 10 and 11 , in the circuit element layer forming process S202, a circuit element layer 14 is provided on each first main surface 211A of each of the plurality of substrates 211 of the mother substrate 21. In the circuit element layer forming process S202, a test TFT 216 is provided for each of the plurality of substrates 211. In the circuit element layer forming process S202, in addition to the test TFT 216 and the like, scanning wiring (first wiring) 22, input wiring (second wiring) 23, output wiring (third wiring) 24, a first signal supply unit 25, and a second signal supply unit 26 are provided as the circuit element layer 14.

[0070] 11 , the scanning lines 22 extend in the first direction on the mother substrate 21 and are arranged so as to straddle all of the substrates 211 lined up in the first direction. The scanning lines 22 are connected to the gate electrodes 216A of the TFTs 216 provided on the substrates 211 lined up in the first direction. A plurality of the scanning lines 22 are arranged on the mother substrate 21 at intervals corresponding to the distance between the substrates 211 in the second direction. The number of the scanning lines 22 matches the number of the substrates 211 lined up in the second direction. In the circuit element layer forming step S202, the scanning lines 22 are formed together with the gate electrodes 216A of the TFTs 216 by patterning the first metal film.

[0071] As shown in FIG. 11 , the input wiring 23 extends along the second direction on the mother substrate 21, straddling all of the substrates 211 arranged along the second direction, and intersecting with the plurality of scanning wirings 22 arranged at intervals in the second direction. The input wiring 23 is connected to each source electrode 216B of the plurality of TFTs 216 provided on the plurality of substrates 211 arranged along the first direction. Note that a plurality of TFTs 216 are arranged in a matrix at locations where the scanning wirings 22 and the input wiring 23 intersect. The plurality of input wirings 23 are arranged on the mother substrate 21 at intervals corresponding to the distance between the substrates 211 in the first direction. The number of input wirings 23 provided corresponds to the number of substrates 211 arranged in the second direction. In the circuit element layer forming step S202, the input wiring 23 is formed together with the source electrodes 216B and drain electrodes 216C of the TFTs 216 by patterning the second metal film.

[0072] As shown in FIG. 11 , the output wiring 24 extends along the second direction on the mother substrate 21, straddling all of the substrates 211 arranged along the second direction, and is arranged so as to intersect with the plurality of scanning wirings 22 arranged at intervals in the second direction. The output wiring 24 is connected to a plurality of rewirings 13A connected to the drain electrodes 216C of the plurality of TFTs 216 provided on the plurality of substrates 211 arranged along the first direction. The output wiring 24 is arranged at a position spaced apart from the input wiring 23 in the first direction. A plurality of output wirings 24 are arranged on the mother substrate 21 at intervals corresponding to the distances between the substrates 211 in the first direction. The number of output wirings 24 installed matches the number of substrates 211 arranged in the second direction. In the circuit element layer forming process S202, the output wiring 24 is formed together with the source electrodes 216B, the drain electrodes 216C, and the input wiring 23 by patterning the second metal film.

[0073] As shown in FIG. 11 , the first signal supply unit 25 is disposed at an end of the mother substrate 21 in the first direction and is formed in a strip-like area extending in the second direction. The first signal supply unit 25 is connected to all of the scanning lines 22 arranged in the second direction. The first signal supply unit 25 supplies scanning signals to the multiple scanning lines 22 and is monolithically provided on the mother substrate 21. The first signal supply unit 25 is a so-called GDM (Gate Driver Monolithic) circuit. The first signal supply unit 25 includes a shift register circuit that outputs scanning signals at a predetermined timing and a buffer circuit that amplifies the scanning signals. The scanning signals are supplied from the first signal supply unit 25 to the multiple scanning lines 22 in a predetermined order. The scanning signals supplied from the first signal supply unit 25 to the scanning lines 22 include a potential higher than the threshold voltage of the TFTs 216.

[0074] 11 , the second signal supply unit 26 is disposed at an end of the motherboard 21 in the second direction, and is formed in a strip-like range extending along the first direction. The second signal supply unit 26 is connected to all of the input wirings 23 and output wirings 24 arranged along the first direction. The second signal supply unit 26 supplies inspection signals to the plurality of input wirings 23 and receives signals output from the output wirings 24, and is monolithically provided on the motherboard 21. The second signal supply unit 26 supplies inspection signals to the plurality of input wirings 23 in synchronization with the supply of scanning signals to the plurality of scanning wirings 22 by the first signal supply unit 25.

[0075] 10 , in the redistribution layer forming process S203, a redistribution layer 13 is provided on each of the first main surfaces 211A of the plurality of substrates 211 of the mother substrate 21. In the first inspection process S204, as shown in FIGS. 10 and 11 , an external inspection device IN is connected to the first signal supply unit 25 and the second signal supply unit 26 of the mother substrate 21. The inspection device IN controls the operations of the first signal supply unit 25 and the second signal supply unit 26. The first signal supply unit 25 sequentially supplies scanning signals to the plurality of scanning lines 22 in a predetermined order. In synchronization with the supply of the scanning signals to the scanning lines 22, the second signal supply unit 26 supplies inspection signals to the plurality of input lines 23. When the multiple TFTs 216 connected to the scanning lines 22 are driven collectively based on the scanning signal, the inspection signal supplied to the multiple input lines 23 is transmitted from the source electrode 216B of each TFT 216 to the drain electrode 216C via the semiconductor portion 216D and then supplied to the rewiring 213A connected to the drain electrode 216C. If no break occurs in the rewiring 213A being inspected, the inspection signal is returned to the second signal supply unit 26 via the output line 24, allowing the inspection device IN to detect the inspection signal. On the other hand, if a break occurs in the rewiring 213A being inspected, the inspection signal is not returned to the second signal supply unit 26 via the output line 24, and therefore the inspection device IN does not detect the inspection signal. By supplying the inspection signal to each input line 23 while scanning all the scanning lines 22 in this manner, the multiple rewirings 213A provided on all the substrates 211 can be inspected collectively. This improves the efficiency of the inspection in the first inspection step S204, thereby shortening the time required for the inspection. In particular, in this embodiment, the TFT 216 having the semiconductor portion 216D made of polysilicon material described in the second embodiment is used for the inspection, so that the time required for the inspection can be further shortened.

[0076] In the semiconductor chip mounting process S205, as shown in Fig. 10, a semiconductor chip 212 is provided on each of the first main surfaces 211A of the plurality of substrates 211 of the mother substrate 21. In the second inspection process S206, as shown in Figs. 10 and 12, an external inspection device IN is connected to the first signal supply unit 25 and the second signal supply unit 26 of the mother substrate 21. The inspection device IN controls the operations of the first signal supply unit 25 and the second signal supply unit 26. Scanning signals are sequentially supplied from the first signal supply unit 25 to the plurality of scanning wirings 22 in a predetermined order. In synchronization with the supply of the scanning signals to the scanning wirings 22, inspection signals are supplied from the second signal supply unit 26 to the plurality of input wirings 23. When the multiple TFTs 216 connected to the scanning lines 22 are driven collectively based on the scanning signal, the inspection signal supplied to the multiple input lines 23 is transmitted from the source electrode 216B of each TFT 216 to the drain electrode 216C via the semiconductor portion 216D and then supplied to the semiconductor chip 212 via the rewiring 213A connected to the drain electrode 216C. At this time, if the semiconductor chip 212 being inspected does not have a defect, the inspection signal is returned to the second signal supply unit 26 via the output line 24, allowing the inspection device IN to detect the inspection signal. On the other hand, if the semiconductor chip 212 being inspected has a defect, the inspection signal is not returned to the second signal supply unit 26 via the output line 24, and therefore the inspection device IN does not detect the inspection signal. By supplying the inspection signal to each input line 23 while scanning all the scanning lines 22 as described above, the multiple semiconductor chips 212 provided on all the substrates 211 can be inspected collectively. This improves the efficiency of the inspection in the second inspection step S206, thereby shortening the time required for inspection. In particular, in this embodiment, the TFT 216 having the semiconductor portion 216D made of polysilicon material described in the second embodiment is used for the inspection, so that the time required for the inspection can be further shortened.

[0077] In the manufacturing method of the semiconductor device 210 according to this embodiment, as shown in FIG. 10 , after the second inspection step S206, a molding step S207 is performed, followed by a dividing step S8. In the dividing step S8, as shown in FIG. 13 , the mother substrate 21 is divided along a dividing line (scribe line) using a scribing device. The scribing device includes a scribing wheel and a laser irradiation device that irradiates the mother substrate 21 with a laser beam for dividing. Note that in FIG. 13 , the dividing line on the mother substrate 21 is illustrated with a thick solid line. Also, in FIG. 13 , the range of each semiconductor device 210 on the mother substrate 21 is illustrated with a hatched area. After the dividing step S8, the mother substrate 21 is divided into a plurality of substrates 211, and thus a plurality of semiconductor devices 210 are extracted. In addition, the scanning wiring 22, the input wiring 23, the output wiring 24, the first signal supply unit 25, and the second signal supply unit 26 are all located in a part of the mother board 21 that does not constitute the semiconductor device 210 (a discarded board), and are therefore disposed of together with the discarded board.

[0078] As described above, according to this embodiment, the mother substrate 21 includes a plurality of substrates 211 each having a first main surface 211A and a second main surface 11B. The mother substrate 21 includes a plurality of substrates 211, and the circuit element layer 14 is provided on each of the first main surfaces 211A of the plurality of substrates 211 of the mother substrate 21, and the redistribution layer 13 is provided on each of the first main surfaces 211A of the plurality of substrates 211 of the mother substrate 21, and the semiconductor chips 212 are provided on each of the first main surfaces 211A of the plurality of substrates 211 of the mother substrate 21, thereby manufacturing a plurality of semiconductor devices 210. When the circuit element layer 14 is provided on the mother substrate 21, the circuit element layer 14 includes a plurality of scanning wirings (first wirings) 22 extending in a first direction across the plurality of substrates 211 and arranged at intervals corresponding to the substrates 211 in a second direction intersecting the first direction, and a plurality of scanning wirings (first wirings) 22 extending in the second direction across the plurality of substrates 211 and arranged at intervals corresponding to the substrates 211 in the first direction. The input wiring (second wiring) 23 is provided at intervals, a first signal supply section 25 is provided at an end of the mother substrate 21 in the first direction and connected to the plurality of scanning wirings 22, and a second signal supply section 26 is provided at an end of the mother substrate 21 in the second direction and connected to the plurality of input wirings 23, and a plurality of TFTs 216 are provided at locations where the scanning wirings 22 and the input wirings 23 intersect, and the scanning wirings 22 and the input wirings 23 are connected to the TFTs 216. When inspecting the rewiring 213A, a first signal supply unit 25 and a second signal supply unit 26 are connected to an external inspection device IN, and scanning signals are sequentially output from the first signal supply unit 25 to the plurality of scanning lines 22, sequentially driving the TFTs 216 connected to the scanning lines 22, while the second signal supply unit 26 outputs inspection signals to the plurality of input lines 23, and the inspection signals are input to the rewiring 213A via the TFTs 216 connected to the input lines 23 and in a driven state. By dividing the motherboard 21, on which the circuit element layer 14, the rewiring layer 13, and the semiconductor chips 212 are provided, into multiple substrates 11, multiple semiconductor devices 210 can be manufactured collectively. During inspection, the first signal supply unit 25 and the second signal supply unit 26, connected to the external inspection device IN, output scanning signals and inspection signals to the scanning lines 22 and the input lines 23, respectively.When a test signal is input to the input wiring 23 at the timing when the TFT 216 connected to the scanning wiring 22 to which the scan signal is input is driven, the test signal is input to the TFT 216. This makes it possible to test the rewirings 213A connected to the driven TFT 216. By sequentially outputting scan signals from the first signal supply unit 25 to the plurality of scanning wirings 22 and outputting test signals from the second signal supply unit 26 to the plurality of input wirings 23, it is possible to sequentially test the plurality of rewirings 213A provided on the plurality of substrates 211 while sequentially driving the TFTs 216 arranged in a matrix. This makes it possible to efficiently test the plurality of rewirings 213A.

[0079] <Fourth Embodiment> A fourth embodiment will be described with reference to Fig. 14 or 15. In this fourth embodiment, a circuit element 314A is changed from that of the first embodiment. Note that a redundant description of the structure, operation, and effects similar to those of the first embodiment will be omitted.

[0080] 14 , the circuit element layer 314 according to this embodiment includes a ground-connected protection diode (protection circuit element) 27 as a circuit element 314A. In this embodiment, a Zener diode is used as the diode 27. The diode 27 is connected to a reverse bias state with respect to the rewiring 313A to be protected. Specifically, for example, the anode electrode 27A of the diode 27 is connected to the ground GND, and the cathode electrode 27B is connected between the direct-current power supply DC and the rewiring 313A to be protected.

[0081] As shown in FIG. 15 , the diode 27 has an anode electrode 27A, a cathode electrode 27B, and a semiconductor portion 27C. In addition to the diode 27, the circuit element layer 314 includes a buffer insulating film 317 and a third interlayer insulating film 28, but does not include the gate insulating film 18 and the first interlayer insulating film 19 described in the first embodiment. The semiconductor portion 27C of the diode 27 is formed by patterning a semiconductor film deposited on the buffer insulating film 317 using a photolithography method. The semiconductor portion 27C is formed by a pn junction between a p-type semiconductor and an n-type semiconductor. The anode electrode 27A and the cathode electrode 27B are provided on the semiconductor portion 27C in direct contact with both ends of the semiconductor portion 27C, respectively. The anode electrode 27A and the cathode electrode 27B are formed by patterning a metal film deposited on the semiconductor portion 27C using a photolithography method.

[0082] The third interlayer insulating film 28 is made of an inorganic resin material such as silicon nitride or silicon oxide and is disposed above the anode electrode 27A and the cathode electrode 27B, as shown in FIG. 15 . A fifth contact hole H6 and a sixth contact hole H7 are formed in the third interlayer insulating film 28 at positions overlapping the anode electrode 27A and the cathode electrode 27B, respectively. A portion of the rewiring 313A located at the bottom of the rewiring layer 313 is formed in the fifth contact hole H6. The rewiring 313A disposed in the fifth contact hole H6 is connected to the anode electrode 27A. The rewiring 313A connected to the anode electrode 27A through the fifth contact hole H6 is formed inside the communicating hole H303 and the through-hole 311C, which are interconnected. The rewiring 313A connected to the anode electrode 27A is connected to the external ground GND (see FIG. 14 ). A part of the rewiring 313A located in the lowest layer of the multiple rewirings 313A included in the rewiring layer 313 is formed in the sixth contact hole H7. The rewiring 313A arranged in the sixth contact hole H7 is connected to the cathode electrode 27B. The rewiring 313A connected to the cathode electrode 27B is an object to be protected by the diode 27.

[0083] In this embodiment, as in the first embodiment, the circuit element layer 314 is provided below the redistribution layer 313. Therefore, during manufacturing, when the redistribution layer 313 is provided, i.e., before the semiconductor chip 312 is provided above the redistribution layer 313, the circuit element 314A is connected to the redistribution layer 313A. In this embodiment, the circuit element 314A is a ground-connected protection circuit element, the diode 27. This protects the redistribution layer 313A from electrostatic discharge (ESD) before the semiconductor chip 312 is provided. In this way, the redistribution layer 313A is protected before the semiconductor chip 312 is provided, and ESD-induced burnout of the redistribution layer 313A is avoided, thereby improving the yield of the semiconductor device 310. Improved yield is also advantageous for increasing the size of the substrate 311. It is possible to protect the rewiring 313A and the semiconductor chip 312 from ESD when the semiconductor chip 312 is provided and also at a stage after the semiconductor chip 312 is provided.

[0084] As described above, according to this embodiment, the circuit element 314A includes the ground-connected diode 27. Even if ESD is applied to the rewiring 313A at a stage before the semiconductor chip 312 is provided, the ground-connected diode 27 can dissipate the ESD to ground GND. This protects the rewiring 313A from ESD, thereby improving yield. Furthermore, even at a stage after the semiconductor chip 312 is provided, the diode 27 can dissipate ESD to ground, thereby protecting the rewiring 313A and the semiconductor chip 312 from ESD.

[0085] Fifth Embodiment A fifth embodiment will be described with reference to Fig. 16 or 17. In this fifth embodiment, a circuit element 414A is changed from that of the first embodiment. Note that a redundant description of the structure, operation, and effects similar to those of the first embodiment will be omitted.

[0086] 16 , the circuit element layer 414 according to this embodiment includes a ground-connected capacitor 29 as a circuit element 414A. The capacitor 29 is connected to the ground GND and a rewiring 413A connected to the semiconductor chip 412 that is the target of noise suppression. Specifically, for example, one electrode 29A of the capacitor 29 is connected to the ground GND, and the other electrode 29B is connected between the direct-current power supply DC and the rewiring 413A connected to the semiconductor chip 412.

[0087] As shown in FIG. 18 , the capacitor 29 has one electrode 29A, the other electrode 29B, and a dielectric layer 29C. In addition to the capacitor 29, the circuit element layer 414 includes a buffer insulating film 417, a gate insulating film 418, and a first interlayer insulating film 419, but does not include the semiconductor film described in the first embodiment. The one electrode 29A of the capacitor 29 is formed by patterning a first metal film deposited on the buffer insulating film 417 using a photolithography method. The dielectric layer 29C is made of a portion of the gate insulating film 418 that overlaps the one electrode 29A. The other electrode 29B of the capacitor 29 is formed by patterning a second metal film deposited on the gate insulating film 418 using a photolithography method. The other electrode 29B is disposed with the dielectric layer 29C, which is part of the gate insulating film 418, sandwiched between the one electrode 29A and the one electrode 29A.

[0088] A seventh contact hole H8 is formed in the gate insulating film 418 and the first interlayer insulating film 419 at a position overlapping the one electrode 29A. A portion of the rewiring 413A located in the lowest layer of the multiple rewirings 413A included in the rewiring layer 413 is formed in the seventh contact hole H8. The rewiring 413A arranged in the seventh contact hole H8 is connected to the one electrode 29A. The rewiring 413A connected to the one electrode 29A through the seventh contact hole H8 is formed inside the communicating hole H403 and the through hole 411C, which are mutually communicating. The rewiring 413A connected to the one electrode 29A is connected to the external ground GND (see FIG. 16 ). An eighth contact hole H9 is formed in the first interlayer insulating film 419 at a position overlapping the other electrode 29B. A part of the rewiring 413A located in the lowest layer of the multiple rewirings 413A included in the rewiring layer 413 is formed in the eighth contact hole H9. The rewiring 413A arranged in the eighth contact hole H9 is connected to the other electrode 29B. The rewiring 413A connected to the other electrode 29B is connected to the semiconductor chip 412 that is the target of noise suppression.

[0089] 16, this configuration allows noise generated on the DC power supply side to flow to ground GND by capacitor 29. This prevents noise from being transmitted to the rewiring 413A connected to semiconductor chip 412, thereby providing noise protection for semiconductor chip 412. Capacitor 29 also has the effect of maintaining a constant power supply voltage. Note that ground-connected capacitor 29 can also protect rewiring 413A and semiconductor chip 412 from ESD and can function as a protective circuit element.

[0090] As described above, according to this embodiment, the circuit element 414A includes the ground-connected capacitor 29. Noise that may be input to the rewiring 413A can be channeled to the ground GND by the capacitor 29. This provides a noise countermeasure.

[0091] Sixth Embodiment A sixth embodiment will be described with reference to Fig. 18. In this sixth embodiment, a circuit element 514A is changed from that of the first embodiment. Note that a redundant description of the structure, operation, and effects similar to those of the first embodiment will be omitted.

[0092] As shown in FIG. 18 , the circuit element layer 14 according to this embodiment includes a ground-connected protective TFT (switching element) 30 as a circuit element 514A. The TFT 30 is connected to ground GND and the rewiring 513A to be protected. Specifically, for example, the gate electrode 30A and source electrode 30B of the TFT 30 are connected to ground GND, and the drain electrode 30C is connected between a direct-current power supply DC and the rewiring 513A to be protected. By utilizing the switchback operation of the TFT 30, ESD can be passed to ground GND. The cross-sectional configuration of the TFT 30 is similar to that of the TFT 16 described in the first embodiment (see FIG. 3 ), and the TFT 30 includes a semiconductor portion 30D connected to the source electrode 30B and the drain electrode 30C.

[0093] In this embodiment, as in the first embodiment, the circuit element layer 14 is provided below the redistribution layer 13. Therefore, during manufacturing, when the redistribution layer 13 is provided, i.e., before the semiconductor chip 512 is provided above the redistribution layer 13, the circuit element 514A is connected to the redistribution 513A. In this embodiment, the circuit element 514A is a TFT 30, which is a ground-connected protective circuit element. This allows the redistribution 513A to be protected from ESD before the semiconductor chip 512 is provided. In this way, the redistribution 513A is protected before the semiconductor chip 512 is provided, and ESD-induced burnout of the redistribution 513A is avoided, thereby improving the yield of the semiconductor device 10. Improved yield is also advantageous for increasing the size of the substrate 11. Furthermore, the redistribution 513A and the semiconductor chip 512 can be protected from ESD both when the semiconductor chip 512 is provided and after the semiconductor chip 512 is provided.

[0094] As described above, according to this embodiment, the circuit element 514A includes a ground-connected TFT (switching element) 30. Even if ESD is applied to the rewiring 513A at a stage before the semiconductor chip 512 is provided, the ground-connected TFT 30 can dissipate the ESD to ground GND. This protects the rewiring 513A from ESD, thereby improving yield. Furthermore, even at a stage after the semiconductor chip 512 is provided, the TFT 30 can dissipate ESD to ground, thereby protecting the rewiring 513A and the semiconductor chip 512 from ESD.

[0095] Seventh Embodiment A seventh embodiment will be described with reference to Fig. 19. In this seventh embodiment, a circuit element 614A is changed from that of the first embodiment. Note that a redundant description of the structure, operation, and effects similar to those of the first embodiment will be omitted.

[0096] As shown in FIG. 19 , the circuit element layer 14 according to this embodiment includes, as circuit elements 614A, TFTs (switching elements) 31 and capacitors 32 that constitute a power supply circuit PS. The power supply circuit PS according to this embodiment is a so-called switching regulator, and in addition to the TFTs 31 and capacitors 32 described above, includes a power supply PW and a control unit CT. The TFTs 31 have a gate electrode 31A connected to the control unit CT, a source electrode 31B connected to the power supply PW, and a drain electrode 31C connected to a rewiring 613A connected to a semiconductor chip 612 to which power is to be supplied. The cross-sectional configuration of the TFTs 31 is similar to that of the TFTs 16 described in the first embodiment (see FIG. 3 ), and include a semiconductor portion 31D connected to the source electrode 31B and the drain electrode 31C. The capacitors 32 have one electrode 32A connected to ground GND and the other electrode 32B connected to the drain electrode 31C of the TFTs 31 and the rewiring 613A. The cross-sectional structure of the capacitor 32 is similar to that of the capacitor 29 described in the fifth embodiment (see FIG. 17), and includes a dielectric layer sandwiched between one electrode 32A and the other electrode 32B.

[0097] In the power supply circuit PS configured as described above, the control unit CT turns the TFT 31 on and off, converting the power supply voltage from the power supply PW into a pulse wave. The output voltage is controlled by adjusting the ratio of the on-period and off-period of the TFT 31 using the control unit CT. Although the output voltage output from the drain electrode 31C of the TFT 31 may fluctuate due to the switching operation of the TFT 31, the capacitor 32 smooths the output voltage fluctuations. The control unit CT monitors the smoothed output voltage and provides feedback to the control of the TFT 31. In this way, the power supply voltage can be adjusted to a voltage suitable for driving the semiconductor chip 612. This allows power to be supplied to the semiconductor chip 612.

[0098] As described above, according to this embodiment, the TFT (switching element) 31 is connected to an external power supply PW and receives a power supply voltage from the power supply PW. When the external power supply PW is connected to the TFT 31 and the power supply voltage from the power supply PW is input to the TFT 31, the TFT 31 can adjust the power supply voltage to a voltage suitable for driving the semiconductor chip 612. This allows power to be supplied to the semiconductor chip 612.

[0099] <Embodiment 8> Embodiment 8 will be described with reference to Fig. 20. In this embodiment 8, a dummy TFT (dummy circuit element) 33 in the same layer as the circuit element 14A is added to the above-mentioned embodiment 1. Note that a duplicated description of the structure, action, and effect similar to those of the above-mentioned embodiment 1 will be omitted.

[0100] As shown in FIG. 20 , the circuit element layer 714 according to this embodiment includes a dummy TFT 33 in the same layer as the circuit element 14A. The dummy TFT 33 is not connected to the semiconductor chip 712 or the rewiring 713A. That is, the dummy TFT 33 is provided on the first main surface 711A of the substrate 711 as an electrically isolated floating island. Note that the configuration of the dummy TFT 33 is similar to that of the TFT 16 (see FIG. 3 ), which is the circuit element 14A described in the first embodiment, except that it is not connected to the semiconductor chip 712 or the rewiring 713A. The dummy TFT 33 includes a gate electrode 33A, a source electrode 33B, a drain electrode 33C, and a semiconductor portion 33D. With this configuration, when ESD occurs, it is possible to apply the ESD to the dummy TFT 33, which is not connected to the semiconductor chip 712 or the rewiring 713A. Even if the dummy TFT 33 is burned out by ESD, it is possible to avoid functional problems occurring in the semiconductor chip 712 and the rewiring 713A, thereby protecting the semiconductor chip 712 and the rewiring 713A from ESD.

[0101] As described above, according to this embodiment, the circuit element layer 714 includes dummy TFTs (dummy circuit elements) 33 that are not connected to the semiconductor chip 712 and the rewiring 713A. When ESD occurs, it is possible to apply the ESD to the dummy TFTs 33 that are not connected to the semiconductor chip 712 and the rewiring 713A. Even if the dummy TFTs 33 are burned out by ESD, functional problems with the semiconductor chip 712 and the rewiring 713A can be avoided. This makes it possible to protect the semiconductor chip 712 and the rewiring 713A from ESD.

[0102] 21 to 23. In this embodiment 9, a manufacturing method of a semiconductor device 810 is changed from that of the above-described embodiment 1. Note that redundant descriptions of the structure, operation, and effects similar to those of the above-described embodiment 1 will be omitted.

[0103] In the manufacturing method of the semiconductor device 810 according to this embodiment, the substrate 811 is peeled off (lifted off) after the semiconductor chip 812 is mounted. Specifically, as shown in FIG. 21 , after the semiconductor chip 812 is mounted on the first main surface 811A of the substrate 811, the substrate 811 is irradiated with laser light from the second main surface 811B side (the lower side in FIG. 21 ). Note that in the circuit element layer forming step S2, a peeling layer (not shown) is provided between the first main surface 811A of the substrate 811 and the buffer insulating film 817 of the circuit element layer 814. Also, in this embodiment, in the substrate forming step S1, the through-hole 11C (see FIG. 3 ) described in embodiment 1 is not formed in the substrate 811.

[0104] When the release layer is irradiated with laser light, the substrate 811 becomes easy to peel from the circuit element layer 814, so as shown in Fig. 22, the substrate 811 is peeled from the circuit element layer 814. After the substrate 811 has been peeled, as shown in Fig. 23, solder balls 815 are provided on the lower surface of the buffer insulating film 817 of the circuit element layer 814 at positions that overlap the through holes H803. This allows the solder balls 815 to be connected to the rewiring 813A provided in the through holes H803.

[0105] As described above, according to this embodiment, a circuit element layer 814, a rewiring layer 813, and a semiconductor chip 812 are provided on the first main surface 811A of a substrate 811 having a first main surface 811A and a second main surface 811B, and then the substrate 811 is peeled off. After the semiconductor chip 812 is provided, the substrate 811 is peeled off to obtain a semiconductor device 810. This is advantageous in terms of, for example, reducing the thickness of the semiconductor device 810.

[0106] Other Embodiments The technology disclosed in this specification is not limited to the embodiments described above with reference to the drawings, and the following embodiments, for example, are also included in the technical scope.

[0107] (1) The circuit elements 14A, 314A, 414A, 514A, 614A, and 814A provided in the circuit element layers 14, 114, 314, 414, 714, and 814 may include both the TFT 16 described in embodiment 1 and at least one of the diode 27, capacitor 29, TFT 30, and TFT 31 described in embodiments 4 to 7. It is also possible to configure a circuit using the TFT 16 described in embodiment 1 and at least one of the diode 27, capacitor 29, TFT 30, and TFT 31 described in embodiments 4 to 7.

[0108] (2) The circuit elements 14A, 314A, 414A, 514A, 614A, 814A provided in the circuit element layers 14, 114, 314, 414, 714, 814 may include both the TFTs 116, 216 described in embodiments 2 and 3 and at least one of the diode 27, capacitor 29, TFT 30, and TFT 31 described in embodiments 4 to 7. It is also possible to configure a circuit using the TFTs 116, 216 described in embodiments 2 and 3 and at least one of the diode 27, capacitor 29, TFT 30, and TFT 31 described in embodiments 4 to 7.

[0109] (3) The circuit elements 14A, 314A, 414A, 514A, 614A, and 814A provided in the circuit element layers 14, 114, 314, 414, 714, and 814 may not include the TFT 16 described in embodiment 1 or the TFTs 116 and 216 described in embodiments 2 and 3, but may include at least two of the diode 27, capacitor 29, TFT 30, and TFT 31 described in embodiments 4 to 7. It is also possible to configure a circuit using at least two of the diode 27, capacitor 29, TFT 30, and TFT 31 described in embodiments 4 to 7.

[0110] (4) The manufacturing method described in the third embodiment can be combined with the first embodiment.

[0111] (5) The manufacturing method described in the third embodiment can be combined with the above-mentioned (1) and (2).

[0112] (6) In the manufacturing method described in the third embodiment, the specific number and arrangement of the substrates 211 included in the mother substrate 21 can be changed as appropriate from those shown in the drawings. The specific circuit configuration for testing can also be changed as appropriate from those shown in the drawings. For example, the output wiring 24 can be omitted. In that case, testing can be performed by connecting an inspection device IN to the rewiring 213A to be tested that is provided on each substrate 211.

[0113] (7) In the configurations described in the fourth and sixth embodiments, in addition to the diode 27 and the TFT 30, a varistor, an ESD suppressor, a multilayer chip capacitor, or the like may also be provided as a protection circuit element.

[0114] (8) In the configuration described in embodiment 7, the power supply circuit PS may be, for example, a linear regulator other than a switching regulator. In that case, a TFT or the like may be provided in the semiconductor device as a circuit element constituting the linear regulator.

[0115] (9) In the configuration described in embodiment 8, the dummy circuit element may be a dummy diode, a dummy capacitor, or the like, in addition to the dummy TFT 33. The dummy diode may have a structure similar to that of the diode 27 described in embodiment 4. The dummy capacitor may have a structure similar to that of the capacitor 28 described in embodiment 5. Furthermore, the configuration described in embodiment 8 may be combined with the configurations and manufacturing methods described in embodiments 2 to 7.

[0116] (10) In the manufacturing method described in the ninth embodiment, after peeling off the substrate 811, a sheet made of a synthetic resin material may be attached to the lower layer side of the circuit element layer 814. Alternatively, after peeling off the substrate 811, a mold resin may be provided on the lower layer side of the circuit element layer 814.

[0117] (11) It is also possible to combine the configurations and manufacturing methods described in the second to eighth embodiments with the manufacturing method described in the ninth embodiment.

[0118] (12) The material of the substrates 11, 211, 311, 711, and 811 may be other than glass, for example, glass epoxy resin material.

[0119] (13) In the configurations and manufacturing methods described in the first, second, third, fourth, sixth, seventh, eighth, and ninth embodiments, the material of the semiconductor film may be an amorphous (non-crystalline) silicon material or a microcrystalline silicon material.

[0120] (14) The number of semiconductor chips 12, 212, 312, 412, 512, 612, 812 provided in the semiconductor device 10, 210, 310, 810 and their arrangement on the substrate 11, 211, 311, 711, 811 may be changed as appropriate to other than those shown in the drawings.

[0121] (15) In the configurations and manufacturing methods described in the first, second, third, sixth, seventh, eighth, and ninth embodiments, the switching elements may be diodes (switching diodes), thyristors, IGBTs (Insulated Gate Bipolar Transistors), etc., in addition to the TFTs 16, 30, 31, 116, and 216.

[0122] (16) In the manufacturing method described in the third embodiment, the second inspection step S206 may be performed, followed by the dividing step S8, and then the molding step S207.

[0123] 10, 210, 310, 810... Semiconductor device, 11, 211, 311, 711, 811... Substrate, 11A, 211A, 711A, 811A... First main surface, 11B, 811B... Second main surface, 12, 212, 312, 412, 512, 612, 812... Semiconductor chip, 13, 313, 413, 713, 831... Rewiring layer, 13A, 213A, 313A, 413A, 513A, 613A, 713A, 813A... Rewiring, 14, 114, 314, 414, 714, 814... Circuit element layer, 14A, 314A, 414A, 514A, 614A, 814A...circuit elements, 16, 116, 216...TFTs (switching elements), 16D, 116D, 216D...semiconductor section, 21...motherboard, 22...scanning wiring (first wiring), 23...input wiring (second wiring), 25...first signal supply section, 26...second signal supply section, 27...diode, 29...capacitor, 30...TFTs (switching elements), 31...TFTs (switching elements), 32...capacitor, 33...dummy TFTs (dummy circuit elements), IN...inspection device, PW...power supply

Claims

1. A semiconductor device comprising: a semiconductor chip; a circuit element layer including circuit elements; and a rewiring layer including rewiring connected to the circuit elements and the semiconductor chip.

2. The semiconductor device according to claim 1, wherein the rewiring layer is disposed above the circuit element layer and below the semiconductor chip.

3. The semiconductor device according to claim 2, wherein the circuit elements include switching elements.

4. A semiconductor device according to claim 3, wherein said switching element is connected to an external testing device and a testing signal is input by said testing device.

5. A semiconductor device according to claim 3, wherein said switching element is connected to an external power supply and receives a power supply voltage from said power supply.

6. The semiconductor device according to claim 3, wherein said switching element is connected to ground.

7. The semiconductor device according to any one of claims 4 to 6, wherein the switching element has a semiconductor portion made of an oxide semiconductor material.

8. The semiconductor device according to any one of claims 4 to 6, wherein the switching element has a semiconductor portion made of polysilicon material.

9. The semiconductor device according to any one of claims 3 to 6, wherein the circuit elements include a diode connected to ground.

10. A semiconductor device according to any one of claims 3 to 6, wherein the circuit elements include a capacitor connected to ground.

11. The semiconductor device according to any one of claims 1 to 6, wherein the circuit element layer includes dummy circuit elements that are not connected to the semiconductor chip and the rewiring.

12. A semiconductor device according to any one of claims 1 to 6, comprising a substrate having a first main surface and a second main surface, wherein the semiconductor chip, the circuit element layer, and the rewiring layer are provided on the first main surface of the substrate.

13. A method for manufacturing a semiconductor device, comprising: providing a circuit element layer including circuit elements; providing a rewiring layer including rewiring connected to the circuit elements; and providing a semiconductor chip connected to the rewiring.

14. The method for manufacturing a semiconductor device according to claim 13, wherein the rewiring layer is provided above the circuit element layer, and the semiconductor chip is provided above the rewiring layer.

15. A method for manufacturing a semiconductor device according to claim 14, wherein a switching element is provided as the circuit element, and before the semiconductor chip is provided, the switching element is connected to an external inspection device, and an inspection signal is input from the inspection device to the switching element to inspect the rewiring.

16. A method for manufacturing a semiconductor device according to claim 15, wherein after the semiconductor chip is provided, the switching element is connected to an external inspection device, and an inspection signal is input from the inspection device to the switching element to inspect the rewiring.

17. A manufacturing method for manufacturing a plurality of semiconductor devices by dividing a motherboard into a plurality of substrates, the plurality of substrates having a first main surface and a second main surface, the method comprising: providing the circuit element layer on each of the first main surfaces of a plurality of the substrates among the motherboard; providing the rewiring layer on each of the first main surfaces of the plurality of the substrates among the motherboard; and providing the semiconductor chip on each of the first main surfaces of the plurality of the substrates among the motherboard, the method comprising: dividing the motherboard into each of the plurality of substrates; When the circuit element layer is provided on the motherboard, the circuit element layer is provided with a plurality of first wirings extending in a first direction across the plurality of substrates and arranged at intervals corresponding to the substrates in a second direction intersecting the first direction, second wirings extending in the second direction across the plurality of substrates and arranged at intervals corresponding to the substrates in the first direction, a first signal supply unit arranged at an end of the motherboard in the first direction and connected to the plurality of first wirings, and a second signal supply unit arranged at an end of the motherboard in the second direction and connected to the plurality of second wirings, and a plurality of the switching elements are provided at locations where the first wirings and the second wirings intersect, and the first wirings and the second wirings are connected to the switching elements, 17. A method for manufacturing a semiconductor device according to claim 15 or 16, wherein when inspecting the rewiring, the first signal supply unit and the second signal supply unit are connected to the external inspection device, a scanning signal is output from the first signal supply unit sequentially to the plurality of first wirings, the switching elements connected to the first wirings are sequentially driven, and the inspection signal is output from the second signal supply unit to the plurality of second wirings, and the inspection signal is input to the rewiring via the switching elements connected to the second wirings and driven.

18. A method for manufacturing a semiconductor device according to any one of claims 13 to 16, wherein a substrate has a first main surface and a second main surface, and after the circuit element layer, the rewiring layer, and the semiconductor chip are provided on the first main surface, the substrate is peeled off.

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