Semiconductor apparatus

Abstract

[Problem] To join chips more appropriately. [Solution] This semiconductor apparatus comprises: a first semiconductor device including a plurality of first metal bump pads including a first metal bump pad, and a plurality of first dummy bump pads including a first dummy bump pad; a second semiconductor device including a plurality of second metal bump pads including a second metal bump pad, and a plurality of second dummy bump pads including a second dummy bump pad: a plurality of metal bumps including a first metal bump; and a plurality of dummy bumps including a first dummy bump. The first semiconductor device and the second semiconductor device are electrically connected via the first metal bump, the first metal bump pad, and the second metal bump pad, and physically connected via the first dummy bump, the first dummy bump pad, and the second dummy bump pad.

Description

Semiconductor Devices

[0001] FIELD Embodiments according to the present disclosure relate to a semiconductor device.

[0002] In a chip stacking structure using a thermal compression bonding method, there is a technology that minimizes the fluidity of the adhesive (NCF) by forming and arranging dummy bumps adjacent to the conductive bumps, thereby preventing deformation of the conductive bumps and the resulting defects and short circuits (see Patent Document 1).

[0003] US Patent Application Publication No. 2021 / 0134761

[0004] However, when joining chips together, there are cases where the chips are significantly warped and the like, making joining difficult.

[0005] Therefore, the present disclosure provides a semiconductor device that can more appropriately bond chips to each other.

[0006] In order to solve the above problems, the present disclosure provides a semiconductor device comprising: a first semiconductor device having a plurality of first metal bump pads including a first metal bump pad and a plurality of first dummy bump pads including a first dummy bump pad; a second semiconductor device having a plurality of second metal bump pads including a second metal bump pad and a plurality of second dummy bump pads including a second dummy bump pad; a plurality of metal bumps including a first metal bump; and a plurality of dummy bumps including a first dummy bump; wherein the first semiconductor device and the second semiconductor device are electrically connected via the first metal bumps, the first metal bump pads, and the second metal bump pads, and are physically connected via the first dummy bumps, the first dummy bump pads, and the second dummy bump pads.

[0007] The dummy bump may be in a floating state via the first dummy bump pad or the second dummy bump pad.

[0008] The connection surfaces of the first semiconductor device and the second semiconductor device may further have an outer circumferential region and a central region, and the ratio of the total number of the plurality of dummy bumps to the total number of the metal bumps and the dummy bumps in the outer circumferential region may be equal to or greater than the ratio of the total number of the plurality of dummy bumps to the total number of the metal bumps and the dummy bumps in the central region.

[0009] The first semiconductor device may include a CMOS (Complementary Metal Oxide Semiconductor) image sensor including vertical signal lines, and a shielding member that shields between the first semiconductor device and the second semiconductor device, and the plurality of dummy bumps may be arranged so as not to overlap with the vertical signal lines and the shielding member in a plan view seen from a connection direction between the first semiconductor device and the second semiconductor device.

[0010] The first semiconductor device and the second semiconductor device may be substantially rectangular chips, and the difference in the total number of the metal bumps and the dummy bumps between the two regions obtained by dividing the chip in the long side direction of the chip may be smaller than the difference in the total number of the metal bumps and the dummy bumps between the two regions obtained by dividing the chip in the short side direction of the chip.

[0011] In the first metal bump, which is divided into two parts, one on the first semiconductor device side and the other on the second semiconductor device side, and electrically connects the first metal bump pad and the second metal bump pad, the volume of the second semiconductor device side may be larger than the volume of the first semiconductor device side.

[0012] The second semiconductor device may be smaller than the first semiconductor device in a plan view seen from a direction in which the first semiconductor device and the second semiconductor device are connected.

[0013] The first semiconductor device may further include an external connection pad, and the first semiconductor device and / or the second semiconductor device may further include a test pad.

[0014] The number of the first dummy bump pads may be greater than the number of the first metal bump pads electrically connected to the external connection pads.

[0015] The number of the second dummy bump pads may be greater than the number of the second metal bump pads electrically connected to the test pads.

[0016] Among the plurality of first metal bump pads connected to the external connection pad, at least one of the first dummy bump pads may be arranged outside the first metal bump pad that is closest to the center of the second semiconductor device.

[0017] 10 is a cross-sectional view showing an example of the configuration of a semiconductor device according to a first embodiment. 11 is a plan view showing an example of the configuration of a semiconductor device according to a second embodiment. 12 is a cross-sectional view showing an example of the configuration of a semiconductor device according to a third embodiment. 13 is a plan view showing an example of the configuration of a semiconductor device according to a third embodiment. 14 is a cross-sectional view showing an example of the configuration of a semiconductor device according to a fourth embodiment. 15 is a cross-sectional view showing an example of the configuration of a metal bump according to a fifth embodiment. 16 is a cross-sectional view showing an example of the configuration of a semiconductor device according to a sixth embodiment. 17 is a plan view showing an example of the configuration of a semiconductor device according to a seventh embodiment. 18 is a cross-sectional view showing an example of the configuration of a semiconductor device according to an eighth embodiment. 19 is a cross-sectional view showing an example of the configuration of a semiconductor device according to a ninth embodiment. 19 is a plan view showing an example of the configuration of a semiconductor device according to a ninth embodiment. 20 is a plan view showing an example of the configuration of a semiconductor device according to a tenth embodiment. 21 is a plan view showing an example of the configuration of a semiconductor device according to an eleventh embodiment. 22 is a cross-sectional view showing an example of the configuration of a semiconductor device according to a twelfth embodiment. 23 is a plan view showing an example of the configuration of a semiconductor device according to a thirteenth embodiment.

[0018] Hereinafter, an embodiment of a semiconductor device will be described with reference to the drawings. The following description will focus on the main components of the semiconductor device, but the semiconductor device may include components and functions that are not shown or described. The following description does not exclude components and functions that are not shown or described.

[0019] (First Embodiment) A stacked image sensor as a solid-state imaging device is obtained, for example, by bonding a pixel chip to a logic chip that has an AD (Analog to Digital) circuit and a logic circuit mounted thereon. The stacked chip structure, or so-called stacked structure, is a structure in which at least two chips, a pixel chip and a logic chip, are stacked. The pixel chip is an example of a first semiconductor chip. The logic chip is an example of a second semiconductor chip. The pixel chip and the logic chip are electrically connected via connecting portions such as vias, Cu-Cu junctions, and bumps.

[0020] Although a solid-state imaging device will be described below, a semiconductor device other than a solid-state imaging device may also be used. In this case, the first semiconductor chip does not have to be a pixel chip, and the second semiconductor chip does not have to be a logic chip.

[0021] 1 is a cross-sectional view showing an example of the configuration of a semiconductor device 100 according to a first embodiment. In this specification, the upward and downward directions are treated along the vertical direction of the paper surface of FIG. 1. The downward direction may or may not coincide with the direction of gravity.

[0022] The semiconductor device 100 includes a first semiconductor chip D1, a second semiconductor chip D2, and a plurality of bumps B.

[0023] The first semiconductor device D1 is, for example, a pixel chip (first chip) including a photoelectric conversion element, but is not limited to this. Note that the photoelectric conversion element is not shown in the drawing.

[0024] The second semiconductor device D2 is, for example, a logic chip (second chip) including a logic element, but is not limited to this. Note that the logic element is not shown in the drawing.

[0025] The bumps B bond the first semiconductor device D1 and the second semiconductor device D2 together and include a plurality of metal bumps (conductive bumps) CB and a plurality of dummy bumps DB.

[0026] The metal bumps CB electrically connect the first semiconductor device D1 and the second semiconductor device D2. That is, the metal bumps CB are electrically connected to the wiring and elements in the first semiconductor device D1 and the second semiconductor device D2. The metal bumps CB also physically connect the first semiconductor device D1 and the second semiconductor device D2.

[0027] The dummy bumps DB physically connect the first semiconductor device D1 and the second semiconductor device D2, i.e., the dummy bumps DB do not need to be electrically connected to the wiring and elements in the first semiconductor device D1 and the second semiconductor device D2.

[0028] Next, the first semiconductor device D1 will be described.

[0029] The first semiconductor device D1 has a semiconductor substrate 11, insulating films 12_1 and 12_2, a plurality of metal bump pads 13, a plurality of dummy bump pads 14, wiring layers M1 to M5, external connection pads (I / O pads) EP, wiring L1, and columnar electrodes (VIA) V.

[0030] The semiconductor substrate 11 is, for example, a silicon substrate.

[0031] The insulating film 12_1 is provided on the semiconductor substrate 11. The insulating film 12_2 is provided below the semiconductor substrate 21.

[0032] The metal bump pads 13 are provided so as to be exposed from the insulating film 12_1. The metal bump pads 13 electrically connect the metal bumps CB and wiring within the first semiconductor device D1.

[0033] The dummy bump pads 14 are provided so as to be exposed from the insulating film 12_1. The dummy bump pads 14 are connected to the dummy bumps DB, but do not need to be electrically connected to the wiring inside the first semiconductor device D1. The number of dummy bump pads 14 is greater than the number of metal bump pads 13 electrically connected to the external connection pads EP.

[0034] The wiring layers M1 to M4 are provided in the insulating film 12_2.

[0035] The external connection pads EP are provided so as to be exposed from the insulating film 12_1 and are electrically connected to wiring within the first semiconductor device D1. The external connection pads EP are used, for example, to connect the semiconductor device 100 to an external device.

[0036] The wiring L1 is provided on the insulating film 12_1 and is a connection wiring that electrically connects the external connection pad EP and the metal bump CB.

[0037] The pillar-shaped electrode V is provided to penetrate the semiconductor substrate 11 and electrically connects the wiring of the insulating film 12_1 and the wiring of the insulating film 12_2. The pillar-shaped electrode V electrically connects, for example, the wiring layer M1 and the wiring L1.

[0038] Next, the second semiconductor device D2 will be described.

[0039] The second semiconductor device D2 has a semiconductor substrate 21, an insulating film 22, a plurality of metal bump pads 23, a plurality of dummy bump pads 24, wiring layers M1 to M10, and a test pad TP.

[0040] The semiconductor substrate 21 is, for example, a silicon substrate.

[0041] The insulating film 22 is provided below the semiconductor substrate 21 .

[0042] The metal bump pads 23 are provided so as to be exposed from the insulating film 22. The metal bump pads 23 electrically connect the metal bumps CB and wiring within the second semiconductor device D2.

[0043] The dummy bump pads 24 are provided so as to be exposed from the insulating film 22. The dummy bump pads 24 are connected to the dummy bumps DB, but do not need to be electrically connected to the wiring in the second semiconductor device D2. The number of dummy bump pads 24 is greater than the number of metal bump pads 23 electrically connected to the test pads TP.

[0044] The wiring layers M1 to M10 are provided in the insulating film 22.

[0045] The test pads TP are provided so as to be exposed from the insulating film 22 and are electrically connected to wiring within the second semiconductor device D2. The test pads TP are used, for example, for an operation test of the second semiconductor device D2 before bonding.

[0046] 2 is a plan view showing an example of the configuration of the semiconductor device 100 according to the first embodiment, showing the arrangement of metal bumps CB, dummy bumps DB, external connection pads EP, and test pads TP.

[0047] 2, the size (area) of the first semiconductor device D1 is different from the size of the second semiconductor device D2 in a plan view seen from the direction in which the first semiconductor device D1 and the second semiconductor device D2 are connected. More specifically, the size of the second semiconductor device D2 is smaller than the size of the first semiconductor device D1 in a plan view.

[0048] The first semiconductor device D1 and the second semiconductor device D2 are, for example, substantially rectangular chips in plan view.

[0049] The external connection pads EP are provided along the sides of the first semiconductor device D1. The second semiconductor device D2 is provided inside the first semiconductor device D1 with respect to the external connection pads EP in a plan view. The test pads TP are provided along one long side of the second semiconductor device D2. Metal bumps CB and dummy bumps DB are provided in areas of the second semiconductor device D2 other than the test pads TP.

[0050] The bonding surface (connection surface) between the first semiconductor device D1 and the second semiconductor device D2 has a peripheral region R1 and a central region R2.

[0051] The peripheral region R1 is a region on the side of the first semiconductor device D1 that faces the external connection pads EP, including the metal bumps CB1, which will be described later. That is, the peripheral region R1 is determined by the distance from the side of the bonding surface on which the external connection pads EP corresponding to the metal bumps CB1 are provided to the position of the metal bumps CB1.

[0052] The central region R2 is a region of the joining surface other than the outer peripheral region R1.

[0053] In a planar view, the second semiconductor device D2 is rectangular, and the semiconductor device 100 has a metal bump CB1 that is located closest to the center of the second semiconductor device D2 among one or more metal bump pads 23 (and / or metal bumps CB) connected via wiring L1 to external connection pads EP arranged along a first side of the second semiconductor device D2.

[0054] The semiconductor device 100 has external connection pads EP arranged along each side of the second semiconductor device D2 in a plan view, and among the metal bump pads 23 (and metal bumps CB) connected to the external connection pads EP corresponding to each side via wiring L1, the semiconductor device 100 has a metal bump CB1 located closest to the center of the second semiconductor device D2. When an outer peripheral region R1 is defined as a region including the same position (same distance from the side as the metal bump CB1) as the metal bump CB1 located closest to the center of the second semiconductor device D2 corresponding to each side in a direction perpendicular to each side, or a position closer to each side, the semiconductor device 100 has at least one dummy bump DB (and / or dummy bump pad 24) in the outer peripheral region R1.

[0055] That is, the metal bump CB1 is the bump that is closest to the center of the second semiconductor device among the metal bumps CB electrically connected via the external connection pads EP and wiring L1 on each side of the first semiconductor device D1. The four metal bumps CB1 are provided to correspond to the four sides of the first semiconductor device D1.

[0056] By placing additional dummy bumps DB and increasing the number of bumps B, the surface tension and interfacial tension acting between devices during bonding (during the alloying reaction between the bumps and pads) can be strengthened, thereby promoting bonding between devices.

[0057] The ratio of the dummy bumps DB to the total number of bumps B, which is the sum of the metal bumps CB and the dummy bumps DB, is in the peripheral region ≧ the central region. That is, the ratio of the total number of the plurality of dummy bumps DB to the total number of the metal bumps CB and the dummy bumps DB in the peripheral region R1 is equal to or greater than the ratio of the total number of the plurality of dummy bumps DB to the total number of the metal bumps CB and the dummy bumps DB in the central region R2.

[0058] As a result, when the second semiconductor device D2 warps, the bonding of the outer periphery region R1 can be strengthened by additionally arranging many dummy bumps DB in the outer periphery region R1.

[0059] The number of dummy bumps DB is greater than the number of metal bumps CB connected to the external connection pads EP or the test pads TP. More specifically, in the first semiconductor device D1, the number of dummy bump pads 14 is greater than the number of metal bump pads 13 connected to the external connection pads EP, and in the second semiconductor device D2, the number of dummy bump pads 24 is greater than the number of metal bump pads 23 connected to the test pads TP.

[0060] As a result, by arranging the dummy bumps DB on the outside of the metal bumps CB1, it is possible to prevent the metal bumps CB, including the bumps connected externally, from being unbonded. Even if unbonding or bonding defects occur due to warping of the device, the dummy bumps DB located on the outside are sacrificed preferentially, thereby preventing the unbonding of the inner metal bumps CB as much as possible.

[0061] As described above, the first semiconductor device D1 and the second semiconductor device D2 are electrically connected via the metal bumps CB and the metal bump pads 13, 23. Furthermore, the first semiconductor device D1 and the second semiconductor device D2 are physically connected via the dummy bumps DB and the dummy bump pads 14, 24.

[0062] Furthermore, the dummy bumps DB can strengthen the bonding between devices (chips). Furthermore, bonding can be strengthened in devices or processes where bonding is difficult due to significant chip warpage during bonding. By adding and arranging many dummy bumps on the periphery of a chip, where bonding becomes difficult when the chip is warped, the surface tension and interfacial tension acting between the chips during bonding (during the alloying reaction between the bumps and pads) can be strengthened, promoting bonding of the periphery and the entire chip. Furthermore, by adding and arranging dummy bumps DB outside the metal bumps CB1, it is possible to prevent non-bonding of the metal bumps CB, including the bumps that are externally connected.

[0063] As a result, the chips can be bonded together more appropriately.

[0064] Furthermore, the dummy bump DB is in an electrically floating state via the dummy bump pad 14 or 24 .

[0065] This makes it possible to prevent the formation of unnecessary capacitance or resistance in the signal circuits of the first semiconductor device D1 and the second semiconductor device D2.

[0066] Furthermore, the material of the dummy bumps DB may be the same as or different from the material of the metal bumps CB. The shape of the dummy bumps DB may be the same as or different from the shape of the metal bumps CB. It is preferable that the material of the dummy bumps DB is the same as the material of the metal bumps CB and that the shape of the dummy bumps DB is the same as the shape of the metal bumps CB.

[0067] This allows the dummy bumps DB and the metal bumps CB to be formed simultaneously.

[0068] The number of wiring layers is not limited to the example shown in FIG.

[0069] The test pads TP may be provided on the first semiconductor device D1, and in this case, the test pads TP do not have to be provided on the second semiconductor device D2.

[0070] 3 is a cross-sectional view showing an example of the configuration of a semiconductor device 100 according to a second embodiment. The second embodiment differs from the first embodiment in that an external connection pad EP is not provided on one side of the first semiconductor device D1.

[0071] The peripheral region R1 is defined excluding the side direction on which no external connection pads EP are provided. Note that the peripheral region R1 may be defined excluding two or more sides.

[0072] Unlike the second embodiment, the external connection pad EP does not have to be provided on one side of the first semiconductor device D1. The semiconductor device 100 according to the second embodiment can achieve the same effects as the first embodiment. Furthermore, each embodiment and / or each component of each embodiment can be combined.

[0073] 4 is a cross-sectional view showing an example of the configuration of a semiconductor device 100 according to a third embodiment. Fig. 5 is a plan view showing an example of the configuration of a semiconductor device 100 according to a third embodiment. The third embodiment differs from the first embodiment in that wiring and the like that interfere with the bump B are provided near the bonding surface.

[0074] The first semiconductor device D1 has a complementary metal oxide semiconductor (CMOS) image sensor (CIS). Dummy bumps DB are arranged so as not to overlap, in plan view, with the vertical signal lines VSL of the first semiconductor device D1 and the shielding member SH (shielding metal) between the first and second semiconductor devices D1 and D2.

[0075] As a result, by additionally arranging the dummy bumps DB in accordance with the design layout of the first semiconductor device D1, it is possible to avoid limitations and restrictions on the structure and degree of freedom of design that can be applied in actual use.

[0076] The vertical signal line VSL is a signal line included in the CMOS image sensor. The vertical signal line VSL is provided, for example, in a layer in which the metal bump pads 13 are provided. The vertical signal line VSL shown in FIGS. 4 and 5 is electrically connected to the metal bump pads 13.

[0077] The shield member SH shields the first semiconductor device D1 and the second semiconductor device D2. The shield member SH is provided, for example, in a layer on which the bumps B are provided. The shield member SH includes a metal. The shield member SH may be connected to the elements and wiring of the first semiconductor device D1, or may not be connected to the elements and wiring of the first semiconductor device D1. The shield member SH may or may not be in the form of a wiring.

[0078] As in the third embodiment, wiring or the like that interferes with the bump B may be provided. The semiconductor device 100 according to the third embodiment can achieve the same effects as the first embodiment. Furthermore, each embodiment and / or each component of each embodiment can be combined.

[0079] 6 is a cross-sectional view showing an example of the configuration of a semiconductor device 100 according to a fourth embodiment. The fourth embodiment is an embodiment that explains the number and arrangement of bumps B.

[0080] The upper part of Fig. 6 is a diagram showing the joining surface divided into two in the short side direction. The dashed line in the upper part of Fig. 6 is a line dividing the joining surface into two in the short side direction. The two divided regions are aligned in the short side direction. The lower part of Fig. 6 is a diagram showing the joining surface divided into two in the long side direction. The dashed line in the lower part of Fig. 6 is a line dividing the joining surface into two in the long side direction. The two divided regions are aligned in the long side direction.

[0081] The difference in the total number of bumps B, including the metal bumps CB and dummy bumps DB, arranged in each of the regions when the second semiconductor device is divided into two along the long side, is smaller than the difference in the total number of bumps B, including the metal bumps CB and dummy bumps DB, arranged in each of the regions when the device is divided into two along the short side.

[0082] This reduces the difference in the number of bumps between the left and right or top and bottom halves of the long side, where warping is greatest, in the event that the device warps, thereby reducing the difference in surface tension and interfacial tension acting on each region and preventing the device from being pulled to one side during bonding. In other words, if the surface tension in one region is high, the device will be pulled to that side, making bonding difficult in the other region.

[0083] The total number of bumps B, including the metal bumps CB and dummy bumps DB, arranged in each region when the second semiconductor device D2 is divided into two in the long side direction and / or short side direction is ±10.

[0084] This minimizes the difference in the number of bumps B when the device is divided into two halves along the long and short sides, thereby reducing the difference in surface tension and interfacial tension acting on each region, suppressing θ rotation of the device during bonding and preventing shape abnormalities (elongation, etc.) of the bumps B.

[0085] The total number of bumps arranged in each of the regions divided in the long side direction and / or short side direction is the same.

[0086] By making the number of bumps B equal in each division direction, the above two effects are enhanced.

[0087] Bumps B may be provided in the number and arrangement shown in the fourth embodiment. The semiconductor device 100 according to the fourth embodiment can obtain the same effects as those of the first embodiment. Furthermore, each embodiment and / or each component of each embodiment can be combined.

[0088] 7 is a cross-sectional view showing an example of the configuration of a metal bump CB according to a fifth embodiment. The fifth embodiment differs from the first embodiment in that the volume of the metal bump CB on the second semiconductor device D2 side is larger than the volume of the metal bump CB on the first semiconductor device D1 side.

[0089] 7 vertically divides the metal bump CB into two parts, that is, the metal bump CB is divided into two parts on the first semiconductor device D1 side and the second semiconductor device D2 side.

[0090] The volume of the metal bump CB on the second semiconductor device D2 side is larger than the volume of the metal bump CB on the first semiconductor device D1 side. For example, the area (opening size) of the metal bump pad 23 exposed from the insulating film 22 is larger than the area of ​​the metal bump pad 13 exposed from the insulating film 12_1.

[0091] This causes the contact angle of the metal bump CB to be smaller on the second semiconductor device side than on the first semiconductor device side, which results in stronger surface tension and interfacial tension acting on the second semiconductor device D2, promoting and strengthening bonding when the second semiconductor device D2 warps.

[0092] The dummy bumps DB may have the same shape as the metal bumps CB, and the volume of the dummy bumps DB on the second semiconductor device D2 side may be larger than the volume of the dummy bumps DB on the first semiconductor device D1 side.

[0093] As in the fifth embodiment, the volume of the metal bump CB on the second semiconductor device D2 side may be larger than the volume of the metal bump CB on the first semiconductor device D1 side. The semiconductor device 100 according to the fifth embodiment can achieve the same effects as the first embodiment. Furthermore, each embodiment and / or each component of each embodiment can be combined.

[0094] 8 is a cross-sectional view showing an example of the configuration of a semiconductor device 100 according to a sixth embodiment. FIG. 9 is a plan view showing an example of the configuration of a semiconductor device 100 according to the sixth embodiment. The sixth embodiment differs from the first embodiment in that the size of the first semiconductor device D1 and the size of the second semiconductor device D2 are substantially the same. Furthermore, in the sixth embodiment, unlike the first embodiment, the external connection pads EP and the test pads TP are not provided.

[0095] As in the sixth embodiment, the size of the first semiconductor device D1 and the size of the second semiconductor device D2 may be substantially the same. The semiconductor device 100 according to the sixth embodiment can achieve the same effects as the first embodiment. Furthermore, the respective embodiments and / or the respective components of the respective embodiments can be combined.

[0096] 10 is a cross-sectional view showing an example of the configuration of a semiconductor device 100 according to a seventh embodiment. The seventh embodiment differs from the sixth embodiment in that external connection pads EP are provided on the surface opposite to the bonding surface.

[0097] The external connection pads EP are provided on the surface opposite to the bonding surface with the second semiconductor device D2, that is, on the bottom surface of the first semiconductor device D1.

[0098] The external connection pads EP and the metal bump pads 13 are electrically connected via the columnar electrodes V and the wiring layers M1 to M4.

[0099] As in the seventh embodiment, the external connection pads EP may be provided on the surface opposite to the bonding surface. The semiconductor device 100 according to the seventh embodiment can achieve the same effects as the sixth embodiment. Furthermore, each embodiment and / or each component of each embodiment can be combined.

[0100] 11 is a cross-sectional view showing an example of the configuration of a semiconductor device 100 according to an eighth embodiment. The eighth embodiment differs from the seventh embodiment in that external connection pads EP are connected to wiring L1 or metal bump pads 13 via columnar electrodes V.

[0101] As in the eighth embodiment, the external connection pad EP may be connected to the wiring L1 or the metal bump pad 13 via the columnar electrode V. The semiconductor device 100 according to the eighth embodiment can obtain the same effects as the seventh embodiment. Furthermore, each embodiment and / or each component of each embodiment can be combined.

[0102] 12 is a cross-sectional view showing an example of the configuration of a semiconductor device 100 according to a ninth embodiment. Fig. 13 is a plan view showing an example of the configuration of a semiconductor device 100 according to a ninth embodiment. The ninth embodiment differs from the seventh embodiment in that a test pad TP is provided.

[0103] The test pads TP are provided on both the first semiconductor device D1 and the second semiconductor device D2. Note that the test pads TP may be provided on either the first semiconductor device D1 or the second semiconductor device D2.

[0104] As in the ninth embodiment, a test pad TP may be provided. The semiconductor device 100 according to the ninth embodiment can obtain the same effects as those of the seventh embodiment. Furthermore, the respective embodiments and / or the respective components of the respective embodiments can be combined.

[0105] 14 is a plan view showing an example of the configuration of a semiconductor device 100 according to a tenth embodiment. The tenth embodiment differs from the first embodiment in that the size of the first semiconductor device D1 and the size of the second semiconductor device D2 are substantially the same. The tenth embodiment is also a combination of the first and sixth embodiments.

[0106] As in the first embodiment, the peripheral region R1 is a region on the side of the external connection pad EP including the metal bump CB1 with respect to each side of the first semiconductor device D1. That is, the peripheral region R1 is determined by the distance from the side of the bonding surface on which the external connection pad EP corresponding to the metal bump CB1 is provided to the position of the metal bump CB1.

[0107] The central region R2 is a region of the bonding surface other than the outer peripheral region R1, as in the first embodiment.

[0108] As in the tenth embodiment, the size of the first semiconductor device D1 and the size of the second semiconductor device D2 may be substantially the same. The semiconductor device 100 according to the tenth embodiment can achieve the same effects as the first embodiment. Furthermore, each embodiment and / or each component of each embodiment can be combined.

[0109] 15 is a plan view showing an example of the configuration of a semiconductor device 100 according to an eleventh embodiment. The eleventh embodiment differs from the tenth embodiment in that no external connection pad EP is provided on one side of the first semiconductor device D1. The eleventh embodiment is also a combination of the second and sixth embodiments.

[0110] Unlike the eleventh embodiment, the external connection pad EP does not have to be provided on one side of the first semiconductor device D1. The semiconductor device 100 according to the eleventh embodiment can achieve the same effects as the tenth embodiment. Furthermore, the respective embodiments and / or the respective components of the respective embodiments can be combined.

[0111] 12th Embodiment Fig. 16 is a cross-sectional view showing an example of the configuration of a semiconductor device 100 according to a 12th embodiment. Fig. 17 is a plan view showing an example of the configuration of a semiconductor device 100 according to a 12th embodiment. The 12th embodiment differs from the 10th embodiment in that wiring and the like that interfere with the bump B are provided near the bonding surface. The 12th embodiment is also a combination of the third embodiment and the sixth embodiment.

[0112] As in the twelfth embodiment, wiring or the like that interferes with the bump B may be provided near the bonding surface. The semiconductor device 100 according to the twelfth embodiment can obtain the same effects as the tenth embodiment. Furthermore, each embodiment and / or each component of each embodiment can be combined.

[0113] 18 is a plan view showing an example of the configuration of a semiconductor device 100 according to a thirteenth embodiment. The thirteenth embodiment is an embodiment that explains the number and arrangement of bumps B. The thirteenth embodiment is also a combination of the fourth and sixth embodiments.

[0114] The upper part of Fig. 18 is a diagram showing the joining surface divided into two in the short side direction. The dashed line in the upper part of Fig. 18 is a line dividing the joining surface into two in the short side direction. The two divided regions are aligned in the short side direction. The lower part of Fig. 18 is a diagram showing the joining surface divided into two in the long side direction. The dashed line in the lower part of Fig. 18 is a line dividing the joining surface into two in the long side direction. The two divided regions are aligned in the long side direction.

[0115] Bumps B may be provided in the number and arrangement shown in the thirteenth embodiment. The semiconductor device 100 according to the thirteenth embodiment can obtain the same effects as those of the tenth embodiment. Furthermore, the respective embodiments and / or the respective components of the respective embodiments can be combined.

[0116] The present technology can be configured as follows: (1) A semiconductor device comprising: a first semiconductor device having a plurality of first metal bump pads including a first metal bump pad and a plurality of first dummy bump pads including a first dummy bump pad; a second semiconductor device having a plurality of second metal bump pads including a second metal bump pad and a plurality of second dummy bump pads including a second dummy bump pad; a plurality of metal bumps including a first metal bump; and a plurality of dummy bumps including a first dummy bump, wherein the first semiconductor device and the second semiconductor device are electrically connected via the first metal bumps, the first metal bump pads, and the second metal bump pads, and are physically connected via the first dummy bumps, the first dummy bump pads, and the second dummy bump pads. (2) The semiconductor device according to (1), wherein the dummy bumps are in a floating state via the first dummy bump pads or the second dummy bump pads. (3) The semiconductor device according to (1), wherein the connection surfaces of the first semiconductor device and the second semiconductor device further have an outer circumferential region and a central region, and a ratio of the total number of the plurality of dummy bumps to the total number of the metal bumps and the dummy bumps in the outer circumferential region is equal to or greater than a ratio of the total number of the plurality of dummy bumps to the total number of the metal bumps and the dummy bumps in the central region. (4) The semiconductor device according to (1), wherein the first semiconductor device has: a CMOS (Complementary Metal Oxide Semiconductor) image sensor including vertical signal lines; and a shielding member that shields between the first semiconductor device and the second semiconductor device, and the plurality of dummy bumps are arranged so as not to overlap the vertical signal lines and the shielding member in a plan view seen from the connection direction of the first semiconductor device and the second semiconductor device.(5) The semiconductor device according to (1), wherein the first semiconductor device and the second semiconductor device are substantially rectangular chips, and the difference in the total number of the metal bumps and the dummy bumps between two regions obtained by dividing the chip in the long side direction of the chip is smaller than the difference in the total number of the metal bumps and the dummy bumps between two regions obtained by dividing the chip in the short side direction of the chip. (6) The semiconductor device according to (1), wherein the first metal bump electrically connects the first metal bump pad and the second metal bump pad, which are divided into two portions on the first semiconductor device side and the second semiconductor device side, and the volume of the second semiconductor device side is larger than the volume of the first semiconductor device side. (7) The semiconductor device according to (1), wherein the second semiconductor device is smaller than the first semiconductor device in a plan view seen from the connection direction of the first semiconductor device and the second semiconductor device. (8) The semiconductor device according to (1), wherein the first semiconductor device further includes an external connection pad, and the first semiconductor device and / or the second semiconductor device further include a test pad. (9) The semiconductor device according to (8), wherein the number of the first dummy bump pads is greater than the number of the first metal bump pads electrically connected to the external connection pad. (10) The semiconductor device according to (8), wherein the number of the second dummy bump pads is greater than the number of the second metal bump pads electrically connected to the test pad. (11) The semiconductor device according to (8), wherein, of the plurality of first metal bump pads connected to the external connection pad, at least one first dummy bump pad is arranged outside the first metal bump pad that is closest to the center of the second semiconductor device.

[0117] The aspects of the present disclosure are not limited to the individual embodiments described above, but include various modifications that may be conceived by those skilled in the art, and the effects of the present disclosure are not limited to the above-described contents. In other words, various additions, modifications, and partial deletions are possible within the scope of the conceptual idea and spirit of the present disclosure, which is derived from the contents defined in the claims and their equivalents.

[0118] 100 semiconductor device, 13 metal bump pad, 14 dummy bump pad, 23 metal bump pad, 24 dummy bump pad, D1 first semiconductor device, D2 second semiconductor device, B bump, CB metal bump, DB dummy bump, M1 to M10 wiring layer, V columnar electrode, EP external connection pad, TP test pad, SH shielding member, R1 peripheral region, R2 central region

Claims

1. A semiconductor device comprising: a first semiconductor device having a plurality of first metal bump pads including a first metal bump pad and a plurality of first dummy bump pads including a first dummy bump pad; a second semiconductor device having a plurality of second metal bump pads including a second metal bump pad and a plurality of second dummy bump pads including a second dummy bump pad; a plurality of metal bumps including a first metal bump; and a plurality of dummy bumps including a first dummy bump; wherein the first semiconductor device and the second semiconductor device are electrically connected via the first metal bumps, the first metal bump pads, and the second metal bump pads, and are physically connected via the first dummy bumps, the first dummy bump pads, and the second dummy bump pads.

2. The semiconductor device according to claim 1, wherein the dummy bump is in a floating state via the first dummy bump pad or the second dummy bump pad.

3. The semiconductor device according to claim 1, wherein the connection surfaces of the first semiconductor device and the second semiconductor device further have an outer periphery region and a central region, and the ratio of the total number of the plurality of dummy bumps to the total number of the metal bumps and the dummy bumps in the outer periphery region is equal to or greater than the ratio of the total number of the plurality of dummy bumps to the total number of the metal bumps and the dummy bumps in the central region.

4. The semiconductor device according to claim 1, wherein the first semiconductor device has a CMOS (Complementary Metal Oxide Semiconductor) image sensor including a vertical signal line, and a shielding member that shields between the first semiconductor device and the second semiconductor device, and the plurality of dummy bumps are arranged so as not to overlap the vertical signal line and the shielding member in a plan view seen from the direction of connection between the first semiconductor device and the second semiconductor device.

5. The semiconductor device according to claim 1, wherein the first semiconductor device and the second semiconductor device are substantially rectangular chips, and the difference in the total number of the metal bumps and the dummy bumps between the two regions obtained by dividing the chip in the long side direction of the chip is smaller than the difference in the total number of the metal bumps and the dummy bumps between the two regions obtained by dividing the chip in the short side direction of the chip.

6. The semiconductor device according to claim 1, wherein the first metal bump electrically connects the first metal bump pad and the second metal bump pad, which are divided into two parts on the first semiconductor device side and the second semiconductor device side, and the volume of the second semiconductor device side is larger than the volume of the first semiconductor device side.

7. The semiconductor device according to claim 1, wherein the second semiconductor device is smaller than the first semiconductor device in a plan view seen from the direction in which the first semiconductor device and the second semiconductor device are connected.

8. The semiconductor device according to claim 1, wherein the first semiconductor device further has an external connection pad, and the first semiconductor device and / or the second semiconductor device further has a test pad.

9. The semiconductor device according to claim 8, wherein the number of said first dummy bump pads is greater than the number of said first metal bump pads electrically connected to said external connection pads.

10. The semiconductor device according to claim 8, wherein the number of said second dummy bump pads is greater than the number of said second metal bump pads electrically connected to said test pads.

11. The semiconductor device according to claim 8, wherein at least one of the first dummy bump pads is arranged outside the first metal bump pad that is closest to the center of the second semiconductor device among the plurality of first metal bump pads connected to the external connection pad.

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