Semiconductor device and method for manufacturing semiconductor device

Abstract

Boron halide is ion-implanted by using an interlayer insulating film as a mask, and a p++-type region is selectively formed in a semiconductor part exposed in a contact hole of the interlayer insulating film. After the surface layer of the interlayer insulating film is removed at a predetermined thickness, a barrier metal is formed along the inner wall of the contact hole and the upper surface of the interlayer insulating film. As a result of removing the surface layer of the interlayer insulating film at a prescribed thickness, the interlayer insulating film does not contain a halogen element, or the concentration of halogen elements per unit volume of the interlayer insulating film is no greater than 1019 / cm3, increasing the adhesion strength between the interlayer insulating film and the barrier metal. The barrier metal forms an ohmic contact with the semiconductor part in the contact hole. Thereafter, a plug is embedded in the contact hole, and a surface electrode is formed from above the plug to above the barrier metal on the upper surface of the interlayer insulating film. Increasing the adhesion strength between the interlayer insulating film and the barrier metal makes it possible to suppress peeling of the surface electrode.

Description

Semiconductor device and method for manufacturing the same

[0001] The present disclosure relates to a semiconductor device and a method for manufacturing the same.

[0002] Patent Document 1 listed below describes a technique for forming a barrier metal between a front surface electrode and a semiconductor portion to improve adhesion between the front surface electrode and the semiconductor portion and form an ohmic contact with the semiconductor portion. Patent Documents 2 and 3 listed below also describe similar techniques. Patent Document 2 listed below describes a structure in which the impurity concentration of the contact region and anode region is relatively high in the portion exposed to the contact hole. Patent Document 3 listed below also describes a similar structure. Patent Document 4 listed below describes a technique for improving adhesion between a silicon substrate and a barrier metal.

[0003] International Publication No. 2019 / 93015 Patent No. 6704057 Patent No. 6319057 Japanese Patent Application Laid-Open No. 2023-45176

[0004] In the above Patent Documents 1 to 3, after forming a contact hole in an interlayer insulating film, if the p-type impurity concentration in the surface of the semiconductor portion exposed in the contact hole is partially increased by ion implantation of p-type impurities, the p-type impurities are also ion implanted into the interlayer insulating film. In this case, depending on the ion species, halogen elements may be introduced into the surface layer of the interlayer insulating film, which may deteriorate the adhesion between the interlayer insulating film and the barrier metal, and may cause the barrier metal to peel off from the interlayer insulating film.

[0005] An object of this disclosure is to provide a semiconductor device and a method for manufacturing the semiconductor device that can suppress peeling of the surface electrode.

[0006] A method for manufacturing a semiconductor device according to one aspect of the present disclosure is as follows: a first step of forming an element structure on a first main surface side of a semiconductor substrate; a second step of forming an interlayer insulating film on the first main surface of the semiconductor substrate to cover the element structure; a third step of forming a first contact hole penetrating the interlayer insulating film in the depth direction and exposing the semiconductor substrate; an implantation step of ion-implanting a predetermined impurity using the interlayer insulating film as an ion implantation mask to selectively form a diffusion region of a predetermined conductivity type in a portion of the semiconductor substrate exposed in the first contact hole; after the implantation step, a removal step of removing a surface layer of the interlayer insulating film to a predetermined thickness; a first film-forming step of forming a barrier metal from inside the first contact hole to the upper surface of the interlayer insulating film exposed by the removal step; a second film-forming step of forming a surface electrode electrically connected to the element structure via the barrier metal; in the removal step, the interlayer insulating film is removed from the upper surface to at least a depth position corresponding to the maximum concentration of the predetermined impurity ion-implanted in the implantation step.

[0007] A method for manufacturing a semiconductor device according to one aspect of the present disclosure is as follows: a first step of forming an element structure on a first main surface side of a semiconductor substrate; a second step of forming an interlayer insulating film covering the element structure on the first main surface of the semiconductor substrate; a third step of forming a first contact hole penetrating the interlayer insulating film in the depth direction to expose the semiconductor substrate; an implantation step of ion-implanting a predetermined impurity to selectively form a diffusion region of a predetermined conductivity type in a portion of the semiconductor substrate exposed in the first contact hole; after the implantation step, a first film-forming step of forming a barrier metal from inside the first contact hole to an upper surface of the interlayer insulating film; and a second film-forming step of forming a surface electrode electrically connected to the element structure via the barrier metal. The implantation step includes a masking step of covering the interlayer insulating film with a mask having an opening in a portion corresponding to a formation region of the diffusion region, a step of ion-implanting the predetermined impurity into the semiconductor substrate through the mask, and a step of removing the mask used in the ion implantation. In the first film-forming step, the barrier metal is formed on the upper surface of the interlayer insulating film exposed by removing the mask.

[0008] Also, a method for manufacturing a semiconductor device according to one aspect of this disclosure is as follows: a first step of forming an element structure on a first main surface side of a semiconductor substrate is performed; a second step of forming an interlayer insulating film on the first main surface of the semiconductor substrate to cover the element structure is performed; a third step of forming a first contact hole that penetrates the interlayer insulating film in the depth direction and exposes the semiconductor substrate is performed; an implantation step of ion-implanting a predetermined impurity using the interlayer insulating film as an ion implantation mask to selectively form a diffusion region of a predetermined conductivity type in a portion of the semiconductor substrate exposed in the first contact hole is performed after the implantation step; a first film-forming step of forming a barrier metal from inside the first contact hole to an upper surface of the interlayer insulating film is performed; and a second film-forming step of forming a surface electrode electrically connected to the element structure via the barrier metal. The method further includes a first processing step, after the first film formation step and before the second film formation step, of removing the barrier metal on the upper surface of the interlayer insulating film to expose the upper surface of the interlayer insulating film and leaving a remaining first barrier metal only inside the first contact hole, a removal step, after the first processing step, of removing a surface layer of the interlayer insulating film by a predetermined thickness, and a third film formation step of forming a second barrier metal on the upper surface of the interlayer insulating film exposed by the removal step. In the removal step, the interlayer insulating film is removed from the upper surface to at least a depth position of a maximum concentration of the predetermined impurity ion-implanted in the implantation step.

[0009] Also, a semiconductor device according to one aspect of this disclosure is as follows: An element structure is provided on a first main surface side of a semiconductor substrate. An interlayer insulating film is provided on the first main surface of the semiconductor substrate. The interlayer insulating film covers the element structure. A first contact hole is provided that penetrates the interlayer insulating film in the depth direction and exposes the semiconductor substrate. A barrier metal is provided from the surface of the semiconductor substrate exposed in the first contact hole to the surface of the interlayer insulating film. The barrier metal is electrically connected to the element structure. A surface electrode is electrically connected to the element structure via the barrier metal. The interlayer insulating film contains a halogen element. The concentration of the halogen element per unit volume of the interlayer insulating film is 1×10 19 / cm 3 The following is the result.

[0010] The semiconductor device and the method for manufacturing the semiconductor device according to the present disclosure have the advantage of being able to suppress peeling of the surface electrode.

[0011] FIG. 1 is a plan view showing a layout of a semiconductor device according to a first embodiment as viewed from the front surface side of a semiconductor substrate. FIG. 2 is a plan view showing an enlarged view of a rectangular frame A in FIG. 1. FIG. 3 is a cross-sectional view showing a cross-sectional structure taken along line B1-B1' in FIG. 2. FIG. 4 is a cross-sectional view showing a cross-sectional structure taken along line B2-B2' in FIG. 2. FIG. 5 is a flowchart showing an outline of a method for manufacturing a semiconductor device according to a first embodiment. FIG. 6 is a cross-sectional view showing a state during manufacturing of a semiconductor device according to a first embodiment (part 1). FIG. 7 is a plan view showing a state during manufacturing of a semiconductor device according to a first embodiment. FIG. 8 is a cross-sectional view showing a cross-sectional structure taken along line C1-C1' in FIG. 7. FIG. 9 is a cross-sectional view showing a cross-sectional structure taken along line C2-C2' in FIG. 7. FIG. 10 is a cross-sectional view showing a state during manufacturing of a semiconductor device according to a first embodiment (part 2). FIG. 11 is a cross-sectional view showing a state during manufacturing of a semiconductor device according to a first embodiment (part 3). FIG. 12 is a cross-sectional view showing a state during manufacturing of a semiconductor device according to a first embodiment (part 4). FIG. 13 is a cross-sectional view showing a state during manufacturing of a semiconductor device according to a first embodiment (part 5). FIG. 14 is a cross-sectional view (part 6) showing a semiconductor device according to the first embodiment in the course of its manufacture. FIG. 15 is a cross-sectional view (part 7) showing a semiconductor device according to the first embodiment in the course of its manufacture. FIG. 16A is a cross-sectional view showing an example of the structure of the semiconductor device according to the first embodiment. FIG. 16B is a cross-sectional view showing another example of the structure of the semiconductor device according to the first embodiment. FIG. 17 is a cross-sectional view showing an example of the structure of the semiconductor device according to the second embodiment. FIG. 18 is a flowchart showing an outline of a method for manufacturing a semiconductor device according to the second embodiment. FIG. 19 is a cross-sectional view showing a semiconductor device according to the second embodiment in the course of its manufacture. FIG. 20 is a plan view showing a semiconductor device according to the second embodiment in the course of its manufacture. FIG. 21 is a cross-sectional view showing a cross-sectional structure taken along line D1-D1' in FIG. 20. FIG. 22 is a cross-sectional view showing a cross-sectional structure taken along line D2-D2' in FIG. 20. FIG. 23 is a cross-sectional view (part 1) showing an example of the structure of the semiconductor device according to the third embodiment. FIG. 24 is a cross-sectional view (part 2) showing an example of the structure of the semiconductor device according to the third embodiment. FIG. 25 is a cross-sectional view showing a structure of the semiconductor device according to the fourth embodiment.FIG. 26 is a flowchart outlining a method for manufacturing a semiconductor device according to a fourth embodiment. FIG. 27 is a cross-sectional view (part 1) showing a state during the manufacturing of a semiconductor device according to the fourth embodiment. FIG. 28 is a cross-sectional view (part 2) showing a state during the manufacturing of a semiconductor device according to the fourth embodiment. FIG. 29 is a cross-sectional view (part 3) showing a state during the manufacturing of a semiconductor device according to the fourth embodiment. FIG. 30 is a cross-sectional view (part 4) showing a state during the manufacturing of a semiconductor device according to the fourth embodiment. FIG. 31 is a cross-sectional view (part 5) showing a state during the manufacturing of a semiconductor device according to the fourth embodiment. FIG. 32 is a cross-sectional view (part 6) showing a state during the manufacturing of a semiconductor device according to the fourth embodiment. FIG. 33 is a cross-sectional view showing a structure of a modified example of the semiconductor device according to the fourth embodiment. FIG. 34 is a cross-sectional view showing a structure of a semiconductor module according to the fifth embodiment. FIG. 35 is a cross-sectional view showing a structure of a semiconductor device according to a reference example. FIG. 36 is a flowchart outlining a method for manufacturing a semiconductor device according to a reference example. FIG. 37 is a cross-sectional view (part 1) showing a state during the manufacturing of a semiconductor device according to a reference example. FIG. 38 is a cross-sectional view (part 2) showing a state during the manufacturing of a semiconductor device according to a reference example. FIG. 39 is a cross-sectional view (part 3) showing a state during the manufacturing of a semiconductor device according to a reference example. FIG. 40 is a cross-sectional view (part 1) showing a structural example of a semiconductor device according to the seventh embodiment. FIG. 41 is a cross-sectional view (part 2) showing a structural example of a semiconductor device according to the seventh embodiment. FIG. 42 is a cross-sectional view (part 3) showing a structural example of a semiconductor device according to the seventh embodiment. FIG. 43 is a plan view showing a layout of a semiconductor device according to an eighth embodiment as viewed from the front surface side of a semiconductor substrate. FIG. 44A is a cross-sectional view showing a cross-sectional structure taken along line E1-E1' in FIG. 43. FIG. 44B is a cross-sectional view (part 1) showing another example of the cross-sectional structure taken along line E1-E1' in FIG. 43. FIG. 44C is a cross-sectional view (part 2) showing another example of the cross-sectional structure taken along line E1-E1' in FIG. 43. FIG. 45 is a cross-sectional view showing a cross-sectional structure taken along line E2-E2' in FIG. 43. FIG. 46 is a plan view showing a semiconductor device according to the eighth embodiment in the middle of its manufacture. FIG. 47A is a cross-sectional view showing a cross-sectional structure taken along line E3-E3' in FIG. 46. FIG. 47B is a cross-sectional view (part 1) showing another example of the cross-sectional structure taken along the line E3-E3' in FIG.47C is a cross-sectional view (part 2) showing another example of the cross-sectional structure taken along the cutting line E3-E3' in FIG. 46. FIG. 48 is a cross-sectional view showing the cross-sectional structure taken along the cutting line E4-E4' in FIG. 46. FIG. 49 is a characteristic diagram showing the halogen element concentration distribution in the depth direction of the interlayer insulating film during the manufacture of semiconductor devices according to the ninth and tenth embodiments. FIG. 50 is a flowchart outlining a method for manufacturing a semiconductor device according to the tenth embodiment. FIG. 51 is a cross-sectional view (part 1) showing a state during the manufacture of a semiconductor device according to the tenth embodiment. FIG. 52 is a cross-sectional view (part 2) showing a state during the manufacture of a semiconductor device according to the tenth embodiment. FIG. 53 is a cross-sectional view (part 3) showing a state during the manufacture of a semiconductor device according to the tenth embodiment. FIG. 54 is a cross-sectional view showing an example of the structure of a semiconductor device according to the tenth embodiment.

[0012] <Outline of an embodiment of the present disclosure> (1) A method for manufacturing a semiconductor device according to one aspect of the present disclosure is as follows: a first step of forming an element structure on a first main surface side of a semiconductor substrate is performed; a second step of forming an interlayer insulating film on the first main surface of the semiconductor substrate to cover the element structure is performed; a third step of forming a first contact hole penetrating the interlayer insulating film in the depth direction and exposing the semiconductor substrate is performed; an implantation step of ion-implanting a predetermined impurity using the interlayer insulating film as an ion implantation mask to selectively form a diffusion region of a predetermined conductivity type in a portion of the semiconductor substrate exposed in the first contact hole is performed; after the implantation step, a removal step of removing a surface layer of the interlayer insulating film to a predetermined thickness is performed; a first film formation step of forming a barrier metal from inside the first contact hole to the upper surface of the interlayer insulating film exposed by the removal step is performed; and a second film formation step of forming a surface electrode electrically connected to the element structure via the barrier metal. In the removal step, the interlayer insulating film is removed from the upper surface to at least a depth position corresponding to the maximum concentration of the predetermined impurity ion-implanted in the implantation step.

[0013] According to the above disclosure, by removing a predetermined thickness of the surface layer of the interlayer insulating film into which a predetermined impurity has been ion-implanted in the implantation step, it is possible to increase the adhesion strength between the interlayer insulating film and the barrier metal, thereby preventing the electrodes (barrier metal and surface electrode) on the first main surface of the semiconductor substrate from peeling off from the interlayer insulating film.

[0014] (2) A method for manufacturing a semiconductor device according to one aspect of this disclosure is as follows: a first step of forming an element structure on a first main surface side of a semiconductor substrate; a second step of forming an interlayer insulating film on the first main surface of the semiconductor substrate to cover the element structure; a third step of forming a first contact hole that penetrates the interlayer insulating film in the depth direction and exposes the semiconductor substrate; an implantation step of ion-implanting a predetermined impurity to selectively form a diffusion region of a predetermined conductivity type in a portion of the semiconductor substrate exposed in the first contact hole; after the implantation step, a first film-forming step of forming a barrier metal from inside the first contact hole to an upper surface of the interlayer insulating film; and a second film-forming step of forming a surface electrode electrically connected to the element structure via the barrier metal. The implantation step includes a masking step of covering the interlayer insulating film with a mask having an opening in a portion corresponding to a formation region of the diffusion region, a step of ion-implanting the predetermined impurity into the semiconductor substrate through the mask, and a step of removing the mask used in the ion implantation. In the first film formation step, the barrier metal is formed on the upper surface of the interlayer insulating film exposed by removing the mask.

[0015] According to the above disclosure, the predetermined impurity is not ion-implanted into the interlayer insulating film in the implantation step, or the surface area of ​​the ion-implanted portion of the interlayer insulating film into which the predetermined impurity is ion-implanted in the implantation step is small relative to the total surface area of ​​the interlayer insulating film, so that the adhesion strength between the interlayer insulating film and the barrier metal can be ensured in the portion of the interlayer insulating film other than the ion-implanted portion, thereby preventing the electrodes (barrier metal and surface electrode) on the first main surface of the semiconductor substrate from peeling off from the interlayer insulating film.

[0016] (3) Furthermore, the method for manufacturing a semiconductor device according to this disclosure may include, in the above-described (1) or (2), a third film formation step in which, after the first film formation step and before the second film formation step, a contact plug is formed on the barrier metal on the upper surface of the interlayer insulating film and the contact plug is embedded on the barrier metal inside the first contact hole, and the surface electrode is formed on the contact plug in the second film formation step.

[0017] According to the above disclosure, it is possible to miniaturize a semiconductor device. Also, the contact plug on the upper surface of the interlayer insulating film functions as an ion trap that captures metal ions diffusing from the surface electrode toward the interlayer insulating film.

[0018] (4) Furthermore, the method for manufacturing a semiconductor device according to this disclosure may include, in the above-described (3), after the third film formation step and before the second film formation step, a step of partially removing the contact plug to leave it only inside the first contact hole and exposing the barrier metal on the upper surface of the interlayer insulating film, and in the second film formation step, the surface electrode may be formed from above the contact plug inside the first contact hole to above the barrier metal on the upper surface of the interlayer insulating film.

[0019] According to the above disclosure, the barrier metal functions as an ion trap that captures metal ions diffusing from the surface electrode to the interlayer insulating film side.

[0020] (5) Furthermore, the method for manufacturing a semiconductor device according to this disclosure may include, in the above-mentioned (3), after the third film formation step and before the second film formation step, a step of partially removing the contact plug and the barrier metal to leave them only inside the first contact hole and expose an upper surface of the interlayer insulating film, and in the second film formation step, the surface electrode may be formed from above the contact plug inside the first contact hole to the upper surface of the interlayer insulating film.

[0021] According to the above disclosure, the barrier metal having a relatively low adhesiveness to the interlayer insulating film is not included between the surface electrode and the interlayer insulating film, so that peeling of the surface electrode can be suppressed.

[0022] (6) A method for manufacturing a semiconductor device according to one aspect of this disclosure is as follows: a first step of forming an element structure on a first main surface side of a semiconductor substrate is performed; a second step of forming an interlayer insulating film on the first main surface of the semiconductor substrate to cover the element structure is performed; a third step of forming a first contact hole that penetrates the interlayer insulating film in the depth direction and exposes the semiconductor substrate is performed; an implantation step of ion-implanting a predetermined impurity using the interlayer insulating film as an ion implantation mask to selectively form a diffusion region of a predetermined conductivity type in a portion of the semiconductor substrate exposed in the first contact hole is performed after the implantation step; a first film-forming step of forming a barrier metal from inside the first contact hole to an upper surface of the interlayer insulating film is performed; and a second film-forming step of forming a surface electrode electrically connected to the element structure via the barrier metal. The method further includes a first processing step, after the first film formation step and before the second film formation step, of removing the barrier metal on the upper surface of the interlayer insulating film to expose the upper surface of the interlayer insulating film and leaving a remaining first barrier metal only inside the first contact hole, a removal step, after the first processing step, of removing a surface layer of the interlayer insulating film by a predetermined thickness, and a third film formation step of forming a second barrier metal on the upper surface of the interlayer insulating film exposed by the removal step. In the removal step, the interlayer insulating film is removed from the upper surface to at least a depth position of a maximum concentration of the predetermined impurity ion-implanted in the implantation step.

[0023] According to the above disclosure, by removing a predetermined thickness of the surface layer of the interlayer insulating film into which a predetermined impurity has been ion-implanted in the implantation step, it is possible to increase the adhesion strength between the interlayer insulating film and the barrier metal, thereby preventing the electrodes (barrier metal and surface electrode) on the first main surface of the semiconductor substrate from peeling off from the interlayer insulating film.

[0024] (7) Furthermore, in the method for manufacturing a semiconductor device according to the present disclosure, in the above-mentioned (6), in the first processing step, the first barrier metal may be left at a position inside the first contact hole lower than the height position of the upper surface of the interlayer insulating film exposed in the removal step.

[0025] According to the above disclosure, the coverage of the surface electrode can be improved.

[0026] (8) In the method for manufacturing a semiconductor device according to the present disclosure, in the above-mentioned (6), the second barrier metal may be formed of the same metal as the first barrier metal in the third film-forming step.

[0027] According to the above disclosure, the second barrier metal can be formed from an existing material.

[0028] (9) Furthermore, the method for manufacturing a semiconductor device according to the present disclosure may further include, in the above-described (7), a fourth film formation step of forming a contact plug on the barrier metal and filling the inside of the first contact hole with the contact plug after the first film formation step and before the first processing step, and a second processing step of partially removing the contact plug to expose the barrier metal on the upper surface of the interlayer insulating film and leaving the remaining first contact plug of the contact plug only inside the first contact hole, wherein the second processing step leaves the first contact plug inside the first contact hole at a position deeper than the upper surface of the interlayer insulating film exposed in the removal step, and the third film formation step may form the second barrier metal from above the first contact plug to the upper surface of the interlayer insulating film exposed in the removal step.

[0029] According to the above disclosure, it is possible to miniaturize a semiconductor device and improve the coverage of the surface electrode.

[0030] (10) Furthermore, the method for manufacturing a semiconductor device according to this disclosure may, in the above-mentioned (9), include a fifth film formation step of forming a second contact plug on the second barrier metal after the third film formation step and before the second film formation step, and the surface electrode may be formed on the second contact plug in the second film formation step.

[0031] According to the above disclosure, the second contact plug functions as an ion trap that captures metal ions diffusing from the surface electrode toward the interlayer insulating film.

[0032] (11) In the method for manufacturing a semiconductor device according to the present disclosure, in the above-mentioned (10), in the fifth film forming step, the second contact plug may be formed of the same metal as the first contact plug.

[0033] According to the above disclosure, the second contact plug can be formed of an existing material.

[0034] (12) In addition, in the method for manufacturing a semiconductor device according to this disclosure, in any one of (1), (3) to (5) described above, the implantation step may include a masking step of forming a mask on the interlayer insulating film, the mask having an opening in a portion corresponding to a region where the diffusion region is to be formed; a step of ion-implanting the predetermined impurity into the semiconductor substrate using the interlayer insulating film and the mask as the ion implantation mask; and a step of removing the mask used in the ion implantation.

[0035] According to the above disclosure, the ion implantation location in the implantation step can be appropriately adjusted using a mask such as a resist.

[0036] (13) In addition, in the method for manufacturing a semiconductor device according to this disclosure, in any one of the above-mentioned (6) to (11), the implantation step may include a masking step of forming a mask on the interlayer insulating film, the mask having an opening in a portion corresponding to a region where the diffusion region is to be formed; a step of ion-implanting the predetermined impurity into the semiconductor substrate using the interlayer insulating film and the mask as the ion implantation mask; and a step of removing the mask used in the ion implantation.

[0037] According to the above disclosure, the ion implantation location in the implantation step can be appropriately adjusted using a mask such as a resist.

[0038] (14) In addition, in the method for manufacturing a semiconductor device according to any one of (1) to (13) above, the predetermined impurity may be a halide.

[0039] According to the above disclosure, it is possible to suppress the vertical (depth) diffusion of impurities of a predetermined conductivity type within a semiconductor substrate.

[0040] (15) In addition, in the method for manufacturing a semiconductor device according to the present disclosure, in any one of (1) to (14) above, the barrier metal may include a titanium film in contact with the interlayer insulating film.

[0041] According to the above disclosure, even if the portion of the barrier metal in contact with the interlayer insulating film contains a titanium film having low adhesion strength to the interlayer insulating film, the adhesion strength between the interlayer insulating film and the titanium film can be increased.

[0042] (16) A semiconductor device according to one aspect of this disclosure is as follows: An element structure is provided on a first main surface side of a semiconductor substrate. An interlayer insulating film is provided on the first main surface of the semiconductor substrate. The interlayer insulating film covers the element structure. A first contact hole is provided that penetrates the interlayer insulating film in the depth direction and exposes the semiconductor substrate. A barrier metal is provided from the surface of the semiconductor substrate exposed in the first contact hole to the surface of the interlayer insulating film. The barrier metal is electrically connected to the element structure. A surface electrode is electrically connected to the element structure via the barrier metal. The interlayer insulating film locally contains a halogen element. The concentration of the halogen element per unit volume of the interlayer insulating film is 1×10 19 / cm 3 The following is the result.

[0043] According to the above disclosure, the halogen element concentration in the interlayer insulating film is low enough not to adversely affect the adhesion between the interlayer insulating film and the barrier metal, so that the electrodes (barrier metal and surface electrode) on the first main surface of the semiconductor substrate can be prevented from peeling off from the interlayer insulating film.

[0044] (17) Furthermore, in the semiconductor device according to the present disclosure, in the above-mentioned (16), the concentration of the halogen element in the interlayer insulating film may be locally maximum in a portion exposed to the first contact hole.

[0045] According to the above disclosure, even if the concentration of halogen elements is locally high in the portion of the interlayer insulating film exposed to the first contact hole, the adhesion strength between the upper surface of the interlayer insulating film and the barrier metal can be ensured between the interlayer insulating film and the barrier metal.

[0046] (18) Furthermore, in the semiconductor device according to this disclosure, in the above-mentioned (17), the interlayer insulating film may have a portion at the upper end corner exposed to the first contact hole where the concentration of the halogen element is at its maximum.

[0047] According to the above disclosure, even if the concentration of halogen elements is locally high in the portion of the interlayer insulating film exposed to the first contact hole, the adhesion strength between the upper surface of the interlayer insulating film and the barrier metal can be ensured between the interlayer insulating film and the barrier metal.

[0048] (19) In the semiconductor device according to the present disclosure, in the above-mentioned (17) or (18), the maximum concentration of the halogen element in the interlayer insulating film is 5×10 19 / cm 3 It may be more than that.

[0049] According to the above disclosure, even if the concentration of halogen elements is locally high in the portion of the interlayer insulating film exposed to the first contact hole, the adhesion strength between the upper surface of the interlayer insulating film and the barrier metal can be ensured between the interlayer insulating film and the barrier metal.

[0050] (20) In addition, in the semiconductor device according to any one of the above (16) to (19), the halogen element may be fluorine.

[0051] According to the above disclosure, it is possible to suppress the vertical (depth) diffusion of impurities of a predetermined conductivity type within a semiconductor substrate.

[0052] (21) In addition, in the semiconductor device according to any one of the above (16) to (20), the barrier metal may include a titanium film in contact with the interlayer insulating film.

[0053] According to the above disclosure, even if the portion of the barrier metal in contact with the interlayer insulating film contains a titanium film having low adhesive strength to the interlayer insulating film, the adhesive strength between the interlayer insulating film and the titanium film is high.

[0054] (22) Furthermore, the method for manufacturing a semiconductor device according to this disclosure, in any one of (1) to (15) above, may include, after the third step and before the implantation step, a step of forming a contact trench continuous with the first contact hole in a portion of the semiconductor substrate exposed in the first contact hole.

[0055] According to the above disclosure, in the implantation step, a diffusion region can be formed only on the bottom surface of the contact trench by ion-implanting a predetermined impurity from a direction substantially perpendicular to the first main surface of the semiconductor substrate. The diffusion region is not formed on the sidewall of the contact trench. Therefore, it is not necessary to form a mask in an element region where the entire bottom surface of the first contact hole is exposed, such as a region where a diode is formed.

[0056] (23) Also, in the method for manufacturing a semiconductor device according to the present disclosure, in the above-described (2), (12), or (13), in the first step, a plurality of trenches are formed on the first main surface side of the semiconductor substrate as the element structure, and conductive portions are formed inside the trenches via insulating films. In the third step, first contact holes are formed extending linearly in the longitudinal direction of the trenches and exposing the semiconductor substrate between adjacent trenches. After the second step and before the masking step, recesses are formed in the upper surface of the interlayer insulating film above the trenches so as to be positioned more inward than the ends of the first contact holes in the longitudinal direction of the trenches. In the masking step, the first contact holes are exposed in openings in the mask, and the mask is formed so as to fill the recesses. In the second film-forming step, the surface electrodes electrically connected to the element structure may be formed in the first contact holes.

[0057] According to the above disclosure, the mask is embedded in a recess in the upper surface of the interlayer insulating film and is caught on the step between the upper surface of the interlayer insulating film and the bottom surface of the recess, thereby preventing the mask from sliding or tipping over on the upper surface of the interlayer insulating film.

[0058] (24) Furthermore, in the method for manufacturing a semiconductor device according to this disclosure, in the above-mentioned (23), the recess may be a second contact hole that penetrates the interlayer insulating film in the depth direction to expose the conductive portion, and in the masking step, the mask and the conductive portion may be brought into contact with each other through the second contact hole, and in the second film formation step, the surface electrode may be formed in the second contact hole so as to be electrically connected to the conductive portion.

[0059] According to the disclosure above, the mask can be brought into contact with the conductive portion, which has higher adhesion to the mask than the interlayer insulating film, and peeling of the mask can be suppressed, which is particularly useful when the mask does not contact the semiconductor substrate or when the contact area between the mask and the semiconductor substrate is relatively small.

[0060] (25) In the method for manufacturing a semiconductor device according to the present disclosure, in the above-mentioned (23) or (24), the recess may be formed simultaneously with the first contact hole in the third step.

[0061] According to the above disclosure, recesses can be formed in the upper surface of the interlayer insulating film while maintaining the number of steps.

[0062] (26) In addition, the method for manufacturing a semiconductor device according to the present disclosure is the method according to the above (14), wherein in the removing step, the concentration of the halogen element on the upper surface of the interlayer insulating film is 5×10 20 / cm 3 The following may also be used.

[0063] According to the above disclosure, the halogen element concentration in the interlayer insulating film is low enough not to adversely affect the adhesion between the interlayer insulating film and the barrier metal, so that the electrode on the first main surface of the semiconductor substrate can be prevented from peeling off from the interlayer insulating film.

[0064] (27) In addition, in the method for manufacturing a semiconductor device according to the present disclosure, in the above-mentioned (14), in the removing step, an integral value obtained by integrating the concentration of the halogen element in the interlayer insulating film in the depth direction over the remaining thickness of the interlayer insulating film is 1×10 14 / cm 2 The following may also be used.

[0065] According to the above disclosure, the halogen element concentration in the interlayer insulating film is low enough not to adversely affect the adhesion between the interlayer insulating film and the barrier metal, so that the electrode on the first main surface of the semiconductor substrate can be prevented from peeling off from the interlayer insulating film.

[0066] (28) Furthermore, the method for manufacturing a semiconductor device according to the present disclosure, in the above-mentioned (14), may further include a heat treatment step of heating the semiconductor substrate after the implantation step and before the removal step, and the heat treatment step may release halogen elements in the interlayer insulating film to the outside.

[0067] According to the disclosure above, the halogen element concentration in the interlayer insulating film can be reduced by the heat treatment process to a level that does not adversely affect the adhesion between the interlayer insulating film and the barrier metal, thereby preventing the electrodes (barrier metal and surface electrode) on the first main surface of the semiconductor substrate from peeling off from the interlayer insulating film.

[0068] (29) The method for manufacturing a semiconductor device according to the present disclosure further comprises the steps of (28) above, wherein in the heat treatment step, the concentration of the halogen element on the upper surface of the interlayer insulating film is 5×10 20 / cm 3 The following may also be used.

[0069] According to the above disclosure, the halogen element concentration in the interlayer insulating film is low enough not to adversely affect the adhesion between the interlayer insulating film and the barrier metal, so that the electrode on the first main surface of the semiconductor substrate can be prevented from peeling off from the interlayer insulating film.

[0070] (30) In addition, in the method for manufacturing a semiconductor device according to the present disclosure, in the above-mentioned (28) or (29), in the heat treatment step, an integral value obtained by integrating the concentration of the halogen element in the interlayer insulating film in the depth direction over the remaining thickness of the interlayer insulating film is 1×10 14 / cm 2 The following may also be used.

[0071] According to the above disclosure, the halogen element concentration in the interlayer insulating film is low enough not to adversely affect the adhesion between the interlayer insulating film and the barrier metal, so that the electrode on the first main surface of the semiconductor substrate can be prevented from peeling off from the interlayer insulating film.

[0072] (31) In addition, in the method for manufacturing a semiconductor device according to the present disclosure, in the above-mentioned (1) or (6), the removing step may remove the interlayer insulating film from the top surface to a depth beyond the depth position of the maximum concentration of the predetermined impurity ion-implanted in the implanting step.

[0073] According to the disclosure above, the more the surface layer of the interlayer insulating film is removed, the lower the concentration per unit volume of the predetermined impurity ions implanted into the interlayer insulating film in the implantation step can be.

[0074] (32) Furthermore, in the method for manufacturing a semiconductor device according to this disclosure, in any one of (2) to (5) above, the third step may form the first contact holes extending in a stripe pattern in a direction parallel to the first main surface of the semiconductor substrate, and the masking step may form the mask in a lattice-like planar shape that covers the interlayer insulating film and is scattered in the longitudinal direction of the first contact holes, selectively covering the portions of the semiconductor substrate exposed to the first contact holes.

[0075] According to the disclosure above, the mask can be brought into contact with the semiconductor substrate to improve the adhesion of the mask.

[0076] (33) In addition, in the semiconductor device according to any one of the above (16) to (21), the interlayer insulating film has a portion where the concentration of the halogen element is relatively high, and the local maximum concentration of the halogen element in the interlayer insulating film is 5×10 20 / cm 3 It may be the following:

[0077] According to the above disclosure, the halogen element concentration in the interlayer insulating film is low enough not to adversely affect the adhesion between the interlayer insulating film and the barrier metal, so that the electrodes (barrier metal and surface electrode) on the first main surface of the semiconductor substrate can be prevented from peeling off from the interlayer insulating film.

[0078] (34) In addition, in the semiconductor device according to any one of the above (16) to (21) and (31), the integral value obtained by integrating the concentration of the halogen element in the interlayer insulating film in the depth direction over the thickness of the interlayer insulating film is 1×10 14 / cm 2 It may be the following:

[0079] According to the above disclosure, the halogen element concentration in the interlayer insulating film is low enough not to adversely affect the adhesion between the interlayer insulating film and the barrier metal, so that the electrode on the first main surface of the semiconductor substrate can be prevented from peeling off from the interlayer insulating film.

[0080] (35) Furthermore, the semiconductor device according to this disclosure may be any one of the above-mentioned (16) to (21), (33), and (34), further comprising a diffusion region of a predetermined conductivity type containing the halogen element, the diffusion region being provided in a portion of the semiconductor substrate exposed to the first contact hole and having a width equal to or greater than the width of the first contact hole, and the interlayer insulating film may have a portion where the concentration of the halogen element is at its maximum in a portion facing the diffusion region in a direction parallel to the first main surface of the semiconductor substrate.

[0081] According to the above disclosure, by providing a diffusion region of a predetermined conductivity type containing a halogen element in the portion of the semiconductor substrate exposed to the first contact hole, even if the concentration of the halogen element is locally high in the portion of the interlayer insulating film exposed to the first contact hole, it is possible to ensure the adhesion strength between the interlayer insulating film and the barrier metal between the upper surface of the interlayer insulating film and the barrier metal.

[0082] (36) Furthermore, the semiconductor device according to this disclosure, in any one of the above (16) to (21), (33), and (34), comprises a contact trench provided contiguous with the first contact hole in a portion of the semiconductor substrate exposed to the first contact hole, and a diffusion region of a predetermined conductivity type provided in a portion of the semiconductor substrate exposed on the bottom surface of the contact trench, and the diffusion region may not be provided in a portion of the semiconductor substrate exposed on the side wall of the contact trench.

[0083] According to the above disclosure, the area of ​​ohmic contact between the barrier metal and the semiconductor substrate can be increased.

[0084] (37) In addition, in the semiconductor device according to any one of (16) to (21) and (33) to (36) above, the element structure includes a plurality of trenches provided on the first main surface side of the semiconductor substrate, and a conductive portion provided inside the trenches via an insulating film. The first contact holes extend linearly in the longitudinal direction of the trenches to expose the semiconductor substrate between adjacent trenches. A recess may be formed in the upper surface of the interlayer insulating film above the trenches, and the recess may be located inside an end of the first contact hole in the longitudinal direction of the trench.

[0085] According to the above disclosure, the recess in the upper surface of the interlayer insulating film can prevent mask misalignment during the masking process, thereby preventing poor formation (misalignment or disappearance) of the plug region formed using the mask.

[0086] (38) Furthermore, in the semiconductor device according to this disclosure, in the above-mentioned (37), the recess may be a second contact hole that penetrates the interlayer insulating film in the depth direction to expose the conductive portion, and the conductive portion and the surface electrode may be electrically connected in the second contact hole.

[0087] According to the above disclosure, the potential of the conductive portion can be stabilized.

[0088] (39) In the semiconductor device according to the present disclosure, in the above-mentioned (37) or (38), the first contact hole and the recess may be connected in the longitudinal direction of the trench.

[0089] According to the above disclosure, it is possible to prevent the recesses on the upper surface of the interlayer insulating film from adversely affecting the opening pattern of the first contact hole.

[0090] (40) In addition, in the semiconductor device according to any one of (16) to (21) and (33) to (39) above, the element structure includes: a plurality of trenches provided on a first main surface side of the semiconductor substrate and extending linearly in a direction parallel to the first main surface of the semiconductor substrate; conductive portions provided within the trenches via insulating films; drift regions of a first conductivity type provided within the semiconductor substrate; and anode regions of a second conductivity type provided between the first main surface of the semiconductor substrate and the drift region, between adjacent trenches. The first contact holes extend linearly in the longitudinal direction of the trenches and expose the semiconductor substrate between the adjacent trenches. The semiconductor substrate may have a second conductivity type diffusion region between the first main surface of the semiconductor substrate and the anode region in a portion exposed to the first contact hole, the diffusion region having a higher impurity concentration than the anode region and containing the halogen element, and a recess in the upper surface of the interlayer insulating film above the trench, the recess being positioned inside the end of the first contact hole in the longitudinal direction of the trench.

[0091] According to the above disclosure, the recess in the upper surface of the interlayer insulating film can prevent mask misalignment during the masking process, thereby preventing poor formation (misalignment or disappearance) of the plug region formed using the mask.

[0092] (41) Furthermore, the semiconductor device according to this disclosure, in any one of the above (16) to (21) and (33) to (40), may also include a contact plug provided on the barrier metal inside the first contact hole and interposed between the barrier metal and the surface electrode.

[0093] According to the above disclosure, semiconductor devices can be miniaturized.

[0094] (42) In the semiconductor device according to the present disclosure, in the above-mentioned (41), the contact plug may extend from inside the first contact hole between the upper surface of the interlayer insulating film and the surface electrode.

[0095] According to the above disclosure, the contact plug functions as an ion trap that captures metal ions diffusing from the surface electrode to the interlayer insulating film side.

[0096] (43) Furthermore, the semiconductor device according to this disclosure, in any one of (37) to (42) above, may also include a contact plug provided on the barrier metal inside the recess and interposed between the barrier metal and the surface electrode.

[0097] According to the above disclosure, semiconductor devices can be miniaturized.

[0098] <Foundation of the Present Disclosure> First, the structure of a semiconductor device of a reference example will be described. Fig. 35 is a cross-sectional view showing the structure of a semiconductor device of a reference example. Fig. 35 shows a p ++ The vicinity of the mold plug region 208 is shown enlarged (the same applies to FIGS. 37 to 39 described later), and the p ++ 35, a semiconductor device 220 includes a front surface electrode made up of a barrier metal 213, a plug 214, and a front surface electrode 215 on the front surface of a semiconductor substrate (semiconductor chip) 210.

[0099] A predetermined front surface element structure is provided on the front surface side of the semiconductor substrate 210. An interlayer insulating film 209 is provided on the entire front surface of the semiconductor substrate 210 so as to cover the front surface element structure. The interlayer insulating film 209 has a surface layer 209b on the upper surface (the surface on the surface electrode 215 side) thereof, which is p ++ The metal ions included in the metal layer 209 include halogen atoms such as fluorine (F) introduced by ion implantation 232 (see FIG. 37) for forming the mold plug region 208. A plug 214 is buried in the contact hole 209a of the interlayer insulating film 209 with a barrier metal 213 interposed therebetween.

[0100] The barrier metal 213 includes a titanium (Ti) film 211 and a titanium nitride (TiN) film 212. The Ti film 211 is provided along the sidewall of the contact hole 209a (the side surface of the interlayer insulating film 209), and extends to the upper surface of the interlayer insulating film 209, covering the entire surface of the interlayer insulating film 209. Inside the contact hole 209a, a p-type barrier metal film 211 of the front surface element structure is formed on the front surface of the semiconductor substrate 210. ++ A silicide film 211a is provided in contact with the mold plug region 208. The silicide film 211a is formed by silicidating the Ti film 211.

[0101] The TiN film 212 is provided on the Ti film 211 and the silicide film 211a and along their surfaces. The plug 214 is provided on the TiN film 212 inside the contact hole 209a. The plug 214 is, for example, a tungsten (W) film. The surface electrode 215 is provided on the plug 214 and the TiN film 212 and is electrically connected to the front surface element structure via the plug 214, the barrier metal 213, and the silicide film 211a. The surface electrode 215 is an aluminum (Al) film or an Al alloy film.

[0102] A method for manufacturing the semiconductor device 220 of the reference example will be described. Fig. 36 is a flowchart showing an outline of the method for manufacturing the semiconductor device of the reference example. Figs. 37 to 39 are cross-sectional views showing the semiconductor device of the reference example in the middle of manufacturing. First, p of a predetermined front surface element structure is formed in each chip region (region that will become the semiconductor base 210 after being separated from the semiconductor wafer: hereinafter referred to as semiconductor base 210) on the front surface side of the semiconductor wafer. ++ Each part (not shown) other than the mold plug region 208 is formed (step S201).

[0103] 37, an interlayer insulating film 209 is formed on the entire front surface of the semiconductor substrate 210 to a thickness t201 of the product (step S202), and a contact hole 209a is formed through the interlayer insulating film 209 in the depth direction (step S203). ++A resist mask (not shown) is formed with openings in portions corresponding to regions for forming the mold plug regions 208 (step S204). Next, using this resist mask and the interlayer insulating film 209 as ion implantation masks, p-type impurity ions are implanted 232 (step S205).

[0104] In the ion implantation 232 of step S205, by using a boron halide such as boron fluoride (BF), which has a heavier mass than boron (B), as the p-type impurity (dopant), the depth position of the range of the ion implantation 232 in the semiconductor substrate 210 becomes shallower, and impurity diffusion in the semiconductor substrate 210 is suppressed, but by using the interlayer insulating film 209 as an ion implantation mask, the boron halide ions are also implanted 232 into a surface layer 209b of the interlayer insulating film 209. Figure 37 shows the portion exposed in the opening 231a of the resist mask, and the maximum depth position reached by the p-type impurity implanted 232 is indicated by a dashed line.

[0105] An example of an opening pattern of the resist mask used in the process of step S205 is, for example, a pattern for forming a p-type resist mask on an RC-IGBT (Reverse Conducting-Insulated Gate Bipolar Transistor). ++ An opening pattern of a resist mask used for ion implantation to form a mold plug region is disclosed in Figure 12 of Patent Document 2. When this example is applied, the contact holes 209a extend in a stripe shape in a direction parallel to the front surface of the semiconductor substrate 210.

[0106] p ++ The p-type plug regions 208 are formed in the shape of islands scattered in the longitudinal direction of each contact hole 209a. ++ The opening pattern of the resist mask is a stripe pattern extending in the short direction of the contact hole 209a, and all the p-type plug regions 208 adjacent to each other in the short direction of the contact hole 209a are ++ The region where the mold plug region 208 is to be formed is exposed through the same opening 231a of the resist mask.

[0107] The opening 231a of the resist mask is provided with p ++ The interlayer insulating film 209 is also exposed in a portion adjacent to the formation region of the mold plug region 208. The portion of the interlayer insulating film 209 exposed in the opening 231 a of the resist mask is used as an ion implantation mask for the ion implantation 232. The interlayer insulating film 209 also has a portion not covered by the resist mask between the active region and the end of the semiconductor substrate 210 (where a wiring layer and a voltage-resistant structure are disposed: not shown), and this portion is also used as an ion implantation mask for the ion implantation 232.

[0108] Next, as shown in FIG. 38, the resist mask is removed (step S206), and impurity activation is performed by heat treatment (annealing) to form p ++ A mold plug region 208 is formed (step S207). Next, as shown in FIG. 39, a Ti film 211 and a TiN film 212 that will become a barrier metal 213 are formed by sputtering (step S208). Next, a heat treatment (sintering) is performed to cause a silicide reaction between the Ti film 211 and the semiconductor substrate 210, thereby forming a silicide film 211a (step S209).

[0109] Next, a plug 214 is formed on the TiN film 212, and the inside of the contact hole 209a is filled with the plug 214 (step S210). Next, the plug 214 is removed by etch-back or the like until the TiN film 212 is exposed, leaving only the inside of the contact hole 209a (step S211). Next, a front surface electrode 215 is formed on the plug 214 and the TiN film 212 (step S212). Then, the front surface electrode 215 and the barrier metal 213 are patterned, thereby completing the front surface structure of the semiconductor device 220 shown in FIG.

[0110] In the manufacturing method of the semiconductor device 220 of the reference example described above, the surface area of ​​the portion of the interlayer insulating film 209 that is not covered with the resist mask during the processing of step S205 and into which halogen elements are ion-implanted 232 becomes relatively large relative to the total surface area of ​​the interlayer insulating film 209. The interlayer insulating film 209 is made of silicate glass (SG) such as BPSG (Boro Phospho Silicate Glass), and has low adhesion strength with the Ti film 211. If the interlayer insulating film 209 contains a halogen element, the adhesion strength between the Ti film 211 and the interlayer insulating film 209 becomes even lower.

[0111] If the adhesion strength between the Ti film 211 and the interlayer insulating film 209 is reduced, stress applied to the surface electrode 215 during wire bonding may cause the Ti film 211 to peel off from the interlayer insulating film 209, which may also peel off the surface electrode 215 thereon. Furthermore, if the Ti film 211 peels off from the interlayer insulating film 209 during the manufacture of the semiconductor device 220, contamination and damage caused by peeled pieces of the Ti film 211 will reduce the reliability of the semiconductor device 220. Even in a structure in which the Ti film 211 is not left on the upper surface of the interlayer insulating film 209, contamination and damage caused by peeled pieces of the Ti film 211 will occur.

[0112] For example, Patent Document 1 discloses wet etching of the front surface of the semiconductor substrate 210 with an aqueous solution containing hydrofluoric acid (HF) as a pretreatment for sputtering to form the barrier metal 213. The interlayer insulating film 209 is also wet-etched in this pretreatment for sputtering, but because this is not a treatment that actively removes a predetermined thickness of the surface layer 209b of the interlayer insulating film 209, the maximum concentration portion of the halogen element implanted by ion implantation 232 (the depth position of the range of ion implantation 232) remains in the surface layer 209b of the interlayer insulating film 209.

[0113] The present inventors have found that when the total surface area of ​​the portions of the interlayer insulating film 209 that are exposed without being covered with a resist mask during the processing of step S205 and into which halogen elements are ion-implanted 232 (hereinafter referred to as "portions containing halogen elements at a high concentration") is about half or more of the total surface area of ​​the interlayer insulating film 209, the Ti film 211 is likely to peel off from the interlayer insulating film 209, but when the total surface area is about one-quarter or one-fifth or less, more preferably less than one-tenth, of the total surface area of ​​the interlayer insulating film 209, the Ti film 211 will not peel off. The present disclosure has been made based on such findings.

[0114] One of the problems to be solved in this embodiment is to suppress peeling of the barrier metal from the interlayer insulating film, thereby suppressing peeling of the surface electrode.

[0115] Preferred embodiments of a semiconductor device and a method for manufacturing a semiconductor device according to this disclosure will be described in detail below with reference to the accompanying drawings. In this specification and the accompanying drawings, layers and regions prefixed with n or p indicate that electrons or holes are the majority carriers, respectively. The + and - symbols attached to n or p indicate that the impurity concentration is higher or lower than that of layers or regions not prefixed with these symbols, respectively. In the following description of the embodiments and the accompanying drawings, similar components are designated by the same reference numerals, and redundant explanations will be omitted.

[0116] (Details of First Embodiment) A semiconductor device according to a first embodiment that solves the above-mentioned problems will be described below. FIG. 1 is a plan view showing the layout of the semiconductor device according to the first embodiment as viewed from the front surface side of a semiconductor substrate. FIG. 2 is an enlarged plan view of rectangular frame A in FIG. 1. FIGS. 3 and 4 are cross-sectional views showing cross-sectional structures taken along cutting lines B1-B1' and B2-B2' in FIG. 2, respectively. A semiconductor device 20 according to the first embodiment shown in FIGS. 1 to 4 includes, on a front surface (first main surface) of a semiconductor substrate (semiconductor chip) 10, a front surface electrode including a barrier metal 13, a plug (contact plug) 14, and a front surface electrode 15.

[0117] Here, the semiconductor device 20 according to the first embodiment will be described as an RC-IGBT in which a vertical IGBT with a trench gate structure and an FWD (Free Wheeling Diode) connected in anti-parallel to the IGBT are integrated into the same semiconductor substrate 10. The semiconductor substrate 10 can be made of a single semiconductor such as silicon (Si) or diamond (C), or a compound semiconductor such as silicon carbide (SiC), gallium nitride (GaN), or gallium oxide (GaO). While the semiconductor substrate 10 is described as a bulk Si substrate, the semiconductor substrate 10 may also be an epitaxial substrate in which an epitaxial layer is grown on a starting substrate (bulk substrate).

[0118] 1 , an active region 41 having, for example, a substantially rectangular planar shape is provided in the approximate center of the semiconductor substrate 10 (chip center). The active region 41 is a region through which a main current flows when the semiconductor device 20 is turned on. In the active region 41, an IGBT region 21, which serves as an operating region for the IGBT, and an FWD region 22, which serves as an operating region for the diode, are provided adjacent to each other. For example, the IGBT regions 21 and the FWD regions 22 are alternately and repeatedly adjacent to each other in a first direction X parallel to the front surface of the semiconductor substrate 10, and are arranged in stripes that extend linearly in a second direction Y that is parallel to the front surface of the semiconductor substrate 10 and perpendicular to the first direction X.

[0119] An edge termination region 42 is located between the active region 41 and the edge (chip edge) of the semiconductor substrate 10. The edge termination region 42 surrounds the periphery of the active region 41 and has the function of alleviating the electric field on the front surface side of the semiconductor substrate 10 to maintain a breakdown voltage. A general breakdown voltage structure (not shown), such as a field limiting ring (FLR), a junction termination extension (JTE), or a guard ring, is disposed in the edge termination region 42. The breakdown voltage is the limit voltage at which the semiconductor device 20 does not malfunction or break down. In addition to the voltage-resistant structure, the edge termination region 42 may also include a gate pad 56, and may also include auxiliary functional elements such as a temperature sensor and a current sensor (not shown) for protecting and controlling the main element (IGBT), other electrode pads for external connection (not shown), and a gate runner 53 (see Figure 2) described later.

[0120] As shown in FIG. 2, the entire area between the active region 41 and the breakdown voltage structure of the edge termination region 42 is connected to the front surface of the semiconductor substrate 10 and the n-type semiconductor substrate 10 (described later). - Between the p-type drift region 1 and the p-type base region 5 described later, a p + A well region 51 is provided. + The well region 51 surrounds the active region 41. + The well region 51 contacts an insulating layer 52 (an extension of the gate insulating film 3, an interlayer insulating film 9, a field oxide film, or a stack of two or more of these insulating films, which will be described later) on the front surface of the semiconductor substrate 10. The insulating layer 52 covers the entire front surface of the semiconductor substrate 10 in the edge termination region 42.

[0121] p + The longitudinal ends of dummy trenches 2 b (described later) terminate inside the mold well region 51. +A gate runner 53 and a gate pad 56 (see FIG. 1) are provided on the mold well region 51 via an insulating layer 52. The gate runner 53 surrounds the active region 41 in a U-shape or an annular shape. The gate runner 53 is formed by laminating a gate polysilicon (poly-Si) wiring layer 54 and a gate metal wiring layer 55 in this order. The gate runner 53 is connected to the gate pad 56 at a portion not shown. The gate polysilicon wiring layer 54 is provided inside the insulating layer 52 and faces the longitudinal end of a gate trench 2a (described later) in the depth direction Z.

[0122] The gate metal wiring layer 55 is provided on the gate polysilicon wiring layer 54 and is connected to the gate polysilicon wiring layer 54 via a contact hole 52b in the insulating layer 52. The gate metal wiring layer 55 and the gate pad 56 are formed, for example, simultaneously with the surface electrode 15 and are located at the same level as the surface electrode 15. A barrier metal (not shown) and a plug (not shown) may be formed inside the contact hole 52b simultaneously with the barrier metal 13 and the plug (contact plug) 14 in the active region 41, respectively. A barrier metal may extend from inside the contact hole 52b between the gate metal wiring layer 55 and the upper surface of the insulating layer 52 (the surface on the surface electrode 15 side). A barrier metal (not shown) may be formed between the gate pad 56 and the upper surface of the insulating layer 52.

[0123] Although not shown, in another example of the gate runner, the gate runner may be formed only by the gate metal wiring layer 55, without providing the gate polysilicon wiring layer 54. In this case, for example, the contact hole 52b of the insulating layer 52 may be provided directly above the longitudinal end of the gate trench 2a (the connection portion connecting adjacent gate trenches 2a in FIG. 2), and the gate metal wiring layer 55 and the gate electrode 4 may be directly connected (or indirectly via a flag and barrier metal, not shown) via the contact hole 52b provided directly above the gate trench 2a.

[0124] Between the active region 41 and the gate runner 53, the front surface electrode and the p-type base region 5 or p +The gate runner 53 may be connected to the p-type well region 51 via a contact hole (not shown) in the insulating layer 52. Between the gate runner 53 and the voltage-withstanding structure, a wiring layer (not shown) having the same potential as the front surface electrode is connected to the p-type well region 51 via a contact hole (not shown) in the insulating layer 52. + In this case, the front surface of the semiconductor substrate 10 and the p-type base region 5 or p-type well region 51 are connected through a contact hole in the insulating layer 52. + For example, the p-type well region 51 of the active region 41 is ++ The p ++ A mold plug region 8 may be provided.

[0125] 3 and 4, an IGBT trench gate structure (front surface element structure) and a diode p-type anode region (front surface element structure) are provided on the front surface side of the semiconductor substrate 10 in the active region 41. A plurality of IGBT cells (functional units of the element) having the same structure are arranged adjacent to each other in the IGBT region 21, and a plurality of diode cells having the same structure are arranged adjacent to each other in the FWD region 22. The trench gate structure includes a trench 2, a gate insulating film 3, a gate electrode 4, a p-type base region 5, an n-type anode region 6, a gate electrode 7, a gate insulating film 8, a gate electrode 9, a gate insulating film 10, a gate electrode 11, a gate insulating film 12, a gate electrode 13, a gate insulating film 14, a gate electrode 15, a gate insulating film 16, a gate electrode 17, a gate insulating film 18, a gate electrode 19, a gate insulating film 20, a gate insulating film 21, a gate insulating film 22, a gate insulating film 23, a gate electrode 24, a gate insulating film 25, a gate insulating film 26, a gate insulating film 27, a gate insulating film 28, a gate insulating film 29, a gate insulating film 29, a gate insulating film 30, a gate insulating film 31, a gate insulating film 32, a gate insulating film 33, a gate insulating film 34, a gate insulating film 35, a gate insulating film 36, a gate insulating film 37, a gate insulating film 38, a gate insulating film 39, a gate insulating film 39, a gate insulating film 40, a gate insulating film 41, a gate insulating film 42, a gate insulating film 43, a gate insulating film 44, a gate insulating film 45, a gate insulating film 46, a gate insulating film 47, a gate insulating film 48, a gate insulating film 49, a gate insulating film + type emitter region 6, p + type contact region 7 and p ++ It is composed of a mold plug region 8.

[0126] Specifically, n - A type drift region 1 is provided. - The n-type drift region 1 extends from the active region 41 to the edge of the chip. The trench 2 penetrates the p-type base region 5 (described later) from the front surface of the semiconductor substrate 10 in the depth direction Z. - The trenches 2 terminate inside the type drift region 1. For example, the trenches 2 extend linearly in one direction (here, second direction Y) parallel to the front surface of the semiconductor substrate 10, and a plurality of trenches 2 are arranged adjacent to each other in a stripe pattern in a direction (here, first direction X) perpendicular to the first direction. The trenches 2 are arranged in approximately the same layout in both the IGBT region 21 and the FWD region 22.

[0127] A gate insulating film 3 is provided along the inner wall of the trench 2. A gate electrode 4 made of polysilicon is provided on the gate insulating film 3 inside the trench 2. The front surface of the semiconductor substrate 10 and the n-type semiconductor substrate 10 are connected over the entire active region 41. - Between the n-type drift region 1, - A p-type base region 5 is provided in contact with the first drift region 1. The p-type base region 5 reaches the sidewalls of each trench 2 on both sides in the first direction X. The p-type base region 5 is located closer to the front surface of the semiconductor substrate 10 than the bottom surfaces of the trenches 2. The p-type base region 5 faces the gate electrode 4 via the gate insulating film 3 on the sidewalls of the trenches 2.

[0128] Of the multiple trenches 2 in the IGBT region 21, some of the trenches 2 may be gate trenches 2a, and the remaining trenches 2 may be dummy trenches 2b. For example, gate trenches 2a and dummy trenches 2b may be alternately arranged in the first direction X in the IGBT region 21. Adjacent gate trenches 2a may be connected to form a U-shaped or annular planar shape surrounding the dummy trench 2b. All trenches 2 in the FWD region 22 may be dummy trenches 2b. For example, adjacent dummy trenches 2b in the FWD region 22 may be connected to form a U-shaped or annular planar shape (see FIG. 2).

[0129] The gate electrode 4 inside the gate trench 2 a is connected to the gate runner 53 at the longitudinal end of the gate trench 2 a and is fixed to the gate potential of the IGBT (see FIG. 2 ). The gate electrode 4 inside the dummy trench 2 b is electrically connected to the surface electrode 15 at the longitudinal end of the dummy trench 2 b via a contact hole 52 a in the insulating layer 52, for example, and is fixed to the emitter potential of the IGBT (see FIG. 2 ). That is, the gate insulating film 3 and the gate electrode 4 inside the dummy trench 2 b serve as a dummy gate insulating film and a dummy gate electrode (conductive portion), respectively, connected to a potential other than the gate potential of the IGBT.

[0130] Although not shown, in another example of the connection between the dummy gate electrode and the surface electrode 15, a polysilicon wiring layer provided inside the insulating layer 52 may be connected to the dummy gate electrode so that the gate electrode 4 inside the gate trench 2a is connected to the gate metal wiring layer 55 via the gate polysilicon wiring layer 54, and the polysilicon wiring layer and the surface electrode 15 may be connected via a contact hole 52a in the insulating layer 52. Alternatively, as will be described later, a contact hole located directly above the dummy trench 2b may be provided in the interlayer insulating film 9 in the active region 41, and the dummy gate electrode and the surface electrode 15 may be directly connected (or indirectly via a flag and a barrier metal, not shown) via the contact hole provided in the interlayer insulating film 9 (see FIGS. 43 to 45 ).

[0131] Between the front surface of the semiconductor substrate 10 and the p-type base region 5 in the IGBT region 21, there are n-type trenches 2 adjacent to each other, which are in contact with the p-type base region 5. + type emitter region 6 and p + The contact regions 7 are selectively provided. + type emitter region 6 and p + The contact regions 7 are alternately and repeatedly arranged adjacent to each other in the longitudinal direction of the trench 2 (second direction Y), and reach the sidewalls of each trench 2 on both sides in the lateral direction of the trench 2 (first direction X). + type emitter region 6 and p + The contact region 7 is located between the other trenches 2 in the first direction X. + type emitter region 6 and p + It faces the mold contact region 7 .

[0132] n + type emitter region 6 and p + The contact region 7 reaches the front surface of the semiconductor body 10. + type emitter region 6 and p + The contact region 7 faces the gate electrode 4 via the gate insulating film 3 on the sidewall of the trench 2. + The p-type emitter region 6 is not provided in the FWD region 22. + Between the p-type contact region 7, +In contact with the contact region 7, ++ A mold plug region 8 is optionally provided. ++ The mold plug region 8 is connected to the front surface of the semiconductor substrate 10 and the n-type + There is no gap between the p-type emitter region 6 and the p-type emitter region 6. ++ The mold plug region 8 is n + It may be in contact with the emitter region 6 .

[0133] p ++ The width of the mold plug region 8 in the first direction X is approximately equal to the width of the lower end side (semiconductor substrate 10 side) of the contact hole 9a described later in the first direction X. ++ The mold plug region 8 does not reach the sidewall of the trench 2. In another example, ++ The width of the mold plug region 8 in the first direction X may be wider than the width of the lower end of the contact hole 9 a in the first direction X due to diffusion of the impurity ions implanted into the semiconductor substrate 10, and may further reach the sidewall of the trench 2. ++ The mold plug region 8 reaches the front surface of the semiconductor substrate 10. ++ Between the mold plug region 8 and the trench 2, + The p-type contact region 7 reaches the front surface of the semiconductor substrate 10. The p-type base region 5 and the n-type - An n-type accumulation region 31 may be provided between the n-type drift region 1 and the n-type accumulation region 31. The n-type accumulation region 31 has the function of enhancing the conductivity modulation effect.

[0134] A boundary region 21a may be provided in a portion of the IGBT region 21 adjacent to the FWD region 22 in the first direction X. The boundary region 21a is a structure for connecting the different structures of the IGBT region 21 and the FWD region 22 with good characteristics, and the boundary region 21a may be provided with a structure different from that of the normal IGBT region 21. In this example, the boundary region 21a is a region sandwiched on both sides by dummy trenches 2b (between adjacent dummy trenches 2b) and is formed on the front surface side of the semiconductor substrate 10 by a p + By providing the n-type contact region 7 + The p-type emitter region 6 is not provided, and the p-type emitter region 6 is provided on the back surface of the semiconductor substrate 10. + The collector region 17 is a region provided.

[0135] Although not shown, in another example of the boundary region between the IGBT region 21 and the FWD region 22, the boundary region is formed on the front surface side of the semiconductor substrate 10 by n-type GaN. + type emitter region 6 and p + The p-type contact region 7 is not provided, and only the p-type base region 5 is provided. + The boundary region between the IGBT region 21 and the FWD region 22 may be provided across a region sandwiched between a plurality of adjacent trenches 2 (gate trenches 2 a or dummy trenches 2 b). The boundary region between the IGBT region 21 and the FWD region 22 does not necessarily have to be provided.

[0136] In the FWD region 22, the p-type base region 5 functions as a p-type anode region. Between the front surface of the semiconductor substrate 10 and the p-type base region 5 in the FWD region 22, p ++ The mold plug region 8 is selectively provided. ++ The configuration other than the layout of the mold plug region 8 in plan view (as viewed from the front surface side of the semiconductor substrate 10) is the same as that of the p ++ The same applies to the type plug region 8. Specifically, in the FWD region 22, p ++ The mold plug region 8 may extend linearly in the second direction Y with a length substantially equal to the longitudinal length of the trench 2, or may be provided in a discrete manner in a portion thereof.

[0137] In the FWD region 22, in a cross-sectional view, ++ The mold plug region 8 reaches the front surface of the semiconductor substrate 10. ++ The width of the mold plug region 8 in the first direction X is approximately equal to the width of the lower end of a contact hole 9a (described later) in the first direction X. ++ The mold plug region 8 does not reach the sidewall of the trench 2. In another example, ++ The width of the mold plug region 8 in the first direction X may be wider than the width of the lower end of the contact hole 9 a in the first direction X due to diffusion of the impurity ions implanted into the semiconductor substrate 10, and may further reach the sidewall of the trench 2.++ Between the p-type plug region 8 and the trench 2, the p-type base region 5 reaches the front surface of the semiconductor substrate 10. ++ Between the p-type plug region 8 and the p-type base region 5, ++ The p + A mold contact region 7 may be provided.

[0138] p-type base region 5, n + type emitter region 6, p + Type contact region 7, p ++ n-type plug region 8, n-type accumulation region 31, p + The well region 51 and the breakdown voltage structure, the n-type FS layer 16 and the p-type + collector region 17 and n + The cathode region 18 is an n-type - The p-type base region 5 and the n-type base region 6 are diffusion regions formed by ion implantation of impurities of a predetermined conductivity type (n-type or p-type) into the semiconductor substrate 10. + type emitter region 6, p + Type contact region 7, p ++ n-type plug region 8, n-type accumulation region 31, p + well region 51, voltage-resistant structure, n-type FS layer 16, p + collector region 17 and n + The portion excluding the cathode region 18 is n - This is the type drift region 1.

[0139] An interlayer insulating film 9 is provided on the entire front surface of the semiconductor substrate 10 so as to cover the front surface element structure. The interlayer insulating film 9 is a silicon oxide (SiO2) film whose outermost surface is made of silica glass such as BPSG, PSG (Phospho Silicate Glass), or NSG (Non-doped Silicate Glass). The interlayer insulating film 9 may have a two-layer structure, for example, a high temperature oxide (HTO) film 61 deposited on the front surface of the semiconductor substrate 10 and a BPSG film 62 deposited on the HTO film 61 (see FIG. 6).

[0140] The interlayer insulating film 9 does not contain a halogen element such as fluorine (F), or even if it contains a halogen element, it does not have a portion containing the halogen element at a high concentration. The portion of the interlayer insulating film 9 containing the halogen element at a high concentration is a surface layer 9b (see FIG. 8) into which the halogen element is ion-implanted 64 because it is not covered with the resist mask 63 during the processing of step S5 described below, and includes a portion of the halogen element at the maximum concentration (the depth position of the range of the ion implantation 64) in the ion implantation 64. The surface layer 9b of the interlayer insulating film 9 containing the halogen element at a high concentration is removed in a subsequent process and does not remain in the product (semiconductor device 20) (see FIG. 11).

[0141] Even if the halogen element ions implanted 64 into the interlayer insulating film 9 diffuse laterally (in a direction parallel to the front surface of the semiconductor substrate 10) and vertically (in the depth direction Z) through the interlayer insulating film 9 and remain in the interlayer insulating film 9, the halogen element concentration per unit volume at the diffusion point of the halogen element is significantly lower than the halogen element concentration per unit volume at the ion-implanted point of the halogen element. Specifically, since the interlayer insulating film 9 does not have a halogen element ion-implanted point (surface layer 9b into which halogen elements have been ion-implanted 64), the halogen element concentration per unit volume of the interlayer insulating film 9 is, for example, 1×10 19 / cm 3 It is about the following.

[0142] A plurality of contact holes (first contact holes) 9a are provided penetrating the interlayer insulating film 9 in the depth direction Z. The plurality of contact holes 9a extend, for example, in stripes in the longitudinal direction of the trenches 2 (second direction Y) (hatched portions in FIG. 2). Each contact hole 9a is provided between different adjacent trenches 2 and exposes the front surface of the semiconductor substrate 10. The contact holes 9a in the IGBT region 21 are provided with n + type emitter region 6 and p ++ The contact plug region 8 and the contact hole 9a in the FWD region 22 are exposed alternately and repeatedly in the second direction Y. ++ The mold plug region 8 is exposed.

[0143] At the end of the contact hole 9a in the longitudinal direction, +The cross-sectional shape of the contact hole 9a may be a substantially rectangular shape with the sidewall of the contact hole 9a perpendicular to the front surface of the semiconductor substrate 10 (FIGS. 3 and 4), or may be a tapered shape with the width in the first direction X narrowing at a constant decreasing rate or in a stepwise manner toward the semiconductor substrate 10 (see FIG. 16A described later). As will be described later, a p-type contact region 7 is formed on the front surface of the semiconductor substrate 10, continuing from the contact hole 9a, so that the p-type contact region 7 is closer to the interface between the interlayer insulating film 9 and the semiconductor substrate 10. + A contact trench (see FIGS. 40 to 42) recessed toward the mold collector region 17 may be provided.

[0144] A barrier metal 13 is provided along the inner wall of the contact hole 9a (the side surface of the interlayer insulating film 9 and the front surface of the semiconductor substrate 10) and the upper surface of the interlayer insulating film 9. The barrier metal 13 is made of a metal that has high adhesion strength with the semiconductor substrate 10, the surface electrode 15, and the plug 14 and can form ohmic contact with the semiconductor substrate 10. Specifically, the barrier metal 13 includes, for example, a titanium (Ti) film 11 that has high adhesion strength with the semiconductor substrate 10, and a titanium nitride (TiN) film 12 that has high adhesion strength with the surface electrode 15 and the plug 14. The barrier metal 13 has the function of preventing the precipitation of Si due to an interaction between the surface electrode 15 and the semiconductor substrate 10.

[0145] The barrier metal 13 also functions as an ion trap that captures metal ions diffusing from the side of the surface electrode 15. For example, migration may occur in the surface electrode 15 when the semiconductor device 20 is mounted. If migration occurs in the surface electrode 15, metal ions such as sodium (Na) ions will diffuse from defects in the surface electrode 15 to the interlayer insulating film 9 side, causing a change in the gate threshold voltage. Therefore, by disposing the barrier metal 13, which does not cause migration, between the surface electrode 15 and the upper surface of the interlayer insulating film 9, it is possible to prevent the diffusion of metal ions from the surface electrode 15 to the gate electrode 4.

[0146] The Ti film 11 is provided along the sidewall of the contact hole 9a (the side surface of the interlayer insulating film 9) and extends onto the upper surface of the interlayer insulating film 9, covering the entire surface of the interlayer insulating film 9. Since no portion containing a high concentration of halogen elements (a portion where halogen elements have been ion-implanted) remains in the interlayer insulating film 9, the adhesion strength of the Ti film 11 to the interlayer insulating film 9 is increased.

[0147] A silicide film 11a is provided on the entire front surface of the semiconductor substrate 10 inside the contact hole 9a (the bottom surface of the contact hole 9a). The silicide film 11a is a titanium silicide (TiSi2 or the like) film formed by silicidation of a Ti film 11 having high adhesive strength with Si. In the contact hole 9a of the IGBT region 21, the silicide film 11a and n + type emitter region 6 and p ++ An ohmic contact is formed with the p-type plug region 8. In the contact hole 9a of the FWD region 22, a silicide film 11a and a p-type plug region 8 are formed. ++ An ohmic contact is made to the mold plug region 8 .

[0148] The TiN film 12 is provided on the Ti film 11 and the silicide film 11a and along their surfaces. The Ti film 11 may extend between the TiN film 12 and the silicide film 11a. A plug 14 is provided on the TiN film 12 inside the contact hole 9a. The plug 14 is, for example, a tungsten (W) film with high embedding properties. Alternatively, the plug 14 may be a copper (Cu) film. A surface electrode 15 is provided on the plug 14 and the TiN film 12 and is connected to the p-type base region 5, n-type base region 6, and n-type base region 7 via the plug 14, barrier metal 13, and silicide film 11a. + type emitter region 6, p + type contact region 7 and p ++ It is electrically connected to the mold plug region 8 .

[0149] The surface electrode 15 is an aluminum (Al) film or an Al alloy film such as aluminum silicon (AlSi). Alternatively, the surface electrode 15 may be a Cu elemental or alloy film. A plug 14 may extend from within the contact hole 9a between the surface electrode 15 and the TiN film 12 on the upper surface of the interlayer insulating film 9 (see FIG. 16B ). The plug 14 between the surface electrode 15 and the interlayer insulating film 9 can improve impact resistance and mechanical strength during wire bonding. The surface electrode 15, plug 14, barrier metal 13, and silicide film 11a constitute the front surface electrode of the semiconductor device 20. The portion of the surface electrode 15 exposed through an opening in the passivation film (not shown) serves as a main electrode pad. The front surface electrode is the emitter electrode of the IGBT and also serves as the anode electrode of the diode. While FIG. 1 does not show a main electrode pad for the front surface electrode, the main electrode pad may have a planar shape and dimensions that fit substantially within the surface of the active region 41. FIG. 1 illustrates the gate pad 56 opening in the passivation film in the edge termination region 42 .

[0150] On the back surface (second main surface) side of the semiconductor substrate 10, an n-type field stop (FS) layer 16, a p + collector region 17 and n + The n-type FS layer 16 is formed on the back surface of the semiconductor substrate 10. + collector region 17 and n + The n-type FS layer 16 is located deeper than the p-type cathode region 18 toward the p-type base region 5. + collector region 17 and n + The n-type FS layer 16 may be in contact with the p-type base region 5 and the n-type cathode region 18 when the semiconductor device 20 is turned off. - The pn junction with the semiconductor drift region 1 functions to suppress the spread of a depletion layer from the pn junction with the semiconductor drift region 1 to the back surface side of the semiconductor substrate 10 .

[0151] p + The n-type collector region 17 is connected to the back surface of the semiconductor substrate 10 in the IGBT region 21. - The n-type drift region 1 is provided between the n-type drift region 1 and the n-type drift region 2. +The cathode region 18 is connected to the back surface of the semiconductor substrate 10 in the FWD region 22. - The n-type drift region 1 is provided between the n-type drift region 1 and the n-type drift region 2. + The cathode region 18 is p + The back electrode 19 is disposed on the entire back surface of the semiconductor substrate 10. The back electrode 19 is disposed adjacent to the p-type collector region 17. + collector region 17 and n + The back electrode 19 is in contact with the cathode region 18 and is electrically connected to these regions. The back electrode 19 is a collector electrode and also serves as a cathode electrode.

[0152] n - A low carrier lifetime region 32 in which the lifetime of minority carriers (holes) is short may be provided inside the type drift region 1. The low carrier lifetime region 32 may be, for example, p + The low carrier lifetime region 32 is formed by introducing lattice defects (indicated by x marks) that act as lifetime killers into the p-type collector region 17 at a position deep inside the n-type FS layer 16 and at a position shallower inside the p-type base region 5 than the n-type FS layer 16. + Type contact region 7 to n - Since the electron injection layer 22 can reduce holes injected into the type drift region 1, it may be provided mainly in the FWD region 22.

[0153] A manufacturing method of the semiconductor device 20 according to the first embodiment will be described. FIG. 5 is a flowchart outlining the manufacturing method of the semiconductor device according to the first embodiment. FIGS. 6 and 10 to 15 are cross-sectional views showing a state during manufacturing of the semiconductor device according to the first embodiment. FIG. 7 is a plan view showing a state during manufacturing of the semiconductor device according to the first embodiment. FIGS. 8 and 9 are cross-sectional views showing cross-sectional structures taken along the cutting lines C1-C1′ and C2-C2′ in FIG. 7, respectively. FIG. 16A is a cross-sectional view showing an example structure of the semiconductor device according to the first embodiment. FIG. 16B is a cross-sectional view showing another example structure of the semiconductor device according to the first embodiment. FIG. 7 shows the opening pattern (pattern of contact holes 9a and openings 63a) of the interlayer insulating film 9 and the resist mask 63 in the IGBT region 21.

[0154] 7, the outline of the interlayer insulating film 9 is shown by a broken line where it overlaps with the resist mask 63 (hatched portion). ++ 9 shows the region where the mold plug region 8 is formed, and FIG. ++ 8 shows an area where the mold plug region 8 is not formed. + The contact region 7 is eliminated. ++ The parts other than the mold plug region 8 are not shown. ++ 16A and 16B show enlarged views of the vicinity of the region where the mold plug region 8 is formed. ++ The vicinity of the mold plug region 8 is shown enlarged, and the p ++ 16A and 16B, the thickness of the surface electrode 15 is shown to be relatively thicker than in FIGS. 3 and 4, but the dimensions of each part of the semiconductor devices 20 and 30 are set appropriately depending on the conditions of use of the product, etc.

[0155] First, on the front surface side of the semiconductor wafer, in each chip region (region that will become the semiconductor substrate 10 when the semiconductor wafer is separated: hereinafter referred to as the semiconductor substrate 10), p ++ 2 to 4) are formed (step S1: first step). When the semiconductor device 20 is an RC-IGBT, the front surface element structure is a trench gate structure and n-type accumulation region 31 in the IGBT region 21, a p-type anode region (p-type base region 5), trench 2, gate insulating film 3, and gate electrode 4 in the FWD region 22, and a p-type anode region (p-type base region 5) in the edge termination region 42. + a well region 51 and a breakdown voltage structure.

[0156] Next, as shown in FIG. 6 , an interlayer insulating film 9 is deposited (formed) over the entire front surface of the semiconductor substrate 10 (step S2: second process). The thickness t11 of the interlayer insulating film 9 is calculated by adding the thickness t1 of the interlayer insulating film 9 as a finished product (see FIGS. 3 and 4 ) to the thickness t12 (see FIG. 11 ) of a surface layer 9c of the interlayer insulating film 9 that will be removed in step S8 (described later). The interlayer insulating film 9 may have a two-layer structure in which an HTO film 61 and a BPSG film 62 are sequentially deposited by chemical vapor deposition (CVD). Instead of the HTO film 61, a thermal oxide film may be formed by thermally oxidizing the semiconductor substrate 10. After the deposition of the interlayer insulating film 9, a heat treatment (reflow) may be performed for planarization.

[0157] Next, a contact hole 9a is formed through the interlayer insulating film 9 in the depth direction Z by photolithography and etching (step S3: third process). + type emitter region 6 and p + The p-type contact region 7 is exposed. The p-type anode region (p-type base region 5) is exposed in the contact hole 9a of the FWD region 22. The p-type base region 5 and the p-type anode region (p-type base region 5) are exposed in the insulating layer 52. + A contact hole may be formed to expose the mold well region 51. After the resist mask used to form the contact hole is removed, the interlayer insulating film 9 and the insulating layer 52 are planarized by heat treatment (reflow). Note that this reflow does not necessarily have to be performed.

[0158] Next, as shown in FIGS. 7 to 9, a p ++ A resist mask 63 is formed with openings in portions corresponding to the regions where the mold plug regions 8 are to be formed (step S4: implantation step). The opening pattern of the resist mask 63 may be the same as the opening pattern of the resist mask disclosed in, for example, FIG. 12 of the above-mentioned Patent Document 2. That is, in the IGBT region 21, the opening pattern of the resist mask 63 is formed in a stripe shape extending in the first direction X (the short-side direction of the contact holes 9a), and all p + Type contact region 7 (p ++The region where the mold plug region 8 is to be formed is exposed through the same opening 63 a of the resist mask 63 .

[0159] In the IGBT region 21, the opening 63a of the resist mask 63 is filled with p + The p-type contact region 7 and the interlayer insulating film 9 are + The portion adjacent to the mold contact region 7 is exposed (FIGS. 7 and 8). + type emitter region 6 (p ++ a region where the die plug region 8 is not formed, and a region where the die plug region 8 is not formed, and a region where the die plug region 8 is not formed. + The portion adjacent to the emitter region 6 is covered with a resist mask 63 ( FIGS. 7 and 9 ). In the FWD region 22, an opening 63 a exposing the entire FWD region 22 is formed in the resist mask 63. Therefore, the entire surface of the interlayer insulating film 9 in the FWD region 22 is exposed to the opening 63 a in the resist mask 63.

[0160] Further, for example, the entire surface of the insulating layer 52 and the contact holes of the insulating layer 52 may be exposed without being covered with the resist mask 63. + Alternatively, only the emitter region 6 may be covered with the resist mask 63. In this case, the entire surfaces of the interlayer insulating film 9 and the insulating layer 52 are not covered with the resist mask 63 and are exposed. ++ When there is a p-type anode region in which no die plug region 8 is formed, the p-type anode region may be covered with a resist mask 63. The exposed portions of the interlayer insulating film 9 and the insulating layer 52 that are not covered with the resist mask 63 are used as an ion implantation mask in the process of step S5 described later.

[0161] Next, p-type impurity ions 64 are implanted using the resist mask 63, the interlayer insulating film 9, and the insulating layer 52 as an ion implantation mask (step S5: implantation step). In the process of step S5, a boron halide (halide (predetermined impurity)) such as boron fluoride (BF2) which has a heavier mass than boron (B) is used as the p-type impurity (dopant) for ion implantation 64. This prevents the ion implantation 64 of the p-type impurity (boron) in the semiconductor substrate 10 from becoming deeper than necessary, and prevents diffusion in the vertical direction (depth direction Z). Therefore, the p ++ The mold plug region 8 can suppress a decrease in the impurity concentration in the vicinity of the front surface of the semiconductor substrate 10 .

[0162] Furthermore, by using the interlayer insulating film 9 and the insulating layer 52 as an ion implantation mask, boron halide ions 64 are implanted into the portion exposed in the contact hole 9a, thereby suppressing the lateral diffusion (direction parallel to the front surface of the semiconductor substrate 10) of the p-type impurity (boron) within the semiconductor substrate 10. In addition, boron and halogen elements are ion-implanted 64 into the surface layer 9b of the interlayer insulating film 9 and the surface layer of the insulating layer 52 in the exposed portion not covered by the resist mask 63 (FIG. 8). The ion implantation 64 is performed, for example, at a dose of 1×10 15 / cm 2 5x10 or more 15 / cm 2 The acceleration energy is set to about 10 keV or more and 50 keV or less. Then, the resist mask 63 is removed (step S6: implantation step).

[0163] Next, as shown in FIG. 10, the semiconductor substrate 10 is heated by heat treatment (annealing) to activate and diffuse the p-type impurity (boron) ions implanted 64 into the semiconductor substrate 10 in the process of step S5. ++ At this time, the p-type impurity (boron) ions implanted 64 into the semiconductor substrate 10 in the process of step S5 diffuses in the lateral direction parallel to the front surface of the semiconductor substrate 10, forming p ++The mold plug region 8 may be formed not only in the portion exposed through the opening of the ion implantation mask (resist mask 63, interlayer insulating film 9, and insulating layer 52), but also extending to just below the ion implantation mask. ++ The width of the opening 63a of the resist mask 63 is set to p so that the mold plug region 8 is formed in a desired range (surface area). ++ It may be narrower than the width of the mold plug region 8 .

[0164] For example, in the IGBT region 21, ++ When the mold plug region 8 is formed to extend beyond the desired range, n + The exposed surface of the n-type emitter region 6 (contact area with the front electrode) becomes small. + Above the emitter region 6, ++ In order to prevent the formation of the mold plug region 8, the process of step S4 is performed to form a mask having a thickness of n when viewed from the front surface side of the semiconductor substrate 10 (when viewed from above). + The outer periphery of the emitter region 6 (p + n-type contact region 7 + An opening 63a may be formed in the resist mask 63 so that the portion of the semiconductor substrate 10 (a portion near the emitter region 6) is not exposed. The process of step S7 may be, for example, RTA (Rapid Thermal Anneal), or may be heat treatment in a hydrogen (H) atmosphere to repair crystal defects caused by the ion implantation 64 in the semiconductor substrate 10 during the process of step S5. The halogen elements implanted by the ion implantation 64 and diffused into the semiconductor substrate 10 do not adversely affect the device characteristics.

[0165] 11, the surface layer 9c of the interlayer insulating film 9 is uniformly removed to a predetermined thickness t12, so that the interlayer insulating film 9 has a final thickness t1 (step S8: removal step). The process of step S8 removes at least the portion of the interlayer insulating film 9 that contains a high concentration of halogen (the surface layer 9b from the upper surface to the depth position of the range of ion implantation 64). This allows the halogen concentration per unit volume of the interlayer insulating film 9 to be reduced to or below the upper limit value. The more the surface layer 9c of the interlayer insulating film 9 is removed, the more of the portion of the interlayer insulating film 9 that contains halogen can be removed. It is also possible to remove all of the portion of the interlayer insulating film 9 that contains halogen.

[0166] The surface layer 9c of the interlayer insulating film 9 may be removed by, for example, isotropic wet etching using a hydrofluoric acid (HF) solution or a dilute hydrofluoric acid solution, or by mechanical polishing such as CMP (Chemical Mechanical Polishing). If the process of step S8 is wet etching using a hydrofluoric acid solution or a dilute hydrofluoric acid solution, the sidewalls of the contact holes 9a (side surfaces of the BPSG 62) are also etched, widening the opening width of the contact holes 9a. This improves the embeddability of the plugs 14 in the contact holes 9a in step S11, which will be described later.

[0167] When wet etching is performed using a hydrofluoric acid solution or a dilute hydrofluoric acid solution, the process of step S8 also serves as a cleaning process (pre-processing for sputtering) for removing a native oxide film from the exposed surface of the semiconductor substrate 10. When the process of step S8 is mechanical polishing, it is preferable to perform wet etching using a hydrofluoric acid solution or a dilute hydrofluoric acid solution after the process of step S8 and before the process of step S9 (sputtering) as a pre-processing for sputtering to remove the native oxide film from the exposed surface of the semiconductor substrate 10. During the process of step S8, at least the portion of the insulating layer 52 containing a high concentration of halogen elements is also removed, as is the surface layer 9c of the interlayer insulating film 9.

[0168] 12, a Ti film 11 and a TiN film 12, which will become a barrier metal 13, are deposited (formed) in this order by sputtering over the entire inner wall of the contact hole 9a (the side surface of the interlayer insulating film 9 and the front surface of the semiconductor substrate 10) and the upper surface of the interlayer insulating film 9 (step S9: first film deposition step). As described above, by removing the portion of the interlayer insulating film 9 containing a high concentration of halogen elements, the newly exposed surface layer of the interlayer insulating film 9 has a low concentration of halogen elements per unit volume or does not contain halogen elements. Therefore, the adhesion strength between the interlayer insulating film 9 (BPSG 62) and the Ti film 11 is higher than in the reference structure (see FIG. 35).

[0169] 13, a silicide film 11a is formed on the bottom surface of the contact hole 9a (the contact point between the Ti film 11 and the front surface of the semiconductor substrate 10) by a silicide reaction between Ti atoms in the Ti film 11 and silicon (Si) atoms in the semiconductor substrate 10 by heat treatment (sintering) (step S10). The entire Ti film 11 on the bottom surface of the contact hole 9a may be silicided, or unreacted Ti film 11 may remain between the Ti film 11 and the TiN film 12. The process of step S7 described above may be omitted, and the process of step S10 may also serve as the process of step S7.

[0170] Next, as shown in FIG. 14 , a plug 14 is formed on the entire surface of the TiN film 12 by chemical vapor deposition (CVD) so as to fill the contact hole 9 a (step S11). Next, as shown in FIG. 15 , the plug 14 is removed by, for example, etch-back until the TiN film 12 is exposed, leaving only the inside of the contact hole 9 a (step S12). Next, as shown in FIG. 16A , a surface electrode 15 is formed on the plug 14 and the TiN film 12 by, for example, sputtering, and the surface electrode 15 and the barrier metal 13 are patterned (step S13: second film formation process). This completes the front surface structure of the semiconductor device 20.

[0171] Then, a structure on the back side of the semiconductor substrate 10 is formed by a general method (step S14). The processing in step S14 includes, for example, grinding the back side of the semiconductor substrate 10 (grinding the semiconductor substrate 10 from the back side to the product thickness), grinding the n-type FS layer 16, p-type FS layer 17, and the like. + collector region 17 and n + These include ion implantation and impurity activation for forming the mold cathode region 18, and formation of the back electrode 19. After this, or during the process from step S13 to the end of step S14, other processes may be performed, such as forming a passivation film and opening (exposing the main electrode pads and gate pad 56, etc.), forming a low carrier lifetime region 32 as needed, and further forming a plating layer on the electrode pads for solder mounting. The semiconductor wafer is then diced (cut) into individual semiconductor chips, thereby completing the semiconductor device 20 shown in FIGS. 1 to 4 and 16A.

[0172] In the method for manufacturing a semiconductor device according to the first embodiment described above, the process of step S12 may be omitted to leave plug 14 on the entire surface of TiN film 12, and in the process of step S13, surface electrode 15 may be formed on the entire surface of plug 14, followed by patterning surface electrode 15, plug 14, and barrier metal 13. In this case, as shown in FIG. 16B , a semiconductor device 30 is fabricated that includes a front surface electrode having a structure in which plug 14 is interposed between surface electrode 15 and barrier metal 13 on the upper surface of interlayer insulating film 9.

[0173] As described above, according to the first embodiment, a high concentration of halogen elements are implanted into the surface layer of the interlayer insulating film during ion implantation of boron halide, and therefore, the surface layer of the interlayer insulating film is actively removed before forming a barrier metal on the surface of the interlayer insulating film. The barrier metal is formed on the surface of the interlayer insulating film after the interlayer insulating film does not contain halogen elements or the halogen element concentration per unit volume of the interlayer insulating film is reduced to a level that does not adversely affect the adhesion between the interlayer insulating film and the barrier metal, thereby increasing the adhesion strength between the interlayer insulating film and the barrier metal. Therefore, peeling of the front surface electrode (barrier metal and front surface electrode) from the interface between the interlayer insulating film and the barrier metal can be suppressed.

[0174] Furthermore, according to the first embodiment, the increased adhesion strength between the interlayer insulating film and the barrier metal can prevent the barrier metal from peeling off during the manufacturing process, thereby preventing contamination and damage caused by peeled pieces of the barrier metal, and improving the reliability of the semiconductor device.

[0175] (Details of Second Embodiment) A method for manufacturing a semiconductor device according to a second embodiment that solves the above-mentioned problems will be described below. FIG. 17 is a cross-sectional view showing an example of the structure of a semiconductor device according to the second embodiment. ++ 1 shows an enlarged view of a structure example in the vicinity of the mold plug region 8, and ++ Portions other than the mold plug region 8 are omitted from the illustration. The structure of the semiconductor device 70 according to the second embodiment shown in FIG. 17 , excluding the illustrated portions, may be the same as the semiconductor device 20 shown in FIGS. 1 to 4. FIG. 18 is a flowchart outlining a method for manufacturing the semiconductor device according to the second embodiment. FIG. 19 is a cross-sectional view showing a state during the manufacturing of the semiconductor device according to the second embodiment. The front surface element structure is omitted from FIG. 19. FIG. 20 is a plan view showing a state during the manufacturing of the semiconductor device according to the second embodiment.

[0176] 20 shows the opening pattern (pattern of contact holes 9a and openings 71a) of the interlayer insulating film 9 and resist mask 71 in the IGBT region 21. In FIG. 20, the outline of the interlayer insulating film 9 is shown by a broken line where it overlaps with the resist mask 71 (hatched portion). FIGS. 21 and 22 are cross-sectional views showing the cross-sectional structures taken along the cutting lines D1-D1' and D2-D2' in FIG. 20, respectively. FIG. 21 shows the p ++ 22 shows the region where the mold plug region 8 is formed, and the p ++ 21 shows an area where the mold plug region 8 is not formed. + The mold contact region 7 is eliminated.

[0177] The manufacturing method of the semiconductor device according to the second embodiment differs from the manufacturing method of the semiconductor device 20 according to the first embodiment (see FIG. 5) in that p ++ The resist mask 71 covers the entire upper surface of the interlayer insulating film 9 and the upper surface of the insulating layer 52 during ion implantation 72 for forming the mold plug region 8. The resist mask 71 is preferably patterned so that the interlayer insulating film 9 and the insulating layer 52 are not exposed. However, the width of the opening 71a of the resist mask 71 in the first direction X is set slightly wider than the width of the contact hole 9a of the interlayer insulating film 9 in the first direction X, so that p ++ The upper corner portion 9 d of the interlayer insulating film 9 facing the mold plug region 8 may be exposed through the opening 71 a of the resist mask 71 .

[0178] By making the width of the opening 71a of the resist mask 71 in the first direction X slightly wider than the width of the contact hole 9a of the interlayer insulating film 9 in the first direction X, even if there is a deviation in the first direction X in the alignment of the photomask for forming the opening pattern of the resist mask 71, p ++This allows the entire area of ​​the portion (bottom surface of contact hole 9 a in interlayer insulating film 9) corresponding to the formation region of mold plug region 8 to be reliably exposed. The opening pattern of resist mask 71 is set so that the total surface area of ​​the portion of interlayer insulating film 9 exposed in opening 71 a in resist mask 71 (portion into which halogen element ions 72 are implanted: see FIG. 21 ) is, for example, about ¼ or less or ⅕ or less, more preferably about less than 1 / 10, of the total surface area of ​​interlayer insulating film 9.

[0179] By the method for manufacturing a semiconductor device according to the second embodiment, the semiconductor device 20 according to the first embodiment (see FIG. 16A) is fabricated (manufactured), or the semiconductor device 70 according to the second embodiment shown in FIG. 17 is fabricated. The semiconductor device 70 according to the second embodiment differs from the semiconductor device 20 according to the first embodiment in that the halogen element concentration is locally maximized at the upper end corner portion 9d of the interlayer insulating film 9. Specifically, ++ The halogen element has the highest concentration at the upper corner 9d of the interlayer insulating film 9 in the portion facing the mold plug region 8. The upper corner 9d of the interlayer insulating film 9 is the boundary between the upper surface and the side surface of the interlayer insulating film 9 (the upper end of the sidewall of the contact hole 9a).

[0180] The halogen element may have a local maximum concentration on the side surface of the interlayer insulating film 9 (the side wall of the contact hole 9 a). The maximum halogen element concentration in the interlayer insulating film 9 is, for example, 5×10 19 / cm 3 The portions of the interlayer insulating film 9 other than those containing a high concentration of halogen elements do not contain halogen elements, or the halogen element concentration per unit volume is, for example, 1×10 due to the halogen elements diffused from the upper corner portion 9d. 19 / cm 3 The inventors have confirmed through extensive research that the Ti film 11 will not peel off from the interlayer insulating film 9 if the total surface area of ​​the portions of the interlayer insulating film 9 that contain a high concentration of halogen elements is about ¼ or ⅕ or less, more preferably less than 1 / 10, of the total surface area of ​​the interlayer insulating film 9.

[0181] In the method of manufacturing a semiconductor device according to the second embodiment (FIG. 18), first, similar to the process of step S1 in the first embodiment (see FIG. 5), p of the front surface element structure is ++ Each portion other than the mold plug region 8 is formed (step S21). Next, as shown in FIG. 19, an interlayer insulating film 9 is formed over the entire front surface of the semiconductor substrate 10 to a thickness approximately equal to the thickness t1 of the finished product (for example, a thickness that takes into account the thickness reduction that normally occurs during the manufacturing process) (step S22). The conditions of step S22 other than the thickness t1 of the interlayer insulating film 9 are the same as those of the process of step S2 in the first embodiment. Next, contact holes 9a are formed (step S23) in the same manner as in the process of step S3 in the first embodiment, and heat treatment (reflow) is performed.

[0182] Next, as shown in FIGS. 20 to 22, a p ++ A resist mask 71 is formed with an opening in a portion corresponding to the region where the mold plug region 8 is to be formed (step S24). ++ The resist mask 71 has an opening 71a only in a portion corresponding to the region where the mold plug region 8 is to be formed. That is, the resist mask 71 covers the entire upper surface of the interlayer insulating film 9 and the upper surface of the insulating layer 52 (see FIG. 2), and the p-type portion of the bottom surface of the contact hole 9a (the front surface of the semiconductor substrate 10). ++ The region where the mold plug region 8 is not formed (n + type emitter region 6, p ++ As described above, the upper corner portion 9d of the interlayer insulating film 9 may be exposed in the opening 71a of the resist mask 71.

[0183] Next, using the resist mask 71 as an ion implantation mask, boron halide ions are implanted 72 (step S25). When the resist mask 71 covers the entire upper surface of the interlayer insulating film 9 and the upper surface of the insulating layer 52, p ++ Boron halide ions are implanted 72 only into the region where the mold plug region 8 is to be formed, thereby fabricating the semiconductor device 20 according to the first embodiment. ++In addition to the formation region of the die plug region 8, boron halide ions are also implanted 72 into the upper corner portion 9d (FIGS. 20 and 21) of the interlayer insulating film 9 and the side surface of the interlayer insulating film 9, thereby fabricating a semiconductor device 70 according to the second embodiment shown in FIG. 17.

[0184] The conditions for the process in step S24, other than the opening pattern of the resist mask 71, are the same as those for the process in step S4 of embodiment 1. The conditions for the process in step S25, other than the location of the boron halide ion implantation 72, are the same as those for the process in step S5 of embodiment 1. Thereafter, similar to the processes in steps S6, S7, and S9 to S14 of embodiment 1, the following steps are performed in order: removal of the resist mask 71 (step S26), annealing for activating and diffusing the impurities (step S27), formation of the barrier metal 13 (step S28), sintering for forming the silicide film 11a (step S29), formation of the plug 14 (step S30), etching back of the plug 14 (step S31), formation of the surface electrode 15 on the front surface side of the semiconductor substrate 10 (step S32), and formation of a structure on the back surface side of the semiconductor substrate 10 (step S33), thereby completing the semiconductor device 20, 70.

[0185] In the manufacturing method of the semiconductor device according to the second embodiment described above, the process of step S31 may be omitted to leave the plug 14 on the entire surface of the TiN film 12, and in the process of step S32, the surface electrode 15 may be formed on the entire surface of the plug 14, and the surface electrode 15, the plug 14, and the barrier metal 13 may be patterned. In this case, the semiconductor device 30 according to the first embodiment shown in Fig. 16B is manufactured, or the semiconductor device 70 according to the second embodiment shown in Fig. 17 is applied to the semiconductor device 30 according to the first embodiment shown in Fig. 16B, resulting in a structure in which the upper end corner portion 9d of the interlayer insulating film 9 contains a high concentration of halogen elements.

[0186] As described above, according to the second embodiment, p ++ By covering substantially the entire surface of the interlayer insulating film with an ion implantation mask during ion implantation to form the mold plug region, and by preventing almost all halogen elements from being ion-implanted into the surface layer of the interlayer insulating film, it is possible to obtain the same effect as in the first embodiment.

[0187] (Details of the Third Embodiment) A semiconductor device according to a third embodiment that solves the above-mentioned problems will be described below. Figures 23 and 24 are cross-sectional views showing an example of the structure of the semiconductor device according to the third embodiment. ++ 1 shows an enlarged view of a structure example in the vicinity of the mold plug region 8, and ++ The illustration does not include portions other than the mold plug region 8. The structures of the semiconductor devices 80 and 90 according to the third embodiment shown in FIGS. 23 and 24, excluding the illustrated portions, may be similar to those of the semiconductor device 20 shown in FIGS.

[0188] A semiconductor device 80 according to the third embodiment shown in FIG. 23 differs from the semiconductor device 20 according to the first embodiment (see FIG. 16A ) in that a barrier metal 83 is provided only on the inner wall of the contact hole 9 a, and is not provided between the surface electrode 15 and the upper surface of the interlayer insulating film 9. The barrier metal 83 includes, for example, a Ti film 81 and a TiN film 82. The configurations of the Ti film 81 and the TiN film 82 are similar to those of the barrier metal 13 (Ti film 11 and TiN film 12) according to the first embodiment, except that the Ti film 81 and the TiN film 82 are provided only on the inner wall of the contact hole 9 a.

[0189] Since the Ti film 81, which has low adhesion to the interlayer insulating film 9, is not provided between the surface electrode 15 and the upper surface of the interlayer insulating film 9, the adhesion strength between the surface electrode 15 and the interlayer insulating film 9 is increased. The manufacturing method of the semiconductor device 80 according to the third embodiment shown in FIG. 23 may be the same as the manufacturing method of the semiconductor device 20 according to the first embodiment (see FIG. 5 ), except that, after the processing of step S12 and before the processing of step S13, the barrier metal 83 is etched back and removed following the etching back of the plug 14, thereby exposing the upper surfaces of the interlayer insulating film 9 and the insulating layer 52. In the semiconductor device 80 according to the third embodiment, the surface electrode 15 is in direct contact with the upper surfaces of the interlayer insulating film 9 and the insulating layer 52, and therefore does not have a function to prevent the penetration and diffusion of metal ions from the surface electrode 15. However, the Ti film 81 does not peel off during the manufacturing process from step S9 to step S13, and therefore contamination or damage due to peeled pieces of the Ti film does not occur.

[0190] 24 differs from the semiconductor device 20 (see FIG. 16A) according to the first embodiment in that a surface electrode 91 is embedded on the barrier metal 13 inside the contact hole 9a without providing a plug. That is, the surface electrode 91 is in contact with the barrier metal 13 (TiN film 12) on both the inner wall of the contact hole 9a and the upper surface of the interlayer insulating film 9. The configuration of the surface electrode 91 is the same as that of the surface electrode 15 according to the first embodiment, except that it is embedded inside the contact hole 9a.

[0191] The manufacturing method of the semiconductor device 90 according to the third embodiment shown in Fig. 24 can omit the processes of steps S11 and S12 in the manufacturing method of the semiconductor device 20 according to the first embodiment (see Fig. 5), thereby simplifying the manufacturing process. The semiconductor device 90 according to the third embodiment shown in Fig. 24 is useful when the width of the contact hole 9a is relatively wide and it is not necessary to consider the embeddability of the metal film in the contact hole 9a (i.e., when the semiconductor device 90 is not miniaturized).

[0192] 23 and 24 according to the third embodiment may be fabricated by applying the method for manufacturing a semiconductor device according to the second embodiment (see FIG. 18). In this case, the semiconductor devices 80 and 90 according to the third embodiment shown in FIGS. 23 and 24 may have a portion where the halogen element concentration is maximum at the upper end corner portion 9 d of the interlayer insulating film 9, similar to the semiconductor device 70 according to the second embodiment shown in FIG.

[0193] The semiconductor device 90 according to the third embodiment shown in FIG. 24 may be applied to the semiconductor device 80 according to the third embodiment shown in FIG. 23, and the surface electrode 91 may be embedded on the barrier metal 13 inside the contact hole 9a without providing a plug.

[0194] As described above, according to the third embodiment, even if the laminated structure of the front surface electrodes is different, it is possible to obtain the same effects as those of the first and second embodiments.

[0195] (Details of the Fourth Embodiment) A semiconductor device according to a fourth embodiment that solves the above-mentioned problems will be described below. Fig. 25 is a cross-sectional view showing the structure of the semiconductor device according to the fourth embodiment. ++ 1 shows an enlarged view of a structure example in the vicinity of the mold plug region 8, and ++ The illustration does not include portions other than the mold plug region 8. The structure of the semiconductor device 100 according to the fourth embodiment shown in FIG. 25, excluding the illustrated portions, may be the same as the semiconductor device 20 shown in FIGS. 1 to 4. FIG. 26 is a flowchart outlining a method for manufacturing the semiconductor device according to the fourth embodiment. FIGS. 27 to 32 are cross-sectional views showing the semiconductor device according to the fourth embodiment in the course of manufacturing. In FIGS. 27 to 32, p ++ The area around the mold plug region 8 is shown enlarged, and the p ++ The parts other than the mold plug region 8 are omitted from the illustration.

[0196] The semiconductor device 100 according to the fourth embodiment differs from the semiconductor device 20 according to the first embodiment (see FIG. 16A ) in that a barrier metal 106 is provided between the surface electrode 15 and the plug 14 (first contact plug). In the fourth embodiment, a barrier metal 103 is provided along the inner wall of the contact hole 9 a. The barrier metal 103 includes, for example, a Ti film 101 and a TiN film 102. The configurations of the Ti film 101 and the TiN film 102 are similar to those of the barrier metal 13 (Ti film 11 and TiN film 12) according to the first embodiment, except that the Ti film 101 and the TiN film 102 are provided only on the inner wall of the contact hole 9 a.

[0197] The plug 14 is provided on the TiN film 102 inside the contact hole 9a. The configuration of the plug 14 is the same as that of the first embodiment. The barrier metal 106 may be made of the same material as the barrier metal 103, and has, for example, a Ti film 104 and a TiN film 105. The Ti film 104 is provided from the upper surface of the plug 14 to the upper surface of the interlayer insulating film 9. The TiN film 105 is provided on the Ti film 104. The surface electrode 15 is provided on the TiN film 105 and is connected to the p-type base region 5, n-type base region 6, and n-type base region 7 via the barrier metal 106, the plug 14, the barrier metal 13, and the silicide film 11a. +type emitter region 6, p + type contact region 7 and p ++ It is electrically connected to the mold plug region 8 .

[0198] Although not shown, in another example, the barrier metal 106 may have a different structure from the barrier metal 103. For example, the thickness of the Ti film 104 may be different from the thickness of the Ti film 101, or the barrier metal 106 may be composed of only the TiN film 105 without the Ti film 104. Furthermore, the barrier metal 106 may have a single-layer structure of another metal, such as tantalum (Ta), nickel (Ni), magnesium (Mg), cobalt (Co), vanadium (V), lanthanum (La), palladium (Pd), molybdenum (Mo), zirconium (Zr), or W, or an alloy containing one or more of these metals, or a stacked structure using any of these metals. According to this other example, the Ti film 104 may be thin or absent, thereby suppressing fluctuations in the gate threshold voltage due to hydrogen absorption by Ti. The absence of the Ti film 104 brings the TiN film 105 into direct contact with the interlayer insulating film 9, thereby increasing the adhesive strength of the front surface electrode.

[0199] The manufacturing method of the semiconductor device 100 according to the fourth embodiment (FIG. 26) differs from the manufacturing method of the semiconductor device 20 according to the first embodiment (see FIG. 5) in the timing of removing the surface layer 9b of the interlayer insulating film 9. Specifically, first, similarly to the processes in steps S1 to S7 (see FIGS. 6 to 10) of the first embodiment, p ++ The following steps are performed in order: formation of each part other than the mold plug region 8 (step S41), formation of the interlayer insulating film 9 (step S42), formation of the contact hole 9a (step S43), formation of the resist mask 63 (step S44), ion implantation of boron halide (step S45), removal of the resist mask 63 (step S46), and annealing for activating and diffusing the impurities (step S47).

[0200] 27, a Ti film 101 and a TiN film 102, which will become a barrier metal 103, are formed in this order on the entire inner wall of the contact hole 9a and the upper surface of the interlayer insulating film 9 by sputtering (step S48). The barrier metal 103 contacts a portion of the interlayer insulating film 9 containing a high concentration of halogen elements (surface layer 9b). Next, as shown in FIG. 28, a silicide film 11a is formed on the bottom surface of the contact hole 9a (the contact portion between the Ti film 101 and the front surface of the semiconductor substrate 10) by heat treatment (sintering) through a silicide reaction between Ti atoms in the Ti film 101 and Si atoms in the semiconductor substrate 10 (step S49).

[0201] 29, a plug 14 is formed on the entire surface of the TiN film 102 by CVD so as to be embedded in the contact hole 9a (step S50: fourth film formation step). Next, as shown in FIG. 30, the plug 14 and the barrier metal 103 are removed, for example, by successive etch-back until the upper surface of the interlayer insulating film 9 is exposed, so that they remain only inside the contact hole 9a (step S51: second processing step, first processing step). In the processing of step S51, it is preferable to leave the plug 14 and the barrier metal 103 at a lower position inside the contact hole 9a than the height position of the upper surface of the interlayer insulating film 9 after processing of step S52, which will be described later.

[0202] 31 , similar to the process of step S8 in the first embodiment, a surface layer 9c of the interlayer insulating film 9 is removed by a predetermined thickness t12, so that the interlayer insulating film 9 has a thickness t1 at the time of production (step S52: removal process). Similar to the process of step S8 in the first embodiment, the process of step S52 removes at least the portion of the interlayer insulating film 9 containing a high concentration of halogen elements (surface layer 9b from the upper surface to the depth position of the range of ion implantation 64). This allows the halogen element concentration per unit volume of the interlayer insulating film 9 to be reduced to the above-mentioned upper limit or less, similar to the process of the first embodiment. The process conditions of the above-described steps S48 to S52 are the same as those of the processes of steps S9 to S12 and S8 in the first embodiment, respectively.

[0203] As shown in FIG. 32 , a Ti film 104 and a TiN film 105, which will become a barrier metal 106, are deposited (formed) in this order on the entire upper surfaces of the plugs 14 and the interlayer insulating film 9 by sputtering (step S53: third film deposition process). Because at least the portion of the interlayer insulating film 9 containing a high concentration of halogen elements has been removed, the adhesion strength between the interlayer insulating film 9 and the Ti film 104 is increased, as in the first embodiment. Next, a surface electrode 15 is formed on the TiN film 105, and the surface electrode 15 and the barrier metal 106 are patterned (step S54). Then, a structure on the back side of the semiconductor substrate 10 is formed (step S55), thereby completing the semiconductor device 100 shown in FIG. 25 . The processing conditions for steps S54 and S55 described above are the same as those for steps S13 and S14, respectively, in the first embodiment.

[0204] 23 may be applied to the semiconductor device 100 according to the fourth embodiment, so that the barrier metal 106 is not provided. In this case, in the manufacturing method of the semiconductor device 100 according to the fourth embodiment (see FIG. 26), the process of step S53 is omitted, and the surface electrode 15 is formed from the upper surface of the plug 14 to the upper surface of the interlayer insulating film 9 in the process of step S54.

[0205] 24 may be applied to the semiconductor device 100 according to the fourth embodiment described above, and the surface electrode 15 may be embedded on the barrier metal 103 inside the contact hole 9a. In this case, step S50 may be omitted from the manufacturing method of the semiconductor device 100 according to the fourth embodiment described above. A barrier metal 106 may be interposed between the barrier metal 103 and the surface electrode 15 inside the contact hole 9a, or the process of step S53 may be omitted and the surface electrode 15 may be formed on the upper surface of the interlayer insulating film 9.

[0206] 33 is a cross-sectional view showing the structure of a modified example of the semiconductor device according to the fourth embodiment. ++ 1 shows an enlarged view of a structure example in the vicinity of the mold plug region 8, and ++The illustration does not include portions other than the mold plug region 8. The semiconductor device 110 according to the fourth embodiment shown in Fig. 33 differs from the semiconductor device 100 according to the fourth embodiment shown in Fig. 25 in that a plug (second contact plug) 111 is provided between the surface electrode 15 and the TiN film 105. The plug 111 has the effect of capturing metal ions diffusing from the surface electrode 15, and further improves the impact resistance and mechanical strength during wire bonding.

[0207] The manufacturing method of the semiconductor device 110 according to the fourth embodiment shown in Figure 33 is the same as the manufacturing method of the semiconductor device 100 according to the fourth embodiment described above (see Figure 26), except that after the processing of step S53 and before the processing of step S54, a plug 111 is formed on the entire surface of the TiN film 105 by, for example, a CVD method (fifth film formation step). The plug 111 may be formed of the same material as the plug 14. During the processing of step S54, a surface electrode 15 is formed on the entire surface of the plug 111, and when the surface electrode 15 is patterned, the plug 111 and the barrier metal 106 are also patterned together with the surface electrode 15.

[0208] As described above, according to the fourth embodiment, by removing at least the portion of the interlayer insulating film containing a high concentration of halogen elements before forming a barrier metal or a surface electrode, which will remain as a product, on the upper surface of the interlayer insulating film, it is possible to obtain the same effect as in the first embodiment.

[0209] (Details of Fifth Embodiment) A semiconductor module according to a fifth embodiment that solves the above-described problems will be described below. Fig. 34 is a cross-sectional view showing an example of the structure of the semiconductor module according to the fifth embodiment. A semiconductor module 120 according to the fifth embodiment is a module in which the semiconductor devices 20, 30, 70, 80, 90, 100, and 110 (see Figs. 1 to 4, 16A, 16B, 17, 23 to 25, and 33) according to the first to fourth embodiments are housed (mounted) in a case or the like by a general assembly process and are ready for shipping. The module includes a semiconductor element 121 that is a semiconductor chip (semiconductor substrate 10), a laminated substrate 122, a metal substrate 126, and a case 127.

[0210] The semiconductor element 121 corresponds to any one of the semiconductor devices 20, 30, 70, 80, 90, 100, and 110 according to the first to fourth embodiments. The laminated substrate 122 has a wiring pattern 124 of a predetermined circuit made of a conductive plate such as copper (Cu) foil on the front surface of an insulating substrate 123 such as a ceramic substrate that ensures insulation, and a conductive plate 125 such as Cu foil on the back surface of the insulating substrate 123. The conductive plate 125 is bonded to a metal substrate 126 by a bonding material 128 such as solder. The metal substrate 126 has a cooling means such as a heat dissipation fin (not shown). A back electrode (not shown, corresponding to the back electrode 19 in FIGS. 3 and 4 ) of the semiconductor element 121 is bonded to the wiring pattern 124 by a bonding material 129 such as solder.

[0211] One end of a conductive wire 130 is joined by ultrasonic bonding or laser bonding to a front surface electrode (not shown, corresponding to the front surface electrode 15, plug 14, and barrier metal 13 in FIGS. 3 and 4 ) which is a main electrode pad of the semiconductor element 121. The other end of the wire 130 is joined to the wiring pattern 124 by ultrasonic bonding or laser bonding. The wire 130 is a metal wiring containing Al, Cu, gold (Au), or the like as a main component, and may be a bonding wire, a cylindrical terminal pin, a flat ribbon, or the like. Instead of the wire 130, a lead frame (not shown) may be joined to the top surface of the semiconductor element 121 or the wiring pattern 124. The semiconductor element 121 is surrounded by a case 127.

[0212] When the semiconductor element 121 is any one of the semiconductor devices 20, 30, 70, 90, 100, and 110 according to the first to fourth embodiments, the halogen element concentration on the upper surface of the interlayer insulating film (not shown, corresponding to the interlayer insulating film 9 in FIGS. 3, 4, 16A, 16B, 17, 23 to 25, and 33 and the insulating layer 52 in FIG. 2) below the front surface electrode is sufficiently low. This makes it possible to increase the adhesion strength between the interlayer insulating film and the barrier metal (not shown, corresponding to the barrier metal 13 in FIGS. 3, 4, 16A, 16B, 17, 23, and 24 and the barrier metals 103 and 106 in FIGS. 25 and 33) below the main electrode pad, thereby suppressing peeling of the barrier metal at the interface between the interlayer insulating film and the barrier metal when bonding the wire 130.

[0213] The case 127 is, for example, a resin molded product integrally molded with a plurality of external connection terminals 131. All of the external connection terminals 131 (not shown) are separated from one another and integrally molded with the case 127 in substantially the same manner as the external connection terminals 131 shown in FIG. 34 . Of the plurality of external connection terminals 131, one end of the external connection terminal 131 (not shown) that passes a main current to the semiconductor element 121 is joined to the wiring pattern 124 outside the range of the cross-sectional view of FIG. 34 . Of the plurality of external connection terminals 131, one end of the external connection terminal 131 that passes a signal current to the semiconductor element 121 is electrically connected to a signal front surface electrode (not shown, corresponding to gate pad 56 in FIG. 1 ) of the semiconductor element 121 by a conductive wire 132.

[0214] The front surface signal electrode is provided on an interlayer insulating film (corresponding to insulating layer 52 in FIG. 2 ). Alternatively, a contact hole may be provided in the interlayer insulating film, similar to the area under the main electrode pad in the active region, and the front surface signal electrode may be connected to the area under the contact hole. As described above, the halogen element concentration on the top surface of the interlayer insulating film of the semiconductor element 121 is sufficiently low, which increases the adhesion strength between the interlayer insulating film and the barrier metal and prevents the barrier metal from peeling off at the interface between the interlayer insulating film and the barrier metal when bonding the wire 132. The other end of the external connection terminal 131 is exposed to the outside of the case 127.

[0215] The case 127 is bonded to a laminated assembly (e.g., the metal substrate 126) of the semiconductor element 121, the laminated substrate 122, and the metal substrate 126 via an adhesive. The interior of the case 127 is filled with a sealant 133, such as a hard resin such as epoxy or a gel. The sealant 133 insulates and protects the semiconductor element 121, the wires 130 and 132, and the wiring pattern 124. If the sealant 133 contains a large amount of metal ions, the semiconductor element 121 may be any of the semiconductor devices 20, 30, 70, 90, 100, and 110 according to the first to fourth embodiments, which include a barrier metal on an interlayer insulating film. If the sealant 133 does not contain a problematic amount of metal ions or if the intrusion of metal ions into the interlayer insulating layer can be prevented without relying on a barrier metal, the semiconductor element 121 may be the semiconductor device 80 according to the third embodiment.

[0216] The semiconductor element 121 may also be mounted in a caseless semiconductor module that does not have a case. Although not shown, an example of the structure of the caseless semiconductor module is a structure in which, instead of the wires 130 and 132 in FIG. 34 , implant pins and a printed circuit board joined to the implant pins are provided, and the components including these are sealed with a thermosetting resin sealing layer. The caseless semiconductor module is produced by assembling the sealed components including the laminated substrate 122, the semiconductor element 121, the implant pins, and the printed circuit board, placing them in a predetermined mold, and filling the mold with a thermosetting resin composition that constitutes the thermosetting resin sealing layer and curing it.

[0217] As described above, according to the fifth embodiment, it is possible to provide a semiconductor module in which the semiconductor device according to the first to fourth embodiments is mounted.

[0218] (Details of Sixth Embodiment) A method for manufacturing a semiconductor device according to a sixth embodiment that solves the above-mentioned problems will be described below. The method for manufacturing a semiconductor device according to the sixth embodiment differs from the method for manufacturing a semiconductor device according to the first embodiment (see FIG. 5) in that boron (B) is used as the p-type impurity to be ion-implanted 64 (see FIGS. 8 and 9) in the process of step S5 instead of boron halide. That is, in the semiconductor device 20 according to the first embodiment (see FIGS. 1 to 4, 16A, and 16B), the halogen element implanted 64 in the process of step S5 may remain inside the semiconductor substrate 10, the interlayer insulating film 9, and the insulating layer 52, whereas the semiconductor device according to the sixth embodiment differs from the semiconductor device 20 according to the first embodiment in that the halogen element is not included.

[0219] For example, in the process of step S5 of FIG. 5, boron ions are implanted 64 into the interlayer insulating film 9 and the insulating layer 52, and the boron concentration in the surface layer of the interlayer insulating film 9 and the surface layer of the insulating layer 52 becomes, for example, 1.0×10 20 / cm 3 If the concentration becomes as high as or greater than this, there is a problem that the adhesive strength of the barrier metal 13 on the surface layers of the interlayer insulating film 9 and the insulating layer 52 containing boron at such a high concentration decreases. For this reason, also in the sixth embodiment, as in the first embodiment, it is useful to actively remove the surface layer 9c of the interlayer insulating film 9 and the insulating layer 52 containing boron at a high concentration by the process of step S8 in Fig. 5. By the process of step S8 in Fig. 5, at least the portions of the surface layers of the interlayer insulating film 9 and the insulating layer 52 containing boron at a high concentration are removed, and the boron concentration in the surface layers of the interlayer insulating film 9 and the insulating layer 52 is reduced to 1.0 x 10 20 / cm 3 less than 1.0 x 10 19 / cm 3 By doing as follows, the adhesive strength between the interlayer insulating film 9 and the insulating layer 52 and the barrier metal 13 can be increased, as in the first embodiment.

[0220] The semiconductor device manufacturing method according to the sixth embodiment may be applied to the semiconductor device manufacturing method according to the second embodiment (see FIG. 18 ), and in the process of step S25, boron ions 72 may be implanted in a state in which the entire upper surfaces of the interlayer insulating film 9 and the insulating layer 52 are covered with a resist mask 71 (see FIGS. 21 and 22 ). In this case, boron ions are not implanted into the surface layers of the interlayer insulating film 9 and the insulating layer 52. Alternatively, the upper corners 9d of the interlayer insulating film 9 and the insulating layer 52 are exposed in the openings 71a of the resist mask 71, so that the maximum concentration of boron at the upper corners 9d of the interlayer insulating film 9 and the insulating layer 52 is, for example, 5×10 19 / cm 3 It may be about the same or higher (see FIGS. 17, 20, and 21).

[0221] The structure of the semiconductor device according to the sixth embodiment, except that the interlayer insulating film 9 does not contain a halogen element, may be the same as that of the semiconductor device 20 according to the first embodiment (see FIGS. 1 to 4, 16A, and 16B). For example, in the semiconductor device according to the sixth embodiment, the plug 14 may be provided only inside the contact hole 9a (see FIG. 16A), or may extend from the inside of the contact hole 9a to the upper surface of the interlayer insulating film 9 and the upper surface of the insulating layer 52 and be interposed between the surface electrode 15 and the barrier metal 13 (see FIG. 16B).

[0222] The semiconductor device 80, 90 (see FIGS. 23 and 24) according to the third embodiment may be applied to the semiconductor device according to the sixth embodiment, and the barrier metal 13 may be provided only on the inner wall of the contact hole 9 a, or a plug may not be provided and the surface electrode 15 may be embedded inside the contact hole 9 a on the barrier metal 13. The semiconductor device 100 (see FIG. 25) according to the fourth embodiment may be applied to the semiconductor device according to the sixth embodiment, and a barrier metal 106 may be provided between the surface electrode 15 and the plug 14.

[0223] Moreover, the semiconductor device according to the sixth embodiment can be mounted on the semiconductor module 120 (see FIG. 34) according to the fifth embodiment by a general assembly process.

[0224] As described above, according to the sixth embodiment, the p ++ Even if boron is used as the p-type impurity ion-implanted to form the p-type plug region, after the boron ion implantation, at least the surface layer of the interlayer insulating film and the insulating layer containing a high concentration of boron is actively removed as in embodiment 1, or the boron ion implantation is performed with the entire upper surface of the interlayer insulating film and the upper surface of the insulating layer covered with a resist mask as in embodiment 2. This provides the same effects as in embodiments 1 to 4.

[0225] (Details of Seventh Embodiment) A semiconductor device according to a seventh embodiment that solves the above-mentioned problems will be described below. Figures 40 to 42 are cross-sectional views showing examples of the structure of the semiconductor device according to the seventh embodiment. Figures 40 and 41 show p ++ 42 shows an enlarged view of a structure example in the vicinity of the mold plug region 142. ++ The enlarged view shows an example of the structure in the vicinity of the mold plug region 142. ++ The structure in the vicinity of the mold plug region 142 may be similar to that shown in Fig. 42. The structure of the semiconductor device 140 according to the seventh embodiment, excluding the portions shown in Figs. 40 to 42, may be similar to that of the semiconductor device 20 according to the first embodiment (see Figs. 1 to 4, 16A, and 16B).

[0226] The semiconductor device 140 according to the seventh embodiment differs from the semiconductor device 20 according to the first embodiment in that a contact trench 141 is provided in continuity with the contact hole 9a of the interlayer insulating film 9. The contact trench 141 is formed by connecting the front surface of the semiconductor substrate 10 to the p + The contact trench 141 is a recess having a substantially rectangular cross section that is recessed toward the mold collector region 17. The contact trench 141 is provided between adjacent trenches 2 and spaced apart from the trenches 2. The contact trench 141 may have a tapered cross section that narrows from the opening side toward the bottom surface, as long as ions are not implanted into the sidewall of the contact trench 141 in a direction substantially perpendicular to the front surface of the semiconductor substrate 10.

[0227] The contact trench 141 is arranged in substantially the same layout as the contact hole 9a in plan view, has substantially the same width as the lower end (end on the semiconductor substrate 10 side) of the contact hole 9a in the first direction X, and extends linearly in the second direction Y with substantially the same length as the contact hole 9a. If the contact trench 141 has a tapered cross-sectional shape, the upper end (on the contact hole 9a side) of the contact trench 141 and the lower end of the contact hole 9a will have substantially the same width. The contact trench 141 may be wider in the first direction X and longer in the second direction Y than the contact hole 9a due to silicidation of the semiconductor substrate 10 during the formation of the silicide film 143.

[0228] In the IGBT region 21, the contact trench 141 is + type emitter region 6 and p + It terminates inside the contact region 7 (FIGS. 40 and 41). + The emitter region 6 surrounds the contact trench 141 and extends between the trench 2 and the contact trench 141 up to the front surface of the semiconductor substrate 10. + The contact region 7 surrounds the contact trench 141 and extends between the trench 2 and the contact trench 141 up to the front surface of the semiconductor substrate 10. + type emitter region 6 and p + The mold contact region 7 faces the gate electrode 4 on the sidewall of the trench 2 via the gate insulating film 3 , and forms an ohmic contact with the silicide film 143 on the sidewall of the contact trench 141 .

[0229] The bottom surface of the contact trench 141 and the n + type emitter region 6 and p + The entire area between the contact region 7 and the p ++ A mold plug region 142 is provided. ++ The mold plug region 142 is provided apart from the trench 2, and its upper surface (the surface on the surface electrode 15 side) reaches the bottom surface of the contact trench 141. ++ The mold plug region 142 may have approximately the same width as the bottom surface of the contact trench 141 in the first direction X.++ The mold plug region 142 extends linearly along the bottom surface of the contact trench 141 in the second direction Y with substantially the same length as the contact trench 141. ++ The mold plug region 142 forms an ohmic contact with the silicide film 143 at the bottom of the contact trench 141 .

[0230] A silicide film 143 is formed along the inner wall of the contact trench 141, and a p ++ It is sufficient that an ohmic contact is formed between the silicon plug region 142 and the silicide film 143. Therefore, although not shown in the drawing, in another example, the contact trench 141 is + type emitter region 6 or p + The n-type contact region 7 may be penetrated. + type emitter region 6 and p + The mold contact region 7 is provided only between the trench 2 and the contact trench 141. ++ The p-type plug region 142 is provided over the entire area between the bottom surface of the contact trench 141 and the p-type base region 5 , and is in contact with the p-type base region 5 .

[0231] In the FWD region 22, the contact trench 141 terminates inside the p-type anode region (p-type base region 5) (FIG. 42). The p-type anode region surrounds the periphery of the contact trench 141 and extends between the trench 2 and the contact trench 141 up to the front surface of the semiconductor substrate 10. The p-type anode region contacts the gate insulating film 3 on the sidewall of the trench 2 and contacts the silicide film 143 on the sidewall of the contact trench 141. A p-type anode region is formed in the entire area between the bottom surface of the contact trench 141 and the p-type anode region, contacting the p-type anode region. ++ A mold plug region 142 is provided. ++ The contact plug region 142 is formed at the bottom of the contact trench 141 so as to contact the p-type IGBT region 21. ++ The mold plug region 142 is arranged similarly.

[0232] By providing the contact trench 141, the impurity of a predetermined conductivity type ion-implanted from a direction approximately perpendicular to the front surface of the semiconductor substrate 10 is implanted only into the bottom surface of the contact trench 141, and is hardly implanted into the sidewall of the contact trench 141. Therefore, in the element region where the entire bottom surface of the contact hole 9a is exposed, it is not necessary to cover the interlayer insulating film 9 with a resist mask. Boron halide is ion-implanted using the interlayer insulating film 9 and the insulating layer 52 as an ion implantation mask, and p is implanted only into the bottom surface of the contact trench 141. ++ The contact trench 141 is formed in a region where ions are not implanted (the n-type plug region 142 in the IGBT region 21). + type emitter region 6 and p + The p-type contact region 7, the p-type anode region of the FWD region 22, etc. can be left.

[0233] A barrier metal 13 extends from the inner wall of the contact hole 9a (side surface of the interlayer insulating film 9) along the entire inner wall of the contact trench 141. The silicide film 143 is a titanium silicide film formed by silicidating the Ti film 11, and is provided along the entire inner wall of the contact trench 141. The silicide film 143 is a titanium silicide film formed by silicidating the Ti film 11, and is provided along the entire inner wall of the contact trench 141. The silicide film 143 is p-type at the bottom of the contact trench 141 in the IGBT region 21 and the FWD region 22. ++ An ohmic contact is formed with the contact trench 142 in the IGBT region 21, and an n-type + type emitter region 6 and p + An ohmic contact is formed with the mold contact region 7 .

[0234] The configuration of the Ti film 11 is the same as that of the first embodiment. The TiN film 12 is provided on the Ti film 11 and the silicide film 143 and along the surfaces thereof. A portion of the Ti film 11 that is not silicided may remain between the TiN film 12 and the silicide film 143. A plug 144 is provided on the TiN film 12 inside the contact hole 9 a and the contact trench 141 so as to fill the contact hole 9 a and the contact trench 141. The configuration of the plug 144 other than filling the contact trench 141 is the same as that of the plug 14 of the first embodiment. The surface electrode 15 is provided on the plug 144 and the TiN film 12, as in the first embodiment.

[0235] 16B , the plug 144 may extend from inside the contact hole 9 a to the upper surface of the interlayer insulating film 9 and be interposed between the surface electrode 15 and the barrier metal 13. By applying the semiconductor device 80 or 90 according to the third embodiment (see FIGS. 23 and 24 ) to the semiconductor device 140 according to the seventh embodiment, the barrier metal 13 may be provided only on the side wall of the contact hole 9 a and the inner wall of the contact trench 141, or the surface electrode 15 may be embedded on the barrier metal 13 inside the contact hole 9 a and the contact trench 141 without providing a plug. By applying the semiconductor device 100 according to the fourth embodiment (see FIG. 25 ) to the semiconductor device 140 according to the seventh embodiment, a barrier metal may be provided between the surface electrode 15 and the plug 144.

[0236] Similar to the contact trench 141 in the active region 41, a contact trench may be provided on the front surface of the semiconductor substrate 10 in the edge termination region 42, in a layout that is substantially the same as the contact hole (not shown) in the insulating layer 52 in a plan view, and continuous with the contact hole. The periphery of this contact trench is surrounded by the p-type base region 5 (or p + The contact trench is surrounded by a p-type well region 51. A silicide film, a barrier metal, and a plug are provided inside the contact trench, similar to the inside of the contact trench 141. The bottom surface of the contact trench and the p-type base region 5 (or p + between the p well region 51)++ As with the mold plug region 142, ++ A mold plug region (not shown) may also be provided.

[0237] Furthermore, in the edge termination region 42, a contact trench (not shown) may be provided on the surface of the polysilicon layer (the gate electrode 4 inside the dummy trench 2b, the gate polysilicon wiring layer 54 inside the insulating layer 52) covered with the insulating layer 52, so as to be continuous with the contact holes 52a, 52b (see FIG. 2) of the insulating layer 52. This contact trench connects the surface of the polysilicon layer to p + The contact trench is a recess having a substantially rectangular cross section recessed toward the collector region 17, and is arranged in substantially the same layout as the contact holes 52a and 52b in plan view. This contact trench terminates inside the polysilicon layer. ++ When the mold plug region 142 is formed, boron halide ions may be implanted into the bottom surface of the contact trench.

[0238] The contact trenches connected to the contact holes 52a and 52b function in the same manner as the contact trenches 141 in the active region 41. ++ During the formation of the n-type plug region 142, the boron halide ions are implanted from a direction substantially perpendicular to the front surface of the semiconductor substrate 10 only into the bottom surfaces of the contact trenches that are continuous with the contact holes 52 a and 52 b, and are not implanted into the sidewalls of the contact trenches. This allows portions of the sidewalls of the contact trenches that are not implanted with boron halide ions (e.g., n-type polysilicon portions) to remain. A silicide film, a barrier metal, and a plug may be provided inside the contact trenches, similar to the inside of the contact trench 141.

[0239] The method for manufacturing a semiconductor device according to the seventh embodiment differs from the method for manufacturing semiconductor device 20 according to the first embodiment (see FIG. 5 ) in the following two points. The first difference is that the method for manufacturing a semiconductor device according to the seventh embodiment includes a step of forming contact trenches 141. In the seventh embodiment, after the process of step S3 in FIG. 5 (forming contact holes 9a, 52a, and 52b) and before the process of step S5 in FIG. 5 (implanting boron halide ions), etching is performed using interlayer insulating film 9 and insulating layer 52 as an etching mask or using the etching mask used to form contact holes 9a, 52a, and 52b to form contact trenches 141 in the front surface of semiconductor substrate 10 in the portions exposed to contact holes 9a, 52a, and 52b.

[0240] 5 (forming a resist mask) and step S6 (removing the resist mask) can be omitted. As described above, even if a resist mask is not placed on the IGBT region 21 during the process of step S5 in FIG. 5, boron halide can be ion-implanted only into the bottom surface of the contact trench 141 using only the interlayer insulating film 9 as an ion implantation mask to form p ++ The n-type plug region 142 is formed to form an ohmic contact with the silicide film 143 to be formed in a later step, and the n-type plug region 142 is formed on the side wall of the contact trench 141. + type emitter region 6 and p + 5, a high concentration of halogen elements remains in the entire surface of the interlayer insulating film 9 and the insulating layer 52, but the subsequent process of step S8 in FIG.

[0241] 5, a silicide reaction occurs between the Ti film 11 and the semiconductor substrate 10 on the inner wall of the contact trench 141, and a silicide film 143 having a certain thickness is formed along the inner wall of the contact trench 141. That is, by the processing of step S10 in FIG. 5, the position of the inner wall of the contact trench 141 (the boundary between the semiconductor substrate 10 and the silicide film 143) is shifted to the trench 2 side and the p +The mold moves to the collector region 17 side, but during the processing of step S7 in FIG. ++ The mold plug region 142 is also diffused and widened. ++ The width of the mold plug region 142 may be approximately the same as the width of the bottom surface of the contact trench 141 in both the first direction X (short direction) and the second direction Y (longitudinal direction), or may be slightly narrower or slightly wider than the width of the bottom surface of the contact trench 141.

[0242] The semiconductor device 140 according to the seventh embodiment can be mounted on the semiconductor module 120 according to the fifth embodiment (see FIG. 34) by a general assembly process.

[0243] The method for manufacturing the semiconductor device according to the sixth embodiment may be applied to the method for manufacturing the semiconductor device 140 according to the seventh embodiment, and the p-type impurity ion-implanted in the process of step S5 of FIG. 5 may be boron (B) instead of boron halide.

[0244] In the method for manufacturing the semiconductor device 140 according to the seventh embodiment, the n + A part of the p-type emitter region 6 and the p-type anode region of the FWD region 22 is covered with a resist mask, and p ++ Alternatively, the mold plug region 142 may not be formed. In the method for manufacturing the semiconductor device 140 according to the seventh embodiment, as in the method for manufacturing the semiconductor device according to the second embodiment (see FIGS. 20 to 22), the p ++ A resist mask may also be placed on the interlayer insulating film 9 adjacent to the bottom surface of the contact hole 9 a where the mold plug region 142 is formed.

[0245] As described above, according to the seventh embodiment, p is implanted only into the bottom surface of the contact trench by ion implantation from a direction substantially perpendicular to the front surface of the semiconductor substrate. ++ A p-type plug region can be formed on the sidewall of the contact trench. ++ Therefore, a resist mask is not placed in the IGBT region, and only the interlayer insulating film is used as an ion implantation mask, and p-type plug regions are formed over the entire bottom surface of the contact hole with high positional accuracy. ++At this time, a resist mask is used to form the n-type plug region of the IGBT region. + In the p-type emitter region and the p-type anode region of the FWD region, ++ It is also possible to prevent the formation of a mold plug region. After that, by actively removing the interlayer insulating film and the surface layer of the insulating layer, the same effects as those of the first, third, fourth and sixth embodiments can be obtained.

[0246] (Details of Eighth Embodiment) A semiconductor device according to an eighth embodiment that solves the above-described problems will be described below. FIG. 43 is a plan view showing a layout of a semiconductor device according to the eighth embodiment as viewed from the front surface side of a semiconductor substrate. FIG. 43 corresponds to the portion surrounded by rectangular frame A in FIG. 1. FIGS. 44A and 45 are cross-sectional views showing cross-sectional structures taken along line E1-E1' and line E2-E2' in FIG. 43, respectively. FIGS. 44B and 44C are cross-sectional views showing another example of the cross-sectional structure taken along line E1-E1' in FIG. 43. The structure of a semiconductor device 150 according to the eighth embodiment, excluding the portions shown in FIGS. 43, 44A, 44B, 44C, and 45, may be similar to that of the semiconductor device 20 according to the first embodiment (see FIGS. 1 to 4, 16A, and 16B).

[0247] The semiconductor device 150 according to the eighth embodiment differs from the semiconductor device 20 according to the first embodiment in that a recess 9e is provided in the upper surface of the interlayer insulating film 9 in the FWD region 22, located directly above the dummy trench 2b. The recess 9e in the upper surface of the interlayer insulating film 9 may be a contact hole penetrating the interlayer insulating film 9 in the depth direction Z. That is, when the depth of the recess 9e is equal to the thickness of the interlayer insulating film 9 above the dummy trench 2b ( FIG. 44A ), the recess 9e penetrates the interlayer insulating film 9 in the depth direction Z to become a contact hole, and the front surface electrode contacts the gate electrode 4 (dummy gate electrode) inside the recess 9e. When the depth of the recess 9e is shallower than the thickness of the interlayer insulating film 9 above the dummy trench 2b, the recess 9e has a recessed shape, and the front surface electrode does not contact the gate electrode 4 even within the recess 9e.

[0248] The recess 9e having a recessed shape includes not only a case in which the depth of the recess 9e is shallower than the thickness of the interlayer insulating film 9 on the front surface of the semiconductor substrate 10 ( FIG. 44C ), but also a case in which the depth of the recess 9e is equal to or greater than the thickness of the interlayer insulating film 9 on the front surface of the semiconductor substrate 10, but the thickness of the interlayer insulating film 9 is locally thicker above the trench 2, so that the bottom surface of the recess 9e does not reach the upper surface of the gate electrode 4 inside the dummy trench 2b ( FIG. 44B ). For example, the upper surface of the gate electrode 4 (the surface on the front electrode 15 side) is recessed toward the back electrode 19 from the front surface of the semiconductor substrate 10 and is located inside the trench 2, and the interlayer insulating film 9 (e.g., HTO film 61) is embedded on the gate electrode 4 inside the trench 2, so that the thickness of the interlayer insulating film 9 can be locally thickened above the trench 2 while maintaining the flatness of the upper surface of the interlayer insulating film 9. Alternatively, the recess 9e also has a hollow shape in a similar case where the lower surface of the interlayer insulating film 9 has substantially the same depth position above the trench 2 and above the mesa (between adjacent trenches 2), but the cross-sectional shape of the upper surface of the interlayer insulating film 9 above the trench 2 is convex upward in a direction away from the front surface of the semiconductor substrate 10, so that a recess 9e having substantially the same depth as the contact hole 9a does not contact the dummy gate electrode 4. Therefore, the depth of the recess 9e may be equal to or greater than the thickness of the interlayer insulating film 9 on the front surface of the semiconductor substrate 10, or may be less than the thickness of the interlayer insulating film 9 on the front surface of the semiconductor substrate 10 (and may even be less than the thickness of the BPSG 62).

[0249] 44B and 44C are similar to the semiconductor device 150 shown in FIG. 44A except that the barrier metal 13 does not contact the semiconductor substrate 10 within the recess 9e, and therefore the barrier metal 13 is not silicided within the recess 9e (i.e., no silicide film 11a is formed on the bottom surface of the recess 9e). Here, an example will be described in which the depth of the recess 9e shown in FIG. 44A is equal to the thickness of the interlayer insulating film 9 on the front surface of the semiconductor substrate 10, and the recess 9e forms a contact hole. In other words, in this case, the thickness of the interlayer insulating film 9 is approximately constant across the entire front surface of the semiconductor substrate 10. The interlayer insulating film 9 is provided with contact holes (first contact holes) 9a that penetrate the interlayer insulating film 9 in the depth direction Z directly above the trenches 2 adjacent to each other in the active region 41 (IGBT region 21, FWD region 22), and recesses 9e that form contact holes (second contact holes) that penetrate the interlayer insulating film 9 in the depth direction Z directly above the dummy trenches 2b in the FWD region 22.

[0250] The structure of the contact hole (hereinafter referred to as the on-mesa contact hole) 9a located directly above the space between the adjacent trenches 2 is the same as that of the first embodiment. That is, the on-mesa contact hole 9a extends linearly between the adjacent trenches 2 in the longitudinal direction of the trench 2 (here, the second direction Y), and terminates within the active region 41. The layer structure of the front surface electrode embedded inside the on-mesa contact hole 9a is the same as that of the first embodiment. The recess 9e is p ++ The recess 9e is formed on the upper surface of the interlayer insulating film 9 before forming a resist mask 151 (see FIG. 46) used as an ion implantation mask for forming the mold plug region 8. For example, if the depth and width in the first direction X of the recess 9e are the same as the depth and width in the first direction X of the on-mesa contact hole 9a, respectively, the recess 9e can be formed simultaneously with the on-mesa contact hole 9a. Hereinafter, the recess 9e located directly above the dummy trench 2b and forming a contact hole in the interlayer insulating film 9 will be referred to as the on-dummy trench contact hole 9e.

[0251] The on-dummy-trench contact holes 9e are located more inward in the second direction Y than the ends of the on-mesa contact holes 9a (toward the center of the on-mesa contact holes 9a in the second direction Y). The on-dummy-trench contact holes 9e are located away from the contact holes 52a located directly above the longitudinal ends of the dummy trenches 2b ( FIG. 43 ). The on-dummy-trench contact holes 9e may be scattered in the second direction Y or may extend linearly in the second direction Y. In another example, the on-dummy-trench contact holes 9e may be connected to the contact holes 52a located directly above the longitudinal ends of the dummy trenches 2b. In this case, one or more on-dummy-trench contact holes 9e may terminate closer to the chip edge than the ends of the on-mesa contact holes 9a in the second direction Y, or may terminate within the edge termination region 42.

[0252] When the over-dummy trench contact holes 9e are scattered in the second direction Y, the over-dummy trench contact holes 9e directly above different dummy trenches 2b may or may not face each other in the first direction X. The multiple over-dummy trench contact holes 9e directly above the same dummy trench 2b may be scattered so as to be located on the same straight line parallel to the second direction Y and passing through approximately the center of the dummy trench 2b in the first direction X. Furthermore, the multiple over-dummy trench contact holes 9e directly above the same dummy trench 2b may be scattered so as to be alternately arranged in the second direction Y at positions close to one of the over-mesa contact holes 9a adjacent to each other on both sides of the dummy trench 2b in the first direction X and at positions close to the other over-mesa contact hole 9a.

[0253] In addition, when the on-dummy trench contact holes 9e are scattered in the second direction Y, each on-dummy trench contact hole 9e may be separated from the on-mesa contact hole 9a, or may be coupled to one or both of the on-mesa contact holes 9a adjacent to each other on both sides of the dummy trench 2b in the first direction X. In other words, each on-dummy trench contact hole 9e scattered in the second direction Y directly above the same dummy trench 2b may be coupled to, for example, only one of the on-mesa contact holes 9a adjacent to each other on both sides of the dummy trench 2b in the first direction X.

[0254] Alternatively, when the over-dummy trench contact holes 9e are scattered in the second direction Y, for example, the multiple over-dummy trench contact holes 9e immediately above the same dummy trench 2b may include a mixture of over-dummy trench contact holes 9e connected to one of the over-mesa contact holes 9a adjacent to each other on both sides of the dummy trench 2b in the first direction X (e.g., arranged alternately in the second direction Y). In this case, the over-dummy trench contact holes 9e may be arranged close to the over-mesa contact holes 9a to which they are connected.

[0255] Alternatively, for example, the on-dummy-trench contact hole 9 e may penetrate the interlayer insulating film 9 in the first direction X and be coupled to both of the on-mesa contact holes 9 a adjacent to each other on both sides of the dummy trench 2 b in the first direction X. That is, in this case, the on-dummy-trench contact holes 9 e extend in a stripe pattern in the first direction X in the interlayer insulating film 9 in the FWD region 22, and the on-dummy-trench contact holes 9 e and the on-mesa contact holes 9 a form a contact hole with a lattice-like planar shape. The interlayer insulating film 9 is arranged in a matrix shape surrounded by the contact holes with the lattice-like planar shape.

[0256] If the opening pattern of the on-mesa contact holes 9 a is adversely affected in a portion close to the on-dummy-trench contact holes 9 e, the area between adjacent trenches 2 where the opening pattern of the on-mesa contact holes 9 a is adversely affected may be covered with the interlayer insulating film 9. In this case, the on-mesa contact holes 9 a extend linearly in the second direction Y while being partially separated. The opening pattern of the on-mesa contact holes 9 a is adversely affected, for example, when the width of the interlayer insulating film 9 in the first direction X narrows in a portion sandwiched between the on-dummy-trench contact holes 9 e and the on-mesa contact holes 9 a in the first direction X, making it impossible to partially maintain the opening pattern of the on-mesa contact holes 9 a.

[0257] The gate electrode 4 (dummy gate electrode) inside the dummy trench 2b is electrically connected to the surface electrode 15 via the dummy-trench contact hole 9e. The layer structure of the front surface electrode embedded inside the dummy-trench contact hole 9e is, for example, the same as that inside the mesa contact hole 9a ( FIG. 44 ). That is, a silicide film 11a, a barrier metal 13 (Ti film 11, TiN film 12), and a plug 14 are provided inside the dummy-trench contact hole 9e. The Ti film 11 is provided along the sidewall of the dummy-trench contact hole 9e (the side surface of the interlayer insulating film 9).

[0258] A silicide film 11a is provided on the entire surface of the gate electrode 4 (the bottom surface of the contact hole 9a) inside the dummy-trench contact hole 9e. A TiN film 12 is provided on and along the surfaces of the Ti film 11 and the silicide film 11a inside the dummy-trench contact hole 9e. The Ti film 11 and the TiN film 12 may extend from the inner wall of the mesa-top contact hole 9a to the inner wall of the dummy-trench contact hole 9e. A plug 14 is buried on the TiN film 12 inside the dummy-trench contact hole 9e, and a surface electrode 15 is provided on the plug 14.

[0259] The gate electrode 4 is covered with the interlayer insulating film 9 in the portion directly above the dummy trench 2b other than the on-dummy-trench contact hole 9e, as in the first embodiment. On the upper surface of the interlayer insulating film 9, a barrier metal 13 (Ti film 11, TiN film 12) extends from the inside of the on-mesa contact hole 9a and the on-dummy-trench contact hole 9e, and a surface electrode 15 is provided on the barrier metal 13 (TiN film 12) ( FIG. 45 ). A plug 14 may extend from the inside of the on-mesa contact hole 9a and the on-dummy-trench contact hole 9e between the surface electrode 15 and the TiN film 12 on the upper surface of the interlayer insulating film 9 (see FIG. 16B ).

[0260] By providing the contact hole 9e on the dummy trench in the FWD region 22, as will be described later, ++ This improves the adhesion of the resist mask 151 (see FIG. 46 ) used as an ion implantation mask for forming the mold plug region 8. Furthermore, by electrically connecting the gate electrode 4 (dummy gate electrode) inside the dummy trench 2 b to the surface electrode 15 via the over-dummy-trench contact hole 9 e, the potential of the dummy gate electrode can be stabilized over the entire FWD region 22, compared to when the dummy gate electrode is electrically connected to the surface electrode 15 only at the end of the dummy trench 2 b via the contact hole 52 a. Note that when the over-dummy-trench contact hole 9 e is provided, the contact hole 52 a does not necessarily have to be provided at the end of the dummy trench 2 b.

[0261] The semiconductor device 150 according to the eighth embodiment may have a portion where the halogen element concentration is maximum at an upper corner 9 d of the interlayer insulating film 9, as in the semiconductor device 70 according to the second embodiment (see FIG. 17 ). That is, in this case, in the manufacturing method of the semiconductor device according to the eighth embodiment described later, during the process of step S25 in FIG. 18 (ion implantation 72 of boron halide), the upper corner 9 d of the interlayer insulating film 9 is exposed in the opening 71 a of the resist mask 71 in the IGBT region 21 (see FIGS. 20 and 21 ) and the opening 151 a of the resist mask 151 in the FWD region 22.

[0262] The semiconductor device 80, 90 according to the third embodiment (see FIGS. 23 and 24) may be applied to the semiconductor device 150 according to the eighth embodiment, and the barrier metal 13 may be provided only on the sidewalls of the on-mesa contact holes 9a and the on-dummy trench contact holes 9e, or a surface electrode 15 may be embedded on the barrier metal 13 inside the on-mesa contact holes 9a and the on-dummy trench contact holes 9e without providing a plug. The semiconductor device 100 according to the fourth embodiment (see FIG. 25) may be applied to the semiconductor device 150 according to the eighth embodiment, and a barrier metal may be provided between the surface electrode 15 and the plug 14.

[0263] The semiconductor device 140 according to the seventh embodiment (see FIGS. 40 to 42) may be applied to the semiconductor device 150 according to the eighth embodiment, and contact trenches may be provided that are connected to the on-mesa contact hole 9a in the interlayer insulating film 9 and the contact holes 52a and 52b in the insulating layer 52. A contact trench may be provided that is connected to the on-dummy trench contact hole 9e. The layer structure of the contact trench connected to the on-dummy trench contact hole 9e and the front surface electrode embedded in the contact trench is the same as, for example, the inside of the contact trench connected to the contact hole 52a in the insulating layer 52.

[0264] FIG. 46 is a plan view showing a state during the manufacturing of a semiconductor device according to the eighth embodiment. FIGS. 47A and 48 are cross-sectional views showing cross-sectional structures taken along the cutting lines E3-E3′ and E4-E4′ in FIG. 46, respectively. FIGS. 47B and 47C are cross-sectional views showing another example of the cross-sectional structure taken along the cutting lines E3-E3′ in FIG. 46. FIGS. 47A, 47B, 47C, and 48 show the cross-sectional structures shown in FIGS. 44A, 44B, 44C, and 45, respectively, during the formation of the cross-sectional structures. The manufacturing method of the semiconductor device according to the eighth embodiment differs from the manufacturing method of the semiconductor device according to the second embodiment (see FIG. 18) in the following two points. The first difference is that in the process of step S23 in FIG. 18 (forming contact holes), the mask pattern is appropriately changed to form the on-mesa contact holes 9a and the on-dummy trench contact holes 9e simultaneously.

[0265] The second difference is the process of step S24 in FIG. ++ In the second embodiment, when the resist mask 151 is used to cover the entire upper surface of the interlayer insulating film 9 in the FWD region 22, the resist mask 151 has an opening pattern formed in stripes extending in the second direction Y, and the entire area of ​​the on-mesa contact hole 9a is exposed in the opening 151a of the resist mask 151 (FIG. 46). In the IGBT region 21, the entire upper surface of the interlayer insulating film 9 may be covered with the resist mask 71 (see FIGS. 20, 21, and 22), as in the second embodiment. The upper corner portion 9d of the interlayer insulating film 9 may be exposed in the opening 71a, 151a of the resist masks 71, 151.

[0266] Resist mask 151 covers the entire upper surface of interlayer insulating film 9. Because adhesion between the resist and interlayer insulating film 9 is low, if a resist mask is formed only on the upper surface of interlayer insulating film 9 as in FWD region 22, there is a risk that the resist mask may slide or fall over on the upper surface of interlayer insulating film 9. In the eighth embodiment, resist mask 151 covers the entire upper surface of interlayer insulating film 9 in FWD region 22, is embedded in over-dummy trench contact hole 9e, and is in contact with gate electrode 4 inside dummy trench 2b at the bottom of over-dummy trench contact hole 9e ( FIGS. 47A and 48 ).

[0267] Since the adhesion between the resist and polysilicon (gate electrode 4) is high, the adhesion of the resist mask 151 can be improved. Also, the p-type anode region (p-type base region 5) is not covered with the resist mask 151. Therefore, for example, in order to improve the adhesion of the resist mask, a part of the p-type anode region is brought into contact with the resist mask, and p is formed at the contact portion. ++ Since the mold plug region 8 is not formed, the p ++ This is useful when it is not desirable for the forward voltage Vf to be higher than when the mold plug region 8 is extended (for example, for lower switching frequencies or for use in resonant circuits).

[0268] Also, a resist mask 151 is used to form a p-type anode region (p++ Since the p-type anode region 22 (the region where the p-type plug region 8 is formed) is not covered, the degree of freedom in adjusting the characteristics of the FWD region 22 increases. A portion of the p-type anode region may be covered with the resist mask 151. That is, because the adhesion between the resist and Si is high, the adhesion of the resist mask may be improved by bringing the resist mask 151 into contact with a portion of the p-type anode region within a range in which predetermined characteristics are ensured in the FWD region 22. In this case, for example, the resist masks 151 extending in a stripe shape in the second direction Y in the FWD region 22 and adjacent to each other in the first direction X are connected in an H-shape or a ladder-like shape by the resist selectively placed in the on-mesa contact holes 9 a.

[0269] A dummy trench contact hole (not shown) located directly above the dummy trench 2 b may be provided in the interlayer insulating film 9 in the IGBT region 21. For example, the dummy trench contact hole in the IGBT region 21 is oriented in the first direction X as follows: ++ 18. The contact holes on the dummy trenches of the IGBT region 21 are formed in positions facing the die plug region 8, and are filled with a resist mask 71 (see FIG. 20) during the process of step S24 of FIG. 18. Alternatively, the contact holes on the dummy trenches of the IGBT region 21 are formed in the n-axis direction in the first direction X. + The dummy trench contact holes 9e are formed in a position facing the emitter region 6, and may be filled with a part of the resist mask 71 (see FIG. 20) formed in a lattice-like planar shape as in the second embodiment, or a part of the resist mask 63 (see FIG. 7) extending in stripes in the first direction X as in the first embodiment. Even when the dummy trench contact holes are provided in the IGBT region 21, the same effect as that obtained by providing the dummy trench contact holes 9e in the FWD region 22 can be obtained.

[0270] The semiconductor device 150 according to the eighth embodiment can be mounted on the semiconductor module 120 according to the fifth embodiment (see FIG. 34) by a general assembly process.

[0271] The semiconductor device manufacturing method according to the first embodiment (see FIG. 5 ) may be applied to the semiconductor device manufacturing method according to the eighth embodiment, and in the process of step S8 of FIG. 5 , a surface layer 9 c (see FIG. 11 ) containing a high concentration of halogen elements in the interlayer insulating film 9 and the insulating layer 52 may be removed. In this case, for example, in the process of step S4 of FIG. 5 , a resist mask may be formed in a stripe shape extending in the first direction X perpendicular to the longitudinal direction of the contact hole (here, the second direction Y) on the semiconductor substrate 10, so that the exposed portion of the interlayer insulating film 9 becomes large (see, for example, FIG. 7 ). By providing the dummy trench contact hole 9 e, the adhesion of the resist mask can be improved. The semiconductor device manufacturing method according to the sixth embodiment may be applied to the semiconductor device manufacturing method according to the eighth embodiment, and boron (B) may be used as the p-type impurity ion-implanted in the process of step S5 of FIG. 5 (ion implantation of boron halide).

[0272] The above-described method for manufacturing a semiconductor device according to the eighth embodiment has been described taking as an example a case in which the thickness of the interlayer insulating film 9 is substantially constant over the entire front surface of the semiconductor substrate 10, the depth of the recess 9 e is equal to the thickness of the interlayer insulating film 9 on the front surface of the semiconductor substrate 10, and the recess 9 e forms a contact hole, but the method is also applicable to a case in which the thickness of the interlayer insulating film 9 differs above the trench 2 and above the mesa but the recess 9 e forms a contact hole (i.e., a case in which the depth of the recess 9 e is different from the depth of the on-mesa contact hole 9 a but the recess 9 e reaches the dummy gate electrode 4). Furthermore, the widths of the recess 9 e and the on-mesa contact hole 9 a may be the same or different.

[0273] Furthermore, as described above, instead of the dummy trench contact holes 9e (recesses 9e forming contact holes), recesses 9e having a depression shape that does not penetrate the interlayer insulating film 9 may be formed ( FIGS. 47B and 47C ). That is, this may apply to the case where the interlayer insulating film 9 also fills the gate electrode 4 inside the trench 2 and reaches deeper than the position of the upper surface of the mesa (the front surface of the semiconductor substrate 10 between adjacent trenches 2) ( FIG. 47B ), or the case where the recesses 9e are formed shallower than the depth of the on-mesa contact holes 9a ( FIG. 47C ). In this case, the resist mask 151 does not contact the gate electrode 4 because the bottom of the recesses 9e does not reach the gate electrode 4. However, the resist mask 151 is also embedded in the recesses 9e and is caught on the step between the upper surface of the interlayer insulating film 9 and the bottom surface of the recesses 9e, thereby preventing the resist mask 151 from sliding or tipping over on the upper surface of the interlayer insulating film 9. Therefore, even in the recess 9e having a recessed shape, it is possible to improve the adhesion of the resist mask 151. Note that, even in the recess 9e having a recessed shape, the widths of the recess 9e and the on-mesa contact hole 9a may be set appropriately and may be the same or different.

[0274] As described above, according to the eighth embodiment, it is possible to obtain the same effects as those of the first to fourth, sixth and seventh embodiments. Furthermore, according to the eighth embodiment, by providing a recessed portion having a depression shape located immediately above the dummy trench or a recessed portion serving as a contact hole (a contact hole above the dummy trench), it is possible to obtain p ++ The adhesion of the resist mask used for ion implantation to form the mold plug region can be improved.

[0275] (Details of the Ninth Embodiment) A method for manufacturing a semiconductor device according to a ninth embodiment that solves the above-mentioned problems will be described below. Fig. 49 is a characteristic diagram showing the distribution of halogen element concentration (here, fluorine concentration) in the depth direction of an interlayer insulating film during the manufacturing of a semiconductor device according to the ninth embodiment. The manufacturing method for a semiconductor device according to the ninth embodiment is the same as the manufacturing method for a semiconductor device according to the first embodiment (see Fig. 5), except that the halogen element concentration in the interlayer insulating film 9 is 5 x 10 20 / cm3 Below 1 × 10, preferably 20 / cm 3 Less than 1×10, more preferably 1×10 19 / cm 3 The portion at the depth position below is exposed to form a new outermost surface (upper surface) of the interlayer insulating film 9.

[0276] In the ninth embodiment, a halogen element concentration distribution in the depth direction Z in the interlayer insulating film 9 after the processing of step S5 or step S7 in Fig. 5 (ion implantation or activation and diffusion of boron halide) is obtained by a general method. The halogen element concentration distribution in the depth direction Z in the interlayer insulating film 9 may be measured during the manufacturing of the semiconductor device, or may be obtained in advance from a sample corresponding to a state during the manufacturing of the semiconductor device or from a simulation. In the halogen element concentration distribution in the depth direction Z in the interlayer insulating film 9 after the processing of step S5 or step S7 in Fig. 5, the halogen element concentration increases with increasing depth from the outermost surface (=0 nm) of the interlayer insulating film 9, reaching a maximum concentration, and decreases with increasing depth from the depth position of the maximum concentration (Fig. 49).

[0277] Step S8 in FIG. 5 is performed for a processing time (etching time and polishing time) appropriately adjusted based on the halogen element concentration distribution in the depth direction Z in the interlayer insulating film 9, and the halogen element concentration is reduced to at least 5×10 from the outermost surface of the interlayer insulating film 9. 20 / cm 3 The surface layer 9c is removed to a depth position where the halogen element concentration per unit volume of the interlayer insulating film 9 is about 1×10 19 / cm 3 For example, when the surface layer 9c-1 (9c) from the outermost surface of the interlayer insulating film 9 to the depth position d1 is removed, the halogen element concentration on the upper surface of the interlayer insulating film 9 becomes 1×10 20 / cm 3 The halogen element concentration on the upper surface of the interlayer insulating film 9 is set to about 1×10 19 / cm 3To achieve a depth of approximately 100 nm or less, it is sufficient to remove the surface layer 9c-2 (9c) from the outermost surface of the interlayer insulating film 9 to at least a depth d2 deeper than the depth d1. FIG. 49 shows the depths d1 and d2 and the surface layers 9c-1 and 9c-2 for the "no heat treatment" sample. The "no heat treatment" sample shows the halogen element concentration distribution after the process of step S5 in FIG. 5. In the process of step S8, the surface layer 9c of the interlayer insulating film 9 may be removed based on the halogen element concentration distribution after the process of step S5. Alternatively, the surface layer 9c of the interlayer insulating film 9 may be removed based on the halogen element concentration after the process of step S7 that is inferred from the halogen element concentration distribution after the process of step S5, or on the actually measured halogen element concentration distribution after the process of step S7.

[0278] For example, if the process of step S8 in FIG. 5 is not performed, as in the manufacturing method of the semiconductor device 220 of the reference example described above (see FIGS. 35 and 36 ), the surface layer of the interlayer insulating film 209 is slightly removed by wet etching in the pretreatment of the process of step S208 (sputtering for forming the barrier metal 213). However, since the pretreatment is short, the halogen element concentration in the new outermost surface (upper surface) of the interlayer insulating film 209 is 1×10 21 / cm 3 In this way, the halogen element concentration on the upper surface of the interlayer insulating film 209 is about 5×10 20 / cm 3 It has been confirmed by the inventors' experiments that if the temperature exceeds 1000 ℃, the barrier metal 213 (Ti film 211) formed on the upper surface of the interlayer insulating film 209 will peel off.

[0279] On the other hand, in the ninth embodiment, the surface layer of the interlayer insulating film 9 is actively removed in the process of step S8 in FIG. 5, so that the halogen element concentration on the upper surface of the interlayer insulating film 9 is 5×10 20 / cm 3 This can prevent the barrier metal 13 (Ti film 11) from peeling off from the upper surface of the interlayer insulating film 9. The halogen element concentration on the upper surface of the interlayer insulating film 9 is further reduced to about 1×10 20 / cm 3 or less, more preferably 1×10 19 / cm 35, the surface layer of the insulating layer 52 is also removed in the same manner as the surface layer of the interlayer insulating film 9, and therefore the halogen element concentration on the upper surface of the insulating layer 52 is also reduced to 5×10 20 / cm 3 It can be made to the following extent.

[0280] The configuration of the semiconductor device according to the ninth embodiment is the same as that of the semiconductor device 20 according to the first embodiment (see FIGS. 1 to 4, 16A, and 16B). 20 / cm 3 By lowering the concentration of halogen elements per unit volume of the interlayer insulating film 9 to about 1×10 19 / cm 3 The local maximum concentration of the halogen element in the interlayer insulating film 9 (peak concentration of the halogen element concentration distribution) can be reduced to, for example, 5×10 20 / cm 3 It will be about the following.

[0281] 5, the halogen element moves in the interlayer insulating film 9 due to the heat treatment in each process after the process of step S8 in FIG. 5, the thermal history during the assembly process, and the manufacturing process. Therefore, the halogen element concentration in the interlayer insulating film 9 becomes 5×10 at a position away from the upper surface of the interlayer insulating film 9 in the depth direction. 20 / cm 3 5 , the halogen element concentration at the upper surface of the interlayer insulating film 9 can be locally higher than the halogen element concentration at the upper surface of the interlayer insulating film 9 within the range of about 1000 to 15000. Furthermore, the lower the halogen element concentration at the upper surface of the interlayer insulating film 9 is by the process of step S8 in FIG. 5 , the more it can be prevented that the halogen element concentration per unit volume of the interlayer insulating film 9 exceeds the above range due to subsequent heat treatment or heat history.

[0282] The integral value obtained by integrating the halogen element concentration of the interlayer insulating film 9 in the depth direction Z over the thickness of the interlayer insulating film 9 (the thickness t1 of the product after the process in step S8 of FIG. 5) is, for example, 1×10 14 / cm 25. This allows the halogen element to be contained in the interlayer insulating film 9 at a concentration of 1×10 or less per unit volume of the interlayer insulating film 9 even if the halogen element moves in the interlayer insulating film 9 due to the heat treatment or thermal history after the process in step S8 of FIG. 19 / cm 3 The thickness t1 of the interlayer insulating film 9 in the finished product may be, for example, about 700 nm.

[0283] The semiconductor device 80, 90 (see FIGS. 23 and 24) according to the third embodiment may be applied to the semiconductor device according to the ninth embodiment, and the barrier metal 13 may be provided only on the inner wall of the contact hole 9 a, or a plug may not be provided and the surface electrode 15 may be embedded inside the contact hole 9 a on the barrier metal 13. The semiconductor device 100 (see FIG. 25) according to the fourth embodiment may be applied to the semiconductor device according to the ninth embodiment, and a barrier metal 106 may be provided between the surface electrode 15 and the plug 14.

[0284] The semiconductor device 140 according to the seventh embodiment (see FIGS. 40 to 42) may be applied to the semiconductor device according to the ninth embodiment, and contact trenches may be provided that are coupled to the contact hole 9a in the interlayer insulating film 9 and the contact holes 52a, 52b in the insulating layer 52. The semiconductor device 150 according to the eighth embodiment (see FIGS. 43 to 44) may be applied to the semiconductor device according to the ninth embodiment, and a contact hole (a contact hole on the dummy trench) located directly above the dummy trench 2b may be provided in the interlayer insulating film 9 in the active region 41.

[0285] Moreover, the semiconductor device according to the ninth embodiment can be mounted on the semiconductor module 120 according to the fifth embodiment (see FIG. 34) by a general assembly process.

[0286] The method for manufacturing a semiconductor device according to the sixth embodiment may be applied to the method for manufacturing a semiconductor device according to the ninth embodiment, and the p-type impurity ions implanted in step S5 (ion implantation of boron halide) in Fig. 5 may be boron (B) instead of boron halide. In this case, as in the sixth embodiment, the boron concentration in the new outermost surface (upper surface) of the interlayer insulating film 9 may be increased to 1.0 x 10 20 / cm 3 less than 1.0 x 10 19 / cm 3 The following would suffice.

[0287] As described above, according to the ninth embodiment, the surface layer of the interlayer insulating film is removed for a treatment time that is appropriately adjusted based on the halogen element concentration distribution in the depth direction Z in the interlayer insulating film, and the halogen element concentration in the interlayer insulating film is reduced to 5×10 20 / cm 3 By exposing the portion at a predetermined depth where the concentration of halogen elements per unit volume of the interlayer insulating film 9 is about 1×10 or less, and making it the new outermost surface, the halogen element concentration per unit volume of the interlayer insulating film 9 is reduced to 1×10 19 / cm 3 The same effects as those of the first, third, fourth, sixth to eighth embodiments can be obtained.

[0288] (Details of Tenth Embodiment) A method for manufacturing a semiconductor device according to a tenth embodiment that solves the above-mentioned problems will be described below. Fig. 50 is a flowchart outlining a method for manufacturing a semiconductor device according to the tenth embodiment. Figs. 51 to 53 are cross-sectional views showing a state during the manufacturing of the semiconductor device according to the tenth embodiment. Fig. 54 is a cross-sectional view showing an example of the structure of the semiconductor device according to the tenth embodiment.

[0289] The manufacturing method of the semiconductor device according to the tenth embodiment (FIG. 50) differs from the manufacturing method of the semiconductor device according to the ninth embodiment in that it includes a step of reducing the halogen element concentration in the interlayer insulating film 9 by heat treatment. The halogen element concentration (here, fluorine concentration) distribution in the depth direction Z of the interlayer insulating film 9 during the manufacturing of the semiconductor device according to the tenth embodiment is shown in FIG. 49 together with the halogen element concentration distribution in the depth direction Z of the interlayer insulating film 9 during the manufacturing of the semiconductor device according to the ninth embodiment (sample without heat treatment).

[0290] Specifically, first, similarly to the processes in steps S1 to S7 in the first embodiment (see FIG. 5), ++ The following steps are performed in order: formation of each part other than the mold plug region 8 (step S61), formation of the interlayer insulating film 9 (step S62), formation of the contact hole 9a (step S63, FIG. 6), formation of the resist mask 63 (step S64, FIG. 7), ion implantation of boron halide (step S65, FIGS. 8 and 9), removal of the resist mask 63 (step S66), and annealing for activating and diffusing the impurities (step S67).

[0291] Next, the semiconductor substrate 10 is instantaneously heated by heat treatment (annealing) (step S68, FIG. 51: heat treatment step). The annealing treatment in step S68 releases the halogen elements in the interlayer insulating film 9 to the outside, thereby reducing the halogen element concentration in the surface layer 9f of the interlayer insulating film 9. The inventors' extensive research has confirmed that the higher the temperature of the annealing treatment in step S68, the more the halogen element concentration in the interlayer insulating film 9 can be reduced (see samples other than the "no heat treatment" sample in FIG. 49).

[0292] For example, the inventors have confirmed through extensive research that if the annealing treatment in step S68 is performed at a temperature exceeding 400° C., the Ti film 11 deposited on the surface of the interlayer insulating film 9 will not peel off from the interlayer insulating film 9, even without the treatment in step S69 (removal of the surface layer of the interlayer insulating film 9) described later. The reason for this is that the annealing treatment in step S68 shifts the halogen element concentration distribution in the vicinity of the upper surface of the interlayer insulating film 9 to the low concentration side, and the halogen element concentration on the upper surface of the interlayer insulating film 9 becomes 5×10 20 / cm 3It is estimated that this will be about the following:

[0293] Furthermore, it is presumed that the annealing treatment in step S68 makes it difficult for the halogen elements to move in the interlayer insulating film 9, thereby preventing the halogen element concentration on the upper surface of the interlayer insulating film 9 from increasing again thereafter. On the other hand, the greater the heat quantity in the annealing treatment in step S68, the more likely it is that the characteristics of the semiconductor device will deviate from the design values. For this reason, the annealing treatment in step S68 is performed at an annealing temperature of 400°C or higher at which peeling of the Ti film 11 does not occur and at a temperature of approximately 1200°C or lower at which the interlayer insulating film 9 having good film properties (density, insulating properties) is obtained, and the product (integrated heat quantity) of the annealing temperature [°C] and the annealing time [seconds] is 5×10 3 [°C / sec] or more 1 x 10 6 The annealing process in step S68 can be performed in a shorter time as the annealing temperature is increased.

[0294] 5 in the ninth embodiment, the surface layer of the interlayer insulating film 9 is removed for a processing time appropriately adjusted based on the halogen element concentration distribution in the depth direction Z in the interlayer insulating film 9, and portions of the interlayer insulating film 9 at depth positions d1 and d2 having a predetermined halogen element concentration are exposed to form a new outermost surface of the interlayer insulating film 9 (step S69, FIG. 52). 20 / cm 3 The surface layer 9f of the interlayer insulating film 9 is required to be 5×10 20 / cm 3 A portion where the halogen element concentration is locally higher than the halogen element concentration on the upper surface of the interlayer insulating film 9 may remain within the range of about 1000 to 15000.

[0295] The annealing process in step S68 reduces the halogen element concentration on the upper surface of the interlayer insulating film 9 to 5×10 20 / cm 3 If the halogen element concentration on the upper surface of the interlayer insulating film 9 is reduced to 5×10 or less by the annealing treatment in step S68 or the treatment in step S69, or both, the process of step S69 may be omitted. 20 / cm3 The subsequent process of step S70 (forming the barrier metal 13) can be performed in a state where the temperature is lowered to about 1000 K or less. The annealing process of step S68 and the annealing process of step S67 may be performed simultaneously.

[0296] Thereafter, similar to the processes of steps S9 to S14 in the first embodiment (see FIG. 5), the formation of barrier metal 13 (step S70, FIG. 53), sintering to form silicide film 11a (step S71), formation of plug 14 (step S72), etching back of plug 14 (step S73), formation of surface electrode 15 on the front surface side of semiconductor substrate 10 (step S74), and formation of a structure on the back surface side of semiconductor substrate 10 (step S75) are carried out in this order, thereby completing semiconductor device 160 shown in FIG. 54.

[0297] In the semiconductor device 160 ( FIG. 54 ) according to the tenth embodiment, the integral value obtained by integrating the halogen element concentration in the interlayer insulating film 9 in the depth direction Z by the thickness t1 of the interlayer insulating film 9 in the finished product is lower than that in the semiconductor device according to the ninth embodiment. The annealing treatment in step S68 makes it possible to make the halogen element concentration on the upper surface of the insulating layer 52 approximately the same as the halogen element concentration on the upper surface of the interlayer insulating film 9. The structure of the semiconductor device 160 according to the tenth embodiment, except for the halogen element concentration in the interlayer insulating film 9, may be the same as that of the semiconductor device according to the ninth embodiment.

[0298] As described above, according to the tenth embodiment, the same effects as those of the first, third, fourth, and sixth to eighth embodiments can be obtained. Furthermore, according to the tenth embodiment, the halogen element concentration in the surface layer of the interlayer insulating film can be reduced by discharging the halogen element in the interlayer insulating film to the outside by heat treatment. This makes it possible to shorten the time required to remove the surface layer of the interlayer insulating film. Alternatively, the step of removing the surface layer of the interlayer insulating film can be omitted.

[0299] As described above, the present disclosure is not limited to the above-described embodiments, and various modifications can be made without departing from the spirit of the present disclosure. For example, the present disclosure may be modified by providing a p-type region (the p ++In each of the above-described embodiments, the p-type plug region is exposed by ion implantation of a halide of an impurity (a predetermined conductivity type impurity) that becomes an acceptor. ++ In the present disclosure, the first conductivity type is n-type and the second conductivity type is p-type. ++ In place of the n-type plug region, or in a p-channel IGBT in which the n-type and p-type are interchanged, ions of a halide of an impurity (predetermined conductivity type impurity: for example, phosphorus (P) or arsenic (As)) that becomes a donor are implanted to form an n ++ The same applies to the case where a mold plug region is formed.

[0300] The present disclosure is also applicable to the case where an IGBT or a diode is fabricated instead of an RC-IGBT. The present disclosure is also applicable to the case where a MOSFET (Metal Oxide Semiconductor Field Effect Transistor: a MOS field effect transistor having an insulated gate with a three-layer structure of metal-oxide-semiconductor) is fabricated instead of an IGBT, or to the case where a Schottky barrier diode (SBD) or a merged pin / Schottky diode (MPS) is fabricated instead of a pin (p-intrinsic-n) diode such as an FWD.

[0301] As described above, the semiconductor device and the method for manufacturing the semiconductor device according to the present disclosure are useful for semiconductor devices that have a plug region at the bottom of a contact hole that forms an ohmic contact with a front surface electrode and that has the same width as the contact hole, and are particularly suitable for power semiconductor devices (semiconductor devices that have a relatively large current capacity and that, for example, supply and cut off power to other devices).

[0302] 1n - 2. Dummy trench 2a. Gate trench 2b. Dummy trench 3. Gate insulating film 4. Gate electrode 5. P-type base region 6. N-type base region + Type emitter region 7p + Type contact area 8,142,208 p++ 1. Die plug region 9, 209 Interlayer insulating film 9a, 209a Contact hole in interlayer insulating film 9b, 9c, 209b Surface layer of interlayer insulating film 9d Upper end corner portion of interlayer insulating film 9e Recessed portion having a recessed shape or a recess forming a contact hole (contact hole on dummy trench) 10, 210 Semiconductor substrate 10a Portion of semiconductor substrate exposed to contact hole 11, 81, 101, 104, 211 Ti film 11a, 143, 211a Silicide film 12, 82, 102, 105, 212 TiN film 13, 83, 103, 106, 213 Barrier metal 14, 111, 144, 214 Plug 15, 91, 215 Surface electrode 16 N-type FS layer 17 p + Type collector region 18 n + 19 Back electrode 20, 30, 70, 80, 90, 100, 110, 140, 150, 160, 220 Semiconductor device 21 IGBT region 22 FWD region 31 n-type accumulation region 32 Low carrier lifetime region 41 Active region 42 Edge termination region 51 p + Mold well region 52 Insulating layer 52a, 52b Contact hole in insulating layer 53 Gate runner 54 Gate polysilicon wiring layer 55 Gate metal wiring layer 56 Gate pad 61 HTO film 62 BPSG 63, 71, 151 Resist mask 63a, 71a, 151a, 231a Opening in resist mask 64, 72, 232 Ion implantation 120 Semiconductor module 121 Semiconductor element 122 Laminated substrate 123 Insulating substrate 124 Wiring pattern 125 Conductive plate 126 Metal substrate 127 Case 128, 129 Bonding material 130, 132 Wire 131 External connection terminal 133 Sealing material 141 Contact trench X First direction Y parallel to the front surface of the semiconductor substrate A second direction Z is parallel to the front surface of the semiconductor substrate and perpendicular to the first direction X. d1, d2 are depth positions from the outermost surface of the interlayer insulating film. t1, t201 are thicknesses of the interlayer insulating film as a finished product. t11 are thicknesses of the interlayer insulating film as deposited. t12 are thicknesses of the surface layer of the interlayer insulating film to be removed.

Claims

a first step of forming an element structure on a first main surface side of a semiconductor substrate; a second step of forming an interlayer insulating film on the first main surface of the semiconductor substrate to cover the element structure; a third step of forming a first contact hole that penetrates the interlayer insulating film in the depth direction to expose the semiconductor substrate; an implantation step of ion-implanting a predetermined impurity using the interlayer insulating film as an ion implantation mask to selectively form a diffusion region of a predetermined conductivity type in the portion of the semiconductor substrate exposed in the first contact hole; a removal step of removing a surface layer of the interlayer insulating film to a predetermined thickness after the implantation step; a first film-forming step of forming a barrier metal from the inside of the first contact hole over the upper surface of the interlayer insulating film exposed by the removal step; and a second film-forming step of forming a surface electrode electrically connected to the element structure via the barrier metal, wherein in the removal step, the interlayer insulating film is removed from the upper surface to at least a depth position of the maximum concentration of the predetermined impurity ion-implanted in the implantation step.

2. A method for manufacturing a semiconductor device comprising: a first step of forming an element structure on a first main surface side of a semiconductor substrate; a second step of forming an interlayer insulating film on the first main surface of the semiconductor substrate to cover the element structure; a third step of forming a first contact hole that penetrates the interlayer insulating film in the depth direction to expose the semiconductor substrate; an implantation step of ion-implanting a predetermined impurity to selectively form a diffusion region of a predetermined conductivity type in a portion of the semiconductor substrate exposed in the first contact hole; a first film-forming step of forming a barrier metal from the inside of the first contact hole to an upper surface of the interlayer insulating film after the implantation step; and a second film-forming step of forming a surface electrode electrically connected to the element structure via the barrier metal, wherein the implantation step comprises: a masking step of covering the interlayer insulating film with a mask having an opening in a portion corresponding to a region where the diffusion region is to be formed; a step of ion-implanting the predetermined impurity into the semiconductor substrate through the mask; and a step of removing the mask used in the ion implantation, wherein in the first film-forming step, the barrier metal is formed on the upper surface of the interlayer insulating film exposed by removing the mask.

3. A method for manufacturing a semiconductor device as described in claim 1 or 2, characterized in that it includes a third film formation process in which, after the first film formation process and before the second film formation process, a contact plug is formed on the barrier metal on the upper surface of the interlayer insulating film and the contact plug is embedded on the barrier metal inside the first contact hole, and in the second film formation process, the surface electrode is formed on the contact plug.

4. The method for manufacturing a semiconductor device according to claim 3, further comprising, after the third film formation step and before the second film formation step, a step of partially removing the contact plug to leave it only inside the first contact hole and exposing the barrier metal on the upper surface of the interlayer insulating film, wherein in the second film formation step, the surface electrode is formed from above the contact plug inside the first contact hole to above the barrier metal on the upper surface of the interlayer insulating film.

5. The method for manufacturing a semiconductor device according to claim 3, further comprising, after the third film formation step and before the second film formation step, a step of partially removing the contact plug and the barrier metal to leave them only inside the first contact hole and expose the upper surface of the interlayer insulating film, wherein in the second film formation step, the surface electrode is formed from above the contact plug inside the first contact hole to the upper surface of the interlayer insulating film.

6. A semiconductor device comprising: a first step of forming an element structure on a first main surface side of a semiconductor substrate; a second step of forming an interlayer insulating film on the first main surface of the semiconductor substrate to cover the element structure; a third step of forming a first contact hole penetrating the interlayer insulating film in the depth direction to expose the semiconductor substrate; an implantation step of ion-implanting a predetermined impurity using the interlayer insulating film as an ion implantation mask to selectively form a diffusion region of a predetermined conductivity type in a portion of the semiconductor substrate exposed in the first contact hole; a first film-forming step of forming a barrier metal from the inside of the first contact hole to the upper surface of the interlayer insulating film after the implantation step; and a second film-forming step of forming a surface electrode electrically connected to the element structure via the barrier metal, wherein after the first film-forming step and before the second film-forming step, a first processing step of removing the barrier metal on the upper surface of the interlayer insulating film to expose the upper surface of the interlayer insulating film and leaving the remaining first barrier metal of the barrier metal only inside the first contact hole; a third film formation step of forming a second barrier metal on an upper surface of the interlayer insulating film exposed by the first processing step, wherein the interlayer insulating film is removed from the upper surface to at least a depth position of a maximum concentration of the predetermined impurity ion-implanted in the implantation step.

7. A method for manufacturing a semiconductor device as described in claim 6, characterized in that in the first processing step, the first barrier metal is left at a lower position inside the first contact hole than the height position of the upper surface of the interlayer insulating film exposed in the removal step.

8. The method for manufacturing a semiconductor device according to claim 6, wherein in the third film formation step, the second barrier metal is formed from the same metal as the first barrier metal.

9. The method for manufacturing a semiconductor device according to claim 7, further comprising: after the first film formation step and before the first processing step, a fourth film formation step of forming a contact plug on the barrier metal and filling the inside of the first contact hole with the contact plug; and a second processing step of partially removing the contact plug to expose the barrier metal on the upper surface of the interlayer insulating film and leaving the remaining first contact plug of the contact plug only inside the first contact hole, wherein in the second processing step, the first contact plug is left inside the first contact hole at a position deeper than the upper surface of the interlayer insulating film exposed in the removal step, and in the third film formation step, the second barrier metal is formed from above the first contact plug to over the upper surface of the interlayer insulating film exposed in the removal step.

10. A method for manufacturing a semiconductor device as described in claim 9, characterized in that it includes a fifth film formation process of forming a second contact plug on the second barrier metal after the third film formation process and before the second film formation process, and in the second film formation process, the surface electrode is formed on the second contact plug.

11. The method for manufacturing a semiconductor device according to claim 10, wherein in the fifth film formation step, the second contact plug is formed from the same metal as the first contact plug.

12. The method for manufacturing a semiconductor device according to claim 1, characterized in that the implantation step includes a masking step of forming a mask on the interlayer insulating film, the mask having an opening in a portion corresponding to the region where the diffusion region is to be formed; a step of ion-implanting the predetermined impurity into the semiconductor substrate using the interlayer insulating film and the mask as the ion implantation mask; and a step of removing the mask used in the ion implantation.

13. The method for manufacturing a semiconductor device according to claim 6, characterized in that the implantation step includes: a masking step of forming a mask on the interlayer insulating film, the mask having an opening in a portion corresponding to the region where the diffusion region is to be formed; a step of ion-implanting the predetermined impurity into the semiconductor substrate using the interlayer insulating film and the mask as the ion implantation mask; and a step of removing the mask used in the ion implantation.

14. The method for manufacturing a semiconductor device according to claim 1 or 6, wherein the predetermined impurity is a halide.

15. The method for manufacturing a semiconductor device according to claim 1, 2 or 6, wherein the barrier metal includes a titanium film in contact with the interlayer insulating film.

16. A semiconductor device comprising: an element structure provided on a first main surface side of a semiconductor substrate; an interlayer insulating film provided on the first main surface of the semiconductor substrate and covering the element structure; a first contact hole penetrating the interlayer insulating film in the depth direction to expose the semiconductor substrate; a barrier metal provided from the surface of the semiconductor substrate exposed in the first contact hole to the surface of the interlayer insulating film and electrically connected to the element structure; and a surface electrode electrically connected to the element structure via the barrier metal, wherein the interlayer insulating film locally contains a halogen element, and the concentration of the halogen element per unit volume of the interlayer insulating film is 1×10 19 / cm 3 A semiconductor device characterized by:

17. The semiconductor device according to claim 16, wherein the concentration of the halogen element in the interlayer insulating film is locally maximized in a portion exposed through the first contact hole.

18. The semiconductor device according to claim 17, wherein the interlayer insulating film has a portion where the concentration of the halogen element is maximum at the upper corner portion of the portion exposed to the first contact hole.

19. The maximum concentration of the halogen element in the interlayer insulating film is 5×10 19 / cm 3 18. The semiconductor device according to claim 17, wherein:

20. The semiconductor device according to claim 16, wherein the halogen element is fluorine.

21. The semiconductor device according to claim 16, wherein the barrier metal includes a titanium film in contact with the interlayer insulating film.

22. A method for manufacturing a semiconductor device as described in claim 1, 2 or 6, characterized in that after the third step and before the implantation step, a step of forming a contact trench continuous with the first contact hole in the portion of the semiconductor substrate exposed to the first contact hole is included.

23. A method for manufacturing a semiconductor device according to claim 2, 12 or 13, characterized in that in the first step, a plurality of trenches are formed as the element structure on the first main surface side of the semiconductor substrate, the trenches extending linearly in a direction parallel to the first main surface of the semiconductor substrate, and conductive portions are formed inside the trenches via insulating films; in the third step, the first contact holes are formed, extending linearly in the longitudinal direction of the trenches and exposing the semiconductor substrate between adjacent trenches; after the second step and before the masking step, recesses are formed in the upper surface of the interlayer insulating film above the trenches so as to be positioned more inward than the ends of the first contact holes in the longitudinal direction of the trenches; in the masking step, the first contact holes are exposed in openings in the mask, and the mask is formed so as to fill the recesses with the mask; and in the second film forming step, the surface electrodes electrically connected to the element structure are formed in the first contact holes.

24. The method for manufacturing a semiconductor device described in claim 23, characterized in that the recess is a second contact hole that penetrates the interlayer insulating film in the depth direction to expose the conductive portion, the masking step brings the mask into contact with the conductive portion through the second contact hole, and the second film formation step forms the surface electrode electrically connected to the conductive portion in the second contact hole.

25. The method for manufacturing a semiconductor device according to claim 23, wherein in the third step, the recess is formed simultaneously with the first contact hole.

26. In the removal step, the concentration of halogen elements on the upper surface of the interlayer insulating film is set to 5×10 20 / cm 3 15. The method for manufacturing a semiconductor device according to claim 14, wherein the following steps are performed:

27. In the removal step, the integral value obtained by integrating the concentration of the halogen element in the interlayer insulating film in the depth direction over the remaining thickness of the interlayer insulating film is 1×10 14 / cm 2 15. The method for manufacturing a semiconductor device according to claim 14, wherein the following steps are performed:

28. The method for manufacturing a semiconductor device according to claim 14, further comprising a heat treatment step of heating the semiconductor substrate after the implantation step and before the removal step, wherein the heat treatment step releases halogen elements in the interlayer insulating film to the outside.

29. In the heat treatment step, the concentration of the halogen element on the upper surface of the interlayer insulating film is set to 5×10 20 / cm 3 29. The method for manufacturing a semiconductor device according to claim 28, wherein the following steps are performed:

30. In the heat treatment step, the integral value obtained by integrating the concentration of the halogen element in the interlayer insulating film in the depth direction over the remaining thickness of the interlayer insulating film is 1×10 14 / cm 2 29. The method for manufacturing a semiconductor device according to claim 28, wherein the following steps are performed:

31. A method for manufacturing a semiconductor device according to claim 1 or 6, characterized in that in the removal step, the interlayer insulating film is removed from the top surface to a depth exceeding the depth position of the maximum concentration of the predetermined impurity ion-implanted in the implantation step.

32. A method for manufacturing a semiconductor device as described in claim 2, characterized in that in the third step, the first contact holes are formed so as to extend in a stripe pattern in a direction parallel to the first main surface of the semiconductor substrate, and in the masking step, the mask is formed in a lattice-like planar shape that covers the interlayer insulating film and is scattered in the longitudinal direction of the first contact holes, selectively covering the portions of the semiconductor substrate exposed to the first contact holes.

33. The interlayer insulating film has a portion where the concentration of the halogen element is relatively high, and the local maximum concentration of the halogen element in the interlayer insulating film is 5×10 20 / cm 3 17. The semiconductor device according to claim 16, wherein:

34. The integral value obtained by integrating the concentration of the halogen element in the interlayer insulating film in the depth direction over the thickness of the interlayer insulating film is 1×10 14 / cm 2 17. The semiconductor device according to claim 16, wherein:

35. A semiconductor device according to any one of claims 16 to 19, characterized in that it comprises a diffusion region of a predetermined conductivity type containing the halogen element, the diffusion region being at least as wide as the first contact hole, in a portion of the semiconductor substrate exposed to the first contact hole, and the interlayer insulating film has a portion in which the concentration of the halogen element is at its maximum in a portion facing the diffusion region in a direction parallel to the first main surface of the semiconductor substrate.

36. A semiconductor device according to any one of claims 16 to 19, characterized in that it comprises: a contact trench provided in a portion of the semiconductor substrate exposed to the first contact hole, the contact trench being continuous with the first contact hole; and a diffusion region of a predetermined conductivity type containing the halogen element provided in a portion of the semiconductor substrate exposed at the bottom surface of the contact trench, wherein the diffusion region is not provided in a portion of the semiconductor substrate exposed at the side wall of the contact trench.

37. A semiconductor device according to any one of claims 16 to 19, characterized in that the element structure comprises: a plurality of trenches provided on the first main surface side of the semiconductor substrate and extending linearly in a direction parallel to the first main surface of the semiconductor substrate; and conductive portions provided inside the trenches via insulating films; the first contact holes extend linearly in the longitudinal direction of the trenches to expose the semiconductor substrate between adjacent trenches; and a recess is formed in the upper surface of the interlayer insulating film above the trenches, and the recess is located more inward than the end of the first contact hole in the longitudinal direction of the trench.

38. The semiconductor device described in claim 37, wherein the recess is a second contact hole that penetrates the interlayer insulating film in the depth direction to expose the conductive portion, and the conductive portion and the surface electrode are electrically connected in the second contact hole.

39. The semiconductor device according to claim 37, wherein the first contact hole and the recess are connected in the longitudinal direction of the trench.

40. The semiconductor device according to any one of claims 16 to 19, characterized in that the element structure comprises: a plurality of trenches provided on the first main surface side of the semiconductor substrate and extending linearly in a direction parallel to the first main surface of the semiconductor substrate; conductive portions provided inside the trenches via insulating films; drift regions of a first conductivity type provided inside the semiconductor substrate; and anode regions of a second conductivity type provided between adjacent trenches and between the first main surface of the semiconductor substrate and the drift region; the first contact holes extend linearly in the longitudinal direction of the trenches to expose the semiconductor substrate between the adjacent trenches; a diffusion region of the second conductivity type having a higher impurity concentration than the anode region and containing the halogen element is provided between the first main surface of the semiconductor substrate and the anode region in the portion of the semiconductor substrate exposed in the first contact holes; a recess in the upper surface of the interlayer insulating film above the trenches, the recess being located inside the end of the first contact hole in the longitudinal direction of the trench.

41. The semiconductor device according to claim 16, further comprising a contact plug provided on the barrier metal inside the first contact hole and interposed between the barrier metal and the surface electrode.

42. The semiconductor device according to claim 41, wherein the contact plug extends from inside the first contact hole between the upper surface of the interlayer insulating film and the surface electrode.

43. The semiconductor device according to claim 37, further comprising a contact plug provided on the barrier metal inside the recess and interposed between the barrier metal and the surface electrode.

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