Common ICCM SRAM for multi-channel DDR phys

Abstract

A system implemented in a system on chip (SoC) includes a shared multi-port static random-access memory (SRAM) located in a memory controller of the SoC. The SoC includes a number of memory channels that are placed substantially equidistant from the SRAM in the memory controller. Computer instructions are stored in the shared SRAM. The number of memory channels access the instructions stored in the shared SRAM. More than one memory channel may access the instructions concurrently. The instructions can include common processing images for the system. Common processing images may include firmware of the SoC, mission mode firmware, and / or memory address mappings. The shared SRAM meets requirements of the microcontroller associated with a memory channel. The amount of SRAM is reduced by a factor of the number of channels in the system compared to an instruction SRAM placed in each memory channel.

Description

GOOGLE-4189COMMON ICCM SRAM FOR MULTI-CHANNEL DDR PHYsBACKGROUND

[0001] Mobile computing devices, such as smart phones, tablets, personal digital assistants (PDAs) and the like allow a user to receive computer-related services from any location. These devices contain many components that require electrical power to function. Mobile devices can use batteries to store electrical energy in a portable form and allow the device to operate when away from a fixed power source. As the device operates, the electrical energy stored in the battery is depleted leading eventually to discharge of the battery. Once discharged, the battery must be recharged, or the device will shut down due to lack of power.

[0002] Research and development efforts have been directed to power conservation and battery architecture to maximize battery life through power conservation or increased battery capacity. Increasing battery capacity may require increasing the size of the battery, which, in turn, typically increases the size of the device housing the battery. However, in product design, limiting size and weight are common goals.SUMMARY

[0003] Technology described in this disclosure provides methods and systems for implementing a shared instruction closely coupled memory (ICCM) in a multi-channel device.

[0004] A system on chip (SoC) design includes providing a common shared static random-access memory (SRAM) serving as an ICCM. The shared ICCM stores instructions that are accessible by memory channels in the device. The shared ICCM includes a multi-port SRAM that allows concurrent access to the shared ICCM from multiple memory channels. The shared ICCM is positioned on the SoC to be equidistant from each memory channel. The ICCM may store a common processing image used by each memory channel. For example, the common processing image may include firmware for the SoC device. By implementing a single, shared ICCM SRAM on the device, the number of SRAMs required for storing instructions is reduced by a factor of the number of memory channels.

[0005] The described technology includes a compute device having a compute processor, a memory in communication with the compute processor, the memory comprising a plurality of memory channels, and a memory sub-system (MSS) in communication with the plurality of memory channels, the MSS comprising a static random-access memory (SRAM), the SRAM being shared by the plurality of memory channels. Each memory channel is equidistant from the shared SRAM. The shared SRAM is a multi-port SRAM comprising anGOOGEE-4189 instruction closely coupled memory (ICCM), wherein the shared ICCM SRAM provides concurrent access to all of the plurality of memory channels. The shared ICCM SRAM transfers data to each memory channel allowing the physical network layer (PHY) microcontroller unit (PMU) of the memory channel to operate within latency requirements for the memory channel. A memory channel may include a single-port data SRAM in communication with the PHY for receiving data at the memory channel.

[0006] The shared ICCM may store a common processing image stored in the shared ICCM SRAM, the common processing image used by the plurality of memory channels. The common processing image may include training firmware for the compute device, mission mode firmware and / or a memory address map shared by all memory channels. The shared ICCM may be placed near the center of a chip of the SoC, around a common memory fabric that provides close to equal latency for each core in the SoC.

[0007] The described technology further describes a method for providing instruction memory in a system on chip (SoC) by placing a multi-port static random access memory (SRAM) in a memory controller of the SoC, storing in the multi-port SRAM, instructions for operation of the SoC, in a plurality of memory channels of the SoC, accessing the stored instructions in the multi-port SRAM, and in the plurality of memory channels, executing the accessed instructions. The instructions in the multi-port SRAM can be accessed by the plurality of memory channels of the SoC concurrently. The multi-port SRAM may store a common processing image the common processing image including training firmware, mission mode firmware, and / or a memory address mapping. The method may include placing the multi-port SRAM at a location on the SoC that is substantially equidistant from all memory channels on the SoC. The multi-port SRAM meets a latency requirement of a microprocessor associated with a memory channel of the SoC. Each memory channel may include a single port SRAM for storing data associated with the memory channel.BRIEF DESCRIPTION OF THE DRAWINGS

[0008] FIG. 1 is a block diagram illustrating system on chip (SoC) device that can implement the technology described in this disclosure.

[0009] FIG. 2 is a block diagram illustrating a multi-channel memory according to aspects of the disclosed technology.

[0010] FIG. 3. is a plan view of a SoC according to aspects of the disclosed technology.GOOGLE-4189

[0011] FIG. 4. is a plan view of a SoC having an instruction closely coupled memory (ICCM) SRAM shared among multiple memory channels according to aspects of the disclosed technology.

[0012] FIG. 5. is a process flow diagram for implementing a shared instruction SRAM in an SoC.

[0013] FIG. 6. is a block diagram of a computing device according to aspects of the disclosed technology.DETAILED DESCRIPTION

[0014] FIG. 1 is a block diagram of a system on chip (SoC) 100. The SoC 100 includes components of a compute device formed on the same piece of semiconductor material. The piece of semiconductor material may be referred to as a chip. . The SoC uses a number of interconnecting fabrics including a memory fabric 110, a high bandwidth fabric 120, a coherent fabric 130 a system fabric 140, a media fabric 150 and a real-time fabric 160. The fabrics 110,120, 130, 140, 150, 160 allow components of the SoC 100 to interact with one another. For example, central processing unit (CPU) 131 is connected to system memory via coherent fabric 130 and memory fabric 110.

[0015] The compute device containing SoC 100 may be connected to a camera system that implements a real time feature through real-time fabric 160. The camera front end 162 may include a user interface that controls the functions of the camera. The camera may provide the view captured by the camera in real-time to a display 161. Additionally, the real-time fabric is in communication with memory via memory fabric 110. Other functions of the camera, which process the signals captured by the sensor in the camera may be included in camera subsystem 152 in cooperation with software for decoding and encoding the signals in video Codec 151. These produce media signals, which are communicated via media fabric 150. Media may interact with system memory via high bandwidth fabric 120.

[0016] High bandwidth fabric 120 provides high speed data communication with memory providing high speed access to components like the graphics processing unit (GPU)121, the data processing unit (DPU) 122 and the digital signal processing module (DSP) 123. The system fabric 140 connects other system components to memory, including power source141, identified as “Power” in Fig. 1, for supporting memory functions, support for peripherals142, security for access to memory 143 and computing processing to data stored in memory 144.GOOGLE-4189

[0017] The memory subsystem includes memory fabric 110 and memory components including system level cache (SLC) generally denoted 111, a memory controller (MC) generally 112, and dynamic random-access memory (DRAM), generally 113 connected to the SoC 100. In the example of FIG. 1, the memory subsystem includes four memory channels, although other systems may include more or fewer memory channels. Each memory channel may include its own functional components. For instance, memory channel 1 will have a dedicated SLC 11 la, a channel memory controller 112a and DRAM 113a. Memory channel 2 has a dedicated SLC 111b, a channel memory controller 112b and DRAM 113b. Memory channel 3 has a dedicated SLC 111c, a channel memory controller 112c and DRAM 113c. Finally, memory channel 4 has a dedicated SLC 11 Id, a channel memory controller 112d and DRAM 113d.

[0018] Each memory component requires some amount of power to operate. An external power management integrated circuit (PMIC) provides power, and each memory channel selectively receives power through power gating controlled through the SoC. Power manager 141 provides hardware and software services of power management of the SoC via system fabric 140 to support each memory channel supported by memory fabric 110. Devices implemented as SoC 100 can be mobile devices that are typically powered by portable energy sources such as batteries. In this regard, power source 141 may include batteries that provide power used to support the components of the SoC 100 including the components of the memory channels 111, 112, 113. During operations, components of the SoC, including the memory components 111, 112, 113 deplete the energy stored in the system battery and reduce the battery’s state of charge. When the battery is sufficiently depleted, the battery can no longer support operations of the device. The battery must be recharged prior to that point to maintain operation of the device as intended. Although Fig. 1 shows the power source 141 as being part of the SoC 100, the power source may be positioned off of the SoC. Additionally, there may be more than one power source, such as multiple batteries.

[0019] FIG. 2 is a block diagram illustrating a quad-channel memory system, which shows a configuration of a multi-channel compute device. Memory subsystem (MSS) 110 includes a number of memory channels that operate in cooperation to provide faster and more efficient memory operations for the compute device associated with the memory channels. Each memory channel includes a DRAM 113. Memory channel 1 includes DRAM 113a, memory channel 2 includes DRAM 113b, memory channel 3 includes DRAM 113c, andGOOGEE-4189 memory channel 4 includes DRAM 113d. Each memory channel further includes a memory controller that establishes a physical layer (PHY) 112 connecting the DRAM 113 to the device. Memory channel 1 includes MC / PHY 112a, memory channel 2 includes MC / PHY 112b, memory channel 3 includes MC / PHY 112c, and memory channel 4 includes MC / PHY 112d. In operation each DRAM 113 as well as each memory controller 112 requires power to operate. Each memory channel draws the power necessary to supply its associated MC / PHY 112 and DRAM 113 with power to operate the memory channel. In a device having four memory channels, each of the four memory channels will draw power from the device and its power source to maintain operations of the active memory channels.

[0020] FIG. 3 is a plan view of a SoC 100 according to the disclosed technology. The SoC 100 incorporates a number of components performing varying functions in a single piece of semiconductor material. Basic functions are performed including but not limited to sensors, computing, debugging, security and power management. The SoC 100 can be configured to support multi-channel memory. The system memory can be managed through a memory subsystem (MSS) 301 that is in communication with multiple memory channels. A first memory channel can include a double data rate (DDR) DRAM 113a operating a microcontroller for the memory channel that is coupled to the SoC 100. A second memory channel can include a DDR DRAM 113b operating a microcontroller for the memory channel that is coupled to the SoC 100. A third memory channel can include a DDR DRAM 113c operating a microcontroller for the memory channel that is coupled to the SoC 100. A fourth memory channel can include a DDR DRAM 113d operating a microcontroller for the memory channel that is coupled to the SoC 100.

[0021] A memory channel can store data related to system processing as well as instructions for performing system and application actions. For instruction storage, a corresponding memory channel includes an SRAM for storing instructions. A plurality of channel SRAMs are included equal to the number memory channels in SoC 100. SRAM is volatile memory that provides the ability to store instructions for as long as power is supplied to the SRAM. SRAM therefore does not need to be refreshed like DRAM, which decays over time. However, SRAM is more expensive the DRAM and requires more semiconductor area that DRAM.

[0022] FIG. 4 is a plan view of a SoC 400 with a shared ICCM SRAM according to aspects of the disclosed technology. The SoC 400 incorporates a number of componentsGOOGLE-4189 performing varying functions in a single piece of semiconductor. Basic functions are performed including but not limited to sensors, computing, debugging, security and power management. The SoC 400 can be configured to support multi-channel memory. The system memory can be managed through a memory sub-system (MSS) 405 that is in communication with multiple memory channels. A first memory channel can include a PHY microcontroller operating double data rate (DDR) DRAM 113a that is coupled to the SoC 400. A second memory channel can include a PHY microcontroller operating DDR DRAM 113b that is coupled to the SoC 400. A third memory channel can include a PHY microcontroller operating a DDR DRAM 113c that is coupled to the SoC 400. A fourth memory channel can include a PHY microcontroller operating a DDR DRAM 113d that is coupled to the SoC 400.

[0023] MSS 405 includes SRAM 403 that stores instructions (or code) for performing system functions. Memory channels store data 401 and refer to SRAM 403 for retrieving instructions for handling the data 401. To provide equal access to the shared SRAM 403, memory channels 113 are placed substantially equidistant to MSS 405. Each DDR memory of memory channels 113 is in communication with shared SRAM 403. SRAM 403 may be a multi-port SRAM for synchronous communication with multiple memory channels. Using shared SRAM 403 for storing instructions, replicated instructions SRAM at each memory channel PHY DRAM 113 location can be eliminated. In this way, the number of instruction SRAMs needed may be reduced from the number of memory channels down to a single instruction SRAM instance 403 in the MCC 405. The result is a reduction in cost and semiconductor space as less SRAMs are required. Additionally, the system will require less power to support multiple instances of SRAM for storing instructions.

[0024] The shared SRAM 403 can store common processing image that is applicable to all memory channels 113. The processing image can be stored once and accessed multiple times as need by different memory channels. The shared processing image can include firmware for the SoC device 400. The shared SRAM 403 can include a memory address map for accessing data or files across all memory channels 113. Firmware implementing a mission mode for the system may be stored in the ICCM defined by shared SRAM 403. A mission mode defines the way in which the device is intended to be used.

[0025] Conventionally, it was considered necessary to have an ICCM for each memory channel in addition to DCCM and other functional SRAM memories. Because the memory channels execute the memory training and dynamic voltage and frequency scaling (DVFS)GOOGLE-4189 operations, the appropriate memories are placed in proximity to the memory channel PHY. Considering that the memory channel writes data that is stored in the DCCM, it makes sense to place these memories in the memory channel. However, the ICCM is written with the same code executed by each microcontroller. The information in the ICCM does not change across different memory channels. Thus, it makes sense to use a single instance of the instructions stored in a shared ICCM to serve each memory channel. To avoid congestion and latency due to retrieving the instructions from the MCC 405, the common ICCM SRAM 403 is centrally placed and verified that it meets the performance and latency requirements of the memory channel PHY microcontroller.

[0026] FIG. 5 is a process flow diagram for a shared ICCM in a multi-channel device according to the disclosed technology. In an SoC, a multi-port SRAM is placed at the memory controller 510. The memory controller may be located substantially centrally in the semiconductor of the SoC. Instructions are stored in the multi-port SRAM at the memory controller 520. The instructions may include instructions that are universally used in the system across different memory channels. By non-limiting example, the instructions may include a common processing image, such as device firmware, mission mode firmware, or memory address mapping information for the system. The stored instructions are accessed by more than one memory channel 530. The multiple memory channels may concurrently access the stored instructions through the multi-port SRAM. The system then executes the accessed instructions in a number of memory channels. The memory channel components may be placed on the SoC’s chip so that they are substantially equidistant from the shared multi-port SRAM.

[0027] FIG. 6 is a block diagram of a compute device which may be used to implement aspects of the disclosed technology. Compute device 600 may be personal computer or a mobile device, intended for use by a person. Compute device 600 having all the internal components normally found in a personal computer such as a central processing unit, CD- ROM, hard drive, and a display device, for example, a monitor having a screen, a projector, a touch-screen, a small LCD screen, a television, or another device such as an electrical device that can be operable to display information processed by a processor 620, speakers, a modem and or network interface device, user input such as a mouse, keyboard, touchscreen, or microphone, and all of the components used for connecting these elements to one another. Moreover, computers in accordance with the systems and methods described herein may include devices capable of processing instructions and transmitting data to and from humansGOOGLE-4189 and other computers including general purpose computers, PDAs, tablets, mobile phones, smartwatches, network computers lacking local storage capability, set top boxes for televisions, and other networked devices.

[0028] The compute device 600 may contain a processor 620, memory 630, and other components typically present in general-purpose computers. The memory 630 can store information accessible by the processor 620 including instructions 632 that can be executed by the processor 620. Memory can also include data 634 that can be retrieved, manipulated or stored by the processor 620. The memory 630 may a type of non-transitory computer readable medium capable of storing information accessible by the processor 620, such as a hard-drive, solid state drive, tape drive, optical storage, memory card, ROM, RAM DVD, CD-ROM, volatile memory such as DRAM or SRAMN, and write-capable and read-only memories. The processor 620 can be a well-known processor or other lesser-known type of processor. Alternatively, the processor 620 can be a dedicated controller such as an Application Specific Integrated Circuit (ASIC)

[0029] The instructions 632 can be a set of instructions executed directly, such as machine code, or indirectly, such as scripts by the processor 620. In this regard, the terms “instructions,’ “steps” and “programs” can be used interchangeably herein. The instructions 632 can be stored in object code format for direct processing by the processor 620, or other types of computer language including scripts or collections of independent source code modules that are interpreted on demand or compiled in advance.

[0030] Memory may be arranged in multiple memory channels including DRAM memory 630 storing data 634. Further, SRAM memory 631 may be configured to store instructions 632. Instructions 632 may be shared between memory channels with DRAM 630 associated with a memory channel being in communication with a shared SRAM memory 631. Shared SRAM memory 631 may be located in a memory sub-system and be a multi-port SRAM for supporting synchronous communication with multiple memory channels.

[0031] The data 634 can be retrieved, stored or modified by the processor 620 in accordance with the instructions 632. For instance, although the system and method are not limited to a particular data structure, the data 634 can be stored in computer registers, in a data store as a structure having a plurality of different fields and records, or documents, or buffers. The data 634 can include information sufficient to identify relevant information, such as numbers, descriptive text, proprietary codes, pointers, references to data stored in otherGOOGLE-4189 memories, including other network locations, or information that is used by a function to calculate relevant data. Although FIG. 6 functionally illustrates a single processor 620 with a single memory 630, there could actually be multiple processors and memories that may or may not be in direct proximity to each other. For example, a compute device may include multiple memories arranged in a multi-channel memory system defining multiple memory channels, each possessing its own memory. In some cases, each memory channel may include an associated microprocessor serving as a memory controller. The compute device may include multiple processing units, including data processing units, central processing units, graphics processing units, and the like.

[0032] Although the invention herein has been described with reference to particular embodiments, it is to be understood that these embodiments are merely illustrative of the principles and applications of the present invention. It is therefore to be understood that numerous modifications may be made to the illustrative embodiments and that other arrangements may be devised without departing from the spirit and scope of the present invention as defined by the appended claims.

[0033] The described technology provides features that conserve energy and prolong battery life in portable devices by selectively providing power to a selected number of memory channels in a multi-channel memory device. The features include:

[0034] Feature 1 includes a compute device having a compute processor, a memory in communication with the compute processor, the memory comprising a plurality of memory channels, and a memory sub-system (MSS) in communication with the plurality of memory channels, the MSS comprising a static random-access memory (SRAM), the SRAM being shared by the plurality of memory channels.

[0035] Feature 1 includes the features of feature 1 wherein each memory channel is equidistant from the shared SRAM.

[0036] Feature 3 includes the features of any of features 1-2 wherein the shared SRAM is a multi-port SRAM comprising an instruction closely coupled memory (ICCM).

[0037] Feature 4 includes the features of any of features 1-3 wherein the shared ICCM SRAM provides concurrent access to all of the plurality of memory channels.

[0038] Feature 5 includes the features of any of features 1-4 wherein the shared ICCM SRAM transfers data to each memory channel that allows the physical network layer (PHY)GOOGLE-4189 microcontroller unit (PMU) of the memory channel to operate within latency requirements for the memory channel.

[0039] Feature 6 includes the features of any of features 1-5 and further includes a single-port data SRAM in communication with the PHY for receiving data at the memory channel.

[0040] Feature 7 includes the features of any of features 1-6 and further includes a common processing image stored in the shared ICCM SRAM, the common processing image used by the plurality of memory channels.

[0041] Feature 8 includes the features of any of features 1-7, wherein the shared image comprises training firmware for the compute device.

[0042] Feature 9 includes the features of any of features 1-8, wherein, the shared image comprises a mission mode firmware for the computing device.

[0043] Feature 10 includes the features of any of features 1-9, wherein the shared image comprises a memory address map shared by all memory channels.

[0044] Feature 11 includes the features of any of features 1-10, wherein the common ICCM is placed at the center of the SoC’s chip around common memory fabric providing substantially equal latency for each core where no one core exhibits markedly higher latency than another core..

[0045] Features of the disclosed technology may further include:

[0046] Feature 12, a method for providing instruction memory in a system on chip(SoC) by placing a multi-port static random- access memory (SRAM) in a memory controller of the SoC, storing in the multi-port SRAM, instructions for operation of the SoC, in a plurality of memory channels of the SoC, accessing the stored instructions in the multi-port SRAM, and in the plurality of memory channels, executing the accessed instructions.

[0047] Feature 13 includes the features of feature 12 and further includes accessing the instructions stored in the multi-port SRAM by the plurality of memory channels of the SoC concurrently.

[0048] Feature 14 includes the features of any of features 12-13 and further includes storing a common processing image within the instructions stored in the multi-port SRAM.

[0049] Feature 15 includes the features of any of features 12-13 and further includes storing firmware of the SoC in the common processing image.GOOGLE-4189

[0050] Feature 16 includes the features of any of features 12-15 and further includes storing a memory address mapping in the common processing image.

[0051] Feature 17 includes the features of any of features 12-16 and further includes storing a mission mode firmware for the SoC in the common processing image.

[0052] Feature 18 includes the features of any of features 12-17 and further includes placing the multi-port SRAM at a location on the SoC that is substantially equidistant from all memory channels on the SoC.

[0053] Feature 19 includes the features of any of features 12-18, wherein the multi-port SRAM meets a latency requirement of a microprocessor associated with a memory channel of the SoC.

[0054] Feature 20 includes the features of any of features 12-19 and further includes placing a single port SRAM for storing data in a memory channel of the SoC.

Claims

GOOGLE-4189CLAIMS1. A compute device comprising: a compute processor; a memory in communication with the compute processor, the memory comprising a plurality of memory channels; and a memory sub-system (MSS) in communication with the plurality of memory channels, the MSS comprising a static random-access memory (SRAM), the SRAM being shared by the plurality of memory channels.

2. The compute device of claim 1, wherein each memory channel is equidistant from the shared SRAM.

3. The computer device of claim 1, wherein the shared SRAM is a multi-port SRAM comprising an instruction closely coupled memory (ICCM).

4. The compute device of claim 3, wherein the shared ICCM SRAM provides concurrent access to each of the plurality of memory channels.

5. The compute device of claim 1, wherein the shared ICCM SRAM transfers data to each memory channel, wherein the transferred data allows the physical network layer (PHY) microcontroller unit (PMU) of the memory channel to operate within latency requirements for the memory channel.

6. The compute device of claim 5, further comprising: a single-port data SRAM in communication with the PHY for receiving data at the memory channel.

7. The compute device of claim 1, further comprising: a common processing image stored in the shared ICCM SRAM, wherein each of the plurality of memory channels is configured to use the common processing image.

8. The compute device of claim 7, wherein the shared image comprises training firmware for the compute device.GOOGLE-41899. The compute device of claim 7, wherein, the shared image comprises a mission mode firmware for the computing device.

10. The compute device of claim 7, wherein the shared image comprises a memory address map shared by all memory channels.

11. The compute device of claim 3, wherein the common ICCM is placed at the center of a chip of the SoC around common memory fabric providing substantially for each core.

12. A method for providing instruction memory in a system on chip (SoC) comprising: placing a multi-port static random-access memory (SRAM) in a memory controller of the SoC; storing in the multi-port SRAM, instructions for operation of the SoC; in a plurality of memory channels of the SoC, accessing the stored instructions in the multi-port SRAM; and in the plurality of memory channels, executing the accessed instructions.

13. The method of claim 12, further comprising: accessing the instructions stored in the multi-port SRAM by the plurality of memory channels of the SoC concurrently.

14. The method of claim 12, further comprising: storing a common processing image within the instructions stored in the multi-port SRAM.

15. The method of claim 14, further comprising: storing firmware of the SoC in the common processing image.

16. The method of claim 14, further comprising: storing a memory address mapping in the common processing image.

17. The method of claim 14, further comprising: storing a mission mode firmware for the SoC in the common processing image.GOOGLE-418918. The method of claim 13, further comprising: placing the multi-port SRAM at a location on the SoC that is substantially equidistant from all memory channels on the SoC.

19. The method of claim 13, wherein the multi-port SRAM transfers data to each memory channel, wherein the transferred data allows meeting a latency requirement of a microprocessor associated with a memory channel of the SoC.

20. The method of claim 13, further comprising: placing a single port SRAM for storing data in a memory channel of the SoC.

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