Display panel, display apparatus and driving method

Abstract

Provided in the embodiments of the present disclosure are a display panel, a display apparatus and a driving method. The display panel comprises: a base substrate, and a plurality of sub-pixels and a plurality of pixel circuits located on the base substrate. One pixel circuit is arranged corresponding to at least two adjacent sub-pixels; each sub-pixel comprises one light-emitting device; first electrodes of light-emitting devices in the at least two adjacent sub-pixels are the same electrode, the first electrodes of the light-emitting devices are electrically connected to the pixel circuit arranged corresponding thereto, second electrodes of light-emitting devices in two adjacent sub-pixels are electrodes independent of each other and spaced apart from each other, and second electrodes of the light-emitting devices in the at least two adjacent sub-pixels are respectively electrically connected to two first power supply signal lines in one-to-one correspondence; and active level signals are applied to the two first power supply signal lines in a time-division manner. Each pixel circuit is configured to drive, when active level signals are applied to first power supply signal lines, light-emitting devices to emit light.

Description

Display panel, display device and driving method TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of display, in particular to a display panel, a display device and a driving method. BACKGROUND

[0002] With the rise of the concept of metaverse, the promotion of virtual reality (VR) and augmented reality (AR) technology, the resolution (Pixels Per Inch, PPI) of the display panel is put forward higher requirements. High resolution means higher pixel density, which can provide more delicate and clear images, thereby significantly improving the visual experience of users in AR / VR devices, which is crucial for AR / VR applications that require high immersion. However, existing display panels are difficult to achieve high resolution due to manufacturing processes, so high-resolution display panels have become a must to overcome.

[0003] SUMMARY

[0004] The display panel provided by the embodiments of the present disclosure comprises: a substrate, a plurality of sub-pixels and a plurality of pixel circuits on the substrate; at least two adjacent sub-pixels are arranged corresponding to one pixel circuit;

[0005] Each of the sub-pixels comprises a light emitting device; the first electrodes of the light emitting devices in the at least two adjacent sub-pixels are the same electrode, the first electrodes of the light emitting devices are electrically connected to the corresponding pixel circuit, the second electrodes of the light emitting devices in the two adjacent sub-pixels are independently and separately arranged electrodes, and the second electrodes of the light emitting devices in the at least two adjacent sub-pixels are respectively electrically connected to two first power signal lines; the two first power signal lines load effective level signals in time division manner;

[0006] The pixel circuit is configured to drive the light emitting device to emit light when the first power signal line loads the effective level signal.

[0007] In some possible implementations, a first electrode layer, a pixel definition layer, an electroluminescent layer and a second electrode layer arranged in sequence together constitute the plurality of light emitting devices;

[0008] The first electrode layer is double-layered, and the first electrode layer comprises the first electrodes of the plurality of light emitting devices;

[0009] The second electrode layer comprises the second electrodes of the plurality of light emitting devices;

[0010] A first electrode of one of the first electrodes overlaps a projection of at least two adjacent second electrodes on the substrate.

[0011] In some possible implementations, the second electrodes of the plurality of light emitting devices extend along a first direction, and the second electrodes of the plurality of light emitting devices are sequentially and spaced apart along a second direction.

[0012] In some possible implementations, the two first power signal lines extend along the second direction, and the two first power signal lines are respectively located on two sides of the second electrodes.

[0013] Two second electrodes adjacent along the second direction are respectively electrically connected to the first power signal lines located on the two sides.

[0014] In some possible implementations, the display panel further includes a color filter layer located on a side of the second electrode layer away from the substrate, and the color filter layer includes at least three color filters of different colors.

[0015] The color filters arranged on the second electrodes of the light emitting devices in the at least two adjacent subpixels are of the same color or different colors.

[0016] In some possible implementations, the first electrodes of the light emitting devices are anodes, the second electrodes of the light emitting devices are cathodes, and the effective level signal loaded on the first power signal line is a low level signal.

[0017] In some possible implementations, the first electrodes of the light emitting devices are cathodes, the second electrodes of the light emitting devices are anodes, and the effective level signal loaded on the first power signal line is a high level signal.

[0018] In some possible implementations, the pixel circuit includes a driving transistor, a first transistor, a second transistor, and a first capacitor.

[0019] The gate of the driving transistor is electrically connected to the first electrode of the first transistor, the first electrode of the driving transistor is electrically connected to a second power signal line, and the second electrode of the driving transistor is electrically connected to the first electrode of the light emitting device in the corresponding at least two adjacent subpixels.

[0020] The gate of the first transistor is electrically connected to a gate signal line, and the second electrode of the first transistor is electrically connected to a data signal line.

[0021] The gate of the second transistor is electrically connected to the gate signal line, the first electrode of the second transistor is electrically connected to the second electrode of the driving transistor, and the second electrode of the second transistor is electrically connected to a compensation signal line.

[0022] The first electrode of the first capacitor is electrically connected with the gate of the driving transistor, and the second electrode of the first capacitor is electrically connected with the second electrode of the driving transistor.

[0023] In some possible implementation manners, the driving transistor is a double-gate structure, and the gate of the driving transistor includes a first gate and a second gate.

[0024] In some possible implementation manners, the display panel further includes a first conductive layer on the substrate, and the first conductive layer includes the data signal line and the compensation signal line.

[0025] The light-blocking layer on the side, away from the substrate, of the first conductive layer includes the first gate of the driving transistor.

[0026] In some possible implementation manners, the display panel further includes a first semiconductor layer on the side, away from the substrate, of the light-blocking layer, and the first semiconductor layer includes the active layer of the driving transistor and the active layer of the first transistor.

[0027] The gate conductive layer on the side, away from the substrate, of the first semiconductor layer includes the gate of the first transistor, the gate of the second transistor, the second gate of the driving transistor, and the first electrode of the first capacitor.

[0028] The second conductive layer on the side, away from the substrate, of the gate conductive layer includes the second electrode of the first capacitor.

[0029] The second semiconductor layer on the side, away from the substrate, of the second conductive layer includes the active layer of the second transistor.

[0030] The third conductive layer on the side, away from the substrate, of the second semiconductor layer includes the second power signal line.

[0031] In some possible implementation manners, the second conductive layer further includes a first adapter, and a projection of the first adapter on the substrate overlaps a projection of the data signal line on the substrate.

[0032] The active layer of the first transistor is electrically connected with the data signal line through the first adapter.

[0033] In some possible implementation manners, the third conductive layer further includes a second adapter, and a projection of the second adapter on the substrate overlaps a projection of the second gate of the driving transistor on the substrate.

[0034] The active layer of the first transistor is electrically connected with the second gate of the driving transistor through the second adapter.

[0035] In some possible implementation manners, the at least two adjacent sub-pixels and the pixel circuit arranged correspondingly to the at least two adjacent sub-pixels jointly constitute a pixel unit.

[0036] The two pixel units adjacent along the first direction are arranged in mirror symmetry to each other, and the two pixel units adjacent along the second direction are arranged in mirror symmetry to each other.

[0037] In some possible implementation manners, the four pixel units adjacent along the first direction and the second direction constitute a pixel arrangement group.

[0038] The pixel units in each pixel arrangement group share one compensation signal line.

[0039] The two pixel arrangement groups adjacent along the second direction share one second power signal line.

[0040] The display device provided by the embodiment of the present disclosure includes the display panel.

[0041] The driving method of the display panel provided by the embodiment of the present disclosure includes:

[0042] In the first light-emitting stage, one of the two first power signal lines is loaded with an effective level signal, and the pixel circuit drives the light-emitting device electrically connected with the first power signal line to emit light.

[0043] In the second light-emitting stage, the other of the two first power signal lines is loaded with an effective level signal, and the pixel circuit drives the light-emitting device electrically connected with the first power signal line to emit light. BRIEF DESCRIPTION OF DRAWINGS

[0044] FIG. 1 is a schematic diagram of some top-view structures of a display panel provided by the embodiment of the present disclosure;

[0045] FIG. 2 is a schematic diagram of some structures of a pixel circuit provided by the embodiment of the present disclosure;

[0046] FIG. 3 is a schematic diagram of some cross-sectional structures of a display panel provided by the embodiment of the present disclosure along the direction of AA';

[0047] FIG. 4 is a schematic diagram of some layout structures of a display panel provided by the embodiment of the present disclosure;

[0048] FIG. 5 is a schematic diagram of another layout structure of a display panel provided by the embodiment of the present disclosure;

[0049] FIG. 6 is another layout structure diagram of a display panel according to an embodiment of the present disclosure;

[0050] FIG. 7 is another layout structure diagram of a display panel according to an embodiment of the present disclosure;

[0051] FIG. 8 is a structure diagram of the layout of the display panel in FIGS. 4-7 superimposed on each other according to an embodiment of the present disclosure;

[0052] FIG. 9 is another layout structure diagram of a display panel according to an embodiment of the present disclosure;

[0053] FIG. 10a is another top structure diagram of a display panel according to an embodiment of the present disclosure;

[0054] FIG. 10b is a structure diagram of some manufacturing processes of a display panel according to an embodiment of the present disclosure;

[0055] FIG. 10c is a structure diagram of another manufacturing process of a display panel according to an embodiment of the present disclosure;

[0056] FIG. 10d is a structure diagram of another manufacturing process of a display panel according to an embodiment of the present disclosure;

[0057] FIG. 10e is a structure diagram of another manufacturing process of a display panel according to an embodiment of the present disclosure;

[0058] FIG. 11 is another layout structure diagram of a display panel according to an embodiment of the present disclosure;

[0059] FIG. 12 is another layout structure diagram of a display panel according to an embodiment of the present disclosure;

[0060] FIG. 13 is another cross-sectional structure diagram of a display panel along the AA' direction according to an embodiment of the present disclosure;

[0061] FIG. 14 is another cross-sectional structure diagram of a display panel along the AA' direction according to an embodiment of the present disclosure;

[0062] FIG. 15 is another structure diagram of a pixel circuit according to an embodiment of the present disclosure;

[0063] FIG. 16 is another cross-sectional structure diagram of a display panel along the AA' direction according to an embodiment of the present disclosure;

[0064] FIG. 17 is another layout structure diagram of a display panel according to an embodiment of the present disclosure;

[0065] FIG. 18 is another layout structure diagram of a display panel according to an embodiment of the present disclosure;

[0066] FIG. 19 is another layout structure diagram of a display panel according to an embodiment of the present disclosure;

[0067] FIG. 20 is another layout structure diagram of a display panel according to an embodiment of the present disclosure;

[0068] FIG. 21 is another layout structure diagram of a display panel according to an embodiment of the present disclosure;

[0069] FIG. 22 is another layout structure diagram of a display panel according to an embodiment of the present disclosure;

[0070] FIG. 23 is another layout structure diagram of a display panel according to an embodiment of the present disclosure;

[0071] FIG. 24 is another layout structure diagram of a display panel according to an embodiment of the present disclosure;

[0072] FIG. 25 is another layout structure diagram of a display panel according to an embodiment of the present disclosure;

[0073] FIG. 26 is another layout structure diagram of a display panel according to an embodiment of the present disclosure;

[0074] FIG. 27 is another layout structure diagram of a display panel according to an embodiment of the present disclosure;

[0075] FIG. 28 is a structure diagram in which the layouts of the display panels in FIGS. 17-25 are superimposed on each other according to an embodiment of the present disclosure;

[0076] FIG. 29 is another layout structure diagram of a display panel according to an embodiment of the present disclosure;

[0077] FIG. 30 is another layout structure diagram of a display panel according to an embodiment of the present disclosure;

[0078] FIG. 31 is another layout structure diagram of a display panel according to an embodiment of the present disclosure;

[0079] FIG. 32 is another layout structure diagram of a display panel according to an embodiment of the present disclosure;

[0080] FIG. 33 is another layout structure diagram of a display panel according to an embodiment of the present disclosure;

[0081] FIG. 34 is a flowchart of a driving method of a pixel circuit according to an embodiment of the present disclosure;

[0082] FIG. 35 is a timing diagram of some signals according to an embodiment of the present disclosure;

[0083] FIG. 36 is another structure diagram of a pixel circuit according to an embodiment of the present disclosure;

[0084] FIG. 37 is another signal timing diagram provided by embodiments of the present disclosure;

[0085] FIG. 38 is yet another structure diagram of a pixel circuit provided by embodiments of the present disclosure;

[0086] FIG. 39 is a structure diagram of a stack structure of a display panel provided by embodiments of the present disclosure;

[0087] FIG. 40 is yet another structure diagram of a pixel circuit provided by embodiments of the present disclosure;

[0088] FIG. 41 is another signal timing diagram provided by embodiments of the present disclosure;

[0089] FIG. 42 is yet another structure diagram of a pixel circuit provided by embodiments of the present disclosure;

[0090] FIG. 43 is another signal timing diagram provided by embodiments of the present disclosure;

[0091] FIG. 44 is another signal timing diagram provided by embodiments of the present disclosure;

[0092] FIG. 45 is a structure diagram of a signal control circuit provided by embodiments of the present disclosure;

[0093] FIG. 46 is another signal timing diagram provided by embodiments of the present disclosure. DETAILED DESCRIPTION

[0094] In order to make the objectives, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be described clearly and completely below with reference to the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, rather than all the embodiments of the present disclosure. Moreover, the embodiments in the present disclosure and the features in the embodiments can be combined with each other without conflict, if possible. Based on the described embodiments of the present disclosure, all other embodiments obtained by a person of ordinary skill in the art without creative effort belong to the scope of protection of the present disclosure.

[0095] Unless otherwise defined, technical terms or scientific terms used in the present disclosure should be understood as their ordinary meanings to a person of ordinary skill in the art to which the present disclosure belongs. The terms “first”, “second” and similar words used in the present disclosure do not represent any order, number or importance, but are only used to distinguish different components. The terms “include” or “contain” and similar words mean that the components or objects before the words cover the components or objects listed after the words and their equivalents, without excluding other components or objects. The terms “connect” or “connected” and similar words are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect.

[0096] It is to be noted that the size and shape of the figures in the drawings do not reflect true proportions, but are intended to illustrate the present disclosure. Also, the same or similar reference numerals are used throughout the drawings to indicate the same or similar elements or elements having the same or similar function.

[0097] Currently, the display device formed based on the glass substrate or the flexible plastic (Polyimide, PI) substrate thin film transistor (TFT) device can only stop at 500-600 resolution (Pixels Per Inch, PPI), and cannot meet the needs of AR / VR applications higher than 1800PPI.

[0098] For example, the existing low temperature poly-silicon (LTPS) technology or low temperature poly-oxide (LTPO) technology adopts 7T1C or 8T1C internal compensation circuit, and since more thin film transistor devices are used, it is difficult to achieve high resolution, and can only stop at 600PPI. The oxide technology adopts 3T1C external compensation circuit, and the oxide type thin film transistor based on the glass substrate or the flexible plastic (Polyimide, PI) substrate needs to consider the device stability, the device size cannot be small, and the low mobility, etc. It can only be applied to large size (pitch) low PPI products (such as televisions).

[0099] Low temperature poly-oxide (Low-Temperature-Polycrystalline-Oxide, LTPO) technology is a technology for simultaneously preparing low temperature poly-silicon type thin film transistors and oxide type thin film transistors on the same substrate. The LTPO technology fully utilizes the advantages of the two types of thin film transistors to make the display device have lower power consumption and superior performance, that is, by combining the low leakage current characteristics of the oxide type thin film transistor and the high mobility characteristics of the low temperature poly-silicon type thin film transistor, the vertical placement of the low temperature poly-silicon type thin film transistor and the oxide type thin film transistor can solve the problem of too many thin film transistor devices, but it brings the problem of too many vias, and the bottleneck of the via connection layer causes the resolution to reach 1000PPI and cannot be improved.

[0100] Therefore, the existing display panel is difficult to achieve high resolution due to the manufacturing process, and therefore a high resolution display panel has become a technology that must be overcome.

[0101] To solve the above technical problems, the display panel provided by the embodiments of the present disclosure, as shown in FIGS. 1-3, comprises: a substrate 100, a plurality of sub-pixels (for example, spx1 and spx2 in FIG. 1) and a plurality of pixel circuits 200 located on the substrate 100; at least two adjacent sub-pixels (for example, spx1 and spx2 in FIG. 1) are arranged correspondingly for each pixel circuit 200.

[0102] Each sub-pixel (for example, spx1 and spx2 in FIGS. 2 and 3) comprises one light emitting device (for example, L1 and L2 in FIGS. 2 and 3); the first electrodes (for example, S1 in FIG. 3) of the light emitting devices (for example, L1 and L2 in FIG. 3) in the at least two adjacent sub-pixels (for example, spx1 and spx2 in FIG. 3) are the same electrode, the first electrodes (for example, S1 in FIG. 3) of the light emitting devices (for example, L1 and L2 in FIG. 3) are electrically connected with the pixel circuit 200 arranged correspondingly, the second electrodes (for example, S2-1 and S2-2 in FIG. 3) of the light emitting devices (for example, L1 and L2 in FIG. 3) in the two adjacent sub-pixels (for example, spx1 and spx2 in FIG. 3) are respectively arranged independently and separately, and the second electrodes of the light emitting devices (for example, L1 and L2 in FIG. 2) in the at least two adjacent sub-pixels are respectively electrically connected with two first power signal lines (for example, VSS1 and VSS2 in FIG. 2) in one-to-one correspondence; the two first power signal lines (for example, VSS1 and VSS2 in FIG. 2) load effective level signals in time division.

[0103] The pixel circuit 200 is configured to drive the light emitting device (for example, L1 and L2 in FIG. 2) to emit light when the first power signal line (for example, VSS1 and VSS2 in FIG. 2) loads the effective level signal.

[0104] The embodiments of the present disclosure make the first electrodes of the light emitting devices in the at least two adjacent sub-pixels the same electrode, electrically connect the first electrodes of the light emitting devices with the pixel circuit arranged correspondingly, make the second electrodes of the light emitting devices in the two adjacent sub-pixels respectively arranged independently and separately, electrically connect the second electrodes of the light emitting devices in the at least two adjacent sub-pixels with the two first power signal lines in one-to-one correspondence, load the effective level signals in time division by the two first power signal lines, drive the at least two adjacent sub-pixels to emit light by one pixel circuit in time division, ensure the size of the sub-pixel to be smaller, and thus realize the display of high resolution (Pixels Per Inch, PPI) and improve the display effect; and by combining the 1um signal line width, 1um signal line spacing and 1.5um via process capability, the resolution of the display panel can reach more than 1800PPI.

[0105] In some embodiments of the present disclosure, as shown in FIGS. 3-8, the first electrode layer 10 (e.g., as shown in FIG. 4), the pixel definition layer 20 (e.g., as shown in FIG. 5), the electroluminescent layer 30 (e.g., as shown in FIG. 6), and the second electrode layer 40 (e.g., as shown in FIG. 7) arranged in sequence together constitute a plurality of light emitting devices (e.g., L1, L2 in FIG. 3); the first electrode layer 10 is arranged in two layers, and the first electrode layer 10 includes the first electrodes S1 of the plurality of light emitting devices L1, L2; the second electrode layer 40 includes the second electrodes S2-1, S2-2 of the plurality of light emitting devices L1, L2; the orthographic projection of one first electrode S1 on the substrate 100 overlaps the orthographic projection of at least two adjacent second electrodes S2-1, S2-2 on the substrate 100.

[0106] For example, the first electrode layer and the second electrode layer are both made of conductive material; for example, the conductive material can include metal materials such as aluminum, molybdenum, titanium, or alloy materials, and can also include metal oxides such as indium tin oxide (ITO) and the like, which are not specifically limited herein.

[0107] For example, the pixel definition layer is made of insulating material, which can be selected as needed from organic insulating materials such as polyimide, resin materials, and the like, or inorganic insulating materials such as silicon oxide, silicon nitride, silicon oxynitride, and the like, which are not specifically limited herein.

[0108] For example, by arranging the first electrode layer in two layers, the first electrode layer can be etched more finely; and etching the first electrode layer and the pixel definition layer in combination with a dry etching process is conducive to high PPI design and facilitates high PPI.

[0109] For example, the light emitting device can be an electroluminescent diode. For example, the light emitting device can include at least one of an organic light emitting diode (OLED), a quantum dot light emitting diode (QLED), a micro light emitting diode (Micro LED), a mini light emitting diode (Mini LED), and the like. For example, the electroluminescent layer of the light emitting device can further include a hole injection layer, a hole transport layer, an electron transport layer, an electron injection layer, and the like. Of course, in actual applications, the specific structure of the light emitting device can be determined according to the needs of actual applications, which are not limited herein.

[0110] It should be noted that when the light emitting device is a single layer (Single) structure, a single pixel definition layer can be used, for example, as shown in FIG. 5, a pixel definition layer 20 is used; but if the light emitting device is a stacked layer (Tandem) structure, a double-layer pixel definition layer is needed to form a partition structure in the light emitting device of the stacked layer structure to define the light emitting area. For example, as shown in FIG. 5 and FIG. 9, a single layer of pixel definition layer 21 is disposed on the pixel definition layer 20. The stacked layer structure refers to stacking multiple light emitting devices (usually two or more) to achieve higher brightness and lower power consumption. The stacked layer structure can significantly improve the performance of the display panel, including higher brightness, longer service life and lower energy consumption.

[0111] In some embodiments of the present disclosure, as shown in FIG. 10a, the second electrodes S2-1, S2-2 of the plurality of light emitting devices extend along the first direction F1, and the second electrodes S2-1, S2-2 of the plurality of light emitting devices are arranged in sequence along the second direction F2.

[0112] For example, when making the second electrodes of the plurality of light emitting devices in the embodiments of the present disclosure, Open Mask is used. Open Mask is a kind of metal mask plate, which is used to accurately control the position and shape of material deposition in the semiconductor manufacturing process, especially in the evaporation process of OLED display panel. In the evaporation process of the display panel, Open Mask can ensure that the organic material or other functional material is only deposited in the predetermined area, thereby forming the required pixel or circuit structure. Its high-precision pattern design is the key to realizing high resolution and high color saturation of the display panel. The pattern accuracy of Open Mask can usually reach microns or even finer to meet the needs of fine patterns of display panels. Because Open Mask has good durability and stability. And according to different display panel design and production needs, Open Mask can be customized to meet specific pattern and size requirements.

[0113] For example, as shown in FIG. 10b, before forming the second electrodes of the plurality of light emitting devices, a plurality of isolation columns 60 are first deposited and patterned on the electroluminescent layer 30; secondly, as shown in FIG. 10c, after the plurality of isolation columns 60 are made, the second electrode layer 40 is formed by using the evaporation process. Due to the presence of the plurality of isolation columns 60, the plurality of second electrodes S2-1, S2-2 in the second electrode layer 40 can be independently spaced. Wherein, the isolation column 60 is in the shape of inverted ladder or H-shaped; the material of the isolation column 60 includes: polystyrene PS and polychloroprene CPM, etc.

[0114] Exemplarily, as shown in FIG. 10d, before forming the second electrodes of the plurality of light emitting devices, a plurality of isolation columns 60 are deposited and patterned on the electroluminescent layer 30, the isolation columns 60 are made of polychloroprene CPM; then, as shown in FIG. 10e, after the plurality of isolation columns 60 are made, the second electrode layer 40 is formed by using an evaporation process, and due to the existence of the plurality of isolation columns 60, the plurality of second electrodes S2-1, S2-2 in the second electrode layer 40 are independently spaced from each other. The material of the second electrode layer can include magnesium or silver. Since the CPM material can prevent magnesium or silver from being deposited, there is no evaporation film layer on the isolation columns 60. The isolation columns 60 are in the shape of inverted ladder or H.

[0115] Exemplarily, the second electrode layer can be single-layered or multi-layered, which is not limited here.

[0116] In some embodiments of the present disclosure, as shown in FIG. 10a, the two first power signal lines VSS1, VSS2 extend along the second direction F2; the two first power signal lines VSS1, VSS2 are respectively located on the two sides of the second electrodes S2-1, S2-2; the two second electrodes S2-1, S2-2 adjacent along the second direction F2 are respectively electrically connected with the first power signal lines VSS1, VSS2 located on the two sides. For example, the second electrode S2-1 is electrically connected with the first power signal line VSS1, and the second electrode S2-2 is electrically connected with the first power signal line VSS2.

[0117] Exemplarily, the second electrodes of the plurality of light emitting devices can also extend along the second direction, and the second electrodes of the plurality of light emitting devices are sequentially and spaced arranged along the first direction. The extending direction of the second electrodes of the plurality of light emitting devices can be set according to requirements. When the second electrodes of the plurality of light emitting devices extend along the second direction, the two first power signal lines extend along the first direction.

[0118] In some embodiments of the present disclosure, as shown in FIG. 11 and FIG. 12, the display panel further includes a color film layer 50 located on the side of the second electrode layer away from the substrate, and the color film layer 50 includes at least three color films R, G, B of different colors.

[0119] In some embodiments of the present disclosure, the color films arranged on the second electrodes of the light emitting devices in at least two adjacent sub-pixels are of the same color, as shown in FIG. 13, the color film arranged on the second electrode S2-1 of the light emitting device L1 in the sub-pixel spx1 is of the same color as the color film arranged on the second electrode S2-2 of the light emitting device L2 in the sub-pixel spx2. In this way, at least three color films of different colors in the color film layer are all long strip patterns extending in the second direction, which can reduce the difficulty of color film design and process, and can also reduce longitudinal color mixing defects; since RGB forms a flat pixel in the horizontal direction, external algorithm matching is required for display, and the image display is adjusted through the algorithm to avoid display abnormalities.

[0120] In some embodiments of the present disclosure, the color films arranged on the second electrodes of the light emitting devices in at least two adjacent sub-pixels are of different colors, as shown in FIG. 14, the color film arranged on the second electrode S2-1 of the light emitting device L1 in the sub-pixel spx1 is of a different color from the color film arranged on the second electrode S2-2 of the light emitting device L2 in the sub-pixel spx2. In this way, at least three color films of different colors in the color film layer need to be designed in a pattern, and in high PPI design, in order to reduce longitudinal color mixing, the opening of the pixel definition layer will be reduced, but RGB forms a pixel unit in the form of a triangle, without the need for external algorithm matching.

[0121] In some embodiments of the present disclosure, as shown in FIG. 15, the pixel circuit 200 includes a driving transistor M0, a first transistor M1, a second transistor M2, and a first capacitor C1; wherein the gate of the driving transistor M0 is electrically connected with the first electrode of the first transistor M1, the first electrode of the driving transistor M0 is electrically connected with a second power supply signal line VDD, the second electrode of the driving transistor M0 is electrically connected with the first electrode S1 of the light emitting device L1, L2 arranged in at least two adjacent sub-pixels spx1, spx2; the gate of the first transistor M1 is electrically connected with a gate signal line Ga, the second electrode of the first transistor M1 is electrically connected with a data signal line Da; the gate of the second transistor M2 is electrically connected with the gate signal line Ga, the first electrode of the second transistor M2 is electrically connected with the second electrode of the driving transistor M0, and the second electrode of the second transistor M2 is electrically connected with a compensation signal line SENS; the first electrode of the first capacitor C1 is electrically connected with the gate of the driving transistor M0, and the second electrode of the first capacitor C1 is electrically connected with the second electrode of the driving transistor M0.

[0122] For example, as shown in FIG. 15, the compensation signal line SENS is electrically connected with a reference voltage signal end VREF through a first switch S_REF, and the compensation signal line SENS is electrically connected with a compensation voltage signal end SAMP through a second switch S_SAMP.

[0123] In some embodiments of the present disclosure, as shown in FIG. 15, the first electrode of the light emitting device L1, L2 is an anode, the second electrode of the light emitting device L1, L2 is a cathode, and the active level signal loaded on the first power supply signal line VSS1, VSS2 is a low level signal.

[0124] For example, as shown in FIG. 15, the driving transistor M0 can be an N-type transistor, wherein the first electrode of the driving transistor M0 is the source electrode, the second electrode of the driving transistor M0 is the drain electrode, and when the driving transistor M0 is in the saturation state, the current flows from the drain electrode to the source electrode of the driving transistor M0. Of course, the driving transistor M0 can also be a P-type transistor, which is not limited herein.

[0125] In addition, the light emitting device generally emits light under the action of the current when the driving transistor M0 is in the saturation state. Of course, in the embodiments of the present disclosure, only the case that the driving transistor M0 is an N-type transistor is taken as an example for description, and the design principle is the same as the present disclosure for the case that the driving transistor M0 is a P-type transistor, which also belongs to the protection scope of the present disclosure.

[0126] For example, the first transistor M1 and the second transistor M2 can be turned on under the control of the active level of the gate signal transmitted on the gate signal line Ga, and can be turned off under the control of the inactive level of the gate signal. For example, the first transistor M1 and the second transistor M2 can be N-type transistors, and the active level of the gate signal is high level and the inactive level of the gate signal is low level. Alternatively, the first transistor M1 and the second transistor M2 can be P-type transistors, and the active level of the gate signal is low level and the inactive level of the gate signal is high level.

[0127] For example, the first electrode of the transistor is the source electrode, and the second electrode of the transistor is the drain electrode, or the first electrode of the transistor is the drain electrode, and the second electrode of the transistor is the source electrode.

[0128] Generally, the leakage current of the transistor with metal oxide semiconductor material as the active layer is small, and therefore, in order to reduce the leakage current, in some embodiments of the present disclosure, the material of the active layer of the transistor can include metal oxide semiconductor material, for example, can be IGZO (Indium Gallium Zinc Oxide), and of course, can also be other metal oxide semiconductor material, which is not limited herein. In this way, the transistor can be set as an oxide transistor (Oxide Thin Film Transistor), so as to reduce the leakage current of the pixel circuit.

[0129] Generally, the transistor with the low temperature poly-silicon (LTPS) material as the active layer has high mobility and can be made thinner, smaller, and lower power consumption, etc. In specific implementation, the material of the active layer of the transistor can also be set as the low temperature poly-silicon material. In this way, the transistor can be set as the LTPS transistor, so that the pixel circuit can have high mobility, can be made thinner, smaller, and lower power consumption, etc.

[0130] Exemplarily, all the transistors in the pixel circuit of the present disclosure can be set as the oxide transistor, or all the transistors in the pixel circuit of the present disclosure can be set as the LTPS transistor, or part of the transistors in the pixel circuit of the present disclosure can be set as the oxide transistor, and the other part of the transistors can be set as the LTPS transistor.

[0131] In some embodiments of the present disclosure, as shown in FIG. 16, the driving transistor M0 is a double-gate structure, and the gate of the driving transistor M0 includes a first gate G1 and a second gate G2. The first gate G1 of the driving transistor M0 completely covers the second gate G2 of the driving transistor M0 in the orthographic projection of the substrate 100, and the first gate G1 of the driving transistor M0 is in a floating state. The first gate can have a light shielding effect, which can improve the display effect.

[0132] It should be noted that the second gate G2 of the driving transistor M0 is electrically connected to the first electrode of the first transistor M1.

[0133] In some embodiments of the present disclosure, as shown in FIGS. 16 to 18, the pixel circuit further includes a first conductive layer 210 on the substrate 100, and the first conductive layer 210 includes a data signal line Da and a compensation signal line SENS. The pixel circuit further includes a light shielding layer 211 on the side of the first conductive layer 210 away from the substrate 100, and the light shielding layer 211 includes the first gate G1 of the driving transistor M0. In the present disclosure, the data signal line Da and the compensation signal line SENS are located in the same film layer, so that the number of film layers of the pixel circuit can be reduced by at least one, thereby reducing the process steps and simplifying the process difficulty.

[0134] Exemplarily, the materials of the first conductive layer and the light shielding layer can be conductive materials. For example, the conductive materials can include metal materials or alloy materials such as aluminum, molybdenum, titanium, etc., or can include metal oxides such as indium tin oxide (ITO) and the like. The materials of the film layers are not limited in the embodiments of the present disclosure.

[0135] In some embodiments of the present disclosure, as shown in FIG. 16 and FIGS. 19-23, further comprising: a first semiconductor layer 212 located on the side of the light shielding layer 211 away from the substrate 100, the first semiconductor layer 212 comprising an active layer B0 of the driving transistor M0 and an active layer B1 of the first transistor M1; a gate conductive layer 213 located on the side of the first semiconductor layer 212 away from the substrate 100, the gate conductive layer 213 comprising a gate G3 of the first transistor M1, a gate G4 of the second transistor M2, a second gate G2 of the driving transistor M0, and a first electrode C1-1 of the first capacitor C1; a second conductive layer 214 located on the side of the gate conductive layer 213 away from the substrate 100, the second conductive layer 214 comprising a second electrode C1-2 of the first capacitor C1; a second semiconductor layer 215 located on the side of the second conductive layer 214 away from the substrate 100, the second semiconductor layer 215 comprising an active layer B2 of the second transistor M2; a third conductive layer 216 located on the side of the second semiconductor layer 215 away from the substrate 100, the third conductive layer 216 comprising a second power signal line VDD.

[0136] For example, as shown in FIG. 16, the driving transistor M0 and the first transistor M1 can both adopt a top-gate structure; and the second transistor M2 can adopt a Back Channel Ethced (BCE) structure.

[0137] For example, as shown in FIG. 16 and FIG. 18, the second gate G2 of the driving transistor is shared as the first electrode C1-1 of the first capacitor, thereby saving layout space.

[0138] For example, as shown in FIG. 16 and FIG. 20, the gate signal line Ga is shared as the gate of the first transistor and the gate of the second transistor, thereby saving layout space.

[0139] For example, as shown in FIG. 16 and FIGS. 24-27, further comprising: a buffer layer 220 located between the first conductive layer 210 and the light shielding layer 211; a first gate insulating layer 221 located between the light shielding layer 211 and the first semiconductor layer 212; a second gate insulating layer 222 located between the first semiconductor layer 212 and the gate conductive layer 213; a third gate insulating layer 223 located between the gate conductive layer 213 and the second conductive layer 214; a fourth gate insulating layer 224 located between the second conductive layer 214 and the second semiconductor layer 215; a planarization layer 225 located on the side of the third conductive layer 216 away from the substrate 100; and a passivation layer 226 located on the side of the planarization layer 225 away from the substrate 100.

[0140] For example, the first semiconductor layer and the second semiconductor layer are formed by patterning a semiconductor material, which includes amorphous silicon, polycrystalline silicon, oxide semiconductor material, etc.

[0141] Exemplarily, the first semiconductor layer can be made of a low-temperature polysilicon semiconductor material. The second semiconductor layer can be made of an oxide semiconductor material. That is, the driving transistor and the first transistor are LTPS type transistors, and the second transistor is an oxide type transistor.

[0142] Exemplarily, the material of the gate conductive layer, the second conductive layer and the third conductive layer can be a conductive material. For example, the conductive material can include metal materials such as aluminum, molybdenum, titanium or alloy materials, and can also include metal oxides such as indium tin oxide (ITO) and the like. Embodiments of the present disclosure do not limit the material of each film layer.

[0143] Exemplarily, the material of the buffer layer, the first gate insulating layer, the second gate insulating layer, the third gate insulating layer, the fourth gate insulating layer, the planarization layer and the passivation layer can be an insulating material. According to needs, an organic insulating material such as polyimide, resin material and the like can be selected, or an inorganic insulating material such as silicon oxide, silicon nitride, silicon oxynitride and the like can be selected. Embodiments of the present disclosure do not specifically limit the material of each film layer.

[0144] In some embodiments of the present disclosure, as shown in FIG. 16, the second conductive layer 214 further includes a first adapter Z1, the first adapter Z1 is in the orthographic projection of the substrate 100 and the orthographic projection of the data signal line Da in the substrate 100 overlap; the active layer B1 of the first transistor M1 is electrically connected to the data signal line Da through the first adapter Z1.

[0145] In some embodiments of the present disclosure, as shown in FIG. 16, the third conductive layer 216 further includes a second adapter Z2, the second adapter Z2 is in the orthographic projection of the substrate 100 and the orthographic projection of the second gate G2 of the driving transistor M0 in the substrate 100 overlap; the active layer B1 of the first transistor M1 is electrically connected to the second gate G2 of the driving transistor M0 through the second adapter Z2.

[0146] Exemplarily, the layout structure schematic diagram shown in FIGS. 17 to 25 is shown in FIG. 28, which is a structure schematic diagram of the layout structure schematic diagrams superimposed on each other; FIGS. 29 to 33 are respectively a layout structure schematic diagram of the first electrode layer 10 close to the substrate, a layout structure schematic diagram of the first electrode layer 10 away from the substrate, a layout structure schematic diagram of the pixel definition layer 20, a layout structure schematic diagram of the electroluminescent layer 30 and a layout structure schematic diagram of the second electrode layer 40 in FIG. 16.

[0147] In some embodiments of the present disclosure, as shown in FIG. 28, at least two adjacent sub-pixels spx1, spx2 and a pixel circuit 200 arranged corresponding to the at least two adjacent sub-pixels spx1, spx2 jointly constitute a pixel unit SPX; two pixel units SPX adjacent along the first direction F1 are arranged mirror-symmetrically to each other, and two pixel units SPX adjacent along the second direction F2 are arranged mirror-symmetrically to each other.

[0148] For example, in combination with a 1um signal wire width, a 1um signal wire pitch and a 1.5um via process capability, the first width W1 of the pixel circuit 200 can reach 9.4 microns, and the second width W2 of the pixel circuit 200 can reach 14.1 microns. Since one pixel circuit corresponds to at least two sub-pixels, the size of the sub-pixel is very small, so that the number of sub-pixels in the display panel in the embodiments of the present disclosure can reach twice or even higher multiples of the number of sub-pixels in the existing display panel, that is, the display panel in the embodiments of the present disclosure can realize high resolution.

[0149] In some embodiments of the present disclosure, as shown in FIG. 28, four pixel units SPX adjacent along the first direction F1 and the second direction F2 constitute a pixel arrangement group; the pixel units SPX in each pixel arrangement group share one compensation signal line SENS; two pixel arrangement groups adjacent along the second direction F2 share one second power signal line VDD. Such arrangement can save space, simplify wiring and improve space utilization.

[0150] For example, as shown in FIG. 28, the pixel units SPX adjacent along the first direction F1 share part of the vias; the pixel units SPX adjacent along the second direction F2 share part of the vias; such design can reduce the number of vias and reduce the process difficulty.

[0151] The embodiments of the present disclosure provide a driving method of a display panel, as shown in FIG. 34, comprising:

[0152] S100, in the first light-emitting stage, one of the two first power signal lines is loaded with an effective level signal, and the pixel circuit drives the light-emitting device electrically connected corresponding to the first power signal line to emit light;

[0153] S200, in the second light-emitting stage, the other of the two first power signal lines is loaded with an effective level signal, and the pixel circuit drives the light-emitting device electrically connected corresponding to the first power signal line to emit light.

[0154] Next, taking the pixel circuit shown in FIG. 15 as an example, the working process of the pixel circuit provided by the embodiments of the present disclosure is described in combination with the signal timing diagram shown in FIG. 35.

[0155] As shown in FIG. 35, ga(l) represents the gate signal on the gate signal line Ga in the first row of pixel circuits; ga(2) represents the gate signal on the gate signal line Ga in the second row of pixel circuits; ga(n) represents the gate signal on the gate signal line Ga in the nth row of pixel circuits; da represents the data signal on the data signal line Da; vss1 represents the first power signal on the first power signal line VSS1; vss2 represents the first power signal on the first power signal line VSS2; s_ref represents the first control signal of the first switch S_REF; s_samp represents the second control signal of the second switch S_SAMP; and sens represents the signal on the compensation signal line SENS.

[0156] Further, a display stage H1 and a compensation stage H2 in a display frame are selected; the display stage H1 includes a first light emitting stage H11 and a second light emitting stage H12; the compensation stage H2 includes a reset stage H21, a threshold voltage compensation stage H22, and an extraction stage H23; the first light emitting stage H11 includes a data writing stage H11-1 and a light emitting stage H11-2; and the second light emitting stage H12 includes a data writing stage H12-1 and a light emitting stage H12-2.

[0157] In the data writing stage H11-1 in the first light emitting stage H11, the first switch S_REF is controlled to work under the high level of the first control signal s_ref, and then the compensation signal line SENS transmits the signal of the reference voltage signal end VREF to the second electrode of the second transistor M2; the second switch S_SAMP is controlled to be disconnected under the low level of the second control signal s_samp; the first transistor M1 and the second transistor M2 are controlled to be turned on under the high level of the gate signal, the turned-on first transistor M1 provides the data signal da to the gate of the driving transistor M0, and the turned-on second transistor M2 provides the signal transmitted on the compensation signal line SENS to the second electrode of the driving transistor M0; the data signal is written to the gate of the driving transistor M0 in each row of pixel circuits row by row; and the first power signal vss1 and the first power signal vss2 are both high level signals, i.e., the first power signal vss1 and the first power signal vss2 are both invalid level signals, so that the light emitting device L1 in the sub-pixel spx1 and the light emitting device L2 in the sub-pixel spx2 do not emit light;

[0158] In the light emitting stage H11-2 in the first light emitting stage H11, the first switch S_REF works under the control of the high level of the first control signal s_ref, and the compensation signal line SENS transmits the signal of the reference voltage signal end VREF to the second electrode of the second transistor M2; the second switch S_SAMP is disconnected under the control of the low level of the second control signal s_samp; the first transistor M1 and the second transistor M2 are cut off under the control of the low level of the gate signal; the first power signal vss1 is a low level signal, that is, the first power signal vss1 is an effective level signal, and the driving current generated by the driving transistor M0 passes through the sub-pixel spx1 electrically connected with the first power signal line VSS1, and the light emitting device L1 in the sub-pixel spx1 emits light under the driving of the driving current, that is, the light emitting device L1 emits light; and the first power signal vss2 is a high level signal, that is, the first power signal vss2 is an ineffective level signal, and the light emitting device L2 in the sub-pixel spx2 does not emit light;

[0159] In the data writing stage H12-1 in the second light emitting stage H12, the first switch S_REF works under the control of the high level of the first control signal s_ref, and the compensation signal line SENS transmits the signal of the reference voltage signal end VREF to the second electrode of the second transistor M2; the second switch S_SAMP is disconnected under the control of the low level of the second control signal s_samp; the first transistor M1 and the second transistor M2 are turned on under the control of the high level of the gate signal, the turned-on first transistor M1 provides the data signal da to the gate of the driving transistor M0, and the turned-on second transistor M2 provides the signal transmitted by the compensation signal line SENS to the second electrode of the driving transistor M0; the gate of the driving transistor M0 in each row of pixel circuits is written with the data signal row by row; and the first power signal vss1 and the first power signal vss2 are both high level signals, that is, the first power signal vss1 and the first power signal vss2 are both ineffective level signals, and the light emitting device L1 in the sub-pixel spx1 and the light emitting device L2 in the sub-pixel spx2 do not emit light;

[0160] In the light emitting stage H12-2 in the second light emitting stage H12, the first switch S_REF works under the control of the high level of the first control signal s_ref, and the compensation signal line SENS transmits the signal of the reference voltage signal end VREF to the second electrode of the second transistor M2; the second switch S_SAMP is disconnected under the control of the low level of the second control signal s_samp; the first transistor M1 and the second transistor M2 are cut off under the control of the low level of the gate signal; the first power signal vss2 is a low level signal, that is, the first power signal vss2 is an effective level signal, and the driving current generated by the driving transistor M0 passes through the sub-pixel spx2 electrically connected with the first power signal line VSS2, and the light emitting device L2 in the sub-pixel spx2 emits light under the driving of the driving current, that is, the light emitting device L2 emits light; and the first power signal vss1 is a high level signal, that is, the first power signal vss1 is an invalid level signal, and the light emitting device L1 in the sub-pixel spx1 does not emit light.

[0161] In the reset stage H21, the first switch S_REF works under the control of the high level of the first control signal s_ref, and the compensation signal line SENS transmits the signal of the reference voltage signal end VREF to the second electrode of the second transistor M2; the second switch S_SAMP is disconnected under the control of the low level of the second control signal s_samp; the first transistor M1 and the second transistor M2 are turned on under the control of the high level of the gate signal, the turned-on first transistor M1 provides the data signal da to the gate of the driving transistor M0, and the turned-on second transistor M2 provides the signal transmitted by the compensation signal line SENS to the second electrode of the driving transistor M0, so as to reset the gate of the driving transistor M0 and the second electrode of the driving transistor M0.

[0162] In the threshold voltage compensation stage H22, the first switch S_REF is disconnected under the control of the low level of the first control signal s_ref; the second switch S_SAMP is disconnected under the control of the low level of the second control signal s_samp; the first transistor M1 and the second transistor M2 are turned on under the control of the high level of the gate signal, the turned-on first transistor M1 provides the data signal da to the gate of the driving transistor M0, and the turned-on second transistor M2 provides the signal transmitted by the compensation signal line SENS to the second electrode of the driving transistor M0, and the second electrode of the driving transistor M0 is charged to write the threshold voltage Vth, so that the voltage of the second electrode of the driving transistor M0 is Vda-Vth; wherein Vda represents the voltage of the data signal da.

[0163] In the extraction stage H23, the first switch S_REF is turned off under the control of the low level of the first control signal s_ref; the second switch S_SAMP is turned on under the control of the high level of the second control signal s_samp, so that the compensation signal line SENS transmits the signal of the compensation voltage signal end SAMP to the second electrode of the second transistor M2; the first transistor M1 and the second transistor M2 are turned on under the control of the high level of the gate signal, the turned-on first transistor M1 provides the data signal da to the gate of the driving transistor M0, and the turned-on second transistor M2 provides the signal transmitted on the compensation signal line SENS to the second electrode of the driving transistor M0, so as to perform the extraction of the threshold voltage Vth.

[0164] The embodiment of the present disclosure provides another structural schematic diagram of a pixel circuit, as shown in FIG. 36, which is a variation of the implementation in the above-mentioned embodiment. Only the differences between the present embodiment and the above-mentioned embodiment are described below, and the same parts are not described herein.

[0165] In some embodiments of the present disclosure, as shown in FIG. 36, the gate of the driving transistor M0 is electrically connected with the first electrode of the first transistor M1, the first electrode of the driving transistor M0 is electrically connected with the second power signal line VSS, and the second electrode of the driving transistor M0 is electrically connected with the first electrode of the light emitting device L1, L2 in the at least two adjacent sub-pixels spx1, spx2.

[0166] In some embodiments of the present disclosure, as shown in FIG. 36, the first electrode of the light emitting device L1, L2 is a cathode, and the second electrode of the light emitting device L1, L2 is an anode; and the effective level signal loaded on the first power signal line VDD1, VDD2 is a high level signal.

[0167] For example, as shown in FIG. 36, the driving transistor M0, the first transistor M1 and the second transistor M2 are all P-type transistors.

[0168] The working process of the pixel circuit provided by the embodiment of the present disclosure is described below by taking the pixel circuit shown in FIG. 36 as an example and in combination with the signal timing diagram shown in FIG. 37.

[0169] As shown in FIG. 37, ga(l) represents the gate signal on the gate signal line Ga in the first row of pixel circuits; ga(2) represents the gate signal on the gate signal line Ga in the second row of pixel circuits; ga(n) represents the gate signal on the gate signal line Ga in the nth row of pixel circuits; da represents the data signal on the data signal line Da; vdd1 represents the first power signal on the first power signal line VDD1; vdd2 represents the first power signal on the first power signal line VDD2; s_ref represents the first control signal of the first switch S_REF; s_samp represents the second control signal of the second switch S_SAMP; and sens represents the signal on the compensation signal line SENS.

[0170] Further, a display stage H1 and a compensation stage H2 in one display frame are selected; the display stage H1 includes a first light emitting stage H11 and a second light emitting stage H12; the compensation stage H2 includes a reset stage H21, a threshold voltage compensation stage H22, and an extraction stage H23; the first light emitting stage H11 includes a data writing stage H11-1 and a light emitting stage H11-2; and the second light emitting stage H12 includes a data writing stage H12-1 and a light emitting stage H12-2.

[0171] In the data writing stage H11-1 in the first light emitting stage H11, the first switch S_REF is controlled to work under the low level of the first control signal s_ref, and then the compensation signal line SENS transmits the signal of the reference voltage signal end VREF to the second electrode of the second transistor M2; the second switch S_SAMP is controlled to be disconnected under the high level of the second control signal s_samp; the first transistor M1 and the second transistor M2 are controlled to be turned on under the low level of the gate signal, the turned-on first transistor M1 provides the data signal da to the gate of the driving transistor M0, and the turned-on second transistor M2 provides the signal transmitted on the compensation signal line SENS to the second electrode of the driving transistor M0; the data signal is written to the gate of the driving transistor M0 in each row of pixel circuits row by row; and the first power signal vdd1 and the first power signal vdd2 are both low level signals, i.e., the first power signal vdd1 and the first power signal vdd2 are both invalid level signals, so that the light emitting device L1 in the sub-pixel spx1 and the light emitting device L2 in the sub-pixel spx2 do not emit light;

[0172] In the light emitting stage H11-2 in the first light emitting stage H11, the first switch S_REF works under the control of the low level of the first control signal s_ref, and the compensation signal line SENS transmits the signal of the reference voltage signal end VREF to the second electrode of the second transistor M2; the second switch S_SAMP is disconnected under the control of the high level of the second control signal s_samp; the first transistor M1 and the second transistor M2 are cut off under the control of the high level of the gate signal; the first power signal vdd1 is a high level signal, that is, the first power signal vdd1 is an effective level signal, and the driving current generated by the driving transistor M0 passes through the sub-pixel spx1 electrically connected with the first power signal line VDD1, and the light emitting device L1 in the sub-pixel spx1 emits light under the driving of the driving current, that is, the light emitting device L1 emits light; and the first power signal vdd2 is a low level signal, that is, the first power signal vdd2 is an ineffective level signal, and the light emitting device L2 in the sub-pixel spx2 does not emit light;

[0173] In the data writing stage H12-1 in the second light emitting stage H12, the first switch S_REF works under the control of the low level of the first control signal s_ref, and the compensation signal line SENS transmits the signal of the reference voltage signal end VREF to the second electrode of the second transistor M2; the second switch S_SAMP is disconnected under the control of the high level of the second control signal s_samp; the first transistor M1 and the second transistor M2 are turned on under the control of the low level of the gate signal, the turned-on first transistor M1 provides the data signal da to the gate of the driving transistor M0, and the turned-on second transistor M2 provides the signal transmitted by the compensation signal line SENS to the second electrode of the driving transistor M0; the gate of the driving transistor M0 in each row of pixel circuits is written with the data signal row by row; and the first power signal vdd1 and the first power signal vdd2 are both low level signals, that is, the first power signal vdd1 and the first power signal vdd2 are both ineffective level signals, and the light emitting device L1 in the sub-pixel spx1 and the light emitting device L2 in the sub-pixel spx2 do not emit light;

[0174] In the light emitting stage H12-2 in the second light emitting stage H12, the first switch S_REF works under the control of the low level of the first control signal s_ref, and the compensation signal line SENS transmits the signal of the reference voltage signal end VREF to the second electrode of the second transistor M2; the second switch S_SAMP is disconnected under the control of the high level of the second control signal s_samp; the first transistor M1 and the second transistor M2 are cut off under the control of the high level of the gate signal; the first power signal vdd2 is a high level signal, that is, the first power signal vdd2 is an effective level signal, and the driving current generated by the driving transistor M0 passes through the sub-pixel spx2 electrically connected with the first power signal line VDD2, and the light emitting device L2 in the sub-pixel spx2 emits light under the driving of the driving current, that is, the light emitting device L2 emits light; and the first power signal vdd1 is a low level signal, that is, the first power signal vdd1 is an ineffective level signal, and the light emitting device L1 in the sub-pixel spx1 does not emit light.

[0175] In the reset stage H21, the first switch S_REF works under the control of the low level of the first control signal s_ref, and the compensation signal line SENS transmits the signal of the reference voltage signal end VREF to the second electrode of the second transistor M2; the second switch S_SAMP is disconnected under the control of the high level of the second control signal s_samp; the first transistor M1 and the second transistor M2 are turned on under the control of the low level of the gate signal, the turned-on first transistor M1 provides the data signal da to the gate of the driving transistor M0, and the turned-on second transistor M2 provides the signal transmitted by the compensation signal line SENS to the second electrode of the driving transistor M0, so as to reset the gate of the driving transistor M0 and the second electrode of the driving transistor M0.

[0176] In the threshold voltage compensation stage H22, the first switch S_REF is disconnected under the control of the high level of the first control signal s_ref; the second switch S_SAMP is disconnected under the control of the high level of the second control signal s_samp; the first transistor M1 and the second transistor M2 are turned on under the control of the low level of the gate signal, the turned-on first transistor M1 provides the data signal da to the gate of the driving transistor M0, and the turned-on second transistor M2 provides the signal transmitted by the compensation signal line SENS to the second electrode of the driving transistor M0, and the second electrode of the driving transistor M0 is charged to write the threshold voltage Vth, so that the voltage of the second electrode of the driving transistor M0 is Vda-Vth; wherein Vda represents the voltage of the data signal da.

[0177] In the extraction stage H23, the first switch S_REF is turned off under the control of the high level of the first control signal s_ref; the second switch S_SAMP is turned on under the control of the low level of the second control signal s_samp, so that the compensation signal line SENS transmits the signal of the compensation voltage signal end SAMP to the second electrode of the second transistor M2; the first transistor M1 and the second transistor M2 are turned on under the control of the high level of the gate signal, the turned-on first transistor M1 provides the data signal da to the gate of the driving transistor M0, and the turned-on second transistor M2 provides the signal transmitted by the compensation signal line SENS to the second electrode of the driving transistor M0, so as to perform the extraction of the threshold voltage Vth.

[0178] The embodiment of the present disclosure provides another structural schematic diagram of the pixel circuit, as shown in FIG. 38, which is a transformation of the implementation in the above-mentioned embodiment. The differences between the present embodiment and the above-mentioned embodiment are described below, and the same parts are not described herein.

[0179] For example, as shown in FIG. 38, the driving transistor M0 is a P-type transistor; the first transistor M1 and the second transistor M2 are both N-type transistors.

[0180] In another embodiment of the present disclosure, the 3T1C pixel circuit shown in FIG. 15, FIG. 36 and FIG. 38 is also applicable to a display panel of micro light emitting diode combined with active matrix (AM) driving technology, and FIG. 39 is a schematic diagram of the stacking structure of the display panel of micro light emitting diode combined with active matrix driving technology.

[0181] Exemplarily, as shown in FIG. 36, the display panel comprises: a barrier layer 510 on the substrate 100; a light shielding layer 410 on the side of the barrier layer 510 away from the substrate 100; a buffer layer 511 on the side of the light shielding layer 410 away from the substrate 100; a first semiconductor layer 411 on the side of the buffer layer 511 away from the substrate 100; a first gate insulating layer 512 on the side of the first semiconductor layer 411 away from the substrate 100; a first gate conductive layer 412 on the side of the first gate insulating layer 512 away from the substrate 100; a second gate insulating layer 513 on the side of the first gate conductive layer 412 away from the substrate 100; a second gate conductive layer 413 on the side of the second gate insulating layer 513 away from the substrate 100; a first interlayer insulating layer 514 on the side of the second gate conductive layer 413 away from the substrate 100; a second semiconductor layer 414 on the side of the first interlayer insulating layer 514 away from the substrate 100; a third gate insulating layer 515 on the side of the second semiconductor layer 414 away from the substrate 100; a third gate conductive layer 415 on the side of the third gate insulating layer 515 away from the substrate 100; a second interlayer insulating layer 516 on the side of the third gate conductive layer 415 away from the substrate 100; a first conductive layer 416 on the side of the second interlayer insulating layer 516 away from the substrate 100; a first planar layer 517 on the side of the first conductive layer 416 away from the substrate 100; a first passivation layer 518 on the side of the first planar layer 517 away from the substrate 100; a second conductive layer 417 on the side of the first passivation layer 518 away from the substrate 100; a second passivation layer 519 on the side of the second conductive layer 417 away from the substrate 100; a second planar layer 520 on the side of the second passivation layer 519 away from the substrate 100.

[0182] Exemplarily, the first semiconductor layer and the second semiconductor layer are formed by patterning semiconductor material, and the semiconductor material includes amorphous silicon, polycrystalline silicon, oxide semiconductor material, etc.

[0183] Exemplarily, the materials of the light shielding layer, the first gate conductive layer, the second gate conductive layer, the third gate conductive layer, the first conductive layer and the second conductive layer can be conductive materials. For example, the conductive materials can include metal materials or alloy materials such as aluminum, molybdenum, titanium, copper, silver, magnesium, etc., and can also include metal oxides such as indium tin oxide (ITO) and other materials. The embodiments of the present disclosure do not limit the materials of the film layers.

[0184] Exemplarily, the materials of the barrier layer, the buffer layer, the first gate insulating layer, the second gate insulating layer, the third gate insulating layer, the first interlayer insulating layer, the second interlayer insulating layer, the first planarization layer, the second planarization layer, the first passivation layer and the second passivation layer can be insulating materials, and can be selected as organic insulating materials such as polyimide, resin materials and the like, or inorganic insulating materials such as silicon oxide, silicon nitride, silicon oxynitride and the like, and the embodiments of the present disclosure do not make specific limitations on the materials of the film layers.

[0185] In some other embodiments of the present disclosure, the pixel circuit can also adopt a 7T1C structure, as shown in FIG. 40, the pixel circuit 200 includes a driving transistor M0, a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, a fifth transistor M5, a sixth transistor M6 and a first capacitor C1; wherein the gate of the driving transistor M0 is electrically connected with the first electrode of the first capacitor C1, the first electrode of the driving transistor M0 is electrically connected with the second electrode of the fourth transistor M4, and the second electrode of the driving transistor M0 is electrically connected with the first electrode of the fifth transistor M5; the gate of the first transistor M1 is electrically connected with a first reset signal terminal RSMA, the first electrode of the first transistor M1 is electrically connected with an initialization signal terminal Vinit, and the second electrode of the first transistor M1 is electrically connected with the first electrode of the first capacitor C1; the gate of the second transistor M2 is electrically connected with a gate signal line Ga, the first electrode of the second transistor M2 is electrically connected with the first electrode of the fifth transistor M5, and the second electrode of the second transistor M2 is electrically connected with a data signal line Da; the gate of the third transistor M3 is electrically connected with the gate signal line Ga, the first electrode of the third transistor M3 is electrically connected with the first electrode of the first capacitor C1, and the second electrode of the third transistor M3 is electrically connected with the first electrode of the driving transistor M0; the gate of the fourth transistor M4 is electrically connected with an emission control signal terminal EM, the first electrode of the fourth transistor M4 is electrically connected with the first electrode of the light emitting device L1, L2 in the at least two adjacent sub-pixels spx1, spx2; the gate of the fifth transistor M5 is electrically connected with the emission control signal terminal EM, and the second electrode of the fifth transistor M5 is electrically connected with a second power signal line VSS; the gate of the sixth transistor M6 is electrically connected with a second reset signal terminal RSMB, the first electrode of the sixth transistor M6 is electrically connected with the initialization signal terminal Vinit, and the second electrode of the sixth transistor M6 is electrically connected with the first electrode of the fourth transistor M4; and the second electrode of the first capacitor C1 is electrically connected with the second power signal line VSS.

[0186] Exemplarily, as shown in FIG. 40, the driving transistor M0, the first transistor M1, the second transistor M2, the third transistor M3, the fourth transistor M4, the fifth transistor M5 and the sixth transistor M6 are all N-type transistors.

[0187] For example, as shown in FIG. 40, the first electrode of the light emitting device L1 and L2 is a cathode, the second electrode of the light emitting device L1 and L2 is an anode, and the active level signal loaded on the first power signal line VDD1 and VDD2 is a high level signal.

[0188] Next, taking the pixel circuit shown in FIG. 40 as an example, the working process of the pixel circuit provided in the embodiment of the present disclosure is described in combination with the signal timing diagram shown in FIG. 41.

[0189] As shown in FIG. 41, em represents the light emitting control signal on the light emitting control signal end EM; rsta(1) represents the first reset signal on the first reset signal end RSMA in the first row of pixel circuits; rsta(n) represents the first reset signal on the first reset signal end RSMA in the nth row of pixel circuits; rstb(1) represents the second reset signal on the second reset signal end RSMB in the first row of pixel circuits; rstb(n) represents the second reset signal on the second reset signal end RSMB in the nth row of pixel circuits; ga(1) represents the gate signal on the gate signal line Ga in the first row of pixel circuits; ga(n) represents the gate signal on the gate signal line Ga in the nth row of pixel circuits; vdd1 represents the first power signal on the first power signal line VDD1; vdd2 represents the first power signal on the first power signal line VDD2; and da represents the data signal on the data signal line Da.

[0190] Further, a first light emitting stage H11 and a second light emitting stage H12 in a display frame 1H are selected; wherein the first light emitting stage H11 includes a data writing stage H11-1 and a light emitting stage H11-2; and the second light emitting stage H12 includes a data writing stage H12-1 and a light emitting stage H12-2.

[0191] In the data writing stage H11-1 in the first light emitting stage H11, the first transistor M1 is turned on under the control of the high level of the first reset signal; the second transistor M2 is turned on under the control of the high level of the gate signal; the third transistor M3 is turned on under the control of the high level of the gate signal; the fourth transistor M4 is turned off under the control of the low level of the light emitting control signal; the fifth transistor M5 is turned off under the control of the low level of the light emitting control signal; the sixth transistor M6 is turned on under the control of the high level of the second reset signal; the turned-on first transistor M1 provides the signal of the initialization signal terminal Vinit to the first electrode of the third transistor M3; the turned-on second transistor M2 provides the data signal da to the second electrode of the driving transistor M0; the turned-on third transistor M3 provides the signal of the initialization signal terminal Vinit on the first electrode to the first electrode of the driving transistor M0; the turned-on sixth transistor M6 provides the signal of the initialization signal terminal Vinit to the first electrode of the light emitting device L1, L2; and the first power signal vdd1 and the first power signal vdd2 are both low level signals, i.e., the first power signal vdd1 and the first power signal vdd2 are both invalid level signals, so that the light emitting device L1 in the sub-pixel spx1 and the light emitting device L2 in the sub-pixel spx2 do not emit light;

[0192] In the light emitting stage H11-2 in the first light emitting stage H11, the first transistor M1 is turned off under the control of the low level of the first reset signal; the second transistor M2 is turned off under the control of the low level of the gate signal; the third transistor M3 is turned off under the control of the low level of the gate signal; the fourth transistor M4 is turned on under the control of the high level of the light emitting control signal; the fifth transistor M5 is turned on under the control of the high level of the light emitting control signal; the sixth transistor M6 is turned off under the control of the low level of the second reset signal; the turned-on fourth transistor M4 connects the first electrode of the driving transistor M0 with the first electrode of the light emitting device L1, L2 in the at least two adjacent sub-pixels spx1, spx2; the turned-on fifth transistor M5 connects the second electrode of the driving transistor M0 with the second power signal line VSS; the first power signal vdd1 is a high level signal, i.e., the first power signal vdd1 is a valid level signal, so that the driving current generated by the driving transistor M0 passes through the sub-pixel spx1 electrically connected with the first power signal line VDD1, and the light emitting device L1 in the sub-pixel spx1 emits light under the driving of the driving current, i.e., the light emitting device L1 emits light; and the first power signal vdd2 is a low level signal, i.e., the first power signal vdd2 is an invalid level signal, so that the light emitting device L2 in the sub-pixel spx2 does not emit light;

[0193] In the data writing stage H12-1 in the second light emitting stage H12, the first transistor M1 is turned on under the control of the high level of the first reset signal; the second transistor M2 is turned on under the control of the high level of the gate signal; the third transistor M3 is turned on under the control of the high level of the gate signal; the fourth transistor M4 is turned off under the control of the low level of the light emitting control signal; the fifth transistor M5 is turned off under the control of the low level of the light emitting control signal; the sixth transistor M6 is turned on under the control of the high level of the second reset signal; the turned-on first transistor M1 provides the signal of the initialization signal terminal Vinit to the first electrode of the third transistor M3; the turned-on second transistor M2 provides the data signal da to the second electrode of the driving transistor M0; the turned-on third transistor M3 provides the signal of the initialization signal terminal Vinit on the first electrode to the first electrode of the driving transistor M0; the turned-on sixth transistor M6 provides the signal of the initialization signal terminal Vinit to the first electrode of the light emitting device L1, L2; and the first power signal vdd1 and the first power signal vdd2 are both low level signals, i.e., the first power signal vdd1 and the first power signal vdd2 are both invalid level signals, so that the light emitting device L1 in the sub-pixel spx1 and the light emitting device L2 in the sub-pixel spx2 do not emit light.

[0194] In the light emitting stage H12-2 in the second light emitting stage H12, the first transistor M1 is turned off under the control of the low level of the first reset signal; the second transistor M2 is turned off under the control of the low level of the gate signal; the third transistor M3 is turned off under the control of the low level of the gate signal; the fourth transistor M4 is turned on under the control of the high level of the light emitting control signal; the fifth transistor M5 is turned on under the control of the high level of the light emitting control signal; the sixth transistor M6 is turned off under the control of the low level of the second reset signal; the turned-on fourth transistor M4 connects the first electrode of the driving transistor M0 with the first electrode of the light emitting device L1, L2 in the at least two adjacent sub-pixels spx1, spx2; the turned-on fifth transistor M5 connects the second electrode of the driving transistor M0 with the second power signal line VSS; the first power signal vdd2 is a high level signal, i.e., the first power signal vdd2 is a valid level signal, so that the driving current generated by the driving transistor M0 passes through the sub-pixel spx2 electrically connected with the first power signal line VDD1, and the light emitting device L2 in the sub-pixel spx2 emits light under the driving of the driving current, i.e., the light emitting device L2 emits light; and the first power signal vdd1 is a low level signal, i.e., the first power signal vdd1 is an invalid level signal, so that the light emitting device L1 in the sub-pixel spx1 does not emit light.

[0195] The embodiment of the present disclosure provides still another structural diagram of the pixel circuit, as shown in Fig. 42, which is a variant of the implementation in the above embodiment. The following only describes the difference between the present embodiment and the above embodiment, and the same parts are not described here.

[0196] In some other embodiments of the present disclosure, as shown in Fig. 42, the gate of the fifth transistor M5 is electrically connected with the light-emitting control signal terminal EM, and the second electrode of the fifth transistor M5 is electrically connected with the second power signal line VDD; and the second electrode of the first capacitor C1 is electrically connected with the second power signal line VDD.

[0197] For example, as shown in Fig. 42, the driving transistor M0, the first transistor M1, the second transistor M2, the third transistor M3, the fourth transistor M4, the fifth transistor M5 and the sixth transistor M6 are all P-type transistors.

[0198] For example, as shown in Fig. 42, the first electrode of the light-emitting device L1 and L2 is an anode, and the second electrode of the light-emitting device L1 and L2 is a cathode; and the effective level signal loaded on the first power signal line VSS1 and VSS2 is a low level signal.

[0199] The working process of the pixel circuit provided by the embodiment of the present disclosure is described below by taking the pixel circuit shown in Fig. 42 as an example in combination with the signal timing diagram shown in Fig. 43.

[0200] As shown in Fig. 43, em represents the light-emitting control signal on the light-emitting control signal terminal EM; rsta(1) represents the first reset signal on the first reset signal terminal RSMA in the first row of pixel circuits; rsta(n) represents the first reset signal on the first reset signal terminal RSMA in the nth row of pixel circuits; rstb(1) represents the second reset signal on the second reset signal terminal RSMB in the first row of pixel circuits; rstb(n) represents the second reset signal on the second reset signal terminal RSMB in the nth row of pixel circuits; ga(1) represents the gate signal on the gate signal line Ga in the first row of pixel circuits; ga(n) represents the gate signal on the gate signal line Ga in the nth row of pixel circuits; vss1 represents the first power signal on the first power signal line VSS1; vss2 represents the first power signal on the first power signal line VSS2; and da represents the data signal on the data signal line Da.

[0201] Furthermore, the first light-emitting stage H11 and the second light-emitting stage H12 in a display frame 1H are selected; wherein the first light-emitting stage H11 includes a data writing stage H11-1 and a light-emitting stage H11-2; and the second light-emitting stage H12 includes a data writing stage H12-1 and a light-emitting stage H12-2.

[0202] In the data writing stage H11-1 in the first light emitting stage H11, the first transistor M1 is turned on under the control of the low level of the first reset signal; the second transistor M2 is turned on under the control of the low level of the gate signal; the third transistor M3 is turned on under the control of the low level of the gate signal; the fourth transistor M4 is turned off under the control of the high level of the light emitting control signal; the fifth transistor M5 is turned off under the control of the high level of the light emitting control signal; the sixth transistor M6 is turned on under the control of the low level of the second reset signal; the turned-on first transistor M1 provides the signal of the initialization signal terminal Vinit to the first electrode of the third transistor M3; the turned-on second transistor M2 provides the data signal da to the second electrode of the driving transistor M0; the turned-on third transistor M3 provides the signal of the initialization signal terminal Vinit on the first electrode to the first electrode of the driving transistor M0; the turned-on sixth transistor M6 provides the signal of the initialization signal terminal Vinit to the first electrode of the light emitting device L1, L2; and the first power signal vss1 and the first power signal vss2 are both high level signals, i.e., the first power signal vss1 and the first power signal vss2 are both invalid level signals, so that the light emitting device L1 in the sub-pixel spx1 and the light emitting device L2 in the sub-pixel spx2 do not emit light;

[0203] In the light emitting stage H11-2 in the first light emitting stage H11, the first transistor M1 is turned off under the control of the high level of the first reset signal; the second transistor M2 is turned off under the control of the high level of the gate signal; the third transistor M3 is turned off under the control of the high level of the gate signal; the fourth transistor M4 is turned on under the control of the low level of the light emitting control signal; the fifth transistor M5 is turned on under the control of the low level of the light emitting control signal; the sixth transistor M6 is turned off under the control of the high level of the second reset signal; the turned-on fourth transistor M4 connects the first electrode of the driving transistor M0 with the first electrode of the light emitting device L1, L2 in the at least two adjacent sub-pixels spx1, spx2; the turned-on fifth transistor M5 connects the second electrode of the driving transistor M0 with the second power signal line VDD; the first power signal vss1 is a low level signal, i.e., the first power signal vss1 is a valid level signal, so that the driving current generated by the driving transistor M0 passes through the sub-pixel spx1 electrically connected with the first power signal line VSS1, and the light emitting device L1 in the sub-pixel spx1 emits light under the driving of the driving current, i.e., the light emitting device L1 emits light; and the first power signal vss2 is a high level signal, i.e., the first power signal vss2 is an invalid level signal, so that the light emitting device L2 in the sub-pixel spx2 does not emit light;

[0204] In the data writing stage H12-1 in the second light emitting stage H12, the first transistor M1 is turned on under the control of the low level of the first reset signal; the second transistor M2 is turned on under the control of the low level of the gate signal; the third transistor M3 is turned on under the control of the low level of the gate signal; the fourth transistor M4 is turned off under the control of the high level of the light emitting control signal; the fifth transistor M5 is turned off under the control of the high level of the light emitting control signal; the sixth transistor M6 is turned on under the control of the low level of the second reset signal; the turned-on first transistor M1 provides the signal of the initialization signal terminal Vinit to the first electrode of the third transistor M3; the turned-on second transistor M2 provides the data signal da to the second electrode of the driving transistor M0; the turned-on third transistor M3 provides the signal of the initialization signal terminal Vinit on the first electrode to the first electrode of the driving transistor M0; the turned-on sixth transistor M6 provides the signal of the initialization signal terminal Vinit to the first electrode of the light emitting device L1, L2; and the first power signal vss1 and the first power signal vss2 are both high level signals, i.e., the first power signal vss1 and the first power signal vss2 are both invalid level signals, so that the light emitting device L1 in the sub-pixel spx1 and the light emitting device L2 in the sub-pixel spx2 do not emit light.

[0205] In the light emitting stage H12-2 in the second light emitting stage H12, the first transistor M1 is turned off under the control of the high level of the first reset signal; the second transistor M2 is turned off under the control of the high level of the gate signal; the third transistor M3 is turned off under the control of the high level of the gate signal; the fourth transistor M4 is turned on under the control of the low level of the light emitting control signal; the fifth transistor M5 is turned on under the control of the low level of the light emitting control signal; the sixth transistor M6 is turned off under the control of the high level of the second reset signal; the turned-on fourth transistor M4 connects the first electrode of the driving transistor M0 with the first electrode of the light emitting device L1, L2 in the at least two adjacent sub-pixels spx1, spx2; the turned-on fifth transistor M5 connects the second electrode of the driving transistor M0 with the second power signal line VDD; the first power signal vss2 is a low level signal, i.e., the first power signal vss2 is a valid level signal, so that the driving current generated by the driving transistor M0 passes through the sub-pixel spx2 electrically connected with the first power signal line VSS2, and the light emitting device L2 in the sub-pixel spx2 emits light under the driving of the driving current, i.e., the light emitting device L2 emits light; and the first power signal vss1 is a high level signal, i.e., the first power signal vss1 is an invalid level signal, so that the light emitting device L1 in the sub-pixel spx1 does not emit light.

[0206] It should be noted that the embodiments of the present disclosure are not limited to the structure of the pixel circuit described above, and the pixel circuit can also be of a structure of 8T1C / 4T2C / 5T1C, which is not limited here.

[0207] In the above embodiments, the signals of the first power signal line and the second power signal line in the display panel are provided to the entire display panel, and the display panel as a whole emits light after all the pixel circuits in the display panel complete data signal writing, which has a certain waiting time and cannot accurately control the light emitting devices in each row to emit light.

[0208] In some embodiments of the present disclosure, as shown in FIG. 42, the signals of the first power signal line VSS1 and the first power signal line VSS2 in the pixel circuit 200 can be provided by a shift register, so that the first power signals on the first power signal line VSS1 and the first power signal line VSS2 can be written into the first electrodes of the light emitting devices L1 and L2 connected thereto row by row, so that the light emitting devices can be driven to emit light row by row.

[0209] For example, as shown in the signal timing diagram in FIG. 44, em(n) represents the light emitting control signal on the light emitting control signal end EM in the first row of pixel circuits; rsta(1) represents the first reset signal on the first reset signal end RSMA in the first row of pixel circuits; rsta(n) represents the first reset signal on the first reset signal end RSMA in the nth row of pixel circuits; rstb(1) represents the second reset signal on the second reset signal end RSMB in the first row of pixel circuits; rstb(n) represents the second reset signal on the second reset signal end RSMB in the nth row of pixel circuits; ga(1) represents the gate signal on the gate signal line Ga in the first row of pixel circuits; ga(n) represents the gate signal on the gate signal line Ga in the nth row of pixel circuits; da represents the data signal on the data signal line Da; vss1(1) represents the first power signal on the first power signal line VSS1 in the first row of pixel circuits; vss1(n) represents the first power signal on the first power signal line VSS1 in the nth row of pixel circuits; vss2(1) represents the first power signal on the first power signal line VSS2 in the first row of pixel circuits; and vss2(n) represents the first power signal on the first power signal line VSS2 in the nth row of pixel circuits.

[0210] Further, a first light emitting stage H11 and a second light emitting stage H12 in a display frame 1H are selected; the first light emitting stage H11 includes a data writing stage H11-1 and a light emitting stage H11-2; and the second light emitting stage H12 includes a data writing stage H12-1 and a light emitting stage H12-2.

[0211] When the pixel circuit 200 is driven by the signal timing shown in FIG. 44, the data signal of each row of pixel circuits 200 can be guaranteed to emit light immediately after being written, without waiting for the data signal writing of all pixel circuits in the display panel to be completed before being able to emit light; and the light emitting device can also be driven row by row to emit light, to achieve more precise control of the display and improve the display effect. However, the service life of the shift register may

[0212] For example, the shift register is arranged in a non-display area of the display panel, and the pixel circuit is arranged in a display area of the display panel. The shift register provides a signal to the first power signal line in the display area, and the shift register will be consumed.

[0213] In order to improve the service life of the shift register, as shown in FIG. 45, the display panel further includes a signal control circuit 300, which includes a first control transistor T11, a second control transistor T12, a third control transistor T13, and a fourth control transistor T14. The gate of the first control transistor T11 is electrically connected to a first control signal end EMB, the first electrode of the first control transistor T11 is electrically connected to a first voltage level signal end VGH, and the second electrode of the first control transistor T11 is electrically connected to a first power signal line VSS1. The gate of the second control transistor T12 is electrically connected to a second control signal end EMA, the first electrode of the second control transistor T12 is electrically connected to the first power signal line VSS1, and the second electrode of the second control transistor T12 is electrically connected to a second voltage level signal end VGL. The gate of the third control transistor T13 is electrically connected to a third control signal end EMD, the first electrode of the third control transistor T13 is electrically connected to the first voltage level signal end VGH, and the second electrode of the third control transistor T13 is electrically connected to a second power signal line VSS2. The gate of the fourth control transistor T14 is electrically connected to a fourth control signal end EMC, the first electrode of the fourth control transistor T14 is electrically connected to the first power signal line VSS2, and the second electrode of the fourth control transistor T14 is electrically connected to the second voltage level signal end VGL.

[0214] For example, the signal of the first voltage level signal end VGH is a high-level signal, and the signal of the second voltage level signal end VGL is a low-level signal.

[0215] The working process of the signal control circuit provided by the present disclosure will be described below with reference to the signal control circuit shown in FIG. 45 and the signal timing diagram shown in FIG. 46.

[0216] As shown in FIG. 46, ema represents a signal of the second control signal terminal EMA; emb represents a signal of the first control signal terminal EMB; emc represents a signal of the fourth control signal terminal EMC; emd represents a signal of the third control signal terminal EMD; vss1 represents a first power signal of the first power signal line VSS1; and vss2 represents a first power signal of the first power signal line VSS2.

[0217] In the first stage V1, the first control transistor T11 is turned off under the control of the high level of the emb signal; the second control transistor T12 is turned on under the control of the low level of the ema signal; the third control transistor T13 is turned on under the control of the low level of the emd signal; the fourth control transistor T14 is turned off under the control of the high level of the emc signal; the turned-on second control transistor T12 provides the signal of the second level signal terminal VGL to the first power signal line VSS1, and the signal on the first power signal line VSS1 is a low level signal. The turned-on third control transistor T13 provides the signal of the first level signal terminal VGH to the first power signal line VSS2, and the signal on the first power signal line VSS2 is a high level signal.

[0218] In the second stage V2, the first control transistor T11 is turned on under the control of the low level of the emb signal; the second control transistor T12 is turned off under the control of the high level of the ema signal; the third control transistor T13 is turned off under the control of the high level of the emd signal; the fourth control transistor T14 is turned on under the control of the low level of the emc signal; the turned-on first control transistor T11 provides the signal of the first level signal terminal VGH to the first power signal line VSS1, and the signal on the first power signal line VSS1 is a high level signal. The turned-on fourth control transistor T14 provides the signal of the second level signal terminal VGL to the first power signal line VSS2, and the signal on the first power signal line VSS2 is a low level signal.

[0219] The display panel provided by the embodiment of the present disclosure can be applied to a display device. The display device provided by the embodiment of the present disclosure comprises the display panel provided by the embodiment of the present disclosure. The display device solves the problem in the prior art in the same way as the display panel, and therefore the implementation of the display device can be referred to the implementation of the display panel, and the repeated parts will not be described here.

[0220] The display device provided by the embodiments of the present disclosure comprises a display panel, and the display area of the display panel comprises a plurality of pixel units arranged in an array, and each pixel unit can comprise a plurality of sub-pixels. For example, each pixel unit comprises a red sub-pixel, a green sub-pixel and a blue sub-pixel, so that color display can be realized by mixing red, green and blue. Alternatively, each pixel unit can comprise a red sub-pixel, a green sub-pixel, a blue sub-pixel and a white sub-pixel, so that color display can be realized by mixing red, green, blue and white. Of course, the light-emitting color of the sub-pixels in the pixel unit can be designed according to the actual application environment in actual application, which is not limited herein.

[0221] In the embodiments of the present disclosure, the display device can be any product or component with display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, AR, VR, etc. Other essential components of the display device are understood by those skilled in the art, and are not described herein, nor should they be construed as limiting the present disclosure.

[0222] Although the preferred embodiments of the present disclosure have been described, those skilled in the art can make further changes and modifications to the embodiments once they know the basic inventive concept. Therefore, the appended claims are intended to be interpreted as including all changes and modifications falling within the scope of the present disclosure.

[0223] Obviously, those skilled in the art can make various modifications and variations to the embodiments of the present disclosure without departing from the spirit and scope of the embodiments of the present disclosure. Thus, if these modifications and variations of the embodiments of the present disclosure fall within the scope of the claims of the present disclosure and their equivalent technologies, the present disclosure also intends to include these modifications and variations.

Claims

1. A display panel, wherein, The application relates to a display panel, which comprises a substrate, a plurality of sub-pixels and a plurality of pixel circuits on the substrate, at least two adjacent sub-pixels corresponding to one pixel circuit, each sub-pixel comprising a light-emitting device, the first electrodes of the light-emitting devices in the at least two adjacent sub-pixels being the same electrode, the first electrodes of the light-emitting devices being electrically connected to the corresponding pixel circuit, the second electrodes of the light-emitting devices in the two adjacent sub-pixels being independently and separately arranged, the second electrodes of the light-emitting devices in the at least two adjacent sub-pixels being electrically connected to two first power signal lines respectively, the two first power signal lines being loaded with effective level signals in time division mode, and the pixel circuit being configured to drive the light-emitting device to emit light when the first power signal line is loaded with the effective level signal. The first electrode layer, the pixel definition layer, the electroluminescent layer and the second electrode layer are sequentially arranged to form the plurality of light-emitting devices. The first electrode layer is double-layered and comprises the first electrodes of the plurality of light-emitting devices. The second electrode layer comprises the second electrodes of the plurality of light-emitting devices. The first electrode of one sub-pixel is overlapped with the second electrodes of at least two adjacent sub-pixels in the orthographic projection of the substrate.

2. The display panel of claim 1, wherein, The second electrodes of the plurality of light-emitting devices extend along a first direction, and the second electrodes of the plurality of light-emitting devices are sequentially and separately arranged along a second direction. The two first power signal lines extend along the second direction and are located on the two sides of the second electrodes respectively. The second electrodes of two adjacent sub-pixels are electrically connected to the first power signal lines on the two sides respectively. The display panel further comprises a color filter layer on the side of the second electrode layer away from the substrate, and the color filter layer comprises at least three color filters of different colors.

3. The display panel of claim 2, wherein, The colors of the color filters arranged on the second electrodes of the light-emitting devices in the at least two adjacent sub-pixels are the same or different.

4. The display panel of claim 3, wherein, The first electrode of the light-emitting device is an anode, the second electrode of the light-emitting device is a cathode, and the effective level signal loaded on the first power signal line is a low level signal. The first electrode of the light-emitting device is a cathode, the second electrode of the light-emitting device is an anode, and the effective level signal loaded on the first power signal line is a high level signal.

5. The display panel of claim 2, wherein, The pixel circuit comprises a driving transistor, a first transistor, a second transistor and a first capacitor. The gate electrode of the driving transistor is electrically connected to the first electrode of the first transistor, the first electrode of the driving transistor is electrically connected to a second power signal line, and the second electrode of the driving transistor is electrically connected to the first electrode of the light-emitting device in the at least two adjacent sub-pixels corresponding to the pixel circuit.

6. The display panel of any of claims 1-5, wherein, The gate electrode of the first transistor is electrically connected to a gate signal line, and the second electrode of the first transistor is electrically connected to a data signal line.

7. The display panel of any of claims 1-5, wherein, The gate electrode of the second transistor is electrically connected to the gate signal line, the first electrode of the second transistor is electrically connected to the second electrode of the driving transistor, and the second electrode of the second transistor is electrically connected to a compensation signal line.

8. The display panel of any of claims 1-7, wherein, ​ ​ ​ ​ A first electrode of the first capacitor is electrically connected to a gate of the driving transistor, and a second electrode of the first capacitor is electrically connected to a second electrode of the driving transistor.

9. The display panel of claim 8, wherein, The driving transistor is of a double-gate structure, and the gate of the driving transistor includes a first gate and a second gate.

10. The display panel of claim 9, wherein, Further comprising a first conductive layer on the substrate, wherein the first conductive layer includes the data signal line and the compensation signal line; A light-shielding layer on a side of the first conductive layer away from the substrate, wherein the light-shielding layer includes the first gate of the driving transistor. Further comprising a first semiconductor layer on a side of the light-shielding layer away from the substrate, wherein the first semiconductor layer includes an active layer of the driving transistor and an active layer of the first transistor; 11. The display panel of claim 10, wherein, A gate conductive layer on a side of the first semiconductor layer away from the substrate, wherein the gate conductive layer includes the gate of the first transistor, the gate of the second transistor, the second gate of the driving transistor, and a first electrode of a first capacitor; A second conductive layer on a side of the gate conductive layer away from the substrate, wherein the second conductive layer includes a second electrode of the first capacitor; A second semiconductor layer on a side of the second conductive layer away from the substrate, wherein the second semiconductor layer includes an active layer of the second transistor; A third conductive layer on a side of the second semiconductor layer away from the substrate, wherein the third conductive layer includes the second power signal line. The second conductive layer further includes a first adapter, and a projection of the first adapter on the substrate overlaps a projection of the data signal line on the substrate.

12. The display panel of claim 11, wherein, The active layer of the first transistor is electrically connected to the data signal line through the first adapter. The third conductive layer further includes a second adapter, and a projection of the second adapter on the substrate overlaps a projection of the second gate of the driving transistor on the substrate.

13. The display panel of claim 11, wherein, The active layer of the first transistor is electrically connected to the second gate of the driving transistor through the second adapter. The at least two adjacent sub-pixels and pixel circuits corresponding to the at least two adjacent sub-pixels together form a pixel unit.

14. The display panel of any of claims 8-13, wherein, Two pixel units adjacent in the first direction are arranged in mirror symmetry with each other, and two pixel units adjacent in the second direction are arranged in mirror symmetry with each other. The four pixel units adjacent in the first direction and the second direction form a pixel arrangement group.

15. The display panel of claim 14, wherein, The pixel units in each pixel arrangement group share one compensation signal line. The two pixel arrangement groups adjacent in the second direction share one second power signal line. The display panel includes the pixel arrangement group.

16. A display device comprising: The display panel includes:

17. A driving method of a display panel according to any one of claims 1 to 15, wherein, In the first light-emitting stage, one of the two first power signal lines is loaded with an effective level signal, and the pixel circuit drives the light-emitting device electrically connected to the first power signal line to emit light. In the second light-emitting stage, the other of the two first power signal lines is loaded with an effective level signal, and the pixel circuit drives the light-emitting device electrically connected to the first power signal line to emit light. ​

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