Pixel driving circuit and display panel

Abstract

The present invention provides a pixel driving circuit and a display panel. The pixel driving circuit comprises: a third transistor, a sixth transistor, a third capacitor, and a first power supply voltage line. The third transistor and the sixth transistor are both double-gate transistors. A first electrode of the third capacitor is separately connected to a midpoint of the third transistor and a midpoint of the sixth transistor, and a second electrode is connected to the first power supply voltage line. The present invention can reduce gate leakage of driving transistors, mitigate low-frequency flickering of display panels, and improve user experience.

Description

Pixel driving circuit and display panel TECHNICAL FIELD

[0001] The present application relates to the field of display panel circuit, in particular, to a pixel driving circuit and display panel. BACKGROUND

[0002] Compared with the OLED display panel in the prior art, the AMOLED (Active-Matrix Organic Light-Emitting Diode) display panel has the advantages of wide color gamut, low energy consumption and low thickness, and therefore, has gradually attracted increasing attention from display technology developers. The AMOLED display panel includes a pixel array and a pixel driving circuit for controlling the pixel array, and the light-emitting pixels in the pixel array emit light under the joint action of the pixel driving circuit, the scan driving circuit and the light-emitting driving circuit.

[0003] In the related art, during the display of a frame of picture, the gate of the driving transistor of the pixel driving circuit of the AMOLED display panel continuously leaks electricity between the gate and the adjacent device due to the voltage difference between the gate and the adjacent device, and the leakage of the gate leads to the change of the brightness of the display panel, and the change of the brightness of the display panel forms a flashing screen phenomenon at a low refresh rate, which affects the user experience.

[0004] It should be noted that the information disclosed in the above BACKGROUND section is only used to enhance the understanding of the background of the present application, and therefore, can include information that does not constitute prior art known to those of ordinary skill in the art.

[0005] SUMMARY

[0006] Therefore, the present application provides a pixel driving circuit and a display panel to at least solve the flashing screen problem of the display panel.

[0007] One aspect of an embodiment of the present application provides a pixel driving circuit, comprising:

[0008] a first transistor, a first electrode of the first transistor being connected to a data signal line, a second electrode being connected to a fourth node, and a gate electrode being connected to a first scan signal line;

[0009] a second transistor, a first electrode of the second transistor being connected to a first node, a second electrode being connected to a third node, and a gate electrode being connected to a second node;

[0010] a third transistor, a first electrode of the third transistor being connected to the second node, a second electrode being connected to the third node, and a gate electrode being connected to a second scan signal line; wherein the third transistor is a double-gate transistor;

[0011] a fourth transistor, a first electrode of the fourth transistor being connected to the first power supply voltage line, a second electrode of the fourth transistor being connected to the first node, and a gate of the fourth transistor being connected to the first light-emitting signal line;

[0012] a fifth transistor, a first electrode of the fifth transistor being connected to the third node, and a gate of the fifth transistor being connected to the second light-emitting signal line;

[0013] a sixth transistor, a first electrode of the sixth transistor being connected to the second node, a second electrode of the sixth transistor being connected to the first initial voltage line, and a gate of the sixth transistor being connected to the third scan signal line; wherein the sixth transistor is a double-gate transistor;

[0014] a seventh transistor, a first electrode of the seventh transistor being connected to the second initial voltage line, a second electrode of the seventh transistor being connected to a second electrode of the fifth transistor, and a gate of the seventh transistor being connected to the fourth scan signal line;

[0015] an eighth transistor, a first electrode of the eighth transistor being connected to the first node, a second electrode of the eighth transistor being connected to the third initial voltage line, and a gate of the eighth transistor being connected to the fourth scan signal line;

[0016] a ninth transistor, a first electrode of the ninth transistor being connected to the fourth node, a second electrode of the ninth transistor being connected to the fourth initial voltage line, and a gate of the ninth transistor being connected to the second scan signal line;

[0017] a second capacitor, a first electrode of the second capacitor being connected to the fourth node, and a second electrode of the second capacitor being connected to the second node;

[0018] a third capacitor, a first electrode of the third capacitor being connected to a midpoint of the third transistor and a midpoint of the sixth transistor respectively, and a second electrode of the third capacitor being connected to the first power supply voltage line;

[0019] a light-emitting diode, a first electrode of the light-emitting diode being connected to the second electrode of the fifth transistor, and a second electrode of the light-emitting diode being connected to a second power supply voltage line.

[0020] In some embodiments, the pixel driving circuit further comprises:

[0021] a first capacitor, a first electrode of the first capacitor being connected to the fourth node, and a second electrode of the first capacitor being connected to the first power supply voltage line.

[0022] In some embodiments, the first transistor and the ninth transistor are double-gate transistors; and the first transistor to the ninth transistor are P-type MOS transistors.

[0023] In some embodiments, the first scan signal line, the second scan signal line, the third scan signal line and the fourth scan signal line provide the first scan signal, the second scan signal, the third scan signal and the fourth scan signal with the same frequency to the pixel driving circuit respectively within a frame time.

[0024] In some embodiments, the second scan signal has a low potential for a longer time than the first scan signal, the third scan signal and the fourth scan signal within a frame time.

[0025] In some embodiments, the first emission signal line and the second emission signal line provide the first emission signal and the second emission signal with the same frequency to the pixel driving circuit respectively within a frame time.

[0026] In some embodiments, the high potential period of the first emission signal is included in the high potential period of the second emission signal within a frame time.

[0027] In some embodiments, the low potential period of the fourth scan signal is included in the high potential period of the first emission signal within a frame time.

[0028] In some embodiments, the low potential period of the first scan signal, the second scan signal, the third scan signal and the fourth scan signal is included in the high potential period of the second emission signal within a frame time.

[0029] In some embodiments, the first scan signal and the first emission signal have the same frequency.

[0030] Another aspect of the embodiments of the present application further provides a display panel comprising the pixel driving circuit.

[0031] The pixel driving circuit and the display panel of the present application reduce the leakage current of the second node, reduce the potential change of the second node, reduce the brightness change of the display panel, and further reduce the low-frequency flicker phenomenon of the display panel, thereby improving the user experience.

[0032] It should be understood that the general description above and the following detailed description are only exemplary and explanatory, and cannot limit the present application. BRIEF DESCRIPTION OF DRAWINGS

[0033] The accompanying drawings, which are incorporated herein and constitute part of this specification, illustrate embodiments consistent with the application and, together with the description, further serve to explain the principles of the application. It is apparent that the drawing in the following description is only some embodiments of the present application, and other drawings can be obtained from these drawings without creative labor for those skilled in the art.

[0034] FIG. 1 is a luminance curve diagram of a display panel in the related art when the refresh rate is 60Hz;

[0035] FIG. 2 is a luminance curve diagram of the display panel in FIG. 1 when the refresh rate is 30Hz;

[0036] FIG. 3 is a driving transistor gate potential curve diagram of the display panel in FIG. 1 when the refresh rate is 30Hz;

[0037] FIG. 4 is a schematic diagram of the overall circuit structure of a display panel according to an embodiment of the present application;

[0038] FIG. 5 is a circuit diagram of a pixel driving circuit in FIG. 4;

[0039] FIG. 6 is a waveform diagram of the pixel driving circuit in FIG. 5 when it is working;

[0040] FIG. 7 is a schematic diagram of the working state of the pixel driving circuit in FIG. 6 at stage t1;

[0041] FIG. 8 is a schematic diagram of the working state of the pixel driving circuit in FIG. 6 at stage t2;

[0042] FIG. 9 is a schematic diagram of the working state of the pixel driving circuit in FIG. 6 at stage t3;

[0043] FIG. 10 is a schematic diagram of the working state of the pixel driving circuit in FIG. 6 at stage t4;

[0044] FIG. 11 is a potential curve diagram of the second node and the midpoint of the third transistor in FIG. 4;

[0045] FIG. 12 is a schematic diagram of a display panel according to an embodiment of the present application.

[0046] Reference sign: 11 pixel driving circuit T1 first transistor T2 second transistor T3 third transistor T4 fourth transistor T5 fifth transistor T6 sixth transistor T7 seventh transistor T8 eighth transistor T9 ninth transistor C1 first capacitor C2 second capacitor C3 third capacitor D light emitting diode N1 first node N2 second node N3 third node N4 fourth node SN1 first scan signal line SN2 second scan signal line SN3 third scan signal line SN4 fourth scan signal line EM1 first light emitting signal line EM2 second light emitting signal line Data data signal line ELVDD first power supply voltage line ELVSS second power supply voltage line Vint1 first initial voltage line Vint2 second initial voltage line Vint3 third initial voltage line Vint4 fourth initial voltage line 10 display panel DETAILED DESCRIPTION

[0047] To make the technical problems solved by the present application, the technical solutions adopted and the technical effects reached more clear, the technical solutions of the embodiments of the present application will be further described in detail below with reference to the drawings. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all the other embodiments obtained by those skilled in the art without creative work under the premise, belong to the scope of protection of the present application.

[0048] In addition, the described features, structures or characteristics can be combined in any suitable way in one or more embodiments. In the following description, many specific details are provided to give a full understanding of the embodiments of the present application. However, those skilled in the art will realize that the technical solutions of the present application can be practiced without one or more of the specific details, or other methods, modules, devices, steps, etc. can be used. In other cases, well-known modules, methods, devices, implementations, steps, or operations are not shown or described in detail to avoid obscuring the aspects of the present application.

[0049] As shown in FIG. 1 and FIG. 2, in the related art, the luminance of the display panel changes by ΔLV. (nit) within a frame time, and the luminance increases by ΔLV. when switching between adjacent frames, thereby forming a luminance jump. When the refresh rate of the display panel is high (for example, 60 Hz), the luminance jump is not obvious to the human eye. However, when the refresh rate of the display panel is low (for example, 30 Hz), the luminance jump is more obvious to the human eye, thereby forming a screen flicker phenomenon.

[0050] As shown in FIG. 3, specifically, the luminance change of the display panel is caused by gate leakage of the driving transistor of the pixel driving circuit. During the display of a frame by the display panel, the gate of the driving transistor of the pixel driving circuit continuously leaks to the adjacent device due to the voltage difference between the gate and the adjacent device, the potential of the gate and the adjacent device decreases by ΔV, and the potential increases by ΔV when switching between adjacent frames, thereby forming a luminance jump. The ΔV change in the potential caused by the gate leakage of the gate causes the luminance of the display panel to change by ΔLV., and the luminance change of the display panel causes a screen flicker phenomenon at a low refresh rate, thereby affecting the user experience.

[0051] The present application provides a solution to the problems in the prior art. The present application provides a pixel driving circuit and a display panel, wherein the pixel driving circuit comprises a third transistor, a sixth transistor, a third capacitor, and a first power supply voltage line; the third transistor and the sixth transistor are both double-gate transistors; the first pole of the third capacitor is connected to the midpoint of the third transistor and the midpoint of the sixth transistor, and the second pole is connected to the first power supply voltage line. The present application can reduce the gate leakage of the driving transistor, reduce the low-frequency screen flicker phenomenon of the display panel, and improve the user experience.

[0052] The technical solutions of the present application will be further described below with reference to the accompanying drawings.

[0053] As shown in FIG. 4, the overall circuit of the display panel of the present application comprises a scan driving circuit, a light-emitting driving circuit, a data driver, a timing controller, and a pixel driving circuit 11. The area within the dashed line in FIG. 4 is the display area, and the area outside the dashed line is the non-display area. The scan driving circuit, the light-emitting driving circuit, the data driver, and the timing controller are all located in the non-display area, and the pixel driving circuit 11 is located in the display area.

[0054] Specifically, the scan driving circuit leads out a plurality of scan signal lines SN and connects the scan signal lines SN to the pixel driving circuit 11, so as to provide the pixel driving circuit 11 with a scan signal. The light emitting driving circuit leads out a plurality of light emitting signal lines EM and connects the light emitting signal lines EM to the pixel driving circuit 11, so as to provide the pixel driving circuit 11 with a light emitting signal. The data driver leads out a plurality of data signal lines Data and connects the data signal lines Data to the pixel driving circuit 11, so as to provide the pixel driving circuit 11 with a data signal. The display panel comprises a plurality of pixel driving circuits 11 arranged in an array. The pixel driving circuit 11 controls the light emitting state of the light emitting pixel under the joint action of the scan signal, the light emitting signal and the data signal.

[0055] As shown in FIG. 5, one aspect of the embodiment of the present application provides a pixel driving circuit 11, which is a 9T3C circuit, i.e., a circuit comprising 9 transistors and 3 capacitors.

[0056] Specifically, the first electrode of the first transistor T1 is connected to the data signal line Data, the second electrode is connected to the fourth node N4, and the gate electrode is connected to the first scan signal line SN1. The first electrode of the second transistor T2 is connected to the first node N1, the second electrode is connected to the third node N3, and the gate electrode is connected to the second node N2. The first electrode of the third transistor T3 is connected to the second node N2, the second electrode is connected to the third node N3, and the gate electrode is connected to the second scan signal line SN2. The first electrode of the fourth transistor T4 is connected to the first power voltage line ELVDD, the second electrode is connected to the first node N1, and the gate electrode is connected to the first light emitting signal line EM1. The first electrode of the fifth transistor T5 is connected to the third node N3, and the gate electrode is connected to the second light emitting signal line EM2. The first electrode of the sixth transistor T6 is connected to the second node N2, the second electrode is connected to the first initial voltage line Vint1, and the gate electrode is connected to the third scan signal line SN3. The first electrode of the seventh transistor T7 is connected to the second initial voltage line Vint2, the second electrode is connected to the second electrode of the fifth transistor T5, and the gate electrode is connected to the fourth scan signal line SN4. The first electrode of the eighth transistor T8 is connected to the first node N1, the second electrode is connected to the third initial voltage line Vint3, and the gate electrode is connected to the fourth scan signal line SN4. The first electrode of the ninth transistor T9 is connected to the fourth node N4, the second electrode is connected to the fourth initial voltage line Vint4, and the gate electrode is connected to the second scan signal line SN2. The first electrode of the first capacitor C1 is connected to the fourth node N4, and the second electrode is connected to the first power voltage line ELVDD. The first electrode of the second capacitor C2 is connected to the fourth node N4, and the second electrode is connected to the second node N2. The first electrode of the light emitting diode D is connected to the second electrode of the fifth transistor T5, and the second electrode is connected to the second power voltage line ELVSS.

[0057] Further, the third transistor T3 and the sixth transistor T6 are both double-gate transistors. The first pole of the third capacitor C3 is connected to the midpoint of the third transistor T3 and the midpoint of the sixth transistor T6, respectively, and the second pole is connected to the first power voltage line ELVDD. By connecting the midpoint of the third transistor T3 and the midpoint of the sixth transistor T6 together and adding the third capacitor C3 between the midpoint and the first power voltage line ELVDD, the drain-source voltage VDS of the third transistor T3 and the sixth transistor T6 can be reduced, thereby reducing the drain current of the third transistor T3 and the sixth transistor T6. At the same time, the voltage difference between the second node N2 (i.e., the gate of the driving transistor of the pixel driving circuit 11 in this embodiment) and the midpoint of the third transistor T3 and the midpoint of the sixth transistor T6 can also be reduced, thereby reducing the leakage current from the second node N2 to the first initial voltage line Vint1 and the third node N3, reducing the potential change of the second node N2, reducing the brightness change of the display panel, thereby reducing the low-frequency flicker phenomenon of the display panel, and improving the user experience.

[0058] In some embodiments, in addition to the third transistor T3 and the sixth transistor T6, the first transistor T1 and the ninth transistor T9 are also double-gate transistors. In the pixel driving circuit 11, the above-mentioned transistors using double-gate transistors have the following main advantages over ordinary single-gate transistors: higher driving capability, double-gate transistors have two gates, which can control a channel at the same time, and can provide higher driving current, thereby improving the response speed of the pixel driving circuit 11; better control characteristics, the double-gate structure can better control the switching of current, thereby reducing the leakage current, improving the switching speed and efficiency; lower power consumption, the structure of the double-gate transistor makes it more effective to prevent leakage current in the off state, thereby reducing the static power consumption of the pixel driving circuit 11.

[0059] In some embodiments, the first transistor T1 to the ninth transistor T9 are all P-type MOS transistors. The P-type MOS transistor is also called PMOS transistor, which is the abbreviation of P-type MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor). The control terminal of the PMOS transistor is the gate, the first pole is the source, and the second pole is the drain, or the first pole is the drain, and the second pole is the source. The on level of the PMOS transistor is low, and the off level is high. In other embodiments, those skilled in the art can easily conclude that the pixel driving circuit 11 provided by the present application can be easily changed to all N-type MOS transistors or mixed CMOS transistors. It should be noted that the high and low levels of the on and off of the transistor in the following are taken as an example of the PMOS transistor, and when other corresponding transistor types are selected according to design needs, the high and low levels of the on and off will also change accordingly.

[0060] In some embodiments, the light emitting diode D can be an OLED (Organic Light Emitting Diode) or an AMOLED. The first pole of the light emitting diode D is the anode, and the second pole is the cathode. In addition, the first power voltage line ELVDD provides a positive power voltage for the pixel driving circuit 11, and the second power voltage line ELVSS provides a negative power voltage for the pixel driving circuit 11, but not limited thereto.

[0061] In some embodiments, the first initial voltage line Vint1, the second initial voltage line Vint2, the third initial voltage line Vint3, and the fourth initial voltage line Vint4 provide the first initial voltage, the second initial voltage, the third initial voltage, and the fourth initial voltage to the pixel driving circuit 11, respectively. And the first initial voltage, the second initial voltage, the third initial voltage, and the fourth initial voltage are constant. In addition, the first initial voltage, the second initial voltage, the third initial voltage, and the fourth initial voltage can select different voltages according to the pixel driving circuit 11 to meet different display requirements, which is not limited by the present application. Specifically, the first initial voltage and the second initial voltage can be low, and the third initial voltage and the fourth initial voltage can be high.

[0062] As shown in FIG. 6, in some embodiments, the first scan signal line SN1, the second scan signal line SN2, the third scan signal line SN3 and the fourth scan signal line SN4 provide the pixel driving circuit 11 with the first scan signal, the second scan signal, the third scan signal and the fourth scan signal respectively in the same frequency within a frame time. In the same period, the first scan signal, the second scan signal, the third scan signal and the fourth scan signal each have only one low period, and the four low periods do not coincide. In addition, the four low periods belong to the third scan signal, the second scan signal, the first scan signal and the fourth scan signal in time sequence.

[0063] With continued reference to FIG. 6, in some embodiments, the length of the low period of the second scan signal is greater than the first scan signal, the third scan signal and the fourth scan signal within a frame time. The low periods of the first scan signal, the third scan signal and the fourth scan signal are the same. Specifically, the low period of the second scan signal can be the compensation phase of the pixel driving circuit 11, and the above setting can make the compensation effect of the pixel driving circuit 11 on the second transistor T2, i.e. the driving transistor, better.

[0064] With continued reference to FIG. 6, in some embodiments, the first emission signal line EM1 and the second emission signal line EM2 provide the pixel driving circuit 11 with the first emission signal and the second emission signal respectively in the same frequency within a frame time.

[0065] With continued reference to FIG. 6, in some embodiments, the high period of the first emission signal is contained in the high period of the second emission signal within a frame time.

[0066] With continued reference to FIG. 6, in some embodiments, the low period of the fourth scan signal is contained in the high period of the first emission signal within a frame time.

[0067] With continued reference to FIG. 6, in some embodiments, the low periods of the first scan signal, the second scan signal, the third scan signal and the fourth scan signal are contained in the high period of the second emission signal within a frame time.

[0068] With continued reference to FIG. 6, in some embodiments, the frequency of the first scan signal is the same as that of the first emission signal. Specifically, the first scan signal, the second scan signal, the third scan signal and the fourth scan signal each have only one low period within a frame time, and the first emission signal and the second emission signal each have only one high period.

[0069] Specifically, the pixel driving circuit 11 can work at a low frequency, where the low frequency means that the operating frequency is less than 60 Hz, but the minimum operating frequency is 1 Hz, but not limited to this. Specifically, FIG. 6 can be the timing diagram of the pixel driving circuit 11 of the present application when the operating frequency is 30 Hz, the black insertion and light emission are 1 time in each frame.

[0070] With reference to FIG. 6, in the present embodiment, the working process of the pixel driving circuit 11 is divided into 4 stages, t1 to t4, in one frame of the display screen. In the 4 processes, the light emitting diode D in the pixel driving circuit 11 completes 1 time of the process from black insertion to light emission. The relationship between the input and output of the pixel driving circuit 11 and the light emission in the above 4 processes will be analyzed below in combination with the waveform diagram of FIG. 6 and the circuit diagram of FIG. 5:

[0071] As shown in FIG. 6 and FIG. 7, in the t1 stage, the third scan signal line SN3 and the first light emission signal line EM1 input low level, the first scan signal line SN1, the second scan signal line SN2, the fourth scan signal line SN4 and the second light emission signal line EM2 input high level. The first transistor T1, the third transistor T3, the fifth transistor T5, the seventh transistor T7, the eighth transistor T8 and the ninth transistor T9 are closed, and the fourth transistor T4 and the sixth transistor T6 are opened. In this stage, the first initial voltage line Vint1 writes low potential to the second node N2 through the sixth transistor T6. Since the second node N2 is the gate of the second transistor T2, the second transistor T2 is the driving transistor which directly drives the light emitting diode D to emit light. Therefore, this stage can be the reset stage of the pixel driving circuit 11, and the first initial voltage line Vint1 writes low potential to the second node N2 to reset the second transistor T2. In addition, in this stage, since the fifth transistor T5 is closed, the light emitting diode D does not emit light.

[0072] As shown in FIG. 6 and FIG. 8, in the t2 stage, the second scan signal line SN2 and the first light emission signal line EM1 input low level, the first scan signal line SN1, the third scan signal line SN3, the fourth scan signal line SN4 and the second light emission signal line EM2 input high level. The first transistor T1, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7 and the eighth transistor T8 are closed, and the third transistor T3, the fourth transistor T4 and the ninth transistor T9 are opened. In this stage, the fourth initial voltage line Vint4 writes high potential to the fourth node N4 through the ninth transistor T9, and the first power voltage line ELVDD writes high potential to the first node N1 through the fourth transistor T4. At this time, the potential of the second node N2 is the potential of the first power voltage line ELVDD plus the threshold voltage VTH of the second transistor T2, that is, V N2= ELVDD + VTH. Further, in this stage, since the fifth transistor T5 is turned off, the light emitting diode D does not emit light. Specifically, this stage can be a compensation stage of the pixel driving circuit 11, and by setting the period of the low potential of the second scan signal line SN2 to be longer than the periods of the low potentials of the first scan signal line SN1, the third scan signal line SN3, and the fourth scan signal line SN4, the compensation effect of the pixel driving circuit 11 on the second transistor T2, that is, the driving transistor, can be made better.

[0073] As shown in FIG. 6 and FIG. 9, in the t3 stage, the first scan signal line SN1 and the first emission signal line EM1 input a low level, and the second scan signal line SN2, the third scan signal line SN3, the fourth scan signal line SN4, and the second emission signal line EM2 input a high level. The third transistor T3, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8, and the ninth transistor T9 are turned off, and the first transistor T1 and the fourth transistor T4 are turned on. In this stage, the data signal line Data writes a potential to the fourth node N4 through the first transistor T1, and the potential of the fourth node N4 changes from the high potential of the fourth initial voltage line Vint4 in the t2 stage to the potential of the data signal line Data, that is, V N4 = V Data , and the potential change amount of the N4 is Data - Vint4. At this time, due to the existence of the second capacitor C2, the potential of the second node N2 is the potential in the t2 stage plus the potential change amount of the fourth node N4, that is, V N2 = ELVDD + VTH + V Data - Vint4. Further, in this stage, since the fifth transistor T5 is turned off, the light emitting diode D does not emit light.

[0074] As shown in FIG. 6 and FIG. 10, in the t4 stage, the first emission signal line EM1 and the second emission signal line EM2 input a low level, and the first scan signal line SN1, the second scan signal line SN2, the third scan signal line SN3, and the fourth scan signal line SN4 input a high level. The first transistor T1, the third transistor T3, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8, and the ninth transistor T9 are turned off, and the second transistor T2, the fourth transistor T4, and the fifth transistor T5 are turned on. In this stage, due to the existence of the second capacitor C2, the potential of the second node N2 is maintained at the potential in the previous stage, that is, V N2 = ELVDD + VTH + V Data- Vint4. In addition, in this stage, since the second transistor T2, the fourth transistor T4 and the fifth transistor T5 are turned on, current flows from the first power voltage line ELVDD, through the second transistor T2, the fourth transistor T4, the fifth transistor T5 and the light emitting diode D, to the second power voltage line ELVSS, thus the light emitting diode D emits light. Specifically, the current I flowing through the second transistor T2 T2 = K(VGS-VTH) 2 = K(V N2 - ELVDD-VTH) 2 = K(ELVDD+VTH+V Data - Vint4-ELVDD-VTH) 2 = K(V Data - Vint4) 2 wherein K is the current calculation coefficient of the second transistor T2.

[0075] As shown in FIG. 11, the three curves of the t3 stage from top to bottom represent the potential change curve of the midpoint of the third transistor T3 in the related art, the potential change curve of the midpoint of the third transistor T3 in the present application and the potential change curve of the second node N2 in the present application. Wherein ΔV1 is the voltage difference between the second node N2 and the midpoint of the third transistor T3 in the related art, and ΔV2 is the voltage difference between the second node N2 and the midpoint of the third transistor T3 in the present application.

[0076] It should be noted that, by connecting the midpoint of the third transistor T3 and the midpoint of the sixth transistor T6 together and adding the third capacitor C3 between the midpoint of the third transistor T3 and the midpoint of the sixth transistor T6 and the first power voltage line ELVDD, the potential of the midpoint of the third transistor T3 and the midpoint of the sixth transistor T6 is the same, which can reduce the drain-source voltage difference VDS of the third transistor T3 and the sixth transistor T6, thereby reducing the drain current of the third transistor T3 and the sixth transistor T6, that is, the voltage difference between the second node N2 (i.e. the gate of the driving transistor of the pixel driving circuit 11 in the present embodiment) and the midpoint of the third transistor T3 and the midpoint of the sixth transistor T6 (i.e. ΔV2 < ΔV1) can be reduced, and further the leakage of the second node N2 to the first initial voltage line Vint1 and the third node N3 can be reduced.

[0077] Further, since the present application reduces the leakage of the second node N2 to the first initial voltage line Vint1 and the third node N3, the brightness change of the display panel caused by the potential change of the second node N2 (the gate of the driving transistor) is reduced. Therefore, the present application can reduce the screen flicker phenomenon caused by the brightness change of the display panel when displaying at low frequency, and improve the user experience.

[0078] As shown in FIG. 12, based on the same inventive concept, another aspect of the embodiment of the present application further provides a display panel 10 comprising the pixel driving circuit 11 described above. The display panel 10 can be applied to any product or component with display function, such as mobile phone, tablet computer, television, display, notebook computer, digital photo frame, navigator, etc. The specific implementation of the display panel 10 can refer to the embodiments of the pixel driving circuit 11 described above, and the repeated parts of the technical solutions and technical effects will not be described again.

[0079] In summary, the pixel driving circuit and the display panel of the present application connect the midpoint of the third transistor and the midpoint of the sixth transistor together, and increase the third capacitor between the midpoints and the first power supply voltage line, thereby reducing the leakage current of the second node, reducing the potential change of the second node, reducing the brightness change of the display panel, and further reducing the low-frequency screen flicker phenomenon of the display panel, and improving the user experience.

[0080] The above is a further detailed description of the present application in combination with specific preferred embodiments, and the specific implementation of the present application cannot be limited to these descriptions. For ordinary skilled persons in the technical field to which the present application belongs, some simple deductions or substitutions can be made without departing from the concept of the present application, and all of them should be regarded as falling within the protection scope of the present application.

Claims

1. A pixel driving circuit, characterized by comprising: Comprising: a first transistor, a first electrode of the first transistor being connected to a data signal line, a second electrode being connected to a fourth node, and a gate electrode being connected to a first scan signal line; a second transistor, a first electrode of the second transistor being connected to a first node, a second electrode being connected to a third node, and a gate electrode being connected to a second node; a third transistor, a first electrode of the third transistor being connected to the second node, a second electrode being connected to the third node, and a gate electrode being connected to a second scan signal line; wherein the third transistor is a double-gate transistor; a fourth transistor, a first electrode of the fourth transistor being connected to a first power voltage line, a second electrode being connected to the first node, and a gate electrode being connected to a first light-emitting signal line; a fifth transistor, a first electrode of the fifth transistor being connected to the third node, and a gate electrode being connected to a second light-emitting signal line; a sixth transistor, a first electrode of the sixth transistor being connected to the second node, a second electrode being connected to a first initial voltage line, and a gate electrode being connected to a third scan signal line; wherein the sixth transistor is a double-gate transistor; a seventh transistor, a first electrode of the seventh transistor being connected to a second initial voltage line, a second electrode being connected to a second electrode of the fifth transistor, and a gate electrode being connected to a fourth scan signal line; an eighth transistor, a first electrode of the eighth transistor being connected to the first node, a second electrode being connected to a third initial voltage line, and a gate electrode being connected to the fourth scan signal line; a ninth transistor, a first electrode of the ninth transistor being connected to the fourth node, a second electrode being connected to a fourth initial voltage line, and a gate electrode being connected to the second scan signal line; a second capacitor, a first electrode of the second capacitor being connected to the fourth node, and a second electrode being connected to the second node; a third capacitor, a first electrode of the third capacitor being connected to a midpoint of the third transistor and a midpoint of the sixth transistor respectively, and a second electrode being connected to the first power voltage line; a light-emitting diode, a first electrode of the light-emitting diode being connected to a second electrode of the fifth transistor, and a second electrode being connected to a second power voltage line.

2. The pixel driving circuit according to claim 1, wherein Further comprising: a first capacitor, a first electrode of the first capacitor being connected to the fourth node, and a second electrode being connected to the first power voltage line.

3. The pixel driving circuit of claim 1, wherein, The first transistor and the ninth transistor are double-gate transistors; the first transistor to the ninth transistor are all P-type MOS transistors.

4. The pixel driving circuit of claim 1, wherein, Within a frame time, the first scan signal line, the second scan signal line, the third scan signal line and the fourth scan signal line respectively provide the pixel driving circuit with first, second, third and fourth scan signals of the same frequency.

5. The pixel driving circuit of claim 4, wherein, Within a frame time, the duration of the low potential of the second scan signal is greater than that of the first, third and fourth scan signals.

6. The pixel driving circuit of claim 4, wherein, Within a frame time, the first light-emitting signal line and the second light-emitting signal line respectively provide the pixel driving circuit with first and second light-emitting signals of the same frequency.

7. The pixel driving circuit of claim 6, wherein, Within a frame time, the high potential period of the first light-emitting signal is contained in the high potential period of the second light-emitting signal.

8. The pixel driving circuit of claim 6, wherein, The low potential period of the fourth scanning signal is included in the high potential period of the first light emitting signal within a frame time. The low potential periods of the first scanning signal, the second scanning signal, the third scanning signal and the fourth scanning signal are all included in the high potential period of the second light emitting signal within a frame time.

9. The pixel driving circuit of claim 6, wherein, The first scanning signal and the first light emitting signal have the same frequency.

10. A display panel, characterized by, A pixel driving circuit according to any one of claims 1 to 9. A pixel driving circuit according to any one of claims 1 to 9.

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