Array substrate and display panel

Abstract

An array substrate (100) and a display panel (1000). Each first pixel electrode (20) of the array substrate (100) is connected to a first transistor (T1) after passing through a first via hole (H1), and each second pixel electrode (30) of the array substrate (100) is connected to a second transistor (T2) after passing through a second via hole (H2); and in each sub-pixel (SP), the first via hole (H1) is located on the side of a first gate electrode (G1) close to a data line (DL) connected to the sub-pixel (SP), and the second via hole (H2) is located on the side of a second gate electrode (G2) away from the first gate electrode (G1). Therefore, the problem of existing liquid crystal display panels that use multi-domain display technology having a relatively low aperture ratio is mitigated.

Description

Array substrate and display panel

[0001] This application claims priority to Chinese Patent Application No. 202411102001.7, filed on August 12, 2024, the entire contents of which are incorporated herein by reference. TECHNICAL FIELD

[0002] The present application relates to the technical field of display, in particular to an array substrate and a display panel. BACKGROUND

[0003] Thin film transistor-liquid crystal display (TFT-LCD) panels are widely used due to their long service life, mature technology, and low price. However, the birefringence of liquid crystal molecules in liquid crystal display panels varies greatly at different viewing angles, leading to color shift problems at large viewing angles. Currently, the main method to improve the large viewing angle color shift problem is to use multi-domain display technology, such as 3T8 domain display technology, which controls 8 display domains for each sub-pixel through 3 thin film transistors. However, liquid crystal display panels using multi-domain display technology have the problem of low aperture ratio. SUMMARY

[0004] The present application provides an array substrate and a display panel to alleviate the technical problem of low aperture ratio existing in the current liquid crystal display panel using multi-domain display technology.

[0005] The technical solutions provided by the present application are as follows:

[0006] In a first aspect, the present application provides an array substrate, which includes a substrate and a plurality of sub-pixels arranged in an array on the substrate, each sub-pixel including a first pixel electrode, a second pixel electrode, and a plurality of transistors located between the first pixel electrode and the second pixel electrode, the plurality of transistors including a first transistor and a second transistor, the first pixel electrode being connected to the first transistor through a first via, and the second pixel electrode being connected to the second transistor through a second via; the array substrate further includes:

[0007] a plurality of data lines arranged in an array on the substrate in a first direction, each data line being located on one side of the sub-pixel and connected to the corresponding sub-pixel, and the first pixel electrode and the second pixel electrode of each sub-pixel being arranged in a second direction in sequence.

[0008] Multiple scan lines are spaced apart on the substrate along the second direction. Each scan line is located between the first pixel electrode and the second pixel electrode of each row of sub-pixels and is connected to the first gate of the first transistor and the second gate of the second transistor of each sub-pixel. The first gate and the second gate are arranged sequentially in the first direction and are located on the same side of the scan line to which they are connected.

[0009] In each sub-pixel, the first via is located on the side of the first gate near the data line connected to the sub-pixel, the second via is located on the side of the second gate away from the first gate, and the first via and the second via are located on the same side of the scan line.

[0010] Secondly, embodiments of this application also provide a display panel, which includes an array substrate of one of the foregoing embodiments. Attached Figure Description

[0011] To more clearly illustrate the technical solutions in the embodiments or prior art, the drawings used in the description of the embodiments or prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0012] Figure 1 shows a schematic diagram of the planar structure of a sub-pixel on a liquid crystal display panel.

[0013] Figure 2 shows a schematic diagram of a planar structure of an array substrate in an embodiment of this application.

[0014] Figure 3 shows a schematic diagram of the planar structure of a sub-pixel in Figure 2.

[0015] Figure 4 shows a detailed schematic diagram of part of the structure in Figure 3.

[0016] Figure 5 shows a schematic diagram of the partial film structure of the sub-pixel in Figure 3.

[0017] Figure 6 shows a cross-sectional structural diagram of a display panel in an embodiment of this application. Embodiments of the present invention

[0018] The following description of the embodiments refers to the accompanying drawings, which are meant to exemplify particular embodiments of the application. The orientation of the description and drawings is merely meant to exemplify the application and is not meant to limit the application. In the drawings, like reference numerals refer to like elements throughout. In the drawings, the thicknesses of some layers and regions are exaggerated for clarity and ease of description. That is, the size and thickness of each component shown in the drawings are arbitrarily shown, but the present application is not limited thereto.

[0019] In view of the low aperture ratio of the existing liquid crystal display panel using the multi-domain display technology, the inventors of the present application have found that, referring to FIG. 1, FIG. 1 shows a planar structure schematic diagram of a sub-pixel on a liquid crystal display panel, the sub-pixel includes a first pixel electrode 20', a second pixel electrode 30' and a plurality of transistors, the plurality of transistors includes a first transistor T1' and a second transistor T2', the first pixel electrode 20' is connected with the first transistor T1' through a first via hole H1', and the second pixel electrode 30' is connected with the second transistor T2' through a second via hole H2'. The first via hole H1' and the second via hole H2' are located on opposite sides of a scan line SL'. The scan line SL' is located between two adjacent common electrode lines CL', the scan line SL' and the common electrode line CL' both extend along a first direction X, and the first pixel electrode 20', the plurality of transistors and the second pixel electrode 30' are arranged in sequence along a second direction Y. One of the two common electrode lines CL' forms a first capacitor C1' with the first pixel electrode 20' at a position corresponding to the first via hole H1', and the other common electrode line CL' forms a second capacitor C2' with the second pixel electrode 30' at a position corresponding to the second via hole H2'. Wherein, the first via hole H1' and the second via hole H2' are located on opposite sides of the scan line SL', which causes the plurality of transistors to occupy a large area along the second direction Y, so that the area of the non-opening region is large, and further causes the aperture ratio of the liquid crystal display panel to be low.

[0020] Therefore, the present application provides an array substrate and a display panel.

[0021] Please refer to FIG. 2 to FIG. 5, FIG. 2 shows a schematic diagram of a planar structure of an array substrate in an embodiment of the present application, FIG. 3 shows a schematic diagram of a planar structure of a sub-pixel in FIG. 2, FIG. 4 shows a schematic diagram of a detail structure of a part in FIG. 3, and FIG. 5 shows a schematic diagram of a part of a film layer structure of a sub-pixel in FIG. 3. Referring to FIG. 2, an array substrate 100 includes a substrate 10 and a plurality of gate scanning lines GL and a plurality of data lines DL arranged on the substrate 10. The plurality of gate scanning lines GL extend along a first direction X and are arranged at intervals along a second direction Y. The plurality of data lines DL extend along the second direction Y and are arranged at intervals along the first direction X. The first direction X and the second direction Y are different, for example, the first direction X is a row direction and the second direction Y is a column direction.

[0022] The array substrate 100 further includes a plurality of sub-pixels SP arranged in an array on the substrate 10. Each of the data lines DL is located at one side of the sub-pixels SP and connected with the corresponding sub-pixels SP, for example, each of the data lines DL is connected with a column of the sub-pixels SP, and some of the data lines DL are located between two adjacent columns of the sub-pixels SP. Each of the gate scanning lines GL crosses a row of the sub-pixels SP and is connected with at least the row of the sub-pixels SP. Each of three adjacent sub-pixels SP constitutes a pixel P, for example, any three adjacent sub-pixels SP in the second direction Y constitute a pixel P. That is, each of the pixels P includes three sub-pixels SP arranged in sequence in the second direction Y, and the three sub-pixels SP arranged in sequence have different light-emitting colors, for example, one sub-pixel SP emits red light, one sub-pixel SP emits green light, and one sub-pixel SP emits blue light. Of course, in some embodiments, each of the pixels P can also include three sub-pixels SP arranged in sequence in the first direction X.

[0023] The structure of the array substrate 100 will be described in detail below by taking one sub-pixel SP as an example.

[0024] Referring to FIG. 3, each of the sub-pixels SP includes a first pixel electrode 20, a second pixel electrode 30, and a plurality of transistors located between the first pixel electrode 20 and the second pixel electrode 30, the plurality of transistors including a first transistor T1 and a second transistor T2, the first pixel electrode 20 being connected with the first transistor T1 through a first via hole H1, and the second pixel electrode 30 being connected with the second transistor T2 through a second via hole H2. The first pixel electrode 20 and the second pixel electrode 30 of each of the sub-pixels SP are arranged in sequence in the second direction Y.

[0025] Each of the scan lines SL is located between the first pixel electrode 20 and the second pixel electrode 30 of each row of the sub-pixels SP, and is connected with the first gate G1 of the first transistor T1 and the second gate G2 of the second transistor T2 of each of the sub-pixels SP, the first gate G1 and the second gate G2 are arranged in the first direction X in sequence, and the first gate G1 and the second gate G2 are located on the same side of the scan line SL connected therewith. In each of the sub-pixels SP, the first via hole H1 is located on the side of the first gate G1 close to the data line DL connected with the sub-pixel SP, the second via hole H2 is located on the side of the second gate G2 away from the first gate G1, and the first via hole H1 and the second via hole H2 are located on the same side of the scan line SL.

[0026] In this way, by arranging the first gate G1 and the second gate G2 on the same side of the scan line SL, and arranging the first via hole H1 and the second via hole H2 on the opposite sides of the first gate G1, the space of the region where the plurality of transistors is located in the first direction X is fully utilized, and the space of the region where the plurality of transistors is located in the second direction Y is reduced, so as to reduce the distance between the first gate G1, the second gate G2 and the opening area, thereby reducing the area of the non-opening area, improving the opening rate, and solving the technical problem of low opening rate existing in the liquid crystal display panel adopting the multi-domain display technology. The region where the plurality of transistors is located is the non-opening area, and the region where the first pixel electrode 20 and the second pixel electrode 30 are located is the opening area. In the unit area of the sub-pixel SP, by reducing the area of the non-opening area, the area of the opening area can be increased, so as to improve the opening rate.

[0027] Optionally, continuing to refer to FIG. 3, the first pixel electrode 20 comprises a first trunk electrode 21, a first frame electrode 22, and a first branch electrode 23 connected to the first trunk electrode 21 and the first frame electrode 22. The first trunk electrode 21 comprises a first sub-electrode part 211 extending in the same direction as the data line DL and a third sub-electrode part 212 extending in the same direction as the scan line SL. The first sub-electrode part 211 passes through the midpoint of the third sub-electrode part 212, and the first sub-electrode part 211 and the third sub-electrode part 212 are perpendicular to each other, so as to divide the first pixel electrode 20 into four display domain areas. The first branch electrode 23 in each of the display domain areas extends from the first sub-electrode part 211 or the third sub-electrode part 212 in different directions, the extension directions of the first branch electrode 23 in each of the display domain areas are the same, and the first branch electrode 23 in adjacent two of the display domain areas is symmetrical about the first sub-electrode part 211 or the third sub-electrode part 212.

[0028] The second pixel electrode 30 comprises a second trunk electrode 31, a second frame electrode 32, and a second branch electrode 33 connected to the second trunk electrode 31 and the second frame electrode 32. The second trunk electrode 31 comprises a second sub-electrode part 311 extending in the same direction as the data line DL, and a fourth sub-electrode part 312 extending in the same direction as the scan line SL. In the second direction Y, the length of the second sub-electrode part 311 is greater than the length of the first sub-electrode part 211; in the first direction X, the length of the fourth sub-electrode part 312 is equal to the length of the third sub-electrode part 212. The second sub-electrode part 311 passes through the midpoint of the fourth sub-electrode part 312, and the second sub-electrode part 311 and the fourth sub-electrode part 312 perpendicularly intersect to divide the second pixel electrode 30 into four display domains. The second branch electrode 33 in each display domain extends from the second sub-electrode part 311 or the fourth sub-electrode part 312 in different directions, and the second branch electrode 33 in each display domain extends in the same direction, and the second branch electrode 33 in two adjacent display domains is symmetrical about the second sub-electrode part 311 or the fourth sub-electrode part 312.

[0029] Of course, in other embodiments, the first trunk electrode 21 of the first pixel electrode 20 can not comprise the third sub-electrode part 212, in which case the first pixel electrode 20 is divided by the first sub-electrode part 211 into two display domains, and correspondingly, the second pixel electrode 30 can also comprise two display domains. In addition, the first pixel electrode 20 can also not comprise a first frame electrode 22, and the second pixel electrode 30 can also not comprise a second frame electrode 32.

[0030] Optionally, the first pixel electrode 20 and the second pixel electrode 30 are disposed in the same layer. In the present application, "disposed in the same layer" means that in the preparation process, a film layer formed of the same material is patterned to obtain at least two different structures, and the at least two different structures are disposed in the same layer. For example, in the present embodiment, the first pixel electrode 20 and the second pixel electrode 30 are obtained by patterning a same conductive film layer, and the first pixel electrode 20 and the second pixel electrode 30 are disposed in the same layer. The materials of the first pixel electrode 20 and the second pixel electrode 30 both comprise transparent conductive materials such as indium tin oxide (ITO).

[0031] A plurality of transistors are located between the first pixel electrode 20 and the second pixel electrode 30. The plurality of transistors includes a first transistor T1 electrically connected to the first pixel electrode 20 and a second transistor T2 electrically connected to the second pixel electrode 30. The first transistor T1 and the second transistor T2 are both thin film transistors. The first transistor T1 is configured to provide a driving voltage to the first pixel electrode 20, and the second transistor T2 is configured to provide a driving voltage to the second pixel electrode 30. The driving voltage provided by the first transistor T1 to the first pixel electrode 20 is different from the driving voltage provided by the second transistor T2 to the second pixel electrode 30. In this way, the brightness difference of the corresponding regions of the first pixel electrode 20 and the second pixel electrode 30 can be adjusted by adjusting the voltage ratio on the first pixel electrode 20 and the second pixel electrode 30, thereby forming a complementary in the viewing angle and improving the viewing angle.

[0032] Specifically, a first drain S1 of the first transistor T1 is connected to the data line DL, and a first source D1 of the first transistor T1 is connected to the first pixel electrode 20. The first drain S1 is located on the side of the first gate G1 away from the substrate 10. A second drain S2 of the second transistor T2 is connected to the same data line DL as the first drain S1 of the first transistor T1, and a second source D2 of the second transistor T2 is connected to the second pixel electrode 30. The second drain S2 is located on the side of the second gate G2 away from the substrate 10. The first drain S1 and the second drain S2 are both disposed in the same layer as the data line DL. The first drain S1 and the second drain S2 are both disposed in a U shape, and the openings of the U shapes are the same.

[0033] The first pixel electrode 20 is connected to the first transistor T1 through a first via hole H1. For example, the first pixel electrode 20 includes a first overlap portion 24 connected to the first source D1 of the first transistor T1. The first overlap portion 24 is located in the first via hole H1 and is in contact with the first source D1. The connection position of the first pixel electrode 20 and the first transistor T1 is the position of the first overlap portion 24, i.e., the position of the first via hole H1. The second pixel electrode 30 is connected to the second transistor T2 through a second via hole H2. For example, the second pixel electrode 30 includes a second overlap portion 34 connected to the second source D2 of the second transistor T2. The second overlap portion 34 is located in the second via hole H2 and is in contact with the second source D2. The connection position of the second pixel electrode 30 and the second transistor T2 is the position of the second overlap portion 34, i.e., the position of the second via hole H2.

[0034] Optionally, the first pixel electrode 20 further comprises a first extension electrode 25 connected between the first overlap portion 24 and the first branch electrode 23, the first extension electrode 25 is formed by the first branch electrode 23 extending towards the first overlap portion 24. The second pixel electrode 30 further comprises a second extension electrode 35 connected between the second overlap portion 34 and the second branch electrode 33, the second extension electrode 35 is formed by the second branch electrode 33 extending towards the second overlap portion 34.

[0035] In the first direction X, the first overlap portion 24 at least partially overlaps the first gate G1, and the second overlap portion 34 at least partially overlaps the second gate G2, so that the first overlap portion 24, the first gate G1, the second gate G2 and the second overlap portion 34 are arranged in sequence in the first direction X, so as to make full use of the space of the non-opening area in the first direction X, thereby reducing the space of the non-opening area in the second direction Y and improving the aperture ratio.

[0036] Optionally, the first gate G1 and the second gate G2 are integrally arranged. In the first direction X, the first overlap portion 24 at least partially overlaps the second overlap portion 34, for example, the line connecting the center points of the first overlap portion 24 and the second overlap portion 34 is parallel to the first direction X, so as to further reduce the space of the non-opening area in the second direction Y and improve the aperture ratio.

[0037] The array substrate 100 further comprises a common electrode line CL extending in the same direction as the scan line SL, and the common electrode line CL is arranged in the same layer as the scan line SL. One of the common electrode line CL and the scan line SL is close to the first pixel electrode 20, and the other is close to the second pixel electrode 30, for example, the common electrode is close to the first pixel electrode 20, and the scan line SL is close to the second pixel electrode 30. The orthographic projection of the first pixel electrode 20 on the substrate 10 covers the edge of the orthographic projection of the common electrode on the substrate 10, and the orthographic projection of the second pixel electrode 30 on the substrate 10 covers the edge of the orthographic projection of the scan line SL on the substrate 10. The first overlap portion 24, the second overlap portion 34, the first gate G1 and the second gate G2 are all located between the common electrode line CL and the scan line SL, and all have a gap with the common electrode. The first gate G1 and the second gate G2 are formed by the scan line SL protruding towards the common electrode.

[0038] In an embodiment, the array substrate 100 further comprises a first shielding electrode 41 connected with the common electrode line CL, the first shielding electrode 41 comprises a first shielding portion 411 located between the first overlap portion 24 and the adjacent data line DL to shield the electric field between the first overlap portion 24 and the corresponding data line DL, reduce the parasitic capacitance between the first overlap portion 24 and the corresponding data line DL, and further improve the crosstalk problem caused by the parasitic capacitance. Here, the adjacent data line DL refers to the data line DL which is closer to the first overlap portion 24 among the two data lines DL adjacent to the first overlap portion 24; and in order to reduce the wiring length, the data line DL adjacent to the first overlap portion 24 is the data line DL connected with the first transistor T1.

[0039] Optionally, the first shielding electrode 41 further comprises a second shielding portion 412 connected with the first shielding portion 411, the second shielding portion 412 is located between the first overlap portion 24 and the adjacent scan line SL, so that the first shielding electrode 41 forms a structure of half-enclosing the first overlap portion 24 to further reduce the parasitic capacitance between the first overlap portion 24 and the corresponding data line DL. In the first direction X, the second shielding portion 412 overlaps with the first gate G1, and the second shielding portion 412 has a gap with the first gate G1.

[0040] Optionally, the surface shape of the first shielding electrode 41 comprises an L shape or an arc shape, etc. The first shielding electrode 41 is arranged in the same layer as the common electrode, for example, the first shielding electrode 41 can be formed by extending the common electrode towards the direction close to the scan line SL.

[0041] In an embodiment, the array substrate 100 further comprises a second shielding electrode 42 connected with the common electrode line CL, the second shielding electrode 42 is located on the side of the second overlap portion 34 away from the first overlap portion 24 to shield the electric field between the second overlap portion 34 and the corresponding data line DL, reduce the parasitic capacitance between the second overlap portion 34 and the corresponding data line DL, and further improve the crosstalk problem caused by the parasitic capacitance. Optionally, the second shielding electrode 42 is arranged in the same layer as the common electrode, for example, the second shielding electrode 42 can be formed by extending the common electrode towards the direction close to the scan line SL.

[0042] In an embodiment, the array substrate 100 further comprises a third shielding electrode 43 extending in the same direction as the data line DL, the third shielding electrode 43 is arranged corresponding to the first frame electrode 22, and the third shielding electrode 43 is connected with the common electrode. The third shielding electrode 43 is located between the first pixel electrode 20 and the adjacent data line DL to shield the electric field between the first pixel electrode 20 and the adjacent data line DL, reduce the parasitic capacitance between the first pixel electrode 20 and the adjacent data line DL, and further improve the crosstalk problem caused by the parasitic capacitance. Optionally, the third shielding electrode 43 is arranged in the same layer as the common electrode, for example, the third shielding electrode 43 can be formed by extending the common electrode away from the scan line SL.

[0043] In an embodiment, the array substrate 100 further comprises a fourth shielding electrode 44 extending in the same direction as the data line DL, the fourth shielding electrode 44 is arranged corresponding to the second frame electrode 32, and the fourth shielding electrode 44 has a gap with the common electrode. The fourth shielding electrode 44 is located between the second pixel electrode 30 and the adjacent data line DL to shield the electric field between the second pixel electrode 30 and the adjacent data line DL, reduce the parasitic capacitance between the second pixel electrode 30 and the adjacent data line DL, and further improve the crosstalk problem caused by the parasitic capacitance. Optionally, the fourth shielding electrode 44 is arranged in the same layer as the common electrode.

[0044] In an embodiment, the plurality of transistors further comprises a third transistor T3, and the type of the third transistor T3 is the same as that of the first transistor T1 and / or the second transistor T2. The third transistor T3 is connected in series with the second transistor T2 to divide the voltage of the second transistor T2, so that the driving voltage provided by the second transistor T2 to the second pixel electrode 30 is less than the driving voltage provided by the first transistor T1 to the first pixel electrode 20, and further the voltage on the second pixel electrode 30 is less than the voltage on the first pixel electrode 20. Specifically, a third drain S3 of the third transistor T3 is connected with a second source D2 of the second transistor T2, a third gate G3 of the third transistor T3 is connected with the scan line SL, and the third gate G3 and the first gate G1 are located on the same side of the scan line SL.

[0045] The array substrate 100 further comprises a shared discharge rod SB, which is located between two adjacent data lines DL and is arranged correspondingly to the first sub-electrode part 211 and the second sub-electrode part 311, and in the first direction X, the width of the shared discharge rod SB is less than or equal to the width of the first sub-electrode part 211 and the second sub-electrode part 311, so as to avoid affecting the transmittance of the aperture area. The shared discharge rod SB is connected to the third source D3 of the third transistor T3, so that the third transistor T3 divides the voltage of the second transistor T2. The shared discharge rod SB is arranged in the same layer as the data line DL.

[0046] Optionally, in combination with FIGS. 3 and 4, the array substrate 100 further comprises a first light shielding electrode 51 arranged correspondingly to the first sub-electrode part 211 and a second light shielding electrode 52 arranged correspondingly to the second sub-electrode part 311. The first light shielding electrode 51 is located on the side of the shared discharge rod SB away from the first sub-electrode part 211, and the first light shielding electrode 51 is connected to the third shielding electrode 43 and the common electrode. The second light shielding electrode 52 is located on the side of the shared discharge rod SB away from the second sub-electrode part 311, and the second light shielding electrode 52 is connected to the fourth shielding electrode 44. In the first direction X, the width of the first light shielding electrode 51 is greater than the width of the first sub-electrode part 211, and the width of the second light shielding electrode 52 is greater than the width of the second sub-electrode part 311, so as to shield the shared discharge rod SB. It should be noted that when the array substrate 100 is prepared by using a 4Msak process, all structures arranged in the same layer as the data line DL comprise a metal layer and a semiconductor part located below the metal layer, such as the shared discharge rod SB comprising a metal layer and a semiconductor part located below the metal layer. Therefore, by shielding the shared discharge rod SB by the first light shielding electrode 51 and the second light shielding electrode 52, the semiconductor part in the shared discharge rod SB can be prevented from light leakage.

[0047] In an embodiment, continuing to refer to FIG. 3, the array substrate 100 further comprises a third light shielding electrode 53, which is located on the side of the data line DL away from the substrate 10, and in the first direction X, the width of the third light shielding electrode 53 is greater than the width of the data line DL, so as to shield the data line DL. The third light shielding layer is arranged in the same layer as the first pixel electrode 20 and the second pixel electrode 30.

[0048] The film layer structure of the array substrate 100 will be described below by taking the first transistor T1 and the second transistor T2 as examples.

[0049] Referring to FIG. 5, the array substrate 100 further includes a first conductive layer 1, a gate insulating layer 12, a semiconductor layer 2, a second conductive layer 3, a planarization layer 13, and a third conductive layer 4, which are disposed on the substrate 10. The first conductive layer 1 is disposed on the substrate 10, and the first conductive layer 1 is formed with the scan line SL and the first gate G1 of the first transistor T1, the second gate G2 of the second transistor T2. Optionally, the first conductive layer 1 is further formed with the third gate G3 of the third transistor T3, the common electrode line CL, the first shielding electrode 41, the second shielding electrode 42, the third shielding electrode 43, the fourth shielding electrode 44, the first light shielding electrode 51, and the second light shielding electrode 52. The first conductive layer 1 can be formed as a plurality of layers or a single layer including a low-resistance material such as Al, Ti, Mo, Cu, Ni, or an alloy thereof, or a material having high corrosion resistance.

[0050] Optionally, the substrate 10 can be a rigid substrate or a flexible substrate. When the substrate 10 is a rigid substrate, the substrate 10 can include a hard substrate such as a glass substrate. When the substrate 10 is a flexible substrate, the substrate 10 can include a flexible substrate such as a polyimide (PI) film or an ultra-thin glass film.

[0051] Optionally, a buffer layer 11 can be further disposed between the substrate 10 and the first conductive layer 1. The buffer layer 11 can prevent the diffusion of undesired impurities or contaminants (e.g., moisture, oxygen, etc.) from the substrate 10 to devices that can be damaged by these impurities or contaminants, and can also provide a flat top surface. For example, the material of the buffer layer 11 can include an inorganic material such as silicon oxide or silicon nitride.

[0052] The gate insulating layer 12 is disposed on a side of the first metal layer away from the substrate 10. The gate insulating layer 12 can be a plurality of layers or a single layer including at least one of tetraethyl orthosilicate, silicon nitride, and silicon oxide.

[0053] The semiconductor layer 2 and the second conductive layer 3 are disposed on the side of the first conductive layer 1 away from the substrate 10, and the second conductive layer 3 is formed with the data line DL, the first drain S1 and the first source D1 of the first transistor T1, the second drain S2 and the second source D2 of the second transistor T2, the third drain S3 and the third source D3 of the third transistor T3, and the shared discharging rod SB. The semiconductor layer 2 is formed with the first active part AS1 of the first transistor T1 and the second active part AS2 of the second transistor T2. Optionally, the semiconductor layer 2 can be formed of polysilicon. The second conductive layer 3 can be formed as a plurality of layers or a single layer of a low-resistance material such as Al, Ti, Mo, Cu, Ni or an alloy thereof, or a material with high corrosion resistance. For example, the second conductive layer 3 can be a triple layer of Ti / Cu / Ti, Ti / Ag / Ti, Ti / Al / Ti or Mo / Al / Mo, and others.

[0054] The planar layer 13 is disposed on the side of the second conductive layer 3 away from the substrate 10, and the planar layer 13 is provided with the first via hole H1 at the position corresponding to the first source D1 and the second via hole H2 at the position corresponding to the second source D2. The planar layer 13 can be formed of an organic material including resin such as polyacrylate or polyimide, silica, and the like.

[0055] The third conductive layer 4 is disposed on the side of the planar layer 13 away from the substrate 10, and the third conductive layer 4 is formed with the first pixel electrode 20, the second pixel electrode 30 and the third light-shielding electrode 53. The third conductive layer 4 can be formed of a material such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO) or indium oxide (In2O3).

[0056] The first overlap portion 24 is located in the first via hole H1, the second overlap portion 34 is located in the second via hole H2, the orthographic projection of the first overlap portion 24 on the substrate 10 is separated from the orthographic projection of the first conductive layer 1 on the substrate 10, the orthographic projection of the second overlap portion 34 on the substrate 10 is separated from the orthographic projection of the first conductive layer 1 on the substrate 10, that is, the orthographic projection of the first overlap portion 24 on the substrate 10 does not overlap with the orthographic projection of the first conductive layer 1 on the substrate 10, and the orthographic projection of the second overlap portion 34 on the substrate 10 does not overlap with the orthographic projection of the first conductive layer 1 on the substrate 10, so that the connection position of the first transistor T1 and the first pixel electrode 20 does not form a storage capacitor, and the connection position of the second transistor T2 and the second pixel electrode 30 does not form a storage capacitor. Compared with the sub-pixel structure shown in FIG. 1, the sub-pixel structure of the embodiment removes the first storage capacitor and the second storage capacitor in the non-opening area, so as to further reduce the area of the non-opening area and improve the pixel aperture ratio; and the interference caused by the storage capacitor can also be improved.

[0057] It should be noted that in the sub-pixel structure shown in FIG. 1, the storage capacitor (such as the first storage capacitor C1' and the second storage capacitor C2') is composed of a common electrode line CL', an insulating layer, a semiconductor layer and a pixel electrode (such as the first pixel electrode 20' and the second pixel electrode 30'). When the panel driving mode is positive-negative frame driving, the voltage value of the common electrode line CL' under positive-negative frame is unchanged, and the voltage value of the pixel electrode is different in positive frame and negative frame, so that the direction of the electric field in the storage capacitor in the positive frame is different from that in the negative frame. Due to the existence of the semiconductor layer, the size of the storage capacitor on the common electrode line CL' is affected by the direction of the electric field, and the size of the storage capacitor in the positive frame is different from that in the negative frame, resulting in different brightness in the positive frame and the negative frame, and further causing a series of problems such as crosstalk. In the embodiment, by removing the storage capacitor in the non-opening area, not only the pixel aperture ratio can be further improved, but also the interference caused by the storage capacitor can be avoided.

[0058] Based on the same inventive concept, the application further provides a display panel. Please refer to FIG. 1 to FIG. 6, and FIG. 6 shows a schematic diagram of a cross-sectional structure of the display panel in the application. The display panel comprises the array substrate 100 in any one of the foregoing embodiments. The display panel is a liquid crystal display panel, and the display panel in the embodiment is taken as a liquid crystal display panel for example. Specifically, referring to FIG. 6, the display panel 1000 comprises a first substrate and a second substrate arranged oppositely, and one of the first substrate and the second substrate is the array substrate 100 in any one of the foregoing embodiments. The first substrate is taken as the array substrate 100 for example in the embodiment, and the second substrate 200 is a color film substrate. The display panel 1000 further comprises liquid crystal molecules 300 sandwiched between the array substrate 100 and the second substrate 200.

[0059] According to the foregoing embodiments, it can be known that:

[0060] The application provides an array substrate and a display panel. The array substrate comprises a plurality of sub-pixels arranged in an array. A data line is located between two adjacent columns of sub-pixels and connected to at least one column of sub-pixels. A scan line is located between a first pixel electrode and a second pixel electrode of each row of sub-pixels and connected to a first gate of a first transistor and a second gate of a second transistor. The first gate and the second gate are located on the same side of the scan line. The first pixel electrode is connected to the first transistor through a first via. The second pixel electrode is connected to the second transistor through a second via. In each sub-pixel, the first via is located on a side of the first gate close to the data line connected to the sub-pixel. The second via is located on a side of the second gate away from the first gate. In this way, by arranging the first gate and the second gate on the same side of the scan line and arranging the first via and the second via on opposite sides of the first gate, the distance between the first gate, the second gate and the opening region can be reduced, thereby reducing the area of the non-opening region, improving the aperture ratio and solving the technical problem of low aperture ratio of the existing liquid crystal display panel using multi-domain display technology.

[0061] In the foregoing embodiments, the description of each embodiment has its own focus. The parts not described in detail in a certain embodiment can be referred to the relevant description of other embodiments.

[0062] The embodiments of the application are described in detail above, and the specific examples are applied to explain the principles and implementation manners of the application. The above description of the embodiments is only used to help understand the technical solutions and core ideas of the application; those skilled in the art should understand that the technical solutions recorded in the foregoing embodiments can be modified, or some technical features can be replaced by equivalents; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the application.

Claims

1. An array substrate, comprising: a substrate; a plurality of sub-pixels arranged in an array on the substrate, each of the sub-pixels comprising a first pixel electrode, a second pixel electrode, and a plurality of transistors located between the first pixel electrode and the second pixel electrode, the plurality of transistors comprising a first transistor and a second transistor, the first pixel electrode being connected to the first transistor through a first via, the second pixel electrode being connected to the second transistor through a second via; a plurality of data lines arranged in an array on the substrate in a first direction, each of the data lines being located on one side of the sub-pixels and connected to the corresponding sub-pixels, the first pixel electrode and the second pixel electrode of each of the sub-pixels being arranged in a second direction in sequence; a plurality of scan lines arranged in an array on the substrate in the second direction, each of the scan lines being located between the first pixel electrode and the second pixel electrode of each row of the sub-pixels and connected to a first gate of the first transistor and a second gate of the second transistor of each of the sub-pixels, the first gate and the second gate being arranged in the first direction in sequence, and the first gate and the second gate being located on the same side of the scan line connected thereto; wherein, in each of the sub-pixels, the first via is located on a side of the first gate close to the data line connected to the sub-pixel, the second via is located on a side of the second gate away from the first gate, and the first via and the second via are located on the same side of the scan line.

2. The array substrate according to claim 1, wherein, the first pixel electrode comprises a first overlap portion connected to a first source of the first transistor, the first overlap portion being located in the first via; and the second pixel electrode comprises a second overlap portion connected to a second source of the second transistor, the second overlap portion being located in the second via; in the first direction, the first overlap portion at least partially overlaps the first gate, and the second overlap portion at least partially overlaps the second gate.

3. The array substrate according to claim 2, wherein, the first gate and the second gate are integrally arranged; and a line connecting a center point of the first overlap portion and a center point of the second overlap portion is parallel to the first direction.

4. The array substrate of claim 2, wherein, the array substrate further comprises a common electrode line extending in the same direction as the scan lines, one of the common electrode line and the scan lines being close to the first pixel electrode, and the other being close to the second pixel electrode, the first overlap portion, the second overlap portion, the first gate, and the second gate all being located between the common electrode line and the scan lines.

5. The array substrate according to claim 4, wherein, the array substrate further comprises a first shielding electrode connected to the common electrode line, the first shielding electrode comprising a first shielding portion, the first shielding portion being located between the first overlap portion and the adjacent data line.

6. The array substrate according to claim 5, wherein, the first shielding electrode further comprises a second shielding portion connected to the first shielding portion, the second shielding portion being located between the first overlap portion and the adjacent scan line.

7. The array substrate according to claim 4, wherein, The array substrate further comprises a second shielding electrode connected with the common electrode line, and the second shielding electrode is located on a side of the second overlap portion away from the first overlap portion.

8. The array substrate of claim 4, wherein, The first pixel electrode comprises a first trunk electrode, a first frame electrode and a first branch electrode connected with the first trunk electrode and the first frame electrode, and the second pixel electrode comprises a second trunk electrode, a second frame electrode and a second branch electrode connected with the second trunk electrode and the second frame electrode. The array substrate further comprises a third shielding electrode in the same extension direction as the data line, the third shielding electrode is arranged corresponding to the first frame electrode, and the third shielding electrode is connected with the common electrode. And / or, the array substrate further comprises a fourth shielding electrode in the same extension direction as the data line, the fourth shielding electrode is arranged corresponding to the second frame electrode, and there is a gap between the fourth shielding electrode and the common electrode.

9. The array substrate of claim 8, wherein, The first trunk electrode comprises a first sub-electrode portion in the same extension direction as the data line, and the second trunk electrode comprises a second sub-electrode portion in the same extension direction as the data line. The plurality of transistors further comprises a third transistor, a third drain of the third transistor is connected with a second source of the second transistor, a third gate of the third transistor is connected with the scan line, and the third gate and the first gate are located on the same side of the scan line. The array substrate further comprises a shared discharge rod, the shared discharge rod is located between two adjacent data lines, and is arranged corresponding to the first sub-electrode portion and the second sub-electrode portion, and the shared discharge rod is connected with a third source of the third transistor.

10. The array substrate of claim 9, wherein, The array substrate further comprises a first light shielding electrode arranged corresponding to the first sub-electrode portion and a second light shielding electrode arranged corresponding to the second sub-electrode portion, the first light shielding electrode is located on a side of the shared discharge rod away from the first sub-electrode portion, the first light shielding electrode is connected with the third shielding electrode and the common electrode, the second light shielding electrode is located on a side of the shared discharge rod away from the second sub-electrode portion, and the second light shielding electrode is connected with the fourth shielding electrode.

11. The array substrate according to any one of claims 4 to 10, wherein, The array substrate further comprises: A first conductive layer is arranged on the substrate, and the first conductive layer forms the scan line, the common electrode line, the first gate and the second gate; A second conductive layer is arranged on a side of the first conductive layer away from the substrate, and the second conductive layer forms the data line, the first source and the second source; A planar layer is arranged on a side of the second conductive layer away from the substrate, the planar layer is provided with a first via hole at a position corresponding to the first source and a second via hole at a position corresponding to the second source; A third conductive layer is arranged on a side of the planar layer away from the substrate, and the third conductive layer forms the first pixel electrode and the second pixel electrode. The first overlap portion is located in the first via hole, the second overlap portion is located in the second via hole, a projection of the first overlap portion on the substrate is separate from a projection of the first conductive layer on the substrate, and a projection of the second overlap portion on the substrate is separate from the projection of the first conductive layer on the substrate.

12. The array substrate according to any one of claims 1 to 10, wherein, The first drain of the first transistor and the second drain of the second transistor are connected to the same data line, and the first drain and the second drain are arranged in a U shape and have the same opening of the U shape.

13. A display panel, comprising an array substrate, the array substrate comprising: a substrate; a plurality of sub-pixels arranged in an array on the substrate, each sub-pixel comprising a first pixel electrode, a second pixel electrode, and a plurality of transistors located between the first pixel electrode and the second pixel electrode, the plurality of transistors comprising a first transistor and a second transistor, the first pixel electrode being connected to the first transistor through a first via hole, and the second pixel electrode being connected to the second transistor through a second via hole; a plurality of data lines arranged at intervals in a first direction on the substrate, each data line being located on one side of a corresponding sub-pixel and connected to the corresponding sub-pixel, the first pixel electrode and the second pixel electrode of each sub-pixel being arranged in a second direction in sequence; a plurality of scan lines arranged at intervals in the second direction on the substrate, each scan line being located between the first pixel electrode and the second pixel electrode of each row of sub-pixels and connected to a first gate of the first transistor and a second gate of the second transistor of each sub-pixel, the first gate and the second gate being arranged in sequence in the first direction, and the first gate and the second gate being located on the same side of the scan line connected thereto; wherein, in each sub-pixel, the first via hole is located on a side of the first gate close to the data line connected to the sub-pixel, the second via hole is located on a side of the second gate away from the first gate, and the first via hole and the second via hole are located on the same side of the scan line.

14. The display panel of claim 13, wherein, The first pixel electrode comprises a first overlap portion connected to a first source of the first transistor, and the first overlap portion is located in the first via hole; and the second pixel electrode comprises a second overlap portion connected to a second source of the second transistor, and the second overlap portion is located in the second via hole. In the first direction, the first overlap portion at least partially overlaps the first gate, and the second overlap portion at least partially overlaps the second gate.

15. The display panel of claim 14, wherein, The first gate and the second gate are integrally arranged; and a line connecting a center point of the first overlap portion and a center point of the second overlap portion is parallel to the first direction.

16. The display panel of claim 14, wherein, The array substrate further comprises a common electrode line extending in the same direction as the scan lines, one of the common electrode line and the scan lines is close to the first pixel electrode, and the other is close to the second pixel electrode, and the first overlap portion, the second overlap portion, the first gate and the second gate are all located between the common electrode line and the scan lines.

17. The display panel of claim 16, wherein, The array substrate further comprises a first shielding electrode connected to the common electrode line, and the first shielding electrode comprises a first shielding portion, and the first shielding portion is located between the first overlap portion and the adjacent data line.

18. The display panel of claim 17, wherein, The first shielding electrode further comprises a second shielding portion connected to the first shielding portion, and the second shielding portion is located between the first overlap portion and the adjacent scan line.

19. The display panel of claim 16, wherein, The array substrate further comprises a second shielding electrode connected to the common electrode line, and the second shielding electrode is located on a side of the second overlap portion away from the first overlap portion.

20. The display panel of claim 16, wherein, The first pixel electrode comprises a first trunk electrode, a first frame electrode and a first branch electrode connected to the first trunk electrode and the first frame electrode, and the second pixel electrode comprises a second trunk electrode, a second frame electrode and a second branch electrode connected to the second trunk electrode and the second frame electrode. The array substrate further comprises a third shielding electrode extending in the same direction as the data lines, the third shielding electrode is arranged corresponding to the first frame electrode, and the third shielding electrode is connected to the common electrode. And / or, the array substrate further comprises a fourth shielding electrode extending in the same direction as the data lines, the fourth shielding electrode is arranged corresponding to the second frame electrode, and there is a gap between the fourth shielding electrode and the common electrode.

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