Battery

Abstract

Provided in the present application is a battery. The battery comprises a passivation layer and a single-crystal silicon layer, wherein the passivation layer is present on the surface of the single-crystal silicon layer; and the passivation layer comprises a compound represented by formula 1. In the formula, R1, R2, R3 and R4 are each independently selected from one of a substituted or unsubstituted C1-C20 alkyl, a halogen, a substituted or unsubstituted amino and a substituted or unsubstituted C1-C20 alkoxy; and at least one of R1, R2, R3 and R4 comprises a substituted or unsubstituted C1-C20 alkyl or a substituted or unsubstituted amino, wherein the substituent of the alkyl, the substituent of the amino and the substituent of the alkoxy are each independently selected from one of a halogen, an amino and -Si(CxH2x+1)3, with x being an integer of 1-20. The passivation layer in the battery of the present application can reduce parasitic absorption of the battery and improve the photoelectric conversion efficiency of the battery.

Description

A battery

[0001] The present application claims priority to the Chinese patent application No. 202411103908.5, filed on August 13, 2024, and entitled "A battery", the content of which is incorporated herein by reference in its entirety. TECHNICAL FIELD

[0002] The present application relates to the technical field of photovoltaic cells, in particular to a battery. BACKGROUND

[0003] Nowadays, with the development of society, non-renewable resources such as coal and oil are decreasing, and in order to develop human society, it is urgent to develop renewable energy. Solar energy is inexhaustible new energy, and solar cells can convert solar radiation into electrical energy. Among them, heterojunction solar (HJT) cells, Topcon cells and heterojunction / perovskite stacked cells can achieve high photoelectric conversion efficiency, so these cells are highly concerned in the solar industry and are considered an important direction for the development of future solar cells.

[0004] Currently, in solar cells, hydrogenated amorphous silicon is used as a passivation layer, which can effectively recombine single crystal silicon surface dangling bonds and reduce single crystal silicon surface carrier recombination, thereby obtaining a larger open-circuit voltage and excellent photoelectric conversion efficiency. However, although the hydrogenated amorphous silicon layer ensures the passivation effect of the cell piece, the serious parasitic absorption caused by the hydrogenated amorphous silicon layer is an important factor restricting the further efficiency improvement of solar cells.

[0005] Therefore, those skilled in the art urgently need to develop a battery including a passivation layer capable of reducing parasitic absorption, so that the battery has excellent photoelectric conversion efficiency. SUMMARY

[0006] The present application provides a battery including a passivation layer capable of reducing parasitic absorption, which has excellent photoelectric conversion efficiency.

[0007] The solar cell module provided by the present application includes the above-mentioned battery and has excellent photoelectric conversion performance.

[0008] The present application provides a battery, wherein the battery includes a passivation layer and a single crystal silicon layer, the passivation layer is present on the surface of the single crystal silicon layer; the passivation layer includes a compound represented by Formula 1:

[0009] wherein R1, R2, R3, R4 are each independently selected from one of substituted or unsubstituted C1-C20 alkyl, halogen, substituted or unsubstituted amino, substituted or unsubstituted C1-C20 alkoxy, and at least one of R1, R2, R3, R4 includes the substituted or unsubstituted C1-C20 alkyl or the substituted or unsubstituted amino;

[0010] the substituents of the alkyl, the substituents of the amino, and the substituents of the alkoxy are each independently selected from one of halogen, amino, -Si(C x H 2x+1 )3, and x is an integer of 1-20.

[0011] The battery as described above, wherein R1, R2, R3, R4 are each independently selected from one of substituted or unsubstituted C1-C18 alkyl, halogen, substituted or unsubstituted amino, substituted or unsubstituted C1-C18 alkoxy; the substituents of the alkyl, the substituents of the amino, and the substituents of the alkoxy are each independently selected from one of halogen, amino, -Si(C x H 2x+1 )3, and x is an integer of 1-18.

[0012] The battery as described above, wherein the compound represented by Formula 1 includes one of octadecyltrichlorosilane, 3-aminopropyltriethoxysilane, 1H,1H,2H,2H-perfluorooctyltrichlorosilane, hexamethyldisilazane, octadecyltrimethoxysilane.

[0013] The battery as described above, wherein the thickness of the passivation layer is 2-5 nm.

[0014] The battery as described above, wherein the battery includes a first transparent conductive oxide layer, an n-type doped silicon layer, the passivation layer, a single crystal silicon layer, the passivation layer, a p-type doped silicon layer, a second transparent conductive oxide layer, which are sequentially stacked.

[0015] The battery as described above, wherein the thickness of the first transparent conductive oxide layer is 60-140 nm.

[0016] The battery as described above, wherein the thickness of the p-type doped silicon layer is 10-30 nm.

[0017] The battery as described above, wherein the thickness of the n-type doped silicon layer is 10-25 nm.

[0018] The battery as described above, wherein the thickness of the single crystal silicon layer is 50-150 μm.

[0019] The battery as described above, wherein the thickness of the second transparent conductive oxide layer is 60-140 nm.

[0020] The battery as described above, wherein the p-type doped silicon in the p-type doped silicon layer comprises at least one of p-type doped amorphous silicon, p-type doped microcrystalline silicon.

[0021] The battery as described above, wherein the n-type doped silicon in the n-type doped silicon layer comprises at least one of n-type doped amorphous silicon, n-type doped microcrystalline silicon and n-type doped microcrystalline silicon doped with oxygen.

[0022] The battery as described above, wherein the transparent conductive oxide in the first transparent conductive oxide layer comprises at least one of indium tin oxide, aluminum-doped zinc oxide and fluorine-doped tin oxide; and / or, the transparent conductive oxide in the second transparent conductive oxide layer comprises at least one of indium tin oxide, aluminum-doped zinc oxide and fluorine-doped tin oxide.

[0023] The battery as described above, wherein the single crystal silicon layer comprises at least one of n-type single crystal silicon layer and p-type single crystal silicon layer.

[0024] The battery as described above, wherein the battery is prepared by a method comprising the following processes:

[0025] The single crystal silicon is subjected to a heating treatment in a vapor atmosphere of the compound shown in formula 1 to obtain a single crystal silicon comprising the passivation layer, and then an n-type doped silicon layer and a p-type doped silicon layer are deposited on the front and back surfaces of the single crystal silicon comprising the passivation layer, respectively, and then the first transparent conductive oxide layer is deposited on the side of the n-type doped silicon layer away from the passivation layer, and the second transparent conductive oxide layer is deposited on the side of the p-type doped silicon layer away from the passivation layer, to obtain the battery.

[0026] The vacuum degree of the heating treatment is 10 -4 -10 -1 Pa, the heating temperature is 100-180℃, and the heating time is 40-60 min.

[0027] The battery as described above, wherein the battery comprises, which are sequentially stacked, a SiN x antireflection layer, the passivation layer, a p+ doped single crystal silicon layer, an n doped single crystal silicon layer, a tunneling oxide layer, an n+ doped polycrystalline silicon layer and a SiN x antireflection layer.

[0028] The battery as described above, wherein the battery comprises, which are sequentially stacked, the first transparent conductive oxide layer, an electron transport layer, a perovskite layer, a hole transport layer, the passivation layer, an n-type doped microcrystalline silicon layer, the passivation layer, an n-type single crystal silicon layer, the passivation layer, a p-type doped microcrystalline silicon layer and the second transparent conductive oxide layer.

[0029] The application provides a solar cell module comprising the above-mentioned battery.

[0030] The battery provided by the application comprises a passivation layer and a monocrystalline silicon layer, the passivation layer is present on the surface of the monocrystalline silicon layer, the passivation layer is composed of a compound represented by Formula 1, the compound represented by Formula 1 can react with the dangling bonds on the surface of the monocrystalline silicon to generate the passivation layer, thereby achieving high passivation effect, and after the dangling bonds on the surface of the monocrystalline silicon are saturated by the reaction, no dangling bonds are generated on the surface of the passivation layer, the further growth of the compound represented by Formula 1 on the passivation layer is inhibited, thereby effectively reducing parasitic absorption and further improving the photoelectric conversion efficiency of the battery.

[0031] The solar cell module provided by the application is prepared based on the above-mentioned battery, has excellent photoelectric conversion performance, and can be widely applied to the photovoltaic industry. BRIEF DESCRIPTION OF DRAWINGS

[0032] FIG. 1 is a schematic structural diagram of a heterojunction battery.

[0033] Label explanation: 1-first transparent conductive oxide layer; 2-n-type doped silicon layer; 3-passivation layer; 4-monocrystalline silicon layer; 5-p-type doped silicon layer; 6-second transparent conductive oxide layer. DETAILED DESCRIPTION

[0034] To make the objectives, technical solutions and advantages of the application clearer, the technical solutions in the embodiments of the application will be described clearly and completely below in conjunction with the embodiments of the application. Obviously, the described embodiments are only some of the embodiments of the application, rather than all the embodiments of the application. Based on the embodiments in the application, all other embodiments obtained by those skilled in the art without creative work fall within the scope of protection of the application.

[0035] The application provides a battery, which comprises a passivation layer and a monocrystalline silicon layer, and the passivation layer is present on the surface of the monocrystalline silicon layer.

[0036] wherein R1, R2, R3 and R4 are each independently selected from one of substituted or unsubstituted C1-C20 alkyl, halogen, substituted or unsubstituted amino and substituted or unsubstituted C1-C20 alkoxy, and at least one of R1, R2, R3 and R4 comprises substituted or unsubstituted C1-C20 alkyl or substituted or unsubstituted amino;

[0037] the substituents of the alkyl group, the substituents of the amino group and the substituents of the alkoxy group are each independently selected from one of halogen, amino, -Si(C x H 2x+1 )3 and x is an integer from 1 to 20.

[0038] The passivation layer of the present application is a layer covering the surface of the solar cell sheet, which can reduce the activity of the cell sheet surface, reduce the surface recombination rate, and improve the photoelectric conversion efficiency of the solar cell. At the same time, the passivation layer can protect the cell sheet from the erosion of the external environment and improve the stability of the cell sheet.

[0039] The passivation layer of the present application includes a compound shown in Formula 1, wherein R1, R2, R3, R4 are each independently selected from one of substituted or unsubstituted C1-C20 alkyl, halogen, substituted or unsubstituted amino, substituted or unsubstituted C1-C20 alkoxy, and at least one of R1, R2, R3, R4 includes substituted or unsubstituted C1-C20 alkyl or substituted or unsubstituted amino; the substituent of alkyl, the substituent of amino and the substituent of alkoxy are each independently selected from one of halogen, amino, -Si(C x H 2x+1 )3, and x is an integer of 1-20. The substituted or unsubstituted C1-C20 alkyl of the present application refers to a chain alkyl having a substituent or not having a substituent with a carbon number of 1-20 or a ring alkyl having a substituent or not having a substituent with a carbon number of 3-20, and the substituent of alkyl includes one of halogen, amino, -Si(C x H 2x+1 )3, and x is an integer of 1-20; halogen refers to at least one of F, Cl, Br, I; substituted or unsubstituted amino refers to amino in which the hydrogen ion is replaced by a substituent, and the substituent of amino includes one of halogen, -Si(C x H 2x+1 )3; substituted or unsubstituted C1-C20 alkoxy refers to an alkoxy having a substituent or not having a substituent with a carbon number of 1-20, and the substituent of alkoxy includes one of halogen, amino, -Si(C x H 2x+1 )3, and x is an integer of 1-20. When specified as a hydrocarbon group with a specific carbon number, all geometric isomers with that carbon number are included. And at least one of R1, R2, R3, R4 includes substituted or unsubstituted C1-C20 alkyl or substituted or unsubstituted amino, that is, R1, R2, R3, R4 can be the same or different, but at least one of R1, R2, R3, R4 includes substituted or unsubstituted alkyl or substituted or unsubstituted amino.

[0040] According to the above scheme provided in the present application, the compound shown in formula 1 is used to prepare a passivation layer, which can reduce the parasitic absorption of the battery, so that the solar cell has excellent photoelectric conversion efficiency. The inventors analyzed the principle and considered that the reason may be that the compound shown in formula 1 can react with the dangling bond on the surface of monocrystalline silicon to form a passivation layer, achieving high passivation effect. After the dangling bond on the surface of monocrystalline silicon is saturated by reaction, no dangling bond is generated on the surface of the passivation layer, which can inhibit the further growth of the compound shown in formula 1 on the passivation layer, so that the thickness of the passivation layer is not higher than 5 nm, thereby effectively reducing the parasitic absorption, further improving the short-circuit current of the solar cell, and improving the photoelectric conversion efficiency of the battery.

[0041] In a specific embodiment, R1, R2, R3, R4 are each independently selected from one of substituted or unsubstituted C1-C18 alkyl, halogen, substituted or unsubstituted amino, substituted or unsubstituted C1-C18 alkoxy; the substituents of alkyl, amino and alkoxy are each independently selected from one of halogen, amino, -Si(C x H 2x+1 )3, and x is an integer from 1 to 18. When the substituents of the compound shown in formula 1 include the above substituents, the compound shown in formula 1 can more fully react with the dangling bond on the surface of monocrystalline silicon, so that the passivation effect of the passivation layer is better, and a passivation layer with lower thickness can be generated, further reducing the parasitic absorption, so that the photoelectric conversion efficiency of the battery is higher.

[0042] In a specific embodiment, the compound shown in formula 1 includes one of octadecyltrichlorosilane, 3-aminopropyltriethoxysilane, 1H,1H,2H,2H-perfluorooctyltrichlorosilane, hexamethyldisilazane, octadecyltrimethoxysilane. When the compound shown in formula 1 is selected from the above compounds, the passivation effect of the passivation layer generated by the compound shown in formula 1 is more optimal, and the further growth of the compound shown in formula 1 on the passivation layer can be better inhibited, further reducing the thickness of the passivation layer, so that the parasitic absorption of the battery is smaller, thereby obtaining higher photoelectric conversion efficiency.

[0043] In a specific embodiment, the thickness of the passivation layer is 2-5 nm, for example, 2 nm, 2.5 nm, 3 nm, 3.5 nm, 4 nm, 4.5 nm or 5 nm, etc. When the thickness of the passivation layer is within the above range, the passivation layer can exhibit excellent passivation efficiency, and can effectively reduce the parasitic absorption of the battery, thereby improving the short-circuit current of the solar cell, and further improving the photoelectric conversion efficiency of the battery to a greater extent.

[0044] In one specific embodiment, the battery comprises a heterojunction solar cell, as shown in FIG. 1, which comprises a first transparent conductive oxide layer 1, an n-type doped silicon layer 2, a passivation layer 3, a single crystal silicon layer 4, a passivation layer 3, a p-type doped silicon layer 5, and a second transparent conductive oxide layer 6, which are sequentially stacked.

[0045] The present application does not limit the specific selection of the transparent conductive oxide in the first transparent conductive oxide layer and the second transparent conductive oxide layer, as long as it can improve the conductivity of the heterojunction solar cell and enable the battery to conduct electricity.

[0046] The present application does not limit the specific selection of the p-type doped silicon and the n-type doped silicon in the p-type doped silicon layer and the n-type doped silicon layer, as long as the p-type doped silicon layer and the n-type doped silicon layer form a P-N junction to enable the heterojunction battery to perform photoelectric conversion.

[0047] The present application does not limit the specific selection of the single crystal silicon in the single crystal silicon layer, as long as the single crystal silicon can ensure high photoelectric conversion efficiency of the heterojunction battery.

[0048] The heterojunction battery of the present application is obtained by stacking the above-mentioned layers. The passivation layer exhibits effective passivation effect and can be well compounded with other layers to stabilize the heterojunction battery, while the parasitic absorption of the heterojunction battery is low, thereby achieving high photoelectric conversion efficiency.

[0049] In one specific embodiment, the thickness of the first transparent conductive oxide layer and the second transparent conductive oxide layer is 60-140 nm, for example, 60 nm, 70 nm, 80 nm, 90 nm, 100 nm, 110 nm, 120 nm, 130 nm, or 140 nm, etc. It is worth noting that the thickness of the first transparent conductive oxide layer and the second transparent conductive oxide layer can be the same or different, which can be selected according to actual needs. When the thickness of the transparent conductive oxide layer is within the above range, the heterojunction battery has good conductivity, and the overall thickness of the heterojunction battery is small, which is conducive to reducing the parasitic absorption of the battery, so that the photoelectric conversion efficiency of the battery is higher.

[0050] In one specific embodiment, the thickness of the p-type doped silicon layer is 10-30 nm, for example, 10 nm, 15 nm, 20 nm, 25 nm, or 30 nm, etc. When the thickness of the p-type doped silicon layer is within the above range, the p-type doped silicon layer can form a P-N junction with the n-type doped silicon layer to enable the heterojunction battery to perform photoelectric conversion, and can reduce the parasitic absorption of the battery, thereby further improving the photoelectric conversion efficiency of the battery.

[0051] In an embodiment, the n-type doped silicon layer has a thickness of 10-25 nm, such as 10 nm, 11 nm, 12 nm, 13 nm, 14 nm, 15 nm, 16 nm, 17 nm, 18 nm, 19 nm, 20 nm, 21 nm, 22 nm, 23 nm, 24 nm, or 25 nm, etc. When the n-type doped silicon layer has a thickness within the above range, the n-type doped silicon layer can form a P-N junction with the p-type doped silicon layer, the cell can have photoelectric conversion performance, the cell has lower parasitic absorption, the cell has higher short-circuit current, and the cell has higher photoelectric conversion efficiency.

[0052] In an embodiment, the single crystal silicon layer has a thickness of 50-150 μm, such as 50 μm, 60 μm, 70 μm, 80 μm, 90 μm, 100 μm, 110 μm, 120 μm, 130 μm, 140 μm, or 150 μm, etc. When the single crystal silicon layer has a thickness within the above range, the cell can have light absorption and lower material cost.

[0053] In an embodiment, the p-type doped silicon in the p-type doped silicon layer includes at least one of p-type doped amorphous silicon or p-type doped microcrystalline silicon.

[0054] In an embodiment, the n-type doped silicon in the n-type doped silicon layer includes at least one of n-type doped amorphous silicon, n-type doped microcrystalline silicon, and n-type doped oxygenated microcrystalline silicon.

[0055] In an embodiment, the transparent conductive oxide in the transparent conductive oxide layer includes at least one of transparent conductive oxide indium tin oxide (ITO), aluminum-doped zinc oxide (AZO), and fluorine-doped tin oxide (FTO).

[0056] In an embodiment, the single crystal silicon layer includes at least one of an n-type single crystal silicon layer and a p-type single crystal silicon layer.

[0057] When the p-type doped silicon layer, the n-type doped silicon layer, and the single crystal silicon layer are selected from the above silicon materials, the p-type doped silicon layer, the n-type doped silicon layer, and the single crystal silicon layer can be reasonably matched to effectively form a P-N junction, and the above doped layers can improve the conductivity of the doped layers and reduce the parasitic absorption of the doped layers, thereby improving the conversion efficiency of the heterojunction cell.

[0058] In an embodiment, the cell is prepared by a method including the following processes:

[0059] The single crystal silicon is placed in a steam atmosphere of the compound shown in formula 1, and heated to obtain single crystal silicon including a passivation layer, then an n-type doped silicon layer and a p-type doped silicon layer are deposited on the front and back surfaces of the single crystal silicon including the passivation layer respectively, then a first transparent conductive oxide layer is deposited on the side of the n-type doped silicon layer away from the passivation layer, and a second transparent conductive oxide layer is deposited on the side of the p-type doped silicon layer away from the passivation layer, to obtain a cell;

[0060] wherein the vacuum degree of the heating treatment is 10 -4 -10 -1 Pa, the heating temperature is 100-180℃, and the heating time is 40-60 min.

[0061] Specifically, the single crystal silicon is placed in a closed environment, then the compound shown in formula 1 is added dropwise into the closed environment, and heated to place the single crystal silicon in a steam atmosphere of the compound shown in formula 1, and continue heating, wherein the vacuum degree of the closed environment is 10 -4 -10 -1 Pa, for example, 0.0001 Pa, 0.0005 Pa, 0.001 Pa, 0.005 Pa, 0.01 Pa, 0.05 Pa or 0.1 Pa, etc., the heating temperature is 100-180℃, for example, 100℃, 110℃, 120℃, 130℃, 140℃, 150℃, 160℃, 170℃ or 180℃, etc., and the heating time is 40-60 min, for example, 40 min, 42 min, 44 min, 46 min, 50 min, 52 min, 54 min, 56 min, 58 min or 60 min, etc., to obtain single crystal silicon including a passivation layer; then an n-type doped silicon layer is deposited on the front surface of the single crystal silicon including the passivation layer, and a p-type doped silicon layer is deposited on the back surface of the single crystal silicon including the passivation layer, then a first transparent conductive oxide layer is deposited on the side of the n-type doped silicon layer away from the passivation layer, and a second transparent conductive oxide layer is deposited on the side of the p-type doped silicon layer away from the passivation layer, to obtain a cell, which is a heterojunction cell.

[0062] The single crystal silicon can also be treated by a method comprising the following processes before depositing the passivation layer: surface cleaning of the single crystal silicon wafer to remove contamination and scratches, texturing using alkaline solution to form a surface pyramid antireflection structure, and then RCA cleaning (industrial standard wet cleaning process) to obtain a textured wafer after drying; then the textured wafer is placed in a plasma cleaning machine for plasma treatment, the treatment power is 0.1-1 W, for example, 0.1 W, 0.2 W, 0.3 W, 0.4 W, 0.5 W, 0.6 W, 0.7 W, 0.8 W, 0.9 W or 1 W, and the treatment time is 1-10 s, for example, 1 s, 2 s, 3 s, 4 s, 5 s, 6 s, 7 s, 8 s, 9 s or 10 s, etc., to obtain a single crystal silicon. Through the above operation, the organic impurities on the surface of the single crystal silicon can be removed, and the hydrophilicity of the surface of the single crystal silicon can be increased, which is beneficial to the uniform growth of the compound represented by formula 1 on the surface of the single crystal silicon.

[0063] The size of the single crystal silicon is not limited in the present application, and can be selected according to actual needs, for example, a square silicon wafer of 166 mm x 166 mm (M6), a square silicon wafer of 182 mm x 182 mm, a square silicon wafer of 210 mm x 210 mm (G12), or an experimental wafer of any size cut from the above standard silicon wafers can also be selected.

[0064] The dropwise addition amount of the compound represented by formula 1 is not limited in the present application, as long as a passivation layer of sufficient thickness can be formed on the surface of the single crystal silicon.

[0065] The specific operation of depositing an n-type doped silicon layer and a p-type doped silicon layer on the front and back surfaces of the single crystal silicon including the passivation layer is not limited in the present application, and can be selected according to actual needs, as long as an n-type doped silicon layer and a p-type doped silicon layer of sufficient thickness can be deposited on the surface of the passivation layer, for example, plasma enhanced chemical phase deposition (PECVD) can be selected for deposition.

[0066] The specific operation of depositing a first transparent conductive oxide layer on the surface of the n-type doped silicon layer and a second transparent conductive oxide layer on the surface of the p-type doped silicon layer is not limited in the present application, and can be selected according to actual needs, for example, physical vapor deposition (PVD) can be selected, the working temperature is 20-180℃, and the working pressure is 0.01-0.6 Pa.

[0067] The present application further comprises preparing a grid silver electrode by screen printing or preparing a copper electrode by electroplating copper after depositing the transparent conductive oxide layer.

[0068] The heterojunction cell can be prepared by the above method, the photoelectric conversion efficiency of the heterojunction cell is high, the preparation method is simple to operate, requires low equipment, is environmentally friendly, and is conducive to large-scale production of the heterojunction cell.

[0069] In one embodiment, the battery comprises a Topcon battery, which comprises a SiN x The anti-reflective layer, the passivation layer, the p+ doped monocrystalline silicon layer, the n doped monocrystalline silicon layer, the tunneling oxide layer, the n+ doped polysilicon layer and the SiN x The anti-reflective layer.

[0070] The SiN x The anti-reflective layer is a kind of anti-reflective film, which can reduce the reflection of light on the surface of the Topcon battery, increase the amount of light penetrating into the battery, improve the utilization of light, and thus improve the photoelectric conversion efficiency.

[0071] The application does not limit the specific selection of silicon materials in the p+ doped monocrystalline silicon layer and the n+ doped polysilicon layer, as long as the p+ doped monocrystalline silicon layer and the n+ doped polysilicon layer form a P-N junction to enable the Topcon battery to perform photoelectric conversion.

[0072] The application does not limit the specific selection of materials in the tunneling oxide layer, as long as the tunneling oxide layer can prevent minority carrier recombination, reduce charge carrier loss, and avoid direct contact between metal and semiconductor causing electrochemical reaction.

[0073] The Topcon battery of the application is obtained by stacking the above layers, the passivation layer can exhibit effective passivation effect, block minority carriers, enable majority carriers to pass through without obstacles, reduce carrier recombination, and at the same time, the parasitic absorption of the Topcon battery is low, thereby enabling the Topcon battery to have high photoelectric conversion efficiency.

[0074] In one embodiment, the battery comprises a heterojunction / perovskite stacked battery, which comprises a transparent conductive oxide layer, an electron transport layer, a perovskite layer, a hole transport layer, a passivation layer, an n-type doped microcrystalline silicon layer, a passivation layer, an n-type monocrystalline silicon layer, a passivation layer, a p-type doped microcrystalline silicon layer and a transparent conductive oxide layer, which are sequentially stacked.

[0075] The application does not limit the specific selection of transparent conductive oxides in the transparent conductive oxide layer, as long as it can improve the conductivity of the heterojunction / perovskite stacked battery, enabling the battery to conduct electricity.

[0076] The application does not limit the specific selection of materials of the electron transport layer, as long as the electron transport layer has high electron mobility, can quickly guide the photo-generated electrons generated by the perovskite layer out, and reduces electron recombination.

[0077] The application does not limit the specific selection of materials of the perovskite layer, as long as the perovskite layer can absorb photons and generate excitons.

[0078] The application does not limit the specific selection of the material of the hole transport layer, as long as the hole transport layer can effectively collect and transport holes, effectively separate electrons and holes, and protect the perovskite layer.

[0079] The heterojunction / perovskite tandem battery of the application is obtained by layering the above layers, and the passivation layer achieves effective passivation effect in the heterojunction / perovskite tandem battery, and the parasitic absorption of the heterojunction / perovskite tandem battery is low, so that the heterojunction / perovskite tandem battery presents high photoelectric conversion efficiency.

[0080] The application provides a solar cell module, which is prepared based on the above-mentioned battery and has excellent photoelectric conversion performance, and can be widely applied to the photovoltaic industry.

[0081] Hereinafter, the application will be further described in detail through specific examples.

[0082] Example 1

[0083] The preparation method of the battery of the present embodiment comprises the following steps:

[0084] 1. The n-type doped monocrystalline silicon wafer with a thickness of 120 μm and a size of 166 mm x 166 mm is subjected to surface cleaning to remove contamination and scratches, and is subjected to texturing using an alkali solution to form a surface pyramid antireflection structure, and then is subjected to RCA cleaning to obtain a textured wafer; then the textured wafer is subjected to plasma treatment at a power of 0.1 W for 10 s to obtain an n-type doped monocrystalline silicon wafer after plasma treatment;

[0085] 2. The n-type doped monocrystalline silicon wafer after plasma treatment is placed in a vacuum drying box, and is pumped to a vacuum (10 -2 Pa), and then 5 mL of octadecyltrichlorosilane (OTS) is dropped into the vacuum drying box, and is subjected to heating treatment at a heating temperature of 100°C for 60 min to obtain an n-type doped monocrystalline silicon wafer comprising a passivation layer; the thickness of the passivation layer is 4 nm;

[0086] 3. The front and back surfaces of the n-type doped monocrystalline silicon wafer comprising the passivation layer are subjected to PECVD treatment respectively to deposit an n-type doped amorphous silicon layer with a thickness of 18 nm and a p-type doped amorphous silicon layer with a thickness of 20 nm respectively, to obtain a silicon wafer after PECVD treatment;

[0087] 4. The silicon wafer after PECVD treatment is subjected to magnetron sputtering film plating treatment to deposit a first transparent conductive oxide layer and a second transparent conductive oxide layer on the surfaces of the side of the n-type doped amorphous silicon layer away from the passivation layer and the side of the p-type doped amorphous silicon layer away from the passivation layer respectively, and then a grid silver electrode is prepared by screen printing to obtain a heterojunction battery; the thicknesses of the first transparent conductive oxide layer and the second transparent conductive oxide layer are both 80 nm.

[0088] Example 2

[0089] The battery of this example was prepared in substantially the same manner as in Example 1, except that 3-aminopropyltriethoxysilane was used to prepare the passivation layer.

[0090] Example 3

[0091] The battery of this example was prepared in substantially the same manner as in Example 1, except that 1H, 1H, 2H, 2H-perfluorooctyltrichlorosilane was used to prepare the passivation layer.

[0092] Example 4

[0093] The battery of this example was prepared in substantially the same manner as in Example 1, except that hexamethyldisilazane was used to prepare the passivation layer.

[0094] Example 5

[0095] The battery of this example was prepared in substantially the same manner as in Example 1, except that octadecyltrimethoxysilane was used to prepare the passivation layer.

[0096] Example 6

[0097] The battery of this example was prepared in substantially the same manner as in Example 1, except that the thickness of the passivation layer was 2 nm.

[0098] Example 7

[0099] The battery of this example was prepared in substantially the same manner as in Example 1, except that the thickness of the passivation layer was 5 nm.

[0100] Example 8

[0101] The battery of this example was prepared in substantially the same manner as in Example 1, except that the thickness of the passivation layer was 1 nm.

[0102] Example 9

[0103] The battery of this example was prepared in substantially the same manner as in Example 1, except that the thickness of the passivation layer was 6 nm.

[0104] Example 10

[0105] The battery of this example was prepared in substantially the same manner as in Example 1, except that the thickness of the transparent conductive oxide layer was 60 nm.

[0106] Example 11

[0107] The battery of this example was prepared in substantially the same manner as in Example 1, except that the thickness of the transparent conductive oxide layer was 140 nm.

[0108] Example 12

[0109] The battery of this example was prepared in substantially the same manner as in Example 1, except that the thickness of the transparent conductive oxide layer was 150 nm.

[0110] Example 13

[0111] The battery of this example was prepared in substantially the same manner as in Example 1, except that the thickness of the p-type doped silicon layer was 10 nm.

[0112] Example 14

[0113] The battery of this example was prepared in substantially the same manner as in Example 1, except that the thickness of the p-type doped amorphous silicon layer was 30 nm.

[0114] Example 15

[0115] The battery of this example was prepared in substantially the same manner as in Example 1, except that the thickness of the p-type doped amorphous silicon layer was 40 nm.

[0116] Example 16

[0117] The battery of this example was prepared in substantially the same manner as in Example 1, except that the thickness of the n-type doped silicon layer was 10 nm.

[0118] Example 17

[0119] The battery of this example was prepared in substantially the same manner as in Example 1, except that the thickness of the n-type doped amorphous silicon layer was 25 nm.

[0120] Example 18

[0121] The battery of this example was prepared in substantially the same manner as in Example 1, except that the thickness of the n-type doped amorphous silicon layer was 30 nm.

[0122] Example 19

[0123] The battery of this example was prepared in substantially the same manner as in Example 1, except that p-type doped microcrystalline silicon and n-type doped microcrystalline silicon were deposited on the surface of the passivation layer, respectively, and the transparent conductive oxide was aluminum-doped zinc oxide.

[0124] Example 20

[0125] The battery of this example was prepared in substantially the same manner as in Example 1, except that the vacuum degree of the heating treatment was 10 -4 Pa, the heating temperature was 180°C, and the heating time was 40 min.

[0126] Example 21

[0127] The battery of this example was prepared in substantially the same manner as in Example 1, except that the vacuum degree of the heat treatment was 10 Pa, the heating temperature was 150°C, and the heating time was 50 min. -1 Pa, the heating temperature was 150°C, and the heating time was 50 min.

[0128] Example 22

[0129] The battery of this example was prepared in substantially the same manner as in Example 1, except that the vacuum degree of the heat treatment was 0.2 Pa, the heating temperature was 200°C, and the heating time was 30 min.

[0130] Example 23

[0131] The battery of this example was prepared in substantially the same manner as in Example 1, except that the vacuum degree of the heat treatment was 10 Pa, the heating temperature was 150°C, and the heating time was 50 min.

[0132] 1. Cleaning and texturing: the N-type monocrystalline silicon wafer was surface cleaned to remove contamination and line marks, and an alkali solution was used to form a surface pyramid anti-reflection structure, followed by RCA cleaning;

[0133] 2. Boron diffusion to prepare a front p+ emitter: trichloroboron was used as a boron source to form a front p+ emitter and borosilicate glass in a low-pressure tube furnace at a high temperature, the diffusion temperature was 1000°C, the time was 2 h, and finally a p+ emitter was formed with a diffusion depth of 1.0 μm, a doping concentration of 10 19 / cm 2 , and a square resistance of 150 Ω / sq;

[0134] 3. Backside alkali polishing: hydrofluoric acid was used to remove the borosilicate glass on the backside of the front p+ emitter, and an alkali solution was used to polish the backside to form a polished surface, thereby obtaining the front p+ emitter;

[0135] 4. Tunneling oxide layer preparation: a high-temperature thermal oxidation method was used in a tube quartz furnace to deposit a tunneling oxide layer with a thickness of 2 nm on the backside of the front p+ emitter, the temperature was 600°C, and the time was 20 min;

[0136] 5. Deposition of phosphorus, carbon / nitrogen co-doped polysilicon layer: a PECVD preparation method was used, silane, hydrogen, phosphine, methane, and ammonia were introduced during deposition, and a front p+ emitter with a tunneling oxide layer deposited on the backside was used to prepare phosphorus, carbon / nitrogen co-doped amorphous silicon, followed by annealing and crystallization in a tube furnace at 800°C to form a doped polysilicon layer with a thickness of 100 nm, a phosphorus element doping concentration of 10 19 / cm 2 , and a square resistance of 150 Ω / sq;

[0137] 6. Cleaning: removing the polysilicon on the front side of the doped polysilicon layer by alkali solution, removing the phosphor-silicon glass and boron-silicon glass on the front side of the doped polysilicon layer by hydrofluoric acid, etc., performing RCA cleaning, removing the excess phosphor-silicon glass on the back side of the doped polysilicon layer, and obtaining the cell piece;

[0138] 7. Front side passivation layer: placing the cell piece in step 6 in a vacuum drying box, vacuumizing (10 -2 Pa), then dropping 5 mL of octadecyltrichlorosilane (OTS) into the vacuum drying box, and performing heating treatment, the heating temperature being 100℃, and the heating time being 60 min, to obtain the n-type doped monocrystalline silicon piece including the passivation layer; the thickness of the passivation layer being 4 nm;

[0139] 8. Preparation of front and back side anti-reflection layers: the front side anti-reflection layers of silicon nitride, silicon oxynitride and silicon oxide are prepared by PECVD, the gas sources being silane, ammonia and laughing gas, and the thickness of the anti-reflection layer deposited at 500℃ being 100 nm;

[0140] 9. Electrode metallization: screen printing silver paste, and sintering at 800℃ to form the front and back side electrodes, the printing position being above the doped polysilicon layer.

[0141] Example 24

[0142] The preparation method of the cell of the present embodiment includes the following steps:

[0143] 1. RCA solution is used to perform texturing treatment on the n-type doped monocrystalline silicon piece with a thickness of 120 μm and a size of 166 mm x 166 mm, and cleaning and drying treatment is performed to obtain the textured piece; then the textured piece is subjected to plasma treatment, the power being 0.1 W, and the treatment time being 10 s, to obtain the n-type doped monocrystalline silicon piece after plasma treatment;

[0144] 2. The n-type doped monocrystalline silicon piece after plasma treatment is placed in a vacuum drying box, vacuumized (10 -2 Pa), then 5 mL of octadecyltrichlorosilane (OTS) is dropped into the vacuum drying box, and heating treatment is performed, the heating temperature being 100℃, and the heating time being 60 min, to obtain the n-type doped monocrystalline silicon piece including the passivation layer; the thickness of the passivation layer being 4 nm;

[0145] 3. The front and back sides of the n-type doped monocrystalline silicon piece including the passivation layer are subjected to PECVD treatment respectively, and an n-type doped amorphous silicon layer with a thickness of 18 nm and a p-type doped amorphous silicon layer with a thickness of 20 nm are deposited respectively, to obtain the silicon piece after PECVD treatment;

[0146] 4. The silicon piece after PECVD treatment is subjected to magnetron sputtering film plating treatment, and an ITO film layer with a thickness of 80 nm is deposited on the surface of the p-type doped amorphous silicon layer;

[0147] 5. Repeat step 2 to prepare a 2nm OTS passivation layer on the surface of the n-type doped amorphous silicon layer, and then prepare a 20nm thick NiO layer by thermal evaporation. x A hole transport layer, a 100 nm thick perovskite layer, and a 20 nm thick SnO electron transport layer are stacked sequentially to obtain an ITO film, a SnO electron transport layer, a perovskite layer, and a NiO layer. x Hole transport layer, passivation layer, n-type doped amorphous silicon layer, passivation layer, n-type monocrystalline silicon layer, passivation layer, p-type doped amorphous silicon layer, i.e., solar cell;

[0148] 6. Using a magnetron sputtering device, an 80nm ITO film is deposited on the front side of the solar cell in step 5. Subsequently, silver grid lines on the front and back sides are prepared by screen printing to form the final tandem solar cell, namely a heterojunction / perovskite tandem solar cell.

[0149] Comparative Example 1

[0150] The method for preparing the battery in this comparative example includes the following steps:

[0151] 1. A 166mm×166mm n-type doped single crystal silicon wafer with a thickness of 120μm is surface cleaned to remove contaminants and line marks. It is then texturized using alkaline solution to form a surface pyramid anti-reflection structure. Finally, it is RCA cleaned to obtain a texturized wafer.

[0152] 2. Place the textured wafer into the PECVD (plasma-enhanced chemical vapor deposition) chamber, and deposit hydrogenated amorphous silicon passivation layers with thicknesses of 5 nm and 7 nm on the front and back sides of the textured wafer, respectively, to obtain an n-type doped single crystal silicon wafer including the passivation layer.

[0153] 3. Perform PECVD treatment on the front and back sides of the n-type doped single crystal silicon wafer including the passivation layer to deposit an n-type doped amorphous silicon layer with a thickness of 18 nm and a p-type doped amorphous silicon layer with a thickness of 20 nm, respectively, to obtain the PECVD treated silicon wafer.

[0154] 4. The silicon wafer after PECVD treatment is subjected to magnetron sputtering coating treatment. ITO is deposited on the surface of the n-type doped amorphous silicon layer and the p-type doped amorphous silicon layer, respectively. Then, the gate silver electrode is prepared by screen printing to obtain a heterojunction cell. The thickness of the transparent conductive oxide layer is 80nm.

[0155] Comparative Example 2

[0156] The method for preparing the battery in this comparative example includes the following steps:

[0157] 1. Cleaning and texturing: The surface of the N-type monocrystalline silicon wafer is cleaned to remove contaminants and lines. Alkaline solution is used to texture the surface to form a pyramid anti-reflection structure, followed by RCA cleaning.

[0158] 2. Preparation of front p+emitter by boron diffusion: using boron trichloride as boron source to diffuse in a low pressure tube furnace to form front p+emitter and borosilicate glass, the diffusion temperature is 1000℃, the time is 2h, the final diffusion depth is 1.0μm, the doping concentration is 10 19 / cm 2 , and the square resistance is 150Ω / sq;

[0159] 3. Backside alkali polishing: using hydrofluoric acid to remove the borosilicate glass on the back of the front p+emitter, and using alkali to polish the back to a polished surface to obtain the front p+emitter;

[0160] 4. Preparation of tunneling oxide layer: using high temperature thermal oxidation method in a tube quartz furnace to deposit a 2nm thick tunneling oxide layer on the back of the front p+emitter, the temperature is 600℃, and the time is 20min;

[0161] 5. Deposition of phosphorus, carbon / nitrogen co-doped polysilicon layer: using PECVD preparation method, silane, hydrogen, phosphine, methane and ammonia are introduced during deposition, and the front p+emitter with tunneling oxide layer deposited on the back is used to prepare phosphorus, carbon / nitrogen co-doped amorphous silicon, and then annealed at 800℃ in a tube furnace to crystallize to form a doped polysilicon layer with a thickness of 100nm, a phosphorus element doping concentration of 10 19 / cm 2 , and a square resistance of 150Ω / sq;

[0162] 6. Cleaning: removing the polysilicon around the front of the doped polysilicon layer by alkali, removing the phosphosilicate glass and borosilicate glass on the front of the doped polysilicon layer by hydrofluoric acid, and performing RCA cleaning to remove the excess phosphosilicate glass on the back of the doped polysilicon layer;

[0163] 7. Preparation of front passivation layer: depositing aluminum oxide on the front using atomic layer deposition method, and circulating trimethylaluminum and water at 250℃ to prepare a 10nm thick aluminum oxide layer;

[0164] 8. Preparation of antireflection layer: the front antireflection layer containing silicon nitride, silicon oxynitride and silicon oxide is prepared by PECVD, the gas sources introduced are silane, ammonia and laughing gas, and the antireflection layer with a thickness of 100nm is deposited at 500℃;

[0165] 9. Electrode metallization: screen printing silver paste, and sintering at 800℃ to form front and back electrodes, the printing position is above the doped polysilicon layer, and the battery is obtained.

[0166] Comparative Example 3

[0167] The preparation method of the battery of the present comparative example comprises the following steps:

[0168] 1. The n-type doped monocrystalline silicon wafer with a thickness of 120 μm and a size of 166 mm x 166 mm is subjected to surface cleaning to remove contamination and scratches, and is subjected to etching with alkali to form a surface pyramid antireflection structure, and then is subjected to RCA cleaning to obtain an n-type doped monocrystalline silicon etched wafer.

[0169] 2. The n-type doped monocrystalline silicon etched wafer is placed in a PECVD (plasma enhanced chemical vapor deposition) chamber, and a passivation layer with a thickness of 5 nm and 7 nm is deposited on the front and back surfaces of the n-type doped monocrystalline silicon etched wafer, respectively, to obtain an n-type doped monocrystalline silicon wafer including a passivation layer.

[0170] 3. The front and back surfaces of the n-type doped monocrystalline silicon wafer including a passivation layer are subjected to PECVD treatment, respectively, to deposit an n-type doped amorphous silicon layer with a thickness of 18 nm and a p-type doped amorphous silicon layer with a thickness of 20 nm, respectively, to obtain a silicon wafer after PECVD treatment.

[0171] 4. The silicon wafer after PECVD treatment is subjected to magnetron sputtering film deposition treatment to deposit ITO on the surfaces of the n-type doped amorphous silicon layer and the p-type doped amorphous silicon layer, respectively, and then a grid silver electrode is prepared by screen printing to obtain a heterojunction cell. The thickness of the transparent conductive oxide layer is 80 nm.

[0172] Test Example

[0173] The cells of the examples and the comparative examples are subjected to photoelectric conversion efficiency testing, and are tested by using a solar cell I-V testing device. The testing standard is IEC 61215, and the testing results are shown in Table 1.

[0174] Table 1

[0175] The above results show that the passivation layer of the present application can greatly improve the short circuit current (Isc) while ensuring the effect of the passivation layer, i.e., ensuring that the open circuit voltage (Voc) does not decrease, thereby improving the photoelectric conversion efficiency of the cell. For example, the open circuit voltage of Example 1 and Comparative Example 1 is almost the same, but the short circuit current is increased by 0.39 A. Examples 23 and Comparative Example 2, and Examples 24 and Comparative Example 3, can also illustrate the above conclusion.

[0176] Finally, it should be noted that the above examples are only used to illustrate the technical solutions of the present application, and are not limiting. Although the present application has been described in detail with reference to the foregoing examples, those skilled in the art should understand that they can still modify the technical solutions described in the foregoing examples, or make equivalent substitutions for some or all of the technical features; and such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the examples of the present application.

Claims

1. A battery, wherein, The battery comprises a passivation layer and a monocrystalline silicon layer, the passivation layer is present on the surface of the monocrystalline silicon layer; the passivation layer comprises a compound shown in formula 1: wherein R1, R2, R3, R4 are each independently selected from one of substituted or unsubstituted C1-C20 alkyl, halogen, substituted or unsubstituted amino, substituted or unsubstituted C1-C20 alkoxy, and at least one of R1, R2, R3, R4 comprises the substituted or unsubstituted C1-C20 alkyl or the substituted or unsubstituted amino; the substituents of the alkyl group, the substituents of the amino group, and the substituents of the alkoxy group are each independently selected from the group consisting of halogen, amino, -Si(C x H 2x+1 )3, x is an integer of 1 to 20.

2. The battery of claim 1, wherein, R1, R2, R3, R4are each independently selected from one of substituted or unsubstituted C1-C18 alkyl, halogen, substituted or unsubstituted amino, substituted or unsubstituted C1-C18 alkoxy; the substituents of the alkyl, the substituents of the amino and the substituents of the alkoxy are each independently selected from one of halogen, amino, -Si(C x H 2x+1 )3, x is an integer from 1 to 18.

3. The battery according to claim 1 or 2, wherein the compound of formula 1 comprises one of octadecyltrichlorosilane, 3-aminopropyltriethoxysilane, 1H,1H,2H,2H-perfluorooctyltrichlorosilane, hexamethyldisilazane, octadecyltrimethoxysilane.

4. The battery of any one of claims 1-3, wherein, The thickness of the passivation layer is 2-5 nm.

5. The battery of any one of claims 1-4, wherein, The battery comprises a first transparent conductive oxide layer, an n-type doped silicon layer, the passivation layer, a single crystal silicon layer, the passivation layer, a p-type doped silicon layer, and a second transparent conductive oxide layer which are sequentially stacked.

6. The battery of claim 5, wherein, The thickness of the first transparent conductive oxide layer is 60-140 nm.

7. The battery of claim 5 or 6, wherein, The thickness of the p-type doped silicon layer is 10-30 nm.

8. The battery of any one of claims 5-7, wherein, The thickness of the n-type doped silicon layer is 10-25 nm.

9. The battery of any one of claims 5-8, wherein, The thickness of the single crystal silicon layer is 50-150 μm.

10. The battery of any one of claims 5-9, wherein, The thickness of the second transparent conductive oxide layer is 60-140 nm.

11. The battery of any one of claims 5-10, wherein, The p-type doped silicon in the p-type doped silicon layer comprises at least one of p-type doped amorphous silicon and p-type doped microcrystalline silicon.

12. The battery of any one of claims 5-11, wherein, The n-type doped silicon in the n-type doped silicon layer comprises at least one of n-type doped amorphous silicon, n-type doped microcrystalline silicon, and n-type doped microcrystalline silicon.

13. The battery of any one of claims 5-12, wherein, The transparent conductive oxide in the first transparent conductive oxide layer comprises at least one of indium tin oxide, aluminum-doped zinc oxide, and fluorine-doped tin oxide; and / or the transparent conductive oxide in the second transparent conductive oxide layer comprises at least one of indium tin oxide, aluminum-doped zinc oxide, and fluorine-doped tin oxide.

14. The battery of any one of claims 5-13, wherein, The single crystal silicon layer comprises at least one of an n-type single crystal silicon layer and a p-type single crystal silicon layer.

15. The battery of any one of claims 5-14, wherein, The battery is prepared by a method comprising the following steps: The single crystal silicon is placed in a vapor atmosphere of the compound of formula 1, and subjected to a heating treatment to obtain single crystal silicon comprising the passivation layer, and then an n-type doped silicon layer and a p-type doped silicon layer are deposited on the front and back surfaces of the single crystal silicon comprising the passivation layer, respectively, and then the first transparent conductive oxide layer is deposited on the side of the n-type doped silicon layer away from the passivation layer, and the second transparent conductive oxide layer is deposited on the side of the p-type doped silicon layer away from the passivation layer, to obtain the battery; The vacuum degree of the heating treatment is 10 -4 -10 -1 Pa, the heating temperature is 100-180℃, and the heating time is 40-60min.

16. The battery of any one of claims 1-4, wherein, The battery comprises SiN x The anti-reflection layer, the passivation layer, the p+ doped monocrystalline silicon layer, the n doped monocrystalline silicon layer, the tunneling oxide layer, the n+ doped polysilicon layer and SiN x The anti-reflection layer.

17. The battery of any one of claims 1-4, wherein, The battery comprises a transparent conductive oxide layer, an electron transport layer, a perovskite layer, a hole transport layer, the passivation layer, an n-type doped microcrystalline silicon layer, the passivation layer, an n-type single crystal silicon layer, the passivation layer, a p-type doped microcrystalline silicon layer, and a transparent conductive oxide layer which are sequentially stacked.

18. A solar cell module, wherein, The solar cell module comprises the battery of any one of claims 1-17.

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