Solar cell manufacturing method and solar cell

Abstract

The present disclosure provides a solar cell manufacturing method and a solar cell. The manufacturing method comprises: providing a semiconductor substrate, wherein the semiconductor substrate comprises a first region and a second region arranged in a first direction, and the first region and the second region are adjacent to each other and have a boundary; forming a first semiconductor layer on the first region; forming a plurality of mark points on the first semiconductor layer and the second region; identifying a target pattern corresponding to the plurality of mark points, wherein the target pattern has a target geometric center; forming, on the second region, a second semiconductor layer covering the plurality of mark points, wherein the second semiconductor layer and the first semiconductor layer have different doping types; and using a laser etching process to remove a part of the second semiconductor layer to expose the semiconductor substrate, wherein laser in the laser etching process passes through the target geometric center in an extension direction of the boundary to form an isolation trench, and the isolation trench is used for isolating the first semiconductor layer from the second semiconductor layer.

Description

Solar cell manufacturing method and solar cell TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of semiconductor technology, and in particular, to a solar cell manufacturing method and a solar cell. BACKGROUND

[0002] At present, the main direction of improving the back surface conversion efficiency of the back contact cell (BC type solar cell) is back surface patterning, that is, the P pole and the N pole of the back contact cell are both arranged on the back surface of the cell sheet through back surface patterning and front surface without grid line. This method can significantly improve the efficiency, but the front surface without grid line also needs to ensure the back surface alignment accuracy, and the alignment accuracy stability, the laser alignment accuracy and the metal alignment accuracy are required to be higher.

[0003] In the prior art, the center point of the silicon wafer is usually obtained by grabbing the four edges and four diagonals of the silicon wafer, and then a proper angle compensation is performed to realize the alignment of the laser P pole, the N pole and the metal printing pattern. However, such alignment method is limited by the size accuracy specification of the silicon wafer and the position of the pattern on the silicon wafer. For the back contact cell which needs high-precision alignment, the precision is poor, and it is no longer suitable.

[0004] Therefore, there is an urgent need for a method for improving the alignment accuracy of the P pole and the N pole of the back contact cell. SUMMARY

[0005] The main purpose of the present disclosure is to provide a solar cell manufacturing method and a solar cell to solve the problem of poor alignment accuracy of the P pole and the N pole of the back contact cell in the prior art.

[0006] In order to achieve the above-mentioned purpose, according to one aspect of the present disclosure, a solar cell manufacturing method is provided, comprising: providing a semiconductor substrate, the semiconductor substrate comprising a first region and a second region arranged along a first direction, the first region and the second region being adjacent and having a boundary line; forming a first semiconductor layer on the first region; forming a plurality of mark points on the first semiconductor layer and the second region; identifying a target pattern corresponding to the plurality of mark points, the target pattern having a target geometric center; forming a second semiconductor layer covering the plurality of mark points on the second region, the second semiconductor layer and the first semiconductor layer having different doping types; removing part of the second semiconductor layer to the semiconductor substrate by a laser etching process, the laser of the laser etching process passing through the target geometric center in the extension direction along the boundary line to form an isolation groove, the isolation groove being used to isolate the first semiconductor layer and the second semiconductor layer.

[0007] Optionally, the step of forming the plurality of mark points comprises: recognizing the boundary line by using a visual camera; and forming the plurality of mark points in the first semiconductor layer and the second region by using a laser etching process, positions of the plurality of mark points being determined according to a position of the boundary line.

[0008] Optionally, the step of forming the isolation trench comprises: capturing the target pattern by using a visual camera, and determining a target geometric center of the target pattern; adjusting a laser of the laser etching process so that the laser passes through the target geometric center in an extension direction of the boundary line, and forms a preliminary trench on the surface of the second semiconductor layer; and continuing to etch the second semiconductor layer along the preliminary trench by using a chemical etching process to form the isolation trench.

[0009] Optionally, the plurality of mark points are all arranged outside the boundary line.

[0010] Optionally, the plurality of mark points comprise a first mark point, a second mark point, a third mark point and a fourth mark point, the first mark point, the second mark point, the third mark point and the fourth mark point are sequentially connected to form the target pattern, and the target pattern is a rectangle; the first mark point and the second mark point are arranged on the first region, and the third mark point and the fourth mark point are arranged on the second region; a line connecting the first mark point and the third mark point is a first diagonal line of the rectangle, a line connecting the second mark point and the fourth mark point is a second diagonal line of the rectangle, and an intersection of the first diagonal line and the second diagonal line is the target geometric center.

[0011] Optionally, a line connecting the second mark point and the third mark point is parallel to the first direction; a distance between the second mark point and the third mark point in the first direction is D1; a width of the isolation trench in the first direction is A1, and D1>A1.

[0012] Optionally, at least one of the plurality of mark points is arranged on the boundary line.

[0013] Optionally, the plurality of mark points comprise a first mark point, a second mark point, a third mark point and a fourth mark point, the first mark point, the second mark point, the third mark point and the fourth mark point are sequentially connected to form the target pattern, and the target pattern is a rectangle; the first mark point and the second mark point are arranged on the boundary line, and the third mark point and the fourth mark point are arranged on the second region; a line connecting the first mark point and the third mark point is a first diagonal line of the rectangle, a line connecting the second mark point and the fourth mark point is a second diagonal line of the rectangle, and an intersection of the first diagonal line and the second diagonal line is the target geometric center.

[0014] Optionally, a line connecting the second mark point and the third mark point is parallel to the first direction; a distance between the second mark point and the third mark point in the first direction is D1; a width of the isolation trench in the first direction is A1, and D1≤A1.

[0015] According to another aspect of the present disclosure, a solar cell formed by any of the above-mentioned solar cell manufacturing methods is provided, comprising: a semiconductor substrate comprising a first region and a second region arranged along a first direction, the first region and the second region being adjacent and having a boundary line; a first semiconductor layer on the first region; a second semiconductor layer on the second region, the first semiconductor layer and the second semiconductor layer having different doping types; and an isolation trench between the first semiconductor layer and the second semiconductor layer for isolating the first semiconductor layer and the second semiconductor layer, the boundary line being in the isolation trench.

[0016] The technical solution of the present disclosure provides a solar cell manufacturing method comprising an isolation trench, specifically comprising: first providing a semiconductor substrate, which can comprise a first region and a second region being adjacent and having a boundary line. Then a first semiconductor layer can be formed on the first region, and a second semiconductor layer can be formed on the second region, the first semiconductor layer and the second semiconductor layer having different doping types. In order to isolate the first semiconductor layer and the second semiconductor layer, the present disclosure can first form a plurality of marking points on the first semiconductor layer and the second region after forming the first semiconductor layer on the first region, and then form the second semiconductor layer covering the plurality of marking points on the second region. After that, in the step of removing part of the second semiconductor layer to the semiconductor substrate by using a laser etching process, the laser in the laser etching process can pass through the target geometric center along the extension direction of the boundary line, so as to etch and form the isolation trench, thereby isolating the first semiconductor layer and the second semiconductor layer. That is, according to the present disclosure, since the alignment marks (i.e. the plurality of marking points) required for forming the isolation trench have been identified before the laser etching process, the target geometric center of the target pattern corresponding to the plurality of marking points can be directly aligned and etched in the process of the laser etching process, without being limited by the size accuracy of the silicon wafer and the position of the marking points in the silicon wafer, thereby greatly improving the alignment efficiency and accuracy, and solving the problem of poor alignment accuracy of the P pole and the N pole of the back contact cell in the prior art. BRIEF DESCRIPTION OF DRAWINGS

[0017] The drawings accompanying the specification of the present disclosure serve to provide a further understanding of the present disclosure, and the illustrative embodiments of the present disclosure and their descriptions serve to explain the present disclosure, and do not constitute improper limitations on the present disclosure. In the drawings:

[0018] FIG. 1 shows a cross-sectional structure schematic diagram of a semiconductor substrate formed with a first semiconductor layer according to an embodiment of the present disclosure;

[0019] FIG. 2 shows a planar schematic diagram of a plurality of marking points;

[0020] Fig. 3 shows a schematic diagram of a cross-sectional structure of forming a second semiconductor layer on the structure shown in Fig. 1;

[0021] Fig. 4 shows a schematic diagram of a cross-sectional structure of forming a preliminary trench on the structure shown in Fig. 3;

[0022] Fig. 5 shows a schematic diagram of a cross-sectional structure of forming an isolation trench on the structure shown in Fig. 3;

[0023] Fig. 6 shows a schematic diagram of a cross-sectional structure of forming an aluminum oxide passivation layer on the structure shown in Fig. 5;

[0024] Fig. 7 shows a schematic diagram of a cross-sectional structure of forming a first electrode and a second electrode on the structure shown in Fig. 6.

[0025] In the above drawings, the following reference signs are used: 1000, first region; 2000, second region; 100, mark point; 101, first mark point; 102, second mark point; 103, third mark point; 104, fourth mark point; 200, target geometric center; 10, semiconductor substrate; 20, first semiconductor layer; 201, first passivation layer; 202, first doped layer; 203, first mask; 303, second mask; 204, third mask; 30, second semiconductor layer; 301, second passivation layer; 302, second doped layer; 40, preliminary trench; 50, isolation trench; 60, aluminum oxide passivation layer; 70, first electrode; 80, second electrode. DETAILED DESCRIPTION

[0026] It should be noted that the embodiments in the present disclosure and the features in the embodiments can be combined with each other without conflict. The technical solutions in the embodiments of the present disclosure will be described in detail below with reference to the drawings and in combination with the embodiments.

[0027] In order to enable persons skilled in the art to better understand the present disclosure, the technical solutions in the embodiments of the present disclosure will be described clearly and completely below with reference to the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only a part of the embodiments of the present disclosure, not all the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by persons skilled in the art without creative labor should belong to the protection scope of the present disclosure.

[0028] It is to be understood that the terms "first", "second", and the like, used in the description and the claims of the present disclosure as well as the foregoing drawings of the application merely refer to different categories and do not necessarily imply a sequence or order of, for example, the described embodiments of the present disclosure. It is to be understood that the use of the terms first, second, etc., in describing the embodiments of the present disclosure is not to be construed as limiting the scope of the application, but merely to distinguish one embodiment from another. Furthermore, the terms "comprising", "including", "containing", and "having" and their conjugates, as used herein, are intended to encompass the presence of one or more elements, steps, and / or components without excluding the presence of one or more other elements, steps, components, and / or groups thereof. It is to be understood that the use of the singular herein, like "a" and "said", does not exclude the plural and vice versa unless the context clearly dictates otherwise.

[0029] As described in the background section, the prior art generally uses four edges and four corners of a silicon wafer to obtain the center point of the silicon wafer, and then performs appropriate angle compensation to achieve the alignment of the P and N poles and the metallization printed pattern. However, such alignment method is limited by the size accuracy specification of the silicon wafer and the position of the pattern on the silicon wafer. For back contact cells that require high-precision alignment, the precision is poor and is no longer suitable. In order to solve the problem of poor P and N pole alignment capability of the back contact cell in the prior art, the present disclosure provides a method for forming a semiconductor structure and a semiconductor structure formed by using the above method for forming a semiconductor structure.

[0030] In some optional embodiments, a method for forming a semiconductor structure is provided, the semiconductor structure comprising an isolation trench, the method comprising: providing a semiconductor substrate 10, the semiconductor substrate 10 comprising a first region 1000 and a second region 2000, the first region 1000 and the second region 2000 being adjacent and having a boundary line (not shown in the figure); forming a first semiconductor layer 20 on the first region 1000, as shown in FIG. 1; forming a plurality of marker points 100 on the first semiconductor layer 20 and the second region 2000, respectively; identifying a target pattern corresponding to the plurality of marker points 100, the target pattern having a target geometric center, as shown in FIG. 2; forming a second semiconductor layer 30 on the second region 2000, the second semiconductor layer 30 covering the plurality of marker points 100, the second semiconductor layer 30 and the first semiconductor layer 20 having different doping types, as shown in FIG. 3; removing part of the second semiconductor layer 30 to the semiconductor substrate 10 by a laser etching process, the laser of the laser etching process passing through the target geometric center in the extension direction along the boundary line, to form the isolation trench 50, the isolation trench 50 being used to isolate the first semiconductor layer 20 and the second semiconductor layer 30, as shown in FIG. 5.

[0031] It should be noted that, as shown in FIG. 1, the semiconductor substrate 10 is not actually divided into the first region 1000 and the second region 2000 which are adjacent and have a boundary line, but is artificially set for the purpose of facilitating the description of the positional relationship between the first semiconductor layer 20 and the semiconductor substrate 10 and the positional relationship between the second semiconductor layer 30 and the semiconductor substrate 10.

[0032] Specifically, as shown in FIG. 1, the semiconductor substrate 10 can be a silicon wafer. Before the step of forming the first semiconductor layer 20 in the first region 1000 of the semiconductor substrate 10, the semiconductor substrate 10 can also be subjected to a damage layer removal process, a surface contamination process, a surface polishing process, and the like.

[0033] Specifically, as shown in FIG. 2, the mark 100 is a figure having a geometric center. Exemplarily, the figure of the mark 100 can include, but is not limited to, a circle, a rectangle, a regular polygon, and the like.

[0034] In addition, in order to simplify the forming process of the mark 100, the figure of the plurality of marks 100 formed on the first semiconductor layer 20 and the figure of the plurality of marks 100 formed on the second region 2000 can be the same. Exemplarily, the plurality of marks 100 on the first semiconductor layer 20 and the second region 2000 can all be rectangles.

[0035] In addition, the positions of the plurality of marks 100 in the first semiconductor layer 20 and the plurality of marks 100 in the second region 2000 can be arbitrarily set.

[0036] It should be noted that, before the plurality of marks are formed, since the first semiconductor layer has been formed on the first region 1000, it can be determined that the isolation trench between the first semiconductor layer and the second semiconductor layer to be formed extends along the direction of the boundary line. Furthermore, during the formation of the plurality of marks, the positions of the plurality of marks 100 can be determined according to the boundary line, and after the target figure corresponding to the plurality of marks 100 is identified, the isolation trench can be determined according to the target geometric center of the plurality of marks 100 by using a laser etching process.

[0037] Correspondingly, after the plurality of marks 100 are formed, the step of determining the isolation trench according to the target geometric center of the plurality of marks 100 by using a laser etching process can be understood as follows: as shown in FIG. 2, first, the plurality of marks 100 are identified, and then the geometric center of each mark 100 can be fitted by a computer. After that, the target figure corresponding to the plurality of geometric centers can also be fitted by the computer, and then the target geometric center of the target figure is obtained, and the laser etching process is performed by causing the laser to pass through the target geometric center along the extension direction of the boundary line, thereby forming the isolation trench 50.

[0038] Optionally, the above-mentioned solar cell can be a back contact cell. On this basis, the above-mentioned first semiconductor layer 20 can be the P pole of the back contact cell, and the above-mentioned second semiconductor layer 30 can be the N pole of the back contact cell; or the above-mentioned first semiconductor layer 20 can be the N pole of the back contact cell, and the above-mentioned second semiconductor layer 30 can be the P pole of the back contact cell.

[0039] In the above-mentioned embodiment, for the solar cell comprising the isolation groove, the preparation method can be: first providing a semiconductor substrate 10, which can comprise a first region 1000 and a second region 2000 adjacent to each other and having a boundary line. Then a first semiconductor layer 20 can be formed on the first region 1000, and a second semiconductor layer 30 can be formed on the second region 2000, the first semiconductor layer 20 and the second semiconductor layer 30 having different doping types. In order to isolate the first semiconductor layer 20 and the second semiconductor layer 30, after forming the first semiconductor layer 20 on the first region 1000, the disclosure can first form a plurality of marking points 100 on the first semiconductor layer 20 and the second region 2000, and then after identifying a target pattern corresponding to the above-mentioned plurality of marking points 100, since the target pattern has a target geometric center 200, after the step of forming the second semiconductor layer 30 covering the above-mentioned plurality of marking points 100 on the second region 2000, in the step of removing part of the second semiconductor layer 30 to the semiconductor substrate 10 by using a laser etching process, by passing the laser in the laser etching process through the above-mentioned target geometric center 200 along the extension direction of the boundary line, the isolation groove 50 can be etched and formed, so that the first semiconductor layer 20 and the second semiconductor layer 30 are isolated. That is, by the disclosure, since the alignment marks (i.e. the above-mentioned plurality of marking points 100) required for forming the isolation groove 50 have been identified before the laser etching process, the target geometric center 200 of the target pattern corresponding to the above-mentioned plurality of marking points 100 can be directly aligned and etched during the laser etching process, without being limited by the size accuracy of the silicon wafer and the position of the marking points 100 in the silicon wafer, greatly improving the alignment efficiency and alignment accuracy, thereby solving the problem of poor alignment accuracy of the P pole and the N pole of the back contact cell in the prior art.

[0040] The first semiconductor layer 20 and the second semiconductor layer 30 of the solar cell are both located on the same side of the semiconductor substrate 10. In the step of forming the first semiconductor layer 20 on the first region 1000 of the semiconductor substrate 10, a first semiconductor material layer (not shown in the figure) is formed on one side surface of the semiconductor substrate 10, a first mask 203 is used to cover the part of the first semiconductor material layer located on the first region 1000 so as to expose the part of the first semiconductor material layer located on the second region 2000, and the exposed part of the first semiconductor material layer is etched to the exposed part of the semiconductor substrate 10 so as to form the first semiconductor layer 20, as shown in FIG. 1. Further, the exposed second region 2000 can be polished.

[0041] Optionally, the first semiconductor material layer can include a first passivation material layer, a first doped amorphous silicon layer, and other film layers (i.e., the first mask 203) formed during the formation of the first doped amorphous silicon layer. For example, the first passivation material layer can include, but is not limited to, a silicon oxide layer, the first doped amorphous silicon layer can include, but is not limited to, a boron-doped amorphous silicon layer, and the other film layers (i.e., the first mask 203) can include, but are not limited to, a silicon oxide layer. It should be noted that the first passivation material layer is used to form the first passivation layer 201 in the structure shown in FIG. 1, and the first doped amorphous silicon layer is used to form the first doped layer 202 in the structure shown in FIG. 1. Further, in the step of forming the first semiconductor layer 20, the part of the first mask 203 corresponding to the second region 2000 is etched and removed.

[0042] In some optional embodiments, the step of forming the mark points includes: using a visual camera to identify the demarcation line, as shown in FIGS. 1 and 2; and using a laser etching process to form a plurality of mark points 100 on the first semiconductor layer 20 and the second region 2000, the positions of the plurality of mark points 100 being determined according to the position of the demarcation line. In the process of identifying the demarcation line by the visual camera, the opposite side of the semiconductor substrate 10 on which the first semiconductor layer 20 is formed can be first lighted, and then the visual camera can be used to identify the position of the demarcation line on the side on which the first semiconductor layer 20 is formed, so that the position of the demarcation line can be identified. Further, in the process of forming the plurality of mark points 100 by the laser etching process, the laser etching process can involve a computer fitting process, so that the positions of the plurality of mark points 100 can be determined by the computer fitting process when the position of the demarcation line is known, so that the target geometric center 200 of the target figure corresponding to the plurality of mark points 100 is located on the demarcation line, or the distance between the target geometric center 200 of the target figure corresponding to the plurality of mark points 100 and the demarcation line in the first direction is recorded.

[0043] Optionally, the second semiconductor layer 30 can be formed by referring to the preparation process of the first semiconductor layer 20, as shown in FIG. 1 and FIG. 3. After the second semiconductor layer 30 is formed on the second region 2000 to cover the plurality of mark points 100, the second semiconductor layer 30 on the second region 2000 can include a second doped layer 302 and a second passivation layer 301 between the semiconductor substrate 10 and the second doped layer 302. Exemplarily, the second passivation layer 301 can be a silicon oxide layer. Since the second doped layer 302 is formed by doping amorphous silicon, the doping process can cause other film layers (i.e., a second mask 303) different from the second doped layer 302 to be formed on the side of the second doped layer 302 away from the semiconductor substrate 10. Exemplarily, the second doped layer 302 can include but is not limited to a phosphorus-doped amorphous silicon layer, and the other film layers (i.e., the second mask 303) can include but are not limited to a silicon oxide layer. It is noted that during the formation of the second semiconductor layer 30, the side of the first semiconductor layer 20 away from the semiconductor substrate 10 can correspondingly form the same film layer structure (i.e., the second semiconductor layer 30 and the second mask 303) as the second semiconductor layer 30, so that the third mask 204 is formed on the side of the first semiconductor layer 20 away from the semiconductor substrate 10, and the third mask 204 also includes the first mask 203.

[0044] In some optional embodiments, in combination with FIG. 2, FIG. 4 and FIG. 5, the step of forming the isolation trench 50 includes: capturing the target pattern by a visual camera and determining a target geometric center 200 of the target pattern, as shown in FIG. 2; adjusting a laser of the laser etching process so that the laser passes through the target geometric center 200 in the extension direction of the boundary line and forms a preliminary trench 40 on the surface of the second semiconductor layer 30, as shown in FIG. 4; and continuing to etch the second semiconductor layer 30 along the preliminary trench 40 to the semiconductor substrate 10 by a chemical etching process to form the isolation trench 50, as shown in FIG. 5.

[0045] Specifically, in the present embodiment, in order to form the isolation trench 50, it is first required to remove the part of the other film layer (i.e. the second mask 303) of the second doped layer 302 corresponding to the isolation trench 50 away from the side of the second passivation layer 301. In the removing step, since the positional relationship between the target geometric center 200 of the target pattern corresponding to the plurality of marking points 100 and the demarcation line has been identified in the process of forming the plurality of marking points 100, on the basis of capturing the target pattern corresponding to the plurality of marking points 100 by the vision camera and determining the target geometric center 200 of the target pattern, the laser of the laser etching process can be adjusted to pass through the target geometric center 200 in the extension direction of the demarcation line, so as to remove the part of the other film layer (i.e. the second mask 303) of the second semiconductor layer 30 corresponding to the isolation trench 50, thereby forming a preliminary trench 40 on the surface of the second semiconductor layer 30, as shown in FIG. 4. Further, in the process of etching the second semiconductor layer 30 to the semiconductor substrate 10 along the preliminary trench 40 by the chemical etching process, the second semiconductor layer 30 remaining in the preliminary trench 40 can be removed by self-alignment on the basis of the preliminary trench 40, so that the isolation trench 50 can be formed between the first semiconductor layer 20 and the second semiconductor layer 30, as shown in FIG. 5.

[0046] In some optional embodiments, the plurality of marking points are all arranged outside the demarcation line. As shown in FIG. 2, in the case where the geometric center of a marking point 100 is used to represent the marking point 100 itself, the plurality of marking points 100 can exemplarily include a first marking point 101, a second marking point 102, a third marking point 103 and a fourth marking point 104, the first marking point 101, the second marking point 102, the third marking point 103 and the fourth marking point 104 are sequentially connected to form the target pattern, and the target pattern can be a rectangle; the first marking point 101 and the second marking point 102 are arranged on the first region (specifically, the first marking point 101 and the second marking point 102 are arranged on the first semiconductor layer corresponding to the first region), and the third marking point 103 and the fourth marking point 104 are arranged on the second region; a line connecting the first marking point 101 and the third marking point 103 is a first diagonal line of the rectangle, a line connecting the second marking point 102 and the fourth marking point 104 is a second diagonal line of the rectangle, and an intersection of the first diagonal line and the second diagonal line is the target geometric center 200.

[0047] It is to be noted that in this embodiment, the first mark point 101 and the second mark point 102 are located on the first side of the boundary line, and the third mark point 103 and the fourth mark point 104 are located on the second side of the boundary line, the first side and the second side are opposite sides of the boundary line in the first direction, so that in the first direction, the target geometric center 200 of the target figure (rectangle) corresponding to the first mark point 101, the second mark point 102, the third mark point 103 and the fourth mark point 104 can be located on the boundary line.

[0048] Optionally, in the case that the first mark point 101, the second mark point 102, the third mark point 103 and the fourth mark point 104 are all arranged outside the boundary line, the target figure corresponding to the first mark point 101, the second mark point 102, the third mark point 103 and the fourth mark point 104 is a rectangle, and the line connecting the second mark point 102 and the third mark point 103 in the plurality of mark points is parallel to the first direction, the distance between the second mark point 102 and the third mark point 103 in the first direction can be D1, and the width of the isolation trench in the first direction can be A1, D1>A1.

[0049] In other optional embodiments, at least one of the plurality of mark points is arranged on the boundary line. Exemplarily, two embodiments in which two mark points of the plurality of mark points are located on the boundary line are given as follows:

[0050] The first embodiment is that the plurality of mark points include the first mark point 101, the second mark point 102, the third mark point 103 and the fourth mark point 104, the first mark point 101, the second mark point 102, the third mark point 103 and the fourth mark point 104 are sequentially connected to form the target figure, and the target figure is a rectangle; the first mark point 101 and the second mark point 102 are arranged on the boundary line, and the third mark point 103 and the fourth mark point 104 are arranged on the second region; the line connecting the first mark point 101 and the third mark point 103 is the first diagonal line of the rectangle, the line connecting the second mark point 102 and the fourth mark point 104 is the second diagonal line of the rectangle, and the intersection point of the first diagonal line and the second diagonal line is the target geometric center 200.

[0051] It is to be noted that, in this embodiment, since the first mark point 101 and the second mark point 102 are located on the boundary line, and the third mark point 103 and the fourth mark point 104 are located in the second region, in the first direction, the target geometric center 200 of the target figure (rectangle) corresponding to the first mark point 101, the second mark point 102, the third mark point 103 and the fourth mark point 104 can be located outside the boundary line, but the distance between the target geometric center 200 of the target figure and the boundary line in the first direction can be recorded.

[0052] Optionally, in the case that the first mark point 101 and the second mark point 102 are located on the boundary line, the third mark point 103 and the fourth mark point 104 are located in the second region, the target figure corresponding to the first mark point 101, the second mark point 102, the third mark point 103 and the fourth mark point 104 is a rectangle, and the line connecting the second mark point 102 and the third mark point 103 is parallel to the first direction, the line connecting the second mark point 102 and the third mark point 103 is parallel to the first direction, the distance between the second mark point 102 and the third mark point 103 in the first direction is D1, the width of the isolation trench in the first direction is A1, and D1>A1.

[0053] In a second embodiment, the plurality of mark points include a first mark point 101, a second mark point 102, a third mark point 103 and a fourth mark point 104, the first mark point 101, the second mark point 102, the third mark point 103 and the fourth mark point 104 are sequentially connected to form the target figure; the first mark point 101 and the third mark point 103 are located on the boundary line, the second mark point 102 is located on the first region (specifically, the second mark point 102 is located on the first semiconductor layer corresponding to the first region), and the fourth mark point 104 is located on the second region; the line connecting the first mark point 101 and the third mark point 103 is the first diagonal line of the target figure, the line connecting the second mark point 102 and the fourth mark point 104 is the second diagonal line of the target figure, and the intersection of the first diagonal line and the second diagonal line is the target geometric center 200 of the target figure.

[0054] Of course, the target figure formed by the first mark point 101, the second mark point 102, the third mark point 103 and the fourth mark point 104 mentioned above can also be other figures other than a rectangle, such as a parallelogram or a rhombus, etc.

[0055] Further, after the step of forming the isolation groove 50, the second mask 303 and the third mask 204 in the structure shown in FIG. 4 can be removed to obtain the structure shown in FIG. 5. Further, the solar cell manufacturing method can further include: making an anti-reflection texture on the opposite side of the semiconductor substrate 10 on which the first semiconductor layer 20 is formed, and removing the doped film layer on the opposite side. Further, a chemical passivation treatment can be performed on the outer periphery of the semiconductor structure to form an aluminum oxide passivation layer 60 on the exposed surface of the semiconductor substrate 10 away from the first semiconductor layer 20 and the second semiconductor layer 30, as shown in FIG. 6. Further, a silicon nitride passivation layer (not shown in the figure) can be formed on the side of the aluminum oxide passivation layer 60 away from the semiconductor substrate 10, which can play a light trapping role, corrosion resistance, and protection role of reducing sodium ions and water vapor.

[0056] Optionally, the solar cell manufacturing method can further include: forming a first electrode 70 on the side of the first semiconductor layer 20 away from the semiconductor substrate 10, and forming a second electrode 80 on the side of the second semiconductor layer 30 away from the semiconductor substrate 10, as shown in FIG. 7. The first electrode 70 is in contact with the first semiconductor layer 20, and the second electrode 80 is in contact with the second semiconductor layer 30. The first electrode 70 and the second electrode 80 respectively form ohmic contacts for collecting and leading out current.

[0057] In some optional embodiments, the disclosure further provides a solar cell manufactured by the above-mentioned solar cell manufacturing method, as shown in FIG. 7, which includes: a semiconductor substrate 10 including a first region and a second region, the first region and the second region being adjacent and having a boundary line; a first semiconductor layer 20 located on the first region; a second semiconductor layer 30 located on the second region, the first semiconductor layer 20 and the second semiconductor layer 30 having different doping types; an isolation groove 50 located between the first semiconductor layer 20 and the second semiconductor layer 30 for isolating the first semiconductor layer 20 and the second semiconductor layer 30, and the boundary line is located in the isolation groove 50.

[0058] Specifically, the first semiconductor layer 20 can include a first passivation layer 201 and a first doped layer 202 arranged in a stack, and the second semiconductor layer 30 can include a second passivation layer 301 and a second doped layer 302 arranged in a stack.

[0059] Optionally, the solar cell can further include a first electrode 70 located on the side of the first semiconductor layer 20 away from the semiconductor substrate 10 and in contact with the first doped layer 202 in the first semiconductor layer 20; and a second electrode 80 located on the side of the second semiconductor layer 30 away from the semiconductor substrate 10 and in contact with the second doped layer 302 in the second semiconductor layer 30.

[0060] In the above embodiment, since the solar cell is prepared by the above solar cell preparation method, the alignment accuracy between the first semiconductor layer 20 and the second semiconductor layer 30 is improved, and therefore the solar cell in the embodiment has a higher photoelectric conversion efficiency than the solar cell with the same structure in the prior art.

[0061] From the above description, it can be seen that the above embodiments of the present disclosure achieve the following technical effects:

[0062] For a solar cell including an isolation groove, a preparation method thereof can be as follows: first, a semiconductor substrate is provided, which can include a first region and a second region adjacent to each other and having a boundary line. Then, a first semiconductor layer is formed on the first region, and a second semiconductor layer is formed on the second region, the first semiconductor layer and the second semiconductor layer having different doping types. In order to isolate the first semiconductor layer and the second semiconductor layer, after the first semiconductor layer is formed on the first region, the present disclosure can first form a plurality of marking points on the first semiconductor layer and the second region, and then after a target pattern corresponding to the plurality of marking points is identified, since the target pattern has a target geometric center, after the step of forming the second semiconductor layer on the second region covering the plurality of marking points, in the step of removing part of the second semiconductor layer to the semiconductor substrate by a laser etching process, by passing the laser in the laser etching process through the target geometric center along the extension direction of the boundary line, the isolation groove can be etched to isolate the first semiconductor layer and the second semiconductor layer. That is, by the present disclosure, since the alignment marks (i.e., the plurality of marking points) required for forming the isolation groove have been identified before the laser etching process, the target geometric center of the target pattern corresponding to the plurality of marking points can be directly aligned and etched during the laser etching process, without being limited by the size accuracy of the silicon wafer and the position of the marking points in the silicon wafer, greatly improving the alignment efficiency and accuracy, thereby solving the problem of poor alignment accuracy of the P and N poles of the back contact cell in the prior art.

[0063] The above merely provides preferred embodiments of the present disclosure, and is not used to limit the present disclosure. For those skilled in the art, the present disclosure can have various modifications and variations. Any modifications, equivalent replacements, improvements, etc. made within the principles and technical scope of the present disclosure shall fall into the scope of the present disclosure.

Claims

1. A method for manufacturing a solar cell, comprising: providing a semiconductor substrate, the semiconductor substrate comprising a first region and a second region arranged along a first direction, the first region and the second region being adjacent and having a boundary line; forming a first semiconductor layer on the first region; forming a plurality of mark points on the first semiconductor layer and on the second region; identifying a target pattern corresponding to the plurality of mark points, the target pattern having a target geometric center; forming a second semiconductor layer on the second region, the second semiconductor layer covering the plurality of mark points, the second semiconductor layer and the first semiconductor layer having different doping types; removing part of the second semiconductor layer to the semiconductor substrate by a laser etching process, a laser of the laser etching process passing through the target geometric center along an extension direction of the boundary line to form an isolation trench, the isolation trench being used to isolate the first semiconductor layer and the second semiconductor layer.

2. The method of claim 1, wherein, The step of forming the plurality of mark points comprises: identifying the boundary line by a vision camera; forming the plurality of mark points on the first semiconductor layer and on the second region by a laser etching process, positions of the plurality of mark points being determined according to a position of the boundary line.

3. The method of claim 1, wherein, The step of forming the isolation trench comprises: capturing the target pattern by a vision camera and determining the target geometric center of the target pattern; adjusting the laser of the laser etching process so that the laser passes through the target geometric center along the extension direction of the boundary line and forms a preliminary trench on a surface of the second semiconductor layer; continuing to etch the second semiconductor layer to the semiconductor substrate along the preliminary trench by a chemical etching process to form the isolation trench.

4. The method of any one of claims 1 to 3, wherein, The plurality of mark points are all arranged outside the boundary line. 5.The method of any one of claim 4, wherein, the plurality of mark points comprise a first mark point, a second mark point, a third mark point and a fourth mark point, the first mark point, the second mark point, the third mark point and the fourth mark point being sequentially connected to form the target pattern, the target pattern being a rectangle; the first mark point and the second mark point are arranged on the first region, and the third mark point and the fourth mark point are arranged on the second region; a line connecting the first mark point and the third mark point is a first diagonal line of the rectangle, a line connecting the second mark point and the fourth mark point is a second diagonal line of the rectangle, and an intersection point of the first diagonal line and the second diagonal line is the target geometric center. 6.The method of claim 5, wherein, a line connecting the second mark point and the third mark point is parallel to the first direction; a distance between the second mark point and the third mark point in the first direction is D1; a width of the isolation trench in the first direction is A1, and D1>A1.

7. The method of any one of claims 1 to 3, wherein, At least one of the plurality of mark points is arranged on the boundary line. 8.The method of claim 7, wherein, The plurality of mark points comprises a first mark point, a second mark point, a third mark point and a fourth mark point, the first mark point, the second mark point, the third mark point and the fourth mark point are sequentially connected to form the target pattern, and the target pattern is a rectangle. The first mark point and the second mark point are arranged on the boundary line, and the third mark point and the fourth mark point are arranged on the second region. A line connecting the first mark point and the third mark point is a first diagonal line of the rectangle, a line connecting the second mark point and the fourth mark point is a second diagonal line of the rectangle, and an intersection point of the first diagonal line and the second diagonal line is the target geometric center.

9. The method of claim 8, wherein, A line connecting the second mark point and the third mark point is parallel to the first direction; A distance between the second mark point and the third mark point in the first direction is D1; A width of the isolation groove in the first direction is A1, and D1≤A1.

10. A solar cell prepared by the method of any one of claims 1 to 9, comprising: a semiconductor substrate comprising a first region and a second region arranged along a first direction, the first region and the second region being adjacent and having a boundary line; a first semiconductor layer on the first region; a second semiconductor layer on the second region, the first semiconductor layer and the second semiconductor layer having different doping types; an isolation groove between the first semiconductor layer and the second semiconductor layer for isolating the first semiconductor layer and the second semiconductor layer, and the boundary line is located in the isolation groove.

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