Solar cell

Abstract

Provided in the present application is a solar cell, comprising: a silicon substrate, which has a first surface and a second surface opposite each other; an intrinsic amorphous silicon layer and a doped semiconductor layer, which are stacked in sequence on the first surface and a side surface of the silicon substrate; a tunneling layer and a doped polysilicon layer, which are stacked in sequence on the second surface, wherein the doping type of the doped polysilicon layer is opposite to that of the doped semiconductor layer; a first transparent conductive layer and a second transparent conductive layer, wherein the first transparent conductive layer is arranged on the doped semiconductor layer located on the first surface, the second transparent conductive layer is arranged on the doped polysilicon layer and extends to the side surface of the silicon substrate, and the first transparent conductive layer is also arranged on the doped semiconductor layer located on the side surface of the silicon substrate or on the second transparent conductive layer located on the side surface of the silicon substrate; and an isolation trench, which is located at the edge of the silicon substrate and extends through the first transparent conductive layer and / or the second transparent conductive layer, and / or is located on the side surface of the silicon substrate and extends through the first transparent conductive layer and the second transparent conductive layer.

Description

Solar cell TECHNICAL FIELD

[0001] The present application mainly relates to the field of photovoltaic technology, and particularly relates to a solar cell. BACKGROUND

[0002] The tunnel oxide passivated contact (TOPcon) and the hetero junction (HJT) in the solar cell can improve the conversion efficiency of the solar cell. However, there is a short circuit current between the two, and how to avoid the short circuit between the two is one of the important research directions in the field. SUMMARY

[0003] The technical problem to be solved by the present application is to provide a solar cell which can avoid the short circuit current between the TOPcon passivation structure and the HJT passivation structure.

[0004] To solve the above technical problem, the present application provides a solar cell, comprising: a silicon substrate having opposite first and second surfaces; an intrinsic amorphous silicon layer and a doped semiconductor layer which are sequentially stacked on the first surface and the side surface of the silicon substrate; a tunnel layer and a doped polysilicon layer which are sequentially stacked on the second surface, the doping type of the doped polysilicon layer being opposite to the doping type of the doped semiconductor layer; a first transparent conductive layer disposed on the doped semiconductor layer on the first surface, a second transparent conductive layer disposed on the doped polysilicon layer and extending to the side surface of the silicon substrate, the first transparent conductive layer also being disposed on the doped semiconductor on the side surface of the silicon substrate or on the second transparent conductive layer on the side surface of the silicon substrate; and an isolation groove located at the edge of the silicon substrate and penetrating the first transparent conductive layer and / or the second transparent conductive layer, and / or the isolation groove is located on the side surface of the silicon substrate and penetrates the first transparent conductive layer and the second transparent conductive layer.

[0005] In an embodiment of the present application, the first surface is a light-facing surface, and the second surface is a back light surface, or the first surface is a back light surface, and the second surface is a light-facing surface.

[0006] In an embodiment of the present application, the solar cell further comprises an anti-reflection layer disposed on the transparent conductive layer on the light-facing surface and the side surface of the silicon substrate, wherein the anti-reflection layer comprises any one of silicon nitride, silicon oxide and silicon oxynitride.

[0007] In an embodiment of the present application, the solar cell further comprises a plurality of electrodes in contact with the corresponding transparent conductive layers.

[0008] The solar cell includes a silicon substrate having opposite first and second surfaces; an intrinsic amorphous silicon layer and a doped semiconductor layer sequentially stacked on the first surface and a side surface of the silicon substrate; a tunneling layer and a doped polysilicon layer sequentially stacked on the second surface, the doped polysilicon layer having a doping type opposite to that of the doped semiconductor layer; an anti-reflection layer disposed on the doped semiconductor layer or the doped polysilicon layer and extending to the side surface of the silicon substrate, the anti-reflection layer being located on a light-receiving surface of the silicon substrate; a third transparent conductive layer disposed on the silicon substrate opposite to the anti-reflection layer and extending to the side surface of the silicon substrate; and an isolation groove located at an edge of the silicon substrate and penetrating the third transparent conductive layer, and / or the isolation groove being located on the side surface of the silicon substrate and penetrating the third transparent conductive layer.

[0009] In an embodiment of the present application, the solar cell further includes a plurality of electrodes penetrating the anti-reflection layer and contacting the doped semiconductor layer or the doped polysilicon layer.

[0010] In an embodiment of the present application, the isolation groove has a width greater than 5 μm and less than 5000 μm, and a distance between the isolation groove and an outermost side of the solar cell is less than 15 mm.

[0011] In an embodiment of the present application, the anti-reflection layer includes any of silicon nitride, silicon oxide, and silicon oxynitride.

[0012] In an embodiment of the present application, the intrinsic amorphous silicon layer contains any of oxygen, carbon, and nitrogen.

[0013] In an embodiment of the present application, the doped semiconductor layer includes amorphous silicon and / or microcrystalline silicon.

[0014] Compared with the prior art, the solar cell of the present application has the following advantages: the solar cell of the present application breaks the transparent conductive layer by the isolation groove, thereby reducing short-circuit current. In addition, the isolation groove is located at an edge of the solar cell, so that the area of the transparent conductive layer can be maximized.

[0015] SUMMARY

[0016] The features and characteristics of the present application are further described by the following embodiments and drawings.

[0017] The accompanying drawings are included to provide a further understanding of the present application, and are incorporated in and constitute apart of this application, illustrate embodiments of the present application, and together with the description serve to explain the principles of the present application.

[0018] In the drawings:

[0019] Fig. 1 to Fig. 7 are cross-sectional schematic diagrams of a solar cell in different embodiments of the present application.

[0020] Silicon substrate 110 Tunneling layer 140 Opening 210 First surface 111 Doped polysilicon layer 150 Diffusion layer 220 Second surface 112 First transparent conductive layer 160 First electrode 230 Side surface 113 Second transparent conductive layer 170 Second electrode 240 Intrinsic amorphous silicon layer 120 Isolation groove 180 Third transparent conductive layer 250 Doped semiconductor layer 130 Anti-reflection layer 190

[0021] Preferred embodiments of the present application

[0022] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings needed to be used in the embodiment description will be briefly introduced as follows. Obviously, the drawings in the following description are only some examples or embodiments of the present application, and for those skilled in the art, the present application can also be applied to other similar scenarios without creative labor on the basis of the drawings. Unless it is clear from the language context or otherwise indicated, the same reference numbers in the drawings represent the same structures or operations.

[0023] As shown in the present application and claims, unless the context clearly indicates otherwise, the words "one", "an", "a", and / or "the" do not mean to specify a single number, but can also include a plurality. Generally speaking, the terms "comprise" and "include" only indicate the inclusion of the steps and elements explicitly identified, and these steps and elements do not constitute an exclusive list, and the method or device can also include other steps or elements.

[0024] The foregoing is a summary and thus contains only the most basic embodiment. The application can be practiced with the specific embodiments and options described herein, and it can also be practiced without such specific embodiments and options. Furthermore, the foregoing summary should not limit the scope of the application to a single feature or option described herein. Accordingly, no single feature or option is a requisite for a practice of the application. Unless otherwise specifically explained herein, the relative arrangements of parts, sequences of processes, numerical expressions, and values stated in these embodiments are not meant to limit the scope of the present application. Also, it is understood that the dimensions of the various parts shown in the drawings are not drawn to scale. Techniques, methods, and devices known to those of ordinary skill can not be discussed in detail because such can be understood by persons skilled in the relevant art. In the examples shown and discussed herein, any specific values are to be interpreted as merely exemplary, and not limiting. Other examples of the exemplary embodiments can have different values. It is noted that like numbers and letters refer to like parts throughout the several views of the drawings and, as such, no further discussions on such will be separately undertaken since such will be understood from the description below.

[0025] In the description of the present application, it is to be understood that the orientation or positional relationships indicated by terms such as "front", "back", "up", "down", "left", "right", "lateral", "vertical", "horizontal", and "top", "bottom" are generally based on the orientation or positional relationships shown in the drawings, and are merely for convenience of description and simplification of description, and do not indicate or imply that the devices or elements referred to must have a particular orientation or be constructed and operated in a particular orientation, and therefore cannot be construed as limiting the scope of the present application. The orientation terms "inner", "outer" refer to the inner and outer relative to the contour of the parts themselves.

[0026] For the convenience of description, spatial relative terms such as "over", "above", "upper surface", "upper", and the like can be used herein to describe the spatial positional relationship of one device or feature with respect to other devices or features as shown in the drawings. It should be understood that the spatial relative terms are intended to include different orientations in use or operation in addition to the orientation of the devices described in the drawings. For example, if the devices in the drawings are inverted, the device described as "above" or "over" other devices or structures will be positioned "below" or "under" the other devices or structures. Thus, the exemplary term "above" can include both "above" and "below" orientations. The device can also be positioned in other different ways (rotated 90 degrees or in other orientations), and the spatial relative descriptions used herein are interpreted accordingly.

[0027] In addition, it should be noted that the use of "first", "second", and the like words to define parts is merely for the convenience of distinguishing the corresponding parts, and the above words have no special meaning unless otherwise stated, and therefore cannot be understood as limiting the scope of protection of the present application. In addition, although the terms used in the present application are selected from commonly known terms, some terms mentioned in the specification of the present application can be selected by the applicant according to his or her judgment, and the detailed meanings thereof are described in the relevant part of the description. In addition, the present application is required to be understood not only by the actual terms used, but also by the meaning implied by each term.

[0028] Next, the solar cell of the present application will be described by way of examples.

[0029] Referring to FIG. 1, a silicon substrate 110 has opposite first and second faces 111 and 112. The first face 111 can be a light-receiving face, and the corresponding second face 112 can be a back face. Alternatively, the first face 111 can be a back face, and the corresponding second face 112 can be a light-receiving face. The silicon substrate 110 can be an N-type or P-type doped single crystal silicon.

[0030] An intrinsic amorphous silicon layer 120 and a doped semiconductor layer 130 are sequentially stacked on the first face 111, and the intrinsic amorphous silicon layer 120 and the doped semiconductor layer 130 are also sequentially stacked on the side face 113 of the silicon substrate 110. The thickness of the intrinsic amorphous silicon layer 120 can be 3 nm to 15 nm, for example, 3 nm, 5 nm, 7 nm, 9 nm, 11 nm, 13 nm, or 15 nm. The thickness of the intrinsic amorphous silicon layer 120 can be 3 nm to 60 nm, for example, 3 nm, 13 nm, 23 nm, 33 nm, 43 nm, 53 nm, or 60 nm. The intrinsic amorphous silicon layer 120 can contain any of oxygen (O), carbon (C), and nitrogen (N). The doped semiconductor layer 130 can include amorphous silicon and / or microcrystalline silicon, for example, the doped semiconductor layer 130 can be N-type or P-type doped amorphous silicon. The doped semiconductor layer 130 can contain one or more of oxygen, carbon, or nitrogen.

[0031] The tunneling layer 140 and the doped polysilicon layer 150 are sequentially stacked on the second surface 112. The tunneling layer 140 can be one or more of silicon oxide (SiOx), silicon oxynitride (SiOxNy), aluminum oxide (Al2O3). The thickness of the tunneling layer 140 is equal to or less than 3 nm, for example, the thickness is 1 nm, 2 nm, or 3 nm. The tunneling layer 140 can contain one or more of the doping elements in the doped polysilicon layer 150 and / or the silicon substrate 110. The doped polysilicon layer 150 can be an N-type or P-type doped polysilicon layer, and the doping type of the doped polysilicon layer 150 is opposite to the doping type of the doped semiconductor layer 130, for example, the doped polysilicon layer 150 is N-type doped and the doped semiconductor layer 130 is P-type doped. The doped polysilicon layer 150 can contain one or more of oxygen elements, carbon elements, and nitrogen elements. The thickness of the doped polysilicon layer 150 can be 20 nm to 600 nm, for example, the thickness is 20 nm, 120 nm, 220 nm, 320 nm, 420 nm, 520 nm, or 600 nm.

[0032] In the embodiment of FIG. 1, the tunneling layer 140 and the doped polysilicon layer 150 are not formed on the side surface 113, so that short circuit between the tunneling layer 140 and the doped polysilicon layer 150 (TOPcon passivation structure) on the side surface 113 and the intrinsic amorphous silicon layer 120 and the doped semiconductor layer 130 (HJT passivation structure) can be avoided.

[0033] In an embodiment, the solar cell has a diffusion layer 220. The diffusion layer 220 is between the tunneling layer 140 and the silicon substrate 110, and the doping type of the diffusion layer 220 is the same as the doping type of the doped polysilicon layer 150. The diffusion layer 220 can be an N-type or P-type doped single crystal silicon. The thickness of the diffusion layer 220 is equal to or greater than 20 nm and equal to or less than 1500 nm, for example, the thickness is 20 nm, 120 nm, 220 nm, 320 nm, 420 nm, 520 nm, 620 nm, 720 nm, 820 nm, 920 nm, 1020 nm, 1120 nm, 1220 nm, 1320 nm, 1420 nm, or 1500 nm.

[0034] The first transparent conductive layer 160 is disposed on the doped semiconductor layer 130 on the first surface 111, and the first transparent conductive layer 160 is also disposed on the doped semiconductor layer 130 on the side surface 113. The second transparent conductive layer 170 is disposed on the doped polysilicon layer 150 and extends to the side surface 113.

[0035] Referring to FIG. 4, in some embodiments, the first transparent conductive layer 160 on the side surface 113 is disposed on the second transparent conductive layer 170. In other words, the second transparent conductive layer 170 on the side surface 113 is disposed on the doped semiconductor layer 130 on the side surface 113, and the first transparent conductive layer 160 on the side surface 113 is disposed on the second transparent conductive layer 170 on the side surface 113.

[0036] The first transparent conductive layer 160 can include one or more of zinc oxide (ZnO), indium oxide (InO), and tin oxide (SnO), and the first transparent conductive layer 160 can contain one or more of gallium (Ga), tin (Sn), cesium (Ce), molybdenum (Mo), fluorine (F), tungsten (W), and aluminum (Al). The thickness of the first transparent conductive layer 160 is equal to or greater than 10 nm and less than or equal to 200 nm, for example, the thickness is 10 nm, 50 nm, 90 nm, 130 nm, 170 nm, or 200 nm.

[0037] The second transparent conductive layer 170 can include one or more of zinc oxide, indium oxide, and tin oxide, and the first transparent conductive layer 160 can contain one or more of gallium, tin, cesium, molybdenum, fluorine, tungsten, and aluminum. The thickness of the first transparent conductive layer 160 is equal to or greater than 10 nm and less than or equal to 200 nm, for example, the thickness is 10 nm, 50 nm, 90 nm, 130 nm, 170 nm, or 200 nm. The thickness of the first transparent conductive layer 160 can be equal to or different from the thickness of the second transparent conductive layer 170.

[0038] The isolation groove 180 is located at the edge of the silicon substrate 110, and the isolation groove 180 penetrates the first transparent conductive layer 160. The first transparent conductive layer 160 on the side surface 113 is in contact with the second transparent conductive layer 170 on the side surface, and the penetration of the isolation groove 180 through the first transparent conductive layer 160 can avoid the electrical connection between the first transparent conductive layer 160 on the side surface 113 and the first electrode 230 and the second transparent conductive layer 170, thereby avoiding the short-circuit current between the TOPcon passivation structure and the HJT passivation structure in the battery.

[0039] The first electrode 230 is in contact with the first transparent conductive layer 160, and the second electrode 240 is in contact with the second transparent conductive layer 170.

[0040] Referring to FIG. 2, in the embodiment of FIG. 2, the isolation groove 180 is also located at the edge of the silicon substrate 110. Different from FIG. 1, the isolation groove 180 in FIG. 1 is located on the first surface 111, and the transparent conductive layer that is penetrated is the first transparent conductive layer 160. In FIG. 2, the isolation groove 180 is located on the second surface 112, and the transparent conductive layer that is penetrated is the second transparent conductive layer 170. In some embodiments, the isolation groove 180 can be located on both the first surface 111 and the second surface 112. The isolation groove 180 located on the first surface 111 penetrates the first transparent conductive layer 160, and the isolation groove 180 located on the second surface 112 penetrates the second transparent conductive layer 170.

[0041] As shown in FIG. 2, the isolation groove 180 can penetrate into the doped polysilicon layer 150 to a certain depth. The isolation groove 180 can also penetrate through the doped polysilicon layer 150.

[0042] Referring to FIG. 3, in the embodiment of FIG. 3, the isolation groove 180 is located on the side surface 113 and penetrates the first transparent conductive layer 160 and the second transparent conductive layer 170. In this way, the first transparent conductive layer 160 and the second transparent conductive layer 170 located on the side surface 113 can be prevented from being electrically connected to the first electrode 230 and the second electrode 240.

[0043] If the second surface 112 in FIG. 1 is a light-facing surface, compared with the embodiment in FIG. 2, since the isolation groove 180 in FIG. 1 is located on the back surface (i.e., the first surface 111), FIG. 1 has a full-area second transparent conductive layer 170, which can reduce reflection of incident light and electrical loss.

[0044] In an embodiment, the width of the isolation groove 180 is greater than 5 μm and less than 5000 μm, for example, the width is 500 μm, 1000 μm, 1500 μm, 2000 μm, 2500 μm, 3000 μm, 3500 μm, 4000 μm, or 4500 μm. The isolation groove 180 can be prepared by using a laser.

[0045] Referring to FIGS. 1 and 2, in an embodiment, the distance d1 between the isolation groove 180 and the outermost side of the solar cell is less than 15 mm, for example, the distance d1 is 0 nm, 5 mm, or 10 nm. When the distance d1 is 0 nm, it means that one side of the isolation groove 180 is located at the outermost side of the solar cell. The distance d1 less than 15 mm can maximize the area of the transparent conductive layer on the first surface 111 and / or the second surface 112, so that the photo-generated carriers can be effectively collected.

[0046] Referring to FIG. 5, in an embodiment, the second surface 112 is a light-receiving surface. The solar cell further includes an anti-reflection layer 190 disposed on the second transparent conductive layer 170 on the second surface 112 and the side surface 113. The anti-reflection layer 190 can include any of silicon nitride, silicon oxide, silicon oxynitride. The anti-reflection layer 190 has a thickness greater than or equal to 10 nm and less than or equal to 200 nm, for example, a thickness of 10 nm, 50 nm, 90 nm, 130 nm, 170 nm, or 200 nm. The second electrode 240 contacts the second transparent conductive layer 170 after penetrating the anti-reflection layer 190. The opening 210 for the second electrode 240 to pass through can be formed in the anti-reflection layer 190 by a laser drilling process.

[0047] Referring to FIG. 6, the difference between FIG. 6 and FIG. 5 includes that, at the side surface 113, the second transparent conductive layer 170 covers the doped semiconductor layer 130, the first transparent conductive layer 160 covers the second transparent conductive layer 170, and the anti-reflection layer 190 covers the first transparent conductive layer 160.

[0048] Another aspect of the present application also provides a solar cell, which is described as follows.

[0049] Referring to FIG. 7, in the embodiment of FIG. 7, the second surface 112 is a light-receiving surface. The intrinsic amorphous silicon layer 120 and the doped semiconductor layer 130 are sequentially stacked on the first surface 111 and the side surface 113. The tunneling layer 140 and the doped polysilicon layer 150 are sequentially stacked on the second surface 112. The anti-reflection layer 190 is disposed on the doped polysilicon layer 150 and extends to the side surface 113,

[0050] The third transparent conductive layer 250 is disposed on the silicon substrate 110 opposite to the anti-reflection layer 190 and extends to the side surface 113. In detail, the third transparent conductive layer 250 is disposed on the doped semiconductor layer 130, the intrinsic amorphous silicon layer 120 and the doped semiconductor layer 130 are sequentially stacked on the side surface 113, and the third transparent conductive layer 250 contacts the doped semiconductor layer 130 on the side surface 113. The anti-reflection layer 190 contacts the third transparent conductive layer 250 on the side surface 113.

[0051] The anti-reflection layer 190 can include any of silicon nitride, silicon oxide, silicon oxynitride.

[0052] It should be noted that, in some other embodiments, the first surface 111 is a light-receiving surface, the anti-reflection layer 190 is disposed on the doped semiconductor layer 130 and extends to the side surface 113. The third transparent conductive layer 250 is disposed on the other side opposite to the anti-reflection layer 190.

[0053] The third transparent conductive layer 250 can include one or more of zinc oxide, indium oxide, tin oxide, and can contain one or more of gallium, tin, cesium, molybdenum, fluorine, tungsten, aluminum. The first transparent conductive layer 160 has a thickness equal to or greater than 10 nm and less than or equal to 200 nm, for example, a thickness of 10 nm, 50 nm, 90 nm, 130 nm, 170 nm, or 200 nm.

[0054] The isolation groove 180 is located at the edge of the silicon substrate 110 and penetrates the third transparent conductive layer 250. In one embodiment, the isolation groove 180 is located at the side surface 113 and penetrates the third transparent conductive layer 250 located on the side surface 113. In other embodiments, the isolation groove 180 can be provided at the edge of the silicon substrate 110 and on the side surface 113 at the same time, and the isolation groove 180 penetrates the third transparent conductive layer 250.

[0055] Referring to FIG. 7, in one embodiment, the solar cell further includes a first electrode 230 and a second electrode 240, the first electrode 230 penetrates the anti-reflective layer 190 and contacts the doped polysilicon layer 150. It can be understood that if the anti-reflective layer 190 is provided on the doped semiconductor layer 130, the electrode penetrates the anti-reflective layer 190 and contacts the doped semiconductor layer 130.

[0056] The above description has been made to the basic concept, and it is obvious that the above-described application disclosure is only used as an example and does not constitute a limitation on the application. Although it is not explicitly stated here, those skilled in the art can make various modifications, improvements and corrections to the application. Such modifications, improvements and corrections are suggested in the application, so such modifications, improvements and corrections still belong to the spirit and scope of the exemplary embodiments of the application.

[0057] Meanwhile, specific words are used in the application to describe the embodiments of the application. As "one embodiment", "an embodiment", and / or "some embodiments" means a certain feature, structure or characteristic related to at least one embodiment of the application. Therefore, it should be emphasized and noted that the "one embodiment" or "one embodiment" or "one alternative embodiment" mentioned in different places in the specification does not necessarily refer to the same embodiment. In addition, some features, structures or characteristics of one or more embodiments of the application can be properly combined.

[0058] Similarly, it should be noted that, in order to simplify the description of the application disclosure and to help understand one or more embodiments of the application, sometimes multiple features are combined into one embodiment, figure or description thereof. However, this disclosure method does not mean that the features required by the application are more than the features mentioned in the claims. In fact, the features of the embodiment are less than all the features of the single embodiment disclosed above.

[0059] Some embodiments use numerical descriptors of components, quantities of attributes, and the like. It should be understood that such numerical descriptors used in the description of embodiments are, in some examples, modified by the terms "about," "approximately," or "generally." Unless otherwise stated, "about," "approximately," or "generally" indicates that a deviation of ±20% from the stated numerical value is intended. Accordingly, in some embodiments, numerical values used in the specification and claims are approximations which can vary depending on the desired characteristics of the individual embodiments. In some embodiments, numerical values should be considered in the context of the description of the embodiments and, where appropriate, the number of significant digits can be reported in a range format. Although the numerical ranges and parameters setting forth the broad scope of the application in some embodiments are approximations, the numerical values set forth in the specific examples are reported as precisely as practicable. The numerical values set forth in the specific examples are provided to be as precise as reasonably possible. However, some variations may

[0060] Although the application has been described with reference to the current embodiments, it will be understood that the application is capable of considerable variations and modifications and alternative realizations within the spirit and scope thereof as set forth in the following claims.

Claims

1. A solar cell, characterized by, Comprising: a silicon substrate (110) having opposite first and second faces (111, 112); an intrinsic amorphous silicon layer (120) and a doped semiconductor layer (130) stacked in sequence on the first face (111) and a side face (113) of the silicon substrate (110); a tunneling layer (140) and a doped polysilicon layer (150) stacked in sequence on the second face (112), the doped polysilicon layer (150) having a doping type opposite to that of the doped semiconductor layer (130); a first transparent conductive layer (160) disposed on the doped semiconductor layer (130) on the first face (111), a second transparent conductive layer (170) disposed on the doped polysilicon layer (150) and extending onto the side face (113) of the silicon substrate, the first transparent conductive layer (160) also being disposed on the doped semiconductor layer on the side face (113) of the silicon substrate or on the second transparent conductive layer (170) on the side face of the silicon substrate; and an isolation groove (180) located at an edge of the silicon substrate (110) and penetrating the first transparent conductive layer (160) and / or the second transparent conductive layer (170), and / or the isolation groove (180) is located on the side face (113) of the silicon substrate and penetrates the first transparent conductive layer (160) and the second transparent conductive layer (170).

2. The solar cell of claim 1, wherein, The first face (111) is a light-facing face, and the second face (112) is a back light-facing face, or the first face (111) is a back light-facing face, and the second face (112) is a light-facing face.

3. The solar cell of claim 2, wherein the first and second doped regions are formed by implanting dopants into the first and second surfaces of the substrate. Further comprising an anti-reflection layer (190) disposed on the transparent conductive layer on the light-facing face and the side face of the silicon substrate, wherein the anti-reflection layer comprises any of silicon nitride, silicon oxide, and silicon oxynitride.

4. The solar cell of claim 1, wherein the first and second electrodes are formed of a material selected from the group consisting of silver, aluminum, gold, copper, and combinations thereof. Further comprising a plurality of electrodes in contact with the corresponding transparent conductive layer.

5. A solar cell, characterized by, Comprising: a silicon substrate (110) having opposite first and second faces (111, 112); an intrinsic amorphous silicon layer (120) and a doped semiconductor layer (130) stacked in sequence on the first face (111) and a side face (113) of the silicon substrate (110); a tunneling layer (140) and a doped polysilicon layer (150) stacked in sequence on the second face (112), the doped polysilicon layer (150) having a doping type opposite to that of the doped semiconductor layer (130); an anti-reflection layer (190) disposed on the doped semiconductor layer (130) or the doped polysilicon layer (150) and extending onto the side face (113) of the silicon substrate, the anti-reflection layer (190) being located on the light-facing face of the silicon substrate; a third transparent conductive layer (250) disposed on the silicon substrate (110) opposite the anti-reflection layer (190) and extending onto the side face (113) of the silicon substrate; and a third transparent conductive layer (250) disposed on the silicon substrate (110) opposite the anti-reflection layer (190) and extending onto the side face (113) of the silicon substrate; and An isolation groove (180) is located at the edge of the silicon substrate (110) and penetrates the third transparent conductive layer (250), and / or the isolation groove (180) is located at the side surface (113) of the silicon substrate and penetrates the third transparent conductive layer (250).

6. The solar cell of claim 5, wherein the first and second doped regions are formed by implanting dopants into the first and second surfaces of the substrate. Further comprising a plurality of electrodes penetrating the anti-reflection layer and contacting the doped semiconductor layer (130) or the doped polysilicon layer (150).

7. The solar cell of claim 5, wherein the first and second doped regions are formed by implanting dopants into the first and second surfaces of the substrate. The width of the isolation groove (180) is greater than 5 μm and less than 5000 μm, and the distance between the isolation groove (180) and the outermost side of the solar cell is less than 15 mm.

8. The solar cell as described in claim 5, characterized in that, The anti-reflection layer comprises any of silicon nitride, silicon oxide, silicon oxynitride.

9. The solar cell as claimed in claim 1 or 5, wherein The intrinsic amorphous silicon layer (120) contains any of oxygen element, carbon element, nitrogen element.

10. The solar cell as claimed in claim 1 or 5, wherein The doped semiconductor layer (130) comprises amorphous silicon and / or microcrystalline silicon.

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