Display substrate, preparation method therefor, and display apparatus

Abstract

A display substrate, a preparation method therefor, and a display apparatus. The display substrate comprises a plurality of sub pixels (P1-P4), and a sub-pixel comprises a pixel driving circuit and a light-emitting device. The pixel driving circuit comprises at least a second transistor (T2) and a node electrode (52). The second transistor comprises at least a second active layer (32). The node electrode is connected to a second region of the second active layer by means of a node via (JV). The light-emitting device comprises at least a first electrode (90) and a pixel define layer (206), the first electrode being connected to the node electrode by means of an anode via (YV), and the pixel define layer being provided with a pixel opening (90A) exposing the first electrode. In at least one sub pixel, the orthographic projection of the node via on the plane of the display substrate does not overlap with the orthographic projection of the pixel opening on the plane of the display substrate, and the anode via is arranged on the side of the node via away from the pixel opening. According to the present disclosure, display defects such as mura are effectively eliminated, and the display effect and display quality are improved.

Description

Display substrate, preparation method thereof and display device

[0001] The present application claims priority to the Chinese patent application No. 202411121599.4, filed on August 14, 2024, and entitled "Display substrate, preparation method thereof and display device", the content of which is incorporated herein by reference. TECHNICAL FIELD

[0002] The present disclosure relates to, but is not limited to, the technical field of display, and in particular to a display substrate, a preparation method thereof and a display device. BACKGROUND

[0003] Organic Light Emitting Diode (OLED) and Quantum-dot Light Emitting Diodes (QLED) are active light-emitting display devices, which have the advantages of self-emission, wide viewing angle, high contrast, low power consumption, extremely high response speed, lightness, flexibility and low cost. With the continuous development of display technology, display devices using OLED or QLED as light-emitting devices and controlled by Thin Film Transistor (TFT) have become the mainstream products in the current display field. SUMMARY

[0004] The following is a summary of the subject matter of the detailed description herein. This summary is not intended to limit the scope of the claims.

[0005] In one aspect, the present disclosure provides a display substrate, comprising a plurality of repeating units, at least one repeating unit comprising a plurality of sub-pixels, at least one sub-pixel comprising a pixel driving circuit and a light-emitting device; the pixel driving circuit at least comprising a second transistor as a driving transistor and a node electrode, the second transistor at least comprising a second active layer, the node electrode being connected with a second region of the second active layer through a node via, a first region of the second active layer being connected with a first power line; the light-emitting device at least comprising a first electrode and a pixel definition layer, the first electrode being connected with the node electrode through an anode via, the pixel definition layer being provided with a pixel opening exposing the first electrode; in at least one sub-pixel, a normal projection of the node via on a display substrate plane does not overlap with a normal projection of the pixel opening on the display substrate plane, the anode via being arranged on a side of the node via away from the pixel opening.

[0006] In an example embodiment, the pixel driving circuit further comprises a shielding electrode and a transparent storage capacitor, the storage capacitor comprises a first plate and a second plate, a projection of the first plate on a display substrate plane at least partially overlaps with a projection of the second plate on the display substrate plane, a projection of the shielding electrode on the display substrate plane at least partially overlaps with a projection of the second active layer on the display substrate plane, the shielding electrode is connected with the first plate; in at least one sub-pixel, the node electrode is further connected with the shielding electrode through the node via.

[0007] In an example embodiment, the node electrode comprises at least a first sub-electrode and a second sub-electrode connected with each other, the first sub-electrode is connected with the second region of the second active layer and the shielding electrode through the node via at the same time, the first electrode is connected with the second sub-electrode through an anode via, and the second sub-electrode is arranged on a side of the first sub-electrode away from the pixel opening.

[0008] In an example embodiment, a projection of the second sub-electrode on a display substrate plane at least partially overlaps with a projection of the second region of the second active layer on the display substrate plane, and a projection of the anode via on the display substrate plane at least partially overlaps with a projection of the second region of the second active layer on the display substrate plane.

[0009] In an example embodiment, in at least one sub-pixel, a projection of the first plate on a display substrate plane at least partially overlaps with a projection of the pixel opening on the display substrate plane, and a projection of the second plate on the display substrate plane at least partially overlaps with a projection of the pixel opening on the display substrate plane.

[0010] In an example embodiment, in a direction perpendicular to the display substrate, the display substrate comprises at least a first transparent conductive layer arranged on a substrate, a first conductive layer arranged on a side of the first transparent conductive layer away from the substrate, a semiconductor layer arranged on a side of the first conductive layer away from the substrate, and a second conductive layer arranged on a side of the semiconductor layer away from the substrate, the first plate is arranged in the first transparent conductive layer, the shielding electrode is arranged in the first conductive layer, the second plate and the second active layer are arranged in the semiconductor layer, and the node electrode is arranged in the second conductive layer.

[0011] In an example embodiment, the second transistor further comprises a second gate electrode, and the pixel driving circuit further comprises a first connection electrode; in at least one sub-pixel, the first connection electrode is connected with the second plate and the second gate electrode through a first switching via.

[0012] In an example embodiment, in at least one of the sub-pixels, a projection of the second gate electrode on a display substrate plane at least partially overlaps with a projection of the second plate on the display substrate plane.

[0013] In an example embodiment, in at least one of the first transfer vias, a projection of the second gate electrode on a display substrate plane at least partially overlaps with a projection of the second plate on the display substrate plane.

[0014] In an example embodiment, the at least one repeating unit comprises, in sequence along a first direction, a first sub-pixel, a second sub-pixel, a third sub-pixel, and a fourth sub-pixel, the first power supply line is in a shape of a straight line or a broken line extending along a second direction, and is respectively arranged in the first sub-pixel and the fourth sub-pixel, the first direction and the second direction intersect; the first power supply line in the first sub-pixel is connected to the first region of the second active layer in the first sub-pixel through a power supply via, the first power supply line in the first sub-pixel is connected to the first region of the second active layer in the second sub-pixel through a power supply connection line and a power supply connection electrode, the first power supply line in the fourth sub-pixel is connected to the first region of the second active layer in the third sub-pixel through a power supply connection line and a power supply connection electrode, and the first power supply line in the fourth sub-pixel is connected to the first region of the second active layer in the fourth sub-pixel through a power supply via.

[0015] In an example embodiment, the pixel driving circuit further comprises a shielding electrode, a projection of the shielding electrode on a display substrate plane at least partially overlaps with a projection of the second active layer on the display substrate plane; in the first sub-pixel and the fourth sub-pixel, a projection of the power supply via on the display substrate plane does not overlap with a projection of the shielding electrode on the display substrate plane.

[0016] In an example embodiment, the pixel driving circuit further comprises a shielding electrode, a projection of the shielding electrode on a display substrate plane at least partially overlaps with a projection of the second active layer on the display substrate plane; in the second sub-pixel and the third sub-pixel, a first end of the power supply connection electrode is connected to the first region of the second active layer through a power supply via, a second end of the power supply connection electrode is connected to the first power supply line through the power supply connection line, and a projection of the power supply via on the display substrate plane at least partially overlaps with a projection of the shielding electrode on the display substrate plane.

[0017] In an exemplary embodiment, at least one of the sub-pixels further comprises a data signal line connected to the pixel driving circuit, the data signal line has a shape of a broken line extending along the second direction, at least comprising a first sub-line and a second sub-line in straight line shape, and a third sub-line in slanted line shape, the third sub-line is arranged between the first sub-line and the second sub-line, and two ends of the third sub-line are connected to the first sub-line and the second sub-line respectively; in at least one of the first sub-pixel and the fourth sub-pixel, the first sub-line has a first distance from the first power supply line, the second sub-line has a second distance from the first power supply line, the first distance is greater than the second distance, and the first distance and the second distance are dimensions in the first direction.

[0018] In an exemplary embodiment, at least one of the sub-pixels further comprises a compensation signal line connected to the pixel driving circuit, the compensation signal line is arranged between the second sub-pixel and the third sub-pixel; in at least one of the second sub-pixel and the third sub-pixel, the first sub-line has a third distance from the compensation signal line, the second sub-line has a fourth distance from the compensation signal line, the third distance is less than the fourth distance, and the third distance and the fourth distance are dimensions in the first direction.

[0019] In an exemplary embodiment, a normal projection of the compensation signal line on a display substrate plane does not overlap with a normal projection of the power supply connection line on the display substrate plane.

[0020] In an exemplary embodiment, the pixel driving circuit further comprises a first transistor as a data writing transistor and a third transistor as a compensation transistor, in at least one of the sub-pixels, a gate electrode of the first transistor and a gate electrode of the third transistor are connected to the same scan signal line.

[0021] In an exemplary embodiment, in at least one of the repeating units, gate electrodes of a plurality of the first transistors and gate electrodes of a plurality of the third transistors are connected to the same scan signal line.

[0022] In an exemplary embodiment, in at least one of the repeating units, at least one via hole is arranged on the scan signal line, a normal projection of the via hole on a display substrate plane at least partially overlaps with a normal projection of the first power supply line on the display substrate plane.

[0023] On the other hand, the present disclosure also provides a display device comprising the aforementioned display substrate.

[0024] In another aspect, the present disclosure also provides a preparation method of a display substrate, the display substrate comprising a plurality of sub-pixels, the preparation method comprising:

[0025] forming a pixel driving circuit and a light emitting device in at least one sub-pixel; the pixel driving circuit at least includes a second transistor as a driving transistor and a node electrode, the second transistor at least includes a second active layer, the node electrode is connected with a second region of the second active layer through a node via, a first region of the second active layer is connected with a first power supply line; the light emitting device at least includes a first electrode and a pixel definition layer, the first electrode is connected with the node electrode through an anode via, the pixel definition layer is provided with a pixel opening exposing the first electrode; in at least one sub-pixel, a normal projection of the node via on a display substrate plane does not overlap with a normal projection of the pixel opening on the display substrate plane, the anode via is arranged on a side of the node via away from the pixel opening.

[0026] Other aspects can be apparent after review of the accompanying drawings and detailed description. BRIEF DESCRIPTION OF DRAWINGS

[0027] The accompanying drawings are included to provide a further understanding of the technical solutions of the present disclosure, and constitute a part of the specification, and are used to explain the technical solutions of the present disclosure together with the embodiments of the present disclosure, and do not constitute a limitation to the technical solutions of the present disclosure. The shapes and sizes of the components in the drawings do not reflect true proportions, and the purpose is only to schematically illustrate the present disclosure.

[0028] FIG. 1 is a structural schematic diagram of a display device;

[0029] FIG. 2 is a planar structural schematic diagram of a display substrate according to an example embodiment of the present disclosure;

[0030] FIG. 3 is an equivalent circuit diagram of a pixel driving circuit in a repeat unit according to an example embodiment of the present disclosure;

[0031] FIG. 4 is a structural schematic diagram of a display substrate according to an example embodiment of the present disclosure;

[0032] FIG. 5 is a sectional view along A-A direction in FIG. 4;

[0033] FIG. 6 is a schematic diagram after forming a first transparent conductive layer pattern according to an example embodiment of the present disclosure;

[0034] FIGS. 7A and 7B are schematic diagrams after forming a first conductive layer pattern according to an example embodiment of the present disclosure;

[0035] FIGS. 8A and 8B are schematic diagrams after forming a semiconductor layer pattern according to an example embodiment of the present disclosure;

[0036] FIGS. 9A and 9B are schematic diagrams after forming a second conductive layer pattern according to an example embodiment of the present disclosure;

[0037] FIG. 10 is a schematic diagram after forming a third insulating layer pattern according to an example embodiment of the present disclosure;

[0038] FIGS. 11A and 11B are schematic diagrams of a third conductive layer pattern formed according to an embodiment of the present disclosure;

[0039] FIG. 12 is a schematic diagram of a fourth insulating layer and a planar layer pattern formed according to an embodiment of the present disclosure;

[0040] FIG. 13 is a schematic diagram of a second transparent conductive layer pattern formed according to an embodiment of the present disclosure;

[0041] FIG. 14 is a schematic diagram of a pixel definition layer pattern formed according to an embodiment of the present disclosure.

[0042] BRIEF DESCRIPTION OF DRAWINGS: 11 - first plate; 12 - connecting plate; 13 - connecting line; 21 - power supply connecting line; 22 - compensation connecting line; 22-1 - compensation connecting block; 23 - shielding electrode; 24 - interlayer connecting electrode; 31 - first active layer; 32 - second active layer; 33 - third active layer; 34 - second plate; 42 - second gate electrode; 50 - scanning signal line; 51 - first connecting electrode; 52 - second connecting electrode; 52-1 - first sub-electrode; 52-2 - second sub-electrode; 53 - third connecting electrode; 54 - fourth connecting electrode; 55 - fifth connecting electrode; 56 - power supply connecting electrode; 60 - first power supply line; 70 - data signal line; 70-1 - first sub-line; 70-2 - second sub-line; 70-3 - third sub-line; 80 - compensation signal line; 90 - first electrode; 90A - pixel opening; 100 - repeating unit; 200 - substrate; 201 - first insulating layer; 202 - second insulating layer; 203 - third insulating layer; 204 - fourth insulating layer; 205 - planar layer; 206 - pixel definition layer; DV - power supply via; JV - node via; ZV - first switching via; YV - anode via. DETAILED DESCRIPTION

[0043] In order to make the objects, technical solutions and advantages of the present disclosure clearer, the following will be combined with the accompanying drawings to describe embodiments of the present disclosure in detail. The embodiments can be implemented in a variety of different forms. One skilled in the art can easily understand that the means and content can be varied into various forms without departing from the spirit and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the content described in the following embodiments. The embodiments in the present disclosure and the features in the embodiments can be combined with each other arbitrarily without conflict.

[0044] The scale of the drawings in the present disclosure can be used as a reference in the actual process, but is not limited thereto. For example, the width-length ratio of the channel, the thickness and spacing of each film layer, and the width and spacing of each signal line can be adjusted according to actual needs. The number of pixels in the display substrate and the number of sub-pixels in each pixel are also not limited to the number shown in the drawings. The drawings described in the present disclosure are only schematic structural diagrams, and one embodiment of the present disclosure is not limited to the shapes or values shown in the drawings.

[0045] In the present specification, ordinal numbers such as "first", "second", "third", and the like are provided to avoid confusion of constituent elements, and are not intended to be limited in terms of quantity.

[0046] In the present specification, for the convenience of description, words indicating orientation or positional relationship such as "middle", "upper", "lower", "front", "rear", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like are used to describe the positional relationship of the constituent elements with reference to the drawings, and are only for the convenience of description of the present specification and simplification of the description, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the present disclosure. The positional relationship of the constituent elements is appropriately changed according to the direction of describing each constituent element. Therefore, it is not limited to the words described in the specification, and can be appropriately changed according to the situation.

[0047] In the present specification, unless explicitly specified and limited, the terms "mounting", "connection", "connection" should be understood broadly. For example, it can be fixedly connected, or detachably connected, or integrally connected; it can be mechanically connected, or electrically connected; it can be directly connected, or indirectly connected through an intermediate piece, or the communication inside two elements. Those skilled in the art can understand the specific meaning of the above terms in the present disclosure according to the specific circumstances.

[0048] In this specification, a transistor means an element including at least three terminals of a gate electrode, a drain electrode, and a source electrode. The transistor has a channel region between the drain electrode (a drain electrode terminal, a drain region, or a drain electrode) and the source electrode (a source electrode terminal, a source region, or a source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that, in this specification, the channel region means a region where current flows mainly.

[0049] In this specification, the first terminal can be a drain electrode and the second terminal can be a source electrode, or the first terminal can be a source electrode and the second terminal can be a drain electrode. In the case of using a transistor having opposite polarity or in the case where the direction of current changes in circuit operation, the functions of the "source electrode" and the "drain electrode" are sometimes interchanged with each other. Thus, in this specification, the "source electrode" and the "drain electrode" can be interchanged with each other, and the "source terminal" and the "drain terminal" can be interchanged with each other.

[0050] In this specification, "electrically connected" includes the case where components are connected through an element having some function of electricity. The element having some function of electricity is not particularly limited as long as electric signals can be transmitted and received between components to be connected. Examples of the element having some function of electricity include not only an electrode and a wiring but also a switching element such as a transistor, a resistor, an inductor, a capacitor, and another element having some function.

[0051] In this specification, "parallel" means a state where an angle formed between two straight lines is greater than or equal to -10° and less than or equal to 10°, and thus includes a state where the angle is greater than or equal to -5° and less than or equal to 5°. In addition, "perpendicular" means a state where an angle formed between two straight lines is greater than or equal to 80° and less than or equal to 100°, and thus includes a state where the angle is greater than or equal to 85° and less than or equal to 95°.

[0052] In this specification, a "film" and a "layer" can be interchanged with each other. For example, a "conductive layer" can be replaced with a "conductive film". Similarly, an "insulating film" can be replaced with an "insulating layer".

[0053] In this specification, a triangle, a rectangle, a trapezoid, a pentagon, or a hexagon is not necessarily a strict one, and can be an approximate triangle, rectangle, trapezoid, pentagon, or hexagon. There can be some small deformation due to a tolerance, a rounded corner, a rounded side, or deformation.

[0054] In this specification, "about" means not strictly limited to a limit, and a value within a range of a process and measurement error is allowed.

[0055] FIG. 1 is a structural schematic diagram of a display device. As shown in FIG. 1, the OLED display device can include a timing controller, a data driver, a scan driver, and a pixel array, the timing controller is connected to the data driver and the scan driver respectively, the data driver is connected to a plurality of data signal lines (D1 to Dn) respectively, and the scan driver is connected to a plurality of scan signal lines (S1 to Sm) respectively. The pixel array can include a plurality of sub-pixels Pxij, each sub-pixel Pxij can be connected to a corresponding data signal line and a corresponding scan signal line, i and j can be natural numbers. At least one sub-pixel Pxij can include at least a circuit unit and a display unit, the circuit unit can include at least a pixel driving circuit, the pixel driving circuit is connected to the scan signal line and the data signal line respectively, and the display unit can include at least a light emitting device, the light emitting device is connected to the pixel driving circuit of the circuit unit, and the sub-pixel Pxij can refer to a sub-pixel whose pixel driving circuit is connected to the i-th scan signal line and connected to the j-th data signal line. In an exemplary embodiment, the timing controller can provide a gray value and a control signal suitable for the specification of the data driver to the data driver, and can provide a clock signal, a scan start signal, etc. suitable for the specification of the scan driver to the scan driver. The data driver can generate data voltages to be provided to the data signal lines 531, D2, D3, …, and Dn by using the gray value and the control signal received from the timing controller. For example, the data driver can sample the gray value by using the clock signal, and apply data voltages corresponding to the gray value to the data signal lines 531 to Dn in units of pixels, n can be a natural number. The scan driver can generate scan signals to be provided to the scan signal lines S1, S2, S3, …, and Sm by receiving the clock signal, the scan start signal, etc. from the timing controller. For example, the scan driver can sequentially provide the scan signal having a turn-on level pulse to the scan signal lines S1 to Sm. For example, the scan driver can be configured in the form of a shift register, and can generate the scan signal in a manner of sequentially transmitting the scan start signal provided in the form of a turn-on level pulse to the next stage circuit under the control of the clock signal, m can be a natural number. In an exemplary embodiment, the pixel array can be disposed on a display substrate.

[0056] The exemplary embodiments of the present disclosure provide a display substrate, comprising a plurality of sub-pixels, at least one of which comprises a pixel driving circuit and a light emitting device; the pixel driving circuit comprises at least a second transistor serving as a driving transistor and a node electrode, the second transistor comprises at least a second active layer, the node electrode is connected with a second region of the second active layer through a node via, and a first region of the second active layer is connected with a first power supply line; the light emitting device comprises at least a first electrode and a pixel definition layer, the first electrode is connected with the node electrode through an anode via, and the pixel definition layer is provided with a pixel opening exposing the first electrode; in at least one of the sub-pixels, a normal projection of the node via on a display substrate plane does not overlap with a normal projection of the pixel opening on the display substrate plane, and the anode via is arranged on a side of the node via away from the pixel opening.

[0057] In the exemplary embodiments, the pixel driving circuit further comprises a shielding electrode and a transparent storage capacitor, the storage capacitor comprises a first plate and a second plate, a normal projection of the first plate on a display substrate plane at least partially overlaps with a normal projection of the second plate on the display substrate plane, a normal projection of the shielding electrode on the display substrate plane at least partially overlaps with a normal projection of the second active layer on the display substrate plane, and the shielding electrode is connected with the first plate; in at least one of the sub-pixels, the node electrode is further connected with the shielding electrode through the node via.

[0058] In the exemplary embodiments, the second transistor further comprises a second gate electrode, and the pixel driving circuit further comprises a first connection electrode; in at least one of the sub-pixels, the first connection electrode is connected with the second plate and the second gate electrode at the same time through a first transfer via.

[0059] In the exemplary embodiments, in at least one of the sub-pixels, a normal projection of the second gate electrode on a display substrate plane at least partially overlaps with a normal projection of the second plate on the display substrate plane.

[0060] In the exemplary embodiments, in at least one of the first transfer vias, a normal projection of the second gate electrode on a display substrate plane at least partially overlaps with a normal projection of the second plate on the display substrate plane.

[0061] In an example embodiment, the plurality of sub-pixels includes a first sub-pixel, a second sub-pixel, a third sub-pixel, and a fourth sub-pixel arranged in sequence along a first direction, the first power supply line is in a shape of a straight line or a broken line extending along a second direction, and is arranged in the first sub-pixel and the fourth sub-pixel, respectively, the first direction and the second direction intersect; the first power supply line in the first sub-pixel is connected to the first region of the second active layer in the first sub-pixel through a power supply via, the first power supply line in the first sub-pixel is connected to the first region of the second active layer in the second sub-pixel through a power supply connection line and a power supply connection electrode, the first power supply line in the fourth sub-pixel is connected to the first region of the second active layer in the third sub-pixel through a power supply connection line and a power supply connection electrode, and the first power supply line in the fourth sub-pixel is connected to the first region of the second active layer in the fourth sub-pixel through a power supply via.

[0062] In an example embodiment, at least one of the sub-pixels further includes a data signal line connected to the pixel driving circuit, the data signal line is in a shape of a broken line extending along the second direction, and includes at least a first sub-line and a second sub-line in a straight line shape, and a third sub-line in an oblique line shape, the third sub-line is arranged between the first sub-line and the second sub-line, and two ends of the third sub-line are connected to the first sub-line and the second sub-line, respectively; in at least one of the first sub-pixel and the fourth sub-pixel, the first sub-line has a first distance from the first power supply line, and the second sub-line has a second distance from the first power supply line, the first distance is greater than the second distance, and the first distance and the second distance are dimensions of the first direction.

[0063] In an example embodiment, at least one of the sub-pixels further includes a compensation signal line connected to the pixel driving circuit, the compensation signal line is arranged between the second sub-pixel and the third sub-pixel; in at least one of the second sub-pixel and the third sub-pixel, the first sub-line has a third distance from the compensation signal line, and the second sub-line has a fourth distance from the compensation signal line, the third distance is less than the fourth distance, and the third distance and the fourth distance are dimensions of the first direction.

[0064] The display substrate of the present disclosure is illustrated below through some example embodiments.

[0065] FIG. 2 is a schematic diagram of a planar structure of a display substrate according to an example embodiment of the present disclosure. As shown in FIG. 2, in an example embodiment, in a direction parallel to the display substrate, the display substrate can include a plurality of repeating units 100, and at least one repeating unit 100 can include a plurality of sub-pixels. In an example embodiment, a repeating unit is a basic unit constituting the display substrate, and the display substrate is constituted by repeating and continuously arranging the repeating units in at least one direction, i.e., the display substrate is formed by splicing a plurality of repeating units.

[0066] In an example embodiment, one repeating unit 100 can include four sub-pixels, and the four sub-pixels can include a first sub-pixel P1 emitting first color light, a second sub-pixel P2 emitting second color light, a third sub-pixel P3 emitting third color light, and a fourth sub-pixel P4 emitting fourth color light. The four sub-pixels can be arranged in a horizontal parallel manner, which can effectively increase the aperture ratio.

[0067] In an example embodiment, in at least one repeating unit 100, the second sub-pixel P2 can be disposed on one side of the first sub-pixel P1 in a first direction X, the third sub-pixel P3 can be disposed on one side of the second sub-pixel P2 in the first direction X, and the fourth sub-pixel P4 can be disposed on one side of the third sub-pixel P3 in the first direction X. In an example embodiment, a plurality of sub-pixels arranged in sequence along the first direction X can be referred to as a pixel row, a plurality of sub-pixels arranged in sequence along a second direction Y can be referred to as a pixel column, and the plurality of pixel rows and the plurality of pixel columns constitute a pixel array arranged in an array. The first direction X and the second direction Y intersect each other.

[0068] In an example embodiment, the first direction X can be a horizontal direction, and the second direction Y can be a vertical direction. The first direction X and the second direction Y are perpendicular to each other.

[0069] In an example embodiment, the first sub-pixel P1 can be a red sub-pixel (R) emitting red light, the second sub-pixel P2 can be a white sub-pixel (W) emitting white light, the third sub-pixel P3 can be a blue sub-pixel (B) emitting blue light, and the fourth sub-pixel P4 can be a green sub-pixel (G) emitting green light. In some possible implementations, the arrangement of RWBG can be adjusted according to actual needs, which is not specifically limited in the present disclosure.

[0070] In an example embodiment, in a direction perpendicular to the display substrate, the display substrate can at least include a driving circuit layer disposed on a base, a light emitting structure layer disposed on a side of the driving circuit layer away from the base. In at least one repeating unit, the driving circuit layer can include a plurality of circuit units, and the circuit units can at least include pixel driving circuits. The pixel driving circuits can be connected with a scan signal line, a data signal line, and the like, respectively. The pixel driving circuits are configured to receive data voltages transmitted by the data signal line under the control of the scan signal line, and output corresponding currents to light emitting devices. The light emitting structure layer can include a plurality of light emitting units, and the light emitting units can at least include light emitting devices. The light emitting devices are connected with the pixel driving circuits of the circuit units of the sub-pixels in which the light emitting devices are located. The light emitting devices are configured to emit light with corresponding brightness in response to the currents output by the pixel driving circuits of the sub-pixels in which the light emitting devices are located.

[0071] In another example embodiment, in a direction perpendicular to the display substrate, the display substrate can at least include a driving circuit layer disposed on a base, a color film structure layer disposed on a side of the driving circuit layer away from the base, and a light emitting structure layer disposed on a side of the color film structure layer away from the base. In at least one repeating unit, the color film structure layer can include a plurality of color film units, and the color film units can at least include color filter layers. The color filter layers are configured to make the corresponding sub-pixels emit light with a required color.

[0072] In an example embodiment, the circuit unit in the present disclosure refers to an area divided according to the pixel driving circuit. The color film unit in the present disclosure refers to an area divided according to the color filter layer. The light emitting unit in the present disclosure refers to an area divided according to the light emitting device. The positions of the orthographic projections of the circuit units on the base, the orthographic projections of the color filter layers on the base, and the orthographic projections of the light emitting units on the base can be corresponding, or can be non-corresponding.

[0073] In an example embodiment of the present disclosure, the positions of the orthographic projections of the circuit units on the base, the orthographic projections of the color film units on the base, and the orthographic projections of the light emitting units on the base are substantially corresponding. The circuit units, the color film units, and the light emitting units constitute sub-pixels. In the following content, the sub-pixels are used to refer to the circuit units, the color film units, and the light emitting units.

[0074] FIG. 3 is an equivalent circuit diagram of the pixel driving circuits in one repeating unit in an example embodiment of the present disclosure. As shown in FIG. 3, at least one repeating unit can include four pixel driving circuits. The four pixel driving circuits can be arranged in a horizontal parallel manner. The pixel driving circuits can be of a 3T1C structure.

[0075] In an example embodiment, the at least one pixel driving circuit can include 3 transistors (a first transistor T1, a second transistor T2, and a third transistor T3) and 1 storage capacitor C, and the pixel driving circuit is connected with a scan signal line 50, a first power supply line 60, a data signal line 70, and a compensation signal line 80, respectively.

[0076] In an example embodiment, the at least one pixel driving circuit can include a first node N1 and a second node N2. The first node N1 is connected with a second electrode of the first transistor T1, a gate electrode of the second transistor T2, and a first terminal of the storage capacitor C, respectively, and the second node N2 is connected with a second electrode of the second transistor T2, a second electrode of the third transistor T3, and a second terminal of the storage capacitor C, respectively.

[0077] In an example embodiment, a first terminal of the storage capacitor C is connected with the first node N1, and a second terminal of the storage capacitor C is connected with the second node N2, and the storage capacitor C is used to store a potential of the gate electrode of the second transistor T2.

[0078] In an example embodiment, the first transistor T1 can be referred to as a data writing transistor, the second transistor T2 can be referred to as a driving transistor, and the third transistor T3 can be referred to as a compensation transistor.

[0079] In an example embodiment, a gate electrode of the first transistor T1 is connected with the scan signal line 50, a first electrode of the first transistor T1 is connected with the data signal line 70, and a second electrode of the first transistor T1 is connected with the first node N1. A gate electrode of the second transistor T2 is connected with the first node N1, a first electrode of the second transistor T2 is connected with the first power supply line 60, and a second electrode of the second transistor T2 is connected with the second node N2. A gate electrode of the third transistor T3 is connected with the scan signal line 50, a first electrode of the third transistor T3 is connected with the compensation signal line 80, and a second electrode of the third transistor T3 is connected with the second node N2.

[0080] In an example embodiment, in the pixel driving circuit of the at least one sub-pixel, the gate electrode of the first transistor T1 and the gate electrode of the third transistor T3 are connected with the same scan signal line 50.

[0081] In an example embodiment, in the plurality of pixel driving circuits of the at least one repeating unit, the gate electrodes of the plurality of first transistors T1 are connected with the same scan signal line 50.

[0082] In an example embodiment, in the plurality of pixel driving circuits of the at least one repeating unit, the gate electrodes of the plurality of third transistors T3 are connected with the same scan signal line 50.

[0083] In an example embodiment, in the plurality of pixel driving circuits of the at least one repeating unit, the gate electrodes of the plurality of first transistors T1 and the gate electrodes of the plurality of third transistors T3 are connected to the same scan signal line 50.

[0084] In an example embodiment, in the plurality of pixel driving circuits of the at least one pixel row, the gate electrodes of the plurality of first transistors T1 and the gate electrodes of the plurality of third transistors T3 are connected to the same scan signal line 50.

[0085] In an example embodiment, the light emitting device EL can be an OLED including a first electrode, an organic light emitting layer, and a second electrode stacked, or can be a QLED including a first electrode, a quantum dot light emitting layer, and a second electrode stacked. The first electrode of the light emitting device EL is connected to the second node N2, and the second electrode of the light emitting device EL is connected to the second power supply line VSS. In an example embodiment, the first electrode can be an anode, and the second electrode can be a cathode; or, the first electrode can be a cathode, and the second electrode can be an anode.

[0086] In an example embodiment, the signal of the first power supply line 60 is a high-level signal continuously provided, and the signal of the second power supply line VSS is a low-level signal continuously provided.

[0087] In an example embodiment, the first transistor T1 to the third transistor T3 can be P-type transistors, or can be N-type transistors. Using the same type of transistors in the pixel driving circuit can simplify the process flow, reduce the process difficulty of the display panel, and improve the yield of the product. In some possible implementation manners, the first transistor T1 to the third transistor T3 can include P-type transistors and N-type transistors.

[0088] In an example embodiment, the first transistor T1 to the third transistor T3 can be low-temperature polysilicon thin film transistors, or can be oxide thin film transistors, or can be low-temperature polysilicon thin film transistors and oxide thin film transistors. The active layer of the low-temperature polysilicon thin film transistor adopts low-temperature polysilicon (LTPS), and the active layer of the oxide thin film transistor adopts oxide semiconductor (Oxide). The low-temperature polysilicon thin film transistor has the advantages of high mobility and fast charging, and the oxide thin film transistor has the advantage of low leakage current. Integrating the low-temperature polysilicon thin film transistor and the oxide thin film transistor on one display substrate, that is, an LTPO display substrate, can take advantage of both, can realize low-frequency driving, can reduce power consumption, and can improve display quality.

[0089] FIG. 4 is a structural schematic diagram of a display substrate according to an example embodiment of the present disclosure, which illustrates a structure of one repeating unit (four sub-pixels) in a bottom emission display substrate, and FIG. 5 is a sectional view along A-A in FIG. 4. As shown in FIG. 4 and FIG. 5, in a direction parallel to the display substrate, at least one repeating unit can include a first sub-pixel P1, a second sub-pixel P2, a third sub-pixel P3 and a fourth sub-pixel P4 arranged in sequence along a first direction X. In an example embodiment, in a direction perpendicular to the display substrate, the display substrate can include at least a driving circuit layer disposed on a substrate and a light-emitting structure layer disposed on a side of the driving circuit layer away from the substrate. The driving circuit layer of at least one sub-pixel can include a pixel driving circuit, and the light-emitting structure layer of at least one sub-pixel can include a light-emitting device, and at least one light-emitting device is connected to the pixel driving circuit of the sub-pixel where the light-emitting device is located.

[0090] In an example embodiment, at least one repeating unit can include one scanning signal line 50, two first power supply lines 60, four data signal lines 70 and one compensation signal line 80, which are all connected to the pixel driving circuit in the four sub-pixels.

[0091] In an example embodiment, a plurality of scanning signal lines 50 in the display substrate can be arranged along a second direction Y, and at least one scanning signal line 50 can extend along a first direction X. In at least one repeating unit, the scanning signal line 50 can have a shape of a straight line or a broken line extending along the first direction X, and the first power supply line 60, the data signal line 70 and the compensation signal line 80 can have a shape of a straight line or a broken line extending along the second direction Y. The two first power supply lines 60 can be respectively disposed on two sides of the repeating unit in the first direction X, the four data signal lines 70 and the one compensation signal line 80 can be disposed between the two first power supply lines 60, two of the four data signal lines 70 can be located between the compensation signal line 80 and one first power supply line 60, and the other two of the four data signal lines 70 can be located between the compensation signal line 80 and the other first power supply line 60.

[0092] In the example embodiment, a first sub-pixel P1 is formed between a first power supply line 60 and a data signal line 70 adjacent to the first direction X, a second sub-pixel P2 is formed between the compensation signal line 80 and the data signal line 70 adjacent to the opposite direction of the first direction X, a third sub-pixel P3 is formed between the compensation signal line 80 and the data signal line 70 adjacent to the first direction X, and a fourth sub-pixel P4 is formed between the other first power supply line 60 and the data signal line 70 adjacent to the opposite direction of the first direction X, that is, the two first power supply lines 60 are respectively arranged in the first sub-pixel P1 and the fourth sub-pixel P4, the compensation signal line 80 is arranged between the second sub-pixel P2 and the third sub-pixel P3, and the four data signal lines 70 are respectively arranged in the first sub-pixel P1 to the fourth sub-pixel P4.

[0093] In the example embodiment, the pixel driving circuit of at least one sub-pixel can include a first transistor T1 as a data writing transistor, a second transistor T2 as a driving transistor, a third transistor T3 as a compensation transistor, and a transparent storage capacitor. The first transistor T1, the second transistor T2, and the third transistor T3 can each include an active layer, a gate electrode, a first electrode, and a second electrode, and the storage capacitor can include a transparent first electrode plate 11 and a transparent second electrode plate 34.

[0094] In the example embodiment, in at least one sub-pixel, the gate electrode of the first transistor T1 and the gate electrode of the third transistor T3 are connected to the scan signal line 50, the first electrode of the first transistor T2 is connected to the data signal line 70, the second electrode of the first transistor T1 is connected to the gate electrode of the second transistor T2 and the second electrode plate 34, respectively, the first electrode of the second transistor T2 is connected to the first power supply line 60, and the second electrode of the second transistor T2 is connected to the first electrode of the third transistor T3 and the first electrode plate 11, respectively, and the first electrode of the third transistor T3 is connected to the compensation signal line 80.

[0095] In the example embodiment, the at least one repeating unit can further include two power supply connection lines 21 extending along the first direction X and two power supply connection electrodes 56 extending along the second direction Y. One power supply connection line 21 can be arranged across the first sub-pixel P1 and the second sub-pixel P2, the other power supply connection line 21 can be arranged across the third sub-pixel P3 and the fourth sub-pixel P4, one power supply connection electrode 56 can be arranged in the second sub-pixel P2, and the other power supply connection electrode 56 can be arranged in the third sub-pixel P3.

[0096] In the example embodiment, the second transistor T2 can at least include the second active layer 32 and the second gate electrode 42. The first power supply line 60 in the first sub-pixel P1 can be connected with the first region of the second active layer through a power supply via DV, and connected with the first end of the power supply connection line 21 through a via. The first end of the power supply connection electrode 56 in the second sub-pixel P2 can be connected with the first region of the second active layer through a power supply via DV, and the second end of the power supply connection electrode 56 can be connected with the second end of the power supply connection line 21 through a via, that is, the first power supply line 60 in the first sub-pixel P1 is connected with the first region of the second active layer in the second sub-pixel P2 through the power supply connection line 21 and the power supply connection electrode 56. The first power supply line 60 in the fourth sub-pixel P4 can be connected with the first region of the second active layer through a power supply via DV, and connected with the first end of the power supply connection line 21 through a via. The first end of the power supply connection electrode 56 in the third sub-pixel P3 is connected with the first region of the second active layer through a power supply via DV, and the second end of the power supply connection electrode 56 is connected with the second end of the power supply connection line 21 through a via, that is, the first power supply line 60 in the fourth sub-pixel P4 is connected with the first region of the second active layer in the third sub-pixel P3 through the power supply connection line 21 and the power supply connection electrode 56. In this way, the first power supply line 60 in the first sub-pixel P1 can provide a power supply signal to the pixel driving circuit in the first sub-pixel P1 and the second sub-pixel P2, and the first power supply line 60 in the fourth sub-pixel P4 can provide a power supply signal to the pixel driving circuit in the third sub-pixel P3 and the fourth sub-pixel P4, forming a one-to-two structure of the first power supply line.

[0097] In the example embodiment, the at least one repeating unit can further include two compensation connection lines 22 extending along the first direction X. One compensation connection line 22 can be arranged across the first sub-pixel P1 and the second sub-pixel P2, and the compensation connection line 22 is connected with the compensation signal line 80 through a compensation connection block 22-1 on one side, and connected with the first electrode of the third transistor T3 in the first sub-pixel P1 and the second sub-pixel P2 on the other side, respectively. The other compensation connection line 22 can be arranged across the third sub-pixel P3 and the fourth sub-pixel P4, and the compensation connection line 22 is connected with the compensation signal line 80 through a compensation connection block 22-1 on one side, and connected with the first electrode of the third transistor T3 in the third sub-pixel P3 and the fourth sub-pixel P4 on the other side, respectively. In this way, one compensation signal line 80 can provide a compensation signal to the pixel driving circuit of the four sub-pixels, forming a one-to-four structure of the compensation signal line.

[0098] In the example embodiment, the at least one sub-pixel can further include a shielding electrode 23, a normal projection of the shielding electrode 23 on the display substrate plane at least partially overlaps with a normal projection of the second active layer 32 on the display substrate plane, and the shielding electrode 23 is connected with the first plate 11 of the storage capacitor.

[0099] In an example embodiment, in the first sub-pixel P1 and the fourth sub-pixel P4, the orthographic projection of the power supply via DV on the display substrate plane does not overlap with the orthographic projection of the shielding electrode 23 on the display substrate plane.

[0100] In an example embodiment, in the second sub-pixel P2 and the third sub-pixel P3, the orthographic projection of the power supply via DV on the display substrate plane at least partially overlaps with the orthographic projection of the shielding electrode 23 on the display substrate plane.

[0101] In an example embodiment, in the second sub-pixel P2 and the third sub-pixel P3, the orthographic projection of the power supply via DV on the display substrate plane can be located within the range of the orthographic projection of the shielding electrode 23 on the display substrate plane.

[0102] In an example embodiment, the at least one sub-pixel can further include a first connection electrode 51, and the first connection electrode 51 can be connected to the second plate 34 and the second gate electrode 42 at the same time through the same first switching via ZV.

[0103] In an example embodiment, in the at least one sub-pixel, the orthographic projection of the second gate electrode 42 on the display substrate plane at least partially overlaps with the orthographic projection of the second plate 34 on the display substrate plane.

[0104] In an example embodiment, in the first switching via ZV, the orthographic projection of the second gate electrode 42 on the display substrate plane at least partially overlaps with the orthographic projection of the second plate 34 on the display substrate plane.

[0105] In an example embodiment, the at least one sub-pixel can further include a second connection electrode 52 as a node electrode, and the second connection electrode 52 can be connected to the second region of the second active layer and the shielding electrode 23 at the same time through the same node via JV.

[0106] In an example embodiment, the light emitting device of the at least one sub-pixel can include at least a first electrode 90 and a pixel definition layer, and the first electrode 90 can be connected to the second connection electrode 52 through an anode via YV. The pixel definition layer can be provided with a pixel opening 90A, and the pixel opening 90A exposes the surface of the first electrode 90.

[0107] In an example embodiment, in the at least one sub-pixel, the node via JV can be located on one side of the pixel opening 90A in the second direction Y, and the orthographic projection of the node via JV on the display substrate plane does not overlap with the orthographic projection of the pixel opening 90A on the display substrate plane.

[0108] In an example embodiment, in the at least one sub-pixel, the anode via YV can be located on one side of the node via JV in the second direction Y, i.e., the anode via YV can be located on the side of the node via JV away from the pixel opening 90A.

[0109] In an example embodiment, in at least one of the sub-pixels, the second connection electrode 52 can include at least a first sub-electrode 52-1 and a second sub-electrode 52-2 connected to each other, the second sub-electrode 52-2 can be located on a side of the first sub-electrode 52-1 away from the pixel opening 90A, the first sub-electrode 52-1 can be connected to the second region of the second active layer and the shielding electrode 23 through the node via JV, and the first electrode 90 can be connected to the second sub-electrode 52-2 through the anode via YV.

[0110] In an example embodiment, in at least one of the sub-pixels, a normal projection of the second sub-electrode 52-2 on the display substrate plane at least partially overlaps a normal projection of the second region of the second active layer on the display substrate plane.

[0111] In an example embodiment, in at least one of the sub-pixels, a normal projection of the anode via YV on the display substrate plane at least partially overlaps a normal projection of the second region of the second active layer on the display substrate plane.

[0112] In an example embodiment, in at least one of the sub-pixels, a normal projection of the transparent storage capacitor on the display substrate plane at least partially overlaps a normal projection of the pixel opening 90A on the display substrate plane, i.e., a normal projection of the first plate 11 on the display substrate plane at least partially overlaps a normal projection of the pixel opening 90A on the display substrate plane, and a normal projection of the second plate 34 on the display substrate plane at least partially overlaps a normal projection of the pixel opening 90A on the display substrate plane.

[0113] In an example embodiment, in at least one of the sub-pixels, the data signal line 70 can include a first sub-line 70-1, a second sub-line 70-2, and a third sub-line 70-3. The first sub-line 70-1 and the second sub-line 70-2 are in the shape of straight lines extending along the second direction Y, and the third sub-line 70-3 is in the shape of a straight line or a broken line extending along an oblique direction. The third sub-line 70-3 can be arranged between the first sub-line 70-1 and the second sub-line 70-2, and the two ends of the third sub-line 70-3 are connected to the first sub-line 70-1 and the second sub-line 70-2, respectively.

[0114] In an example embodiment, in at least one of the first sub-pixel P1 and the fourth sub-pixel P4, the first distance L1 between the first sub-line 70-1 and the first power supply line 60 can be greater than the second distance L2 between the second sub-line 70-2 and the first power supply line 60, and the first distance L1 and the second distance L2 can be the dimension of the first direction X.

[0115] In the exemplary embodiments, in at least one of the second sub-pixel P2 and the third sub-pixel P3, the first sub-line 70-1 can have a third distance L3 from the compensation signal line 80, and the second sub-line 70-2 can have a fourth distance L4 from the compensation signal line 80, the third distance L3 can be less than the fourth distance L4, and the third distance L3 and the fourth distance L4 can be dimensions of the first direction X.

[0116] In the exemplary embodiments, in at least one of the repeating units, the pixel driving circuit in the first sub-pixel P1 and the second sub-pixel P2 can be arranged substantially symmetrically with respect to a repeating unit center line, and the repeating unit center line is a broken line that bisects the repeating unit in the first direction X and extends along the second direction Y.

[0117] In the exemplary embodiments, in at least one of the repeating units, the data signal line 70 in the first sub-pixel P1 and the second sub-pixel P2 can be arranged substantially symmetrically with respect to a repeating unit center line, the positions and shapes of the two first power supply lines 60 can be arranged substantially symmetrically with respect to the repeating unit center line, and a normal projection of the compensation signal line 80 on the display substrate plane at least partially overlaps a normal projection of the repeating unit center line on the display substrate plane.

[0118] In the exemplary embodiments, in a direction perpendicular to the display substrate, the display substrate can at least include: a first transparent conductive layer disposed on the base 200, a first conductive layer disposed on a side of the first transparent conductive layer away from the base 200, a first insulating layer 201 disposed on a side of the first conductive layer away from the base 200, a semiconductor layer disposed on a side of the first insulating layer 201 away from the base 200, a second insulating layer 202 disposed on a side of the semiconductor layer away from the base 200, a second conductive layer disposed on a side of the second insulating layer 202 away from the base 200, a third insulating layer 203 disposed on a side of the second conductive layer away from the base 200, a third conductive layer disposed on a side of the third insulating layer 203 away from the base 200, a fourth insulating layer 204 disposed on a side of the third conductive layer away from the base 200, a planarization layer 205 disposed on a side of the fourth insulating layer 204 away from the base 200, a second transparent conductive layer disposed on a side of the planarization layer 205 away from the base 200, and a pixel definition layer 206 disposed on a side of the second transparent conductive layer away from the base 200.

[0119] In the exemplary embodiment, the first transparent conductive layer can include at least the first electrode plate 11, the first conductive layer can include at least the power supply connection line 21, the compensation connection line 22, the shielding electrode 23, and the interlayer connection electrode 24, the semiconductor layer can include at least the second active layer 32, the third active layer 33, and the second electrode plate 34, the second conductive layer can include at least the second gate electrode 42 and the scan signal line 50, the third conductive layer can include at least the first connection electrode 51, the second connection electrode 52, the fourth connection electrode 54, and the fifth connection electrode 55, and the second transparent conductive layer can include at least the first electrode 90. The pixel definition layer can include at least the pixel opening 90A.

[0120] The preparation process of the display substrate is exemplarily described below. The "patterning process" in the present disclosure includes, for metal materials, inorganic materials, or transparent conductive materials, deposition of a film layer, coating photoresist on the film layer, mask exposure, development, etching, stripping of photoresist, etc., and for organic materials, coating of organic materials, mask exposure, development, etc. The deposition can use any one or more of sputtering, evaporation, chemical vapor deposition, the coating can use any one or more of spraying, spin coating, and inkjet printing, and the etching can use any one or more of dry etching and wet etching, which are not limited in the present disclosure. The "film" refers to a film of a certain material made on a substrate by deposition, coating, or other processes. If the "film" does not need to be patterned during the entire manufacturing process, the "film" can also be referred to as a "layer". If the "film" needs to be patterned during the entire manufacturing process, it is referred to as a "film" before the patterning process and as a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern". The "A and B are disposed in the same layer" in the present disclosure means that A and B are formed at the same time by the same patterning process. The "thickness" of the film layer is the dimension of the film layer in the direction perpendicular to the display substrate. In the exemplary embodiment of the present disclosure, "the orthographic projection of B is within the orthographic projection of A" or "the orthographic projection of A contains the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps the boundary of the orthographic projection of B.

[0121] In the exemplary embodiment, taking an example of a repeating unit including four sub-pixels (the first sub-pixel P1, the second sub-pixel P2, the third sub-pixel P3, and the fourth sub-pixel P4), the preparation process of the display substrate in the exemplary embodiment of the present disclosure can include the following operations.

[0122] (1) forming a first transparent conductive layer pattern. In an exemplary embodiment, forming the first transparent conductive layer pattern can include: depositing a first transparent conductive thin film on the substrate, patterning the first transparent conductive thin film by a patterning process, and forming the first transparent conductive layer pattern on the substrate, as shown in FIG. 6. In an exemplary embodiment, the first transparent conductive layer can be referred to as an ITO1 layer.

[0123] In an exemplary embodiment, the first transparent conductive layer pattern of each sub-pixel in the repeating unit can include at least a first plate 11 for storing a capacitor, a connecting plate 12, and a connecting line 13.

[0124] In an exemplary embodiment, the first plate 11 can have a rectangular shape, the corner of the rectangular shape can be provided with a chamfer or a groove, the edge of the rectangular shape can be a straight line or a broken line, the first plate 11 can be arranged in a middle region of the sub-pixel in the second direction Y, and the first plate 11 is configured to form a transparent plate of a transparent capacitor.

[0125] In an exemplary embodiment, the connecting plate 12 can have a block shape (e.g., a rectangular shape), the connecting plate 12 can be arranged on one side of the first plate 11 in the second direction Y and connected to the first plate 11, and the connecting plate 12 is configured to be connected to a subsequent barrier electrode.

[0126] In an exemplary embodiment, the connecting line 13 can have a strip shape extending along the second direction Y, the connecting line 13 can be arranged on a side of the first plate 11 away from the connecting plate 12 and connected to the first plate 11. The end of the connecting line 13 away from the first plate 11 can be provided with a connecting block 13-1, the connecting block 13-1 can have a strip shape extending along the first direction X and connected to the connecting line 13, and the connecting block 13-1 is configured to be connected to a subsequent interlayer connection electrode.

[0127] In an exemplary embodiment, the first plate 11, the connecting plate 12, and the connecting line 13 of each sub-pixel can be an integrated structure connected to each other.

[0128] In an exemplary embodiment, the first transparent conductive layer in the first sub-pixel P1 and the second sub-pixel P2 and the first transparent conductive layer in the third sub-pixel P3 and the fourth sub-pixel P4 can be arranged substantially symmetrically with respect to the center line of the repeating unit. For example, the positions and shapes of the first plate 11, the connecting plate 12, and the connecting line 13 in the first sub-pixel P1 and the fourth sub-pixel P4 can be arranged substantially symmetrically with respect to the center line of the repeating unit. For another example, the positions and shapes of the first plate 11, the connecting plate 12, and the connecting line 13 in the second sub-pixel P2 and the third sub-pixel P3 can be arranged substantially symmetrically with respect to the center line of the repeating unit.

[0129] (2) forming a first conductive layer pattern. In an exemplary embodiment, forming the first conductive layer pattern can include: depositing a first conductive film on the substrate on which the aforementioned pattern is formed, patterning the first conductive film by a patterning process, and forming the first conductive layer pattern on the first transparent conductive layer, as shown in FIGS. 7A and 7B, which is a plan view of the first conductive layer in FIG. 7A. In an exemplary embodiment, the first conductive layer can be referred to as a shielded metal (SHL) layer.

[0130] In an exemplary embodiment, the first conductive layer pattern of each sub-pixel in the repeating unit can include at least a shield electrode 23 and an interlayer connection electrode 24.

[0131] In an exemplary embodiment, the shield electrode 23 can have a rectangular shape, the corners of the rectangular shape can be provided with chamfers or grooves, the edges of the rectangular shape can be straight lines or broken lines, the shield electrode 23 can be arranged in a middle region of the sub-pixel in the second direction Y, the orthographic projection of the shield electrode 23 on the substrate at least partially overlaps the orthographic projection of the connection plate 12 on the substrate, and the shield electrode 23 directly overlaps the connection plate 12. In an exemplary embodiment, the shield electrode 23 is configured to shield the second transistor T2 to avoid the influence of light on the channel region of the second transistor T2, reduce the leakage current, and thus avoid the influence of light on the characteristics of the second transistor T2, thereby ensuring the electrical performance of the second transistor T2.

[0132] In an exemplary embodiment, the orthographic projection of the shield electrode 23 on the substrate can be located within the range of the orthographic projection of the connection plate 12 on the substrate, or the orthographic projection of the shield electrode 23 on the substrate can contain the orthographic projection of the connection plate 12 on the substrate.

[0133] In an exemplary embodiment, the interlayer connection electrode 24 can have a block shape (such as a rectangular shape), the orthographic projection of the interlayer connection electrode 24 on the substrate at least partially overlaps the orthographic projection of the connection block 13-1 in the connection line 13 on the substrate, and the interlayer connection electrode 24 directly overlaps the connection block 13-1. In an exemplary embodiment, the interlayer connection electrode 24 is configured to be connected to the fourth connection electrode formed subsequently.

[0134] In an exemplary embodiment, the first conductive layer pattern of the repeating unit can further include a power connection line 21 and a compensation connection line 22.

[0135] In an exemplary embodiment, the power connection line 21 can have a shape of a strip extending along the first direction X, and can be disposed on a side of the shielding electrode 23 away from the interlayer connection electrode 24. One power connection line 21 can be disposed across the first sub-pixel P1 and the second sub-pixel P2, and another power connection line 21 can be disposed across the third sub-pixel P3 and the fourth sub-pixel P4. The power connection line 21 can be multiplexed as a power horizontal connection line of a repeating unit, and can provide a power signal to the second transistor T2 of the second sub-pixel P2 and the third sub-pixel P3 by being connected to a first power signal line formed later.

[0136] In an exemplary embodiment, the compensation connection line 22 can have a shape of a strip extending along the first direction X, and can be disposed on a side of the interlayer connection electrode 24 away from the shielding electrode 23. One compensation connection line 22 can be disposed across the first sub-pixel P1 and the second sub-pixel P2, and another compensation connection line 22 can be disposed across the third sub-pixel P3 and the fourth sub-pixel P4. The compensation connection line 22 can be multiplexed as a compensation horizontal connection line of a repeating unit, and can provide a compensation signal to the third transistor T3 of the first sub-pixel P1 to the fourth sub-pixel P4 by being connected to a compensation signal line formed later.

[0137] In an exemplary embodiment, the at least one repeating unit can further include a compensation connection block 22-1. The compensation connection block 22-1 can have a shape of a broken line extending along the first direction X, and can be disposed between two compensation connection lines 22, with both ends of the compensation connection block 22-1 connected to the two compensation connection lines 22, respectively.

[0138] In an exemplary embodiment, in the at least one repeating unit, the compensation connection line 22 in the first sub-pixel P1 and the second sub-pixel P2, the compensation connection block 22-1, and the compensation connection line 22 in the third sub-pixel P3 and the fourth sub-pixel P4 can be an integrated structure connected to each other.

[0139] In an exemplary embodiment, the first conductive layer in the first sub-pixel P1 and the second sub-pixel P2 and the first conductive layer in the third sub-pixel P3 and the fourth sub-pixel P4 can be substantially symmetrically disposed with respect to a repeating unit center line. For example, the positions and shapes of the power connection line 21, the compensation connection line 22, the shielding electrode 23, and the interlayer connection electrode 24 in the first sub-pixel P1 and the fourth sub-pixel P4 can be substantially symmetrically disposed with respect to the repeating unit center line. For another example, the positions and shapes of the power connection line 21, the compensation connection line 22, the shielding electrode 23, and the interlayer connection electrode 24 in the second sub-pixel P2 and the third sub-pixel P3 can be substantially symmetrically disposed with respect to the repeating unit center line.

[0140] (3) Forming a semiconductor layer pattern. In an exemplary embodiment, forming a semiconductor layer pattern can include: sequentially depositing a first insulating thin film and a semiconductor thin film on a substrate on which the aforementioned pattern is formed, patterning the semiconductor thin film by a patterning process, forming a first insulating layer covering the first conductive layer, and forming a semiconductor layer pattern on the first insulating layer, as shown in FIGS. 8A and 8B, which is a plan view of the semiconductor layer in FIG. 8A.

[0141] In an exemplary embodiment, the semiconductor layer pattern of each sub-pixel in the repeating unit can include at least a first active layer 31, a second active layer 32, a third active layer 33, and a second plate 34.

[0142] In an exemplary embodiment, the second plate 34 can have a rectangular shape, the corners of the rectangular shape can be provided with a chamfer or a groove, the edges of the rectangular shape can be straight lines or broken lines, the orthographic projection of the second plate 34 on the substrate at least partially overlaps the orthographic projection of the first plate 11 on the substrate, the second plate 34 is configured to form another transparent plate of a transparent storage capacitor, and the first plate 11 and the second plate 34 constitute the transparent storage capacitor.

[0143] In an exemplary embodiment, the first active layer 31 can serve as an active layer of a first transistor T1, the second active layer 32 can serve as an active layer of a second transistor T2, and the third active layer 33 can serve as an active layer of a third transistor T3. The first active layer 31 and the third active layer 33 can be disposed on a side of the second plate 34 away from the power supply connection line 21, and the second active layer 32 can be disposed on a side of the second plate 34 close to the power supply connection line 21.

[0144] In an exemplary embodiment, the first active layer 31, the second active layer 32, and the third active layer 33 can each include a channel region and first and second regions located on both sides of the channel region.

[0145] In an exemplary embodiment, the first active layer 31 can have an "I" shape, the first region 31-1 of the first active layer can be located on a side of the channel region of the first active layer away from the second plate 34, and the second region 31-2 of the first active layer can be located on a side of the channel region of the first active layer close to the second plate 34.

[0146] In an exemplary embodiment, the first active layer 31 can be provided with a plate connection strip 31-1. The plate connection strip 31-1 can have a strip shape extending along the second direction Y and can be disposed between the first active layer 31 and the second plate 34. The first end of the plate connection strip 31-1 is connected to the second region 31-2 of the first active layer, and the second end of the plate connection strip 31-1 is connected to the second plate 34.

[0147] In an example embodiment, the first active layer 31, the plate connecting strip 31-1 and the second plate 34 can be an integrated structure connected to each other.

[0148] In an example embodiment, the second active layer 32 can be in an "L" shape, and a normal projection of the second active layer 32 on the substrate at least partially overlaps with a normal projection of the shielding electrode 23 on the substrate. In the first and second sub-pixels P1 and P2, the first region 32-1 of the second active layer can be located on a side opposite to the first direction X of the channel region of the second active layer, and the second region 32-2 of the second active layer can be located on a side of the first direction X of the channel region of the second active layer. In the third and fourth sub-pixels P3 and P4, the first region 32-1 of the second active layer can be located on a side of the first direction X of the channel region of the second active layer, and the second region 32-2 of the second active layer can be located on a side opposite to the first direction X of the channel region of the second active layer.

[0149] In an example embodiment, a normal projection of the channel region of the second active layer and the second region 32-2 of the second active layer on the substrate can be located within a range of a normal projection of the shielding electrode 23 on the substrate, and the shielding electrode 23 can shield the channel region of the second active layer to avoid the influence of light on the channel and reduce the leakage current, thereby avoiding the influence of light on the characteristics of the transistor.

[0150] In an example embodiment, in the first and fourth sub-pixels P1 and P4, a normal projection of the first region 32-1 of the second active layer on the substrate does not overlap with a normal projection of the shielding electrode 23 on the substrate, and in the second and third sub-pixels P2 and P3, a normal projection of the first region 32-1 of the second active layer on the substrate can be located within a range of a normal projection of the shielding electrode 23 on the substrate.

[0151] In an example embodiment, the third active layer 33 can be in an "I" shape, and a normal projection of the third active layer 33 on the substrate is spaced apart from a normal projection of the second plate 34 on the substrate, i.e., there is no overlapping region between the third active layer 33 and the second plate 42, which is beneficial for designing the channel width-length ratio of the third transistor according to relevant requirements. The first region 33-1 of the third active layer can be located on a side of the channel region of the third active layer away from the second plate 34, and a normal projection of the first region 33-1 of the third active layer on the substrate at least partially overlaps with a normal projection of the compensation connecting line 22 on the substrate. The second region 33-2 of the third active layer can be located on a side of the channel region of the third active layer close to the second plate 34, and a normal projection of the second region 33-2 of the third active layer on the substrate at least partially overlaps with a normal projection of the interlayer connecting electrode 24 on the substrate.

[0152] In an exemplary embodiment, the semiconductor layer can employ a metal oxide, such as an oxide containing indium and tin, an oxide containing tungsten and indium, an oxide containing tungsten and indium and zinc, an oxide containing titanium and indium, an oxide containing titanium and indium and tin, an oxide containing indium and zinc, an oxide containing silicon and indium and tin, an oxide containing indium and gallium and zinc, and the like. The semiconductor layer can be a single layer, or can be a double layer, or can be a multi-layer.

[0153] In an exemplary embodiment, the semiconductor layer in the first sub-pixel P1 and the second sub-pixel P2 can be arranged substantially symmetrically with respect to the repeating unit center line, and the semiconductor layer in the third sub-pixel P3 and the fourth sub-pixel P4. For example, the positions and shapes of the first active layer 31, the second active layer 32, the third active layer 33, and the second plate 34 in the first sub-pixel P1 and the fourth sub-pixel P4 can be arranged substantially symmetrically with respect to the repeating unit center line. For another example, the positions and shapes of the first active layer 31, the second active layer 32, the third active layer 33, and the second plate 34 in the second sub-pixel P2 and the third sub-pixel P3 can be arranged substantially symmetrically with respect to the repeating unit center line.

[0154] (4) Forming a second conductive layer pattern. In an exemplary embodiment, forming the second conductive layer pattern can include: on the substrate on which the aforementioned patterns are formed, sequentially depositing a second insulating thin film and a second conductive thin film, patterning the second conductive thin film and the second insulating thin film by a patterning process, forming a second insulating layer disposed on the semiconductor layer, and a second conductive layer pattern disposed on the second insulating layer, as shown in FIGS. 9A and 9B, FIG. 9B is a plan view of the second conductive layer in FIG. 9A. In an exemplary embodiment, the second conductive layer can be referred to as a gate metal (GATE) layer.

[0155] In an exemplary embodiment, the second conductive layer pattern of each sub-pixel in the repeating unit can include at least a second gate electrode 42 and a scan signal line 50.

[0156] In an exemplary embodiment, the shape of the scan signal line 50 can be a strip shape extending along the first direction X, and the scan signal line 50 can be located between the compensation connection line 22 and the second plate 34. The orthographic projection of the scan signal line 50 on the substrate at least partially overlaps the orthographic projection of the first active layer 31 in each sub-pixel on the substrate, and the scan signal line 50 in the overlapping area can serve as the gate electrode of the first transistor T1. The orthographic projection of the scan signal line 50 on the substrate at least partially overlaps the orthographic projection of the third active layer 33 in each sub-pixel on the substrate, and the scan signal line 50 in the overlapping area can serve as the gate electrode of the third transistor T3.

[0157] In an example embodiment, the scan signal line 50 can be provided with a non-uniform width, the width being a dimension of the scan signal line 50 in the second direction Y. The scan signal line 50 can include a first region overlapping the first active layer 31 and the third active layer 33, and a second region not overlapping the first active layer 31 and the third active layer 33, the width of the first region can be smaller than the width of the second region.

[0158] In an example embodiment, in the second region of the scan signal line 50, a plurality of through holes 50-1 can be provided on the scan signal line 50, the through holes 50-1 can be provided in a strip shape extending along the first direction X, a projection of the through holes 50-1 on the substrate at least partially overlaps a projection of a subsequently formed first power supply line, data signal line, or compensation signal line on the substrate, the through holes 50-1 are configured to reduce parasitic capacitance between the scan signal line 50 and the first power supply line, data signal line, or compensation signal line.

[0159] In an example embodiment, in at least one sub-pixel, one scan signal line 50 can simultaneously serve as a gate electrode of the first transistor T1 and a gate electrode of the third transistor T3.

[0160] In an example embodiment, in a plurality of sub-pixels of at least one repeating unit, gate electrodes of four first transistors T1 are connected to the same scan signal line 50, one scan signal line 50 can simultaneously serve as gate electrodes of the four first transistors T1, the scan signal line 50 is configured to simultaneously control the on or off of all the first transistors T1 in the four sub-pixels of the repeating unit.

[0161] In an example embodiment, in a plurality of sub-pixels of at least one repeating unit, gate electrodes of four third transistors T3 are connected to the same scan signal line 50, one scan signal line 50 can simultaneously serve as gate electrodes of the four third transistors T3, the scan signal line 50 is configured to simultaneously control the on or off of all the third transistors T3 in the four sub-pixels of the repeating unit.

[0162] In an example embodiment, in a plurality of sub-pixels of at least one repeating unit, gate electrodes of four first transistors T1 and gate electrodes of four third transistors T3 are connected to the same scan signal line 50, one scan signal line 50 can simultaneously serve as gate electrodes of the four first transistors T1 and gate electrodes of the four third transistors T3, the scan signal line 50 is configured to simultaneously control the on or off of all the first transistors T1 and all the third transistors T3 in the four sub-pixels of the repeating unit.

[0163] In an example embodiment, in a plurality of sub-pixels of at least one pixel row, one scan signal line 50 can simultaneously serve as gate electrodes of a plurality of first transistors T1 and gate electrodes of a plurality of third transistors T3.

[0164] In an example embodiment, the second gate electrode 42 can have a strip shape extending along the second direction Y, and the second gate electrode 42 can serve as a gate electrode of the second transistor T2. In one aspect, a projection of the second gate electrode 42 on the substrate at least partially overlaps with a projection of the second active layer 32 on the substrate, and the second active layer 32 in the overlapping region is a channel region of the second active layer. In another aspect, a projection of the second gate electrode 42 on the substrate at least partially overlaps with a projection of the second plate 34 on the substrate.

[0165] In an example embodiment, the second conductive layer in the first sub-pixel P1 and the second sub-pixel P2 and the second conductive layer in the third sub-pixel P3 and the fourth sub-pixel P4 can be substantially symmetrically arranged with respect to the repeating unit center line. For example, the positions and shapes of the second gate electrode 42 and the scan signal line 50 in the first sub-pixel P1 and the fourth sub-pixel P4 can be substantially symmetrically arranged with respect to the repeating unit center line. For another example, the positions and shapes of the second gate electrode 42 and the scan signal line 50 in the second sub-pixel P2 and the third sub-pixel P3 can be substantially symmetrically arranged with respect to the repeating unit center line.

[0166] In an example embodiment, the second insulating layer pattern and the second conductive layer pattern formed in the present process can be substantially the same, i.e., a projection of the second insulating layer on the substrate and a projection of the second conductive layer on the substrate can be substantially the same.

[0167] In an example embodiment, the present process further includes a conductorization process. The conductorization process is a plasma treatment using the second conductive layer as a shield after the formation of the second conductive layer pattern. The semiconductor layer shielded by the second conductive layer serves as a channel region of the transistor, and the semiconductor layer not shielded by the second conductive layer is processed into a conductorized layer, forming a conductorized second plate and conductorized first and second regions.

[0168] (5) Forming a third insulating layer pattern. In an example embodiment, forming the third insulating layer pattern can include: depositing a third insulating thin film on the substrate on which the aforementioned patterns are formed, and patterning the third insulating thin film using a patterning process to form a third insulating layer covering the second conductive layer, the third insulating layer being provided with a plurality of vias, as shown in FIG. 10.

[0169] In an example embodiment, the plurality of vias of each sub-pixel in the repeating unit at least includes: a first via V1, a second via V2, a third via V3, a fourth via V4, a fifth via V5, a sixth via V6, and a seventh via V7.

[0170] In an example embodiment, the orthographic projection of the first via V1 on the substrate can be within the orthographic projection of the first region of the first active layer on the substrate, the third insulating layer and the second insulating layer within the first via V1 are etched away, exposing the surface of the first region of the first active layer, and the first via V1 is configured to enable a data signal line formed subsequently to connect with the first region of the first active layer through the via.

[0171] In an example embodiment, the orthographic projection of the second via V2 on the substrate can be within the orthographic projection of the second region of the first active layer on the substrate, the third insulating layer and the second insulating layer within the second via V2 are etched away, exposing the surface of the second region of the first active layer, and the second via V2 is configured to enable a third connection electrode formed subsequently to connect with the second region of the first active layer through the via.

[0172] In an example embodiment, the orthographic projection of the third via V3 on the substrate can be within the orthographic projection of the first region of the second active layer on the substrate, the third insulating layer and the second insulating layer within the third via V3 are etched away, exposing the surface of the first region of the second active layer, and the third via V3 is configured to enable a first power supply line or a power supply connection electrode formed subsequently to connect with the first region of the second active layer through the via. In an example embodiment, the third via V3 can serve as a power supply via of the present disclosure.

[0173] In an example embodiment, in the first sub-pixel P1 and the fourth sub-pixel P4, the orthographic projection of the third via V3 on the substrate does not overlap with the orthographic projection of the shielding electrode 23 on the substrate.

[0174] In an example embodiment, in the second sub-pixel P2 and the third sub-pixel P3, the orthographic projection of the third via V3 on the substrate at least partially overlaps with the orthographic projection of the shielding electrode 23 on the substrate.

[0175] In an example embodiment, in the second sub-pixel P2 and the third sub-pixel P3, the orthographic projection of the third via V3 on the substrate can be within the orthographic projection of the shielding electrode 23 on the substrate.

[0176] In the example embodiment, the fourth via V4 can be located on one side of the second direction Y of the second plate 34, and the orthographic projection of the fourth via V4 on the substrate at least partially overlaps with the orthographic projection of the second region of the second active layer and the shielding electrode 23 on the substrate. The fourth via V4 is a transfer via, which is composed of two half-holes, one of which is formed on the second region of the second active layer, and the third insulating layer and the second insulating layer in the half-hole are etched away to expose the surface of the second region of the second active layer, and the other half-hole is formed on the shielding electrode 23, and the third insulating layer, the second insulating layer and the first insulating layer in the half-hole are etched away to expose the surface of the shielding electrode 23, so that the transfer via composed of the two half-holes simultaneously exposes the surfaces of the second region of the second active layer and the shielding electrode 23. In the example embodiment, the fourth via V4 is configured to enable the second connecting electrode formed subsequently to pass through the via and connect with the second region of the second active layer and the shielding electrode 23, and the fourth via V4 can serve as a node via of the present disclosure.

[0177] In the example embodiment, the fifth via V5 at least partially overlaps with the orthographic projection of the first region of the third active layer and the compensation connection line 22 on the substrate. The fifth via V5 is a transfer via, which is composed of two half-holes, one of which is formed on the first region of the third active layer, and the third insulating layer and the second insulating layer in the half-hole are etched away to expose the surface of the first region of the third active layer, and the other half-hole is formed on the compensation connection line 22, and the third insulating layer, the second insulating layer and the first insulating layer in the half-hole are etched away to expose the surface of the compensation connection line 22, so that the transfer via composed of the two half-holes simultaneously exposes the surfaces of the first region of the third active layer and the compensation connection line 22. In the example embodiment, the fifth via V5 is configured to enable the fifth connecting electrode formed subsequently to pass through the via and connect with the first region of the third active layer and the compensation connection line 22.

[0178] In the example embodiment, the sixth via V6 at least partially overlaps with the orthographic projection of the second region of the third active layer and the interlayer connection electrode 24 on the substrate. The sixth via V6 is a transfer via, which is composed of two half-holes, one of which is formed on the second region of the third active layer, and the third insulating layer and the second insulating layer in the half-hole are etched away to expose the surface of the second region of the third active layer, and the other half-hole is formed on the interlayer connection electrode 24, and the third insulating layer, the second insulating layer and the first insulating layer in the half-hole are etched away to expose the surface of the interlayer connection electrode 24, so that the transfer via composed of the two half-holes simultaneously exposes the surfaces of the second region of the third active layer and the interlayer connection electrode 24. In the example embodiment, the sixth via V6 is configured to enable the fourth connecting electrode formed subsequently to pass through the via and connect with the second region of the third active layer and the interlayer connection electrode 24.

[0179] In the example embodiment, the normal projection of the seventh via V7 on the substrate at least partially overlaps with the normal projection of the second plate 34 and the second gate electrode 42 on the substrate. The seventh via V7 is a transfer via, which is composed of two half holes, one of which is formed on the second plate 34, and the third insulating layer and the second insulating layer in the half hole are etched to expose the surface of the second plate 34, and the other of which is formed on the second gate electrode 42, and the third insulating layer in the half hole is etched to expose the surface of the second gate electrode 42, so that the two half holes composed of the transfer via expose the surfaces of the second plate 34 and the second gate electrode 42 at the same time. In the example embodiment, the seventh via V7 is configured to enable the first connection electrode formed subsequently to connect with the second plate 34 and the second gate electrode 42 through the via, and the seventh via V7 can serve as the first transfer via of the present disclosure.

[0180] In the example embodiment, in the seventh via V7, the normal projection of the second gate electrode 42 on the substrate at least partially overlaps with the normal projection of the second plate 34 on the substrate. Research shows that if the second plate 34 and the second gate electrode 42 in the seventh via V7 do not overlap, over-etching is likely to occur during the dry etching process of the via, which will cause the shielding electrode 23 to be exposed, so that the first connection electrode formed subsequently is connected with the shielding electrode 23, thereby causing a short circuit and dark spot defects. By overlapping the second plate 34 and the second gate electrode 42 in the first transfer via, the present disclosure can effectively avoid short circuit and dark spot defects.

[0181] In the example embodiment, the repeating unit can further include an eighth via V8, a ninth via V9, and a tenth via V10.

[0182] In the example embodiment, the eighth via V8 can be arranged in the first sub-pixel P1 and the fourth sub-pixel P4, and the normal projection of the eighth via V8 on the substrate is located within the normal projection of the first end of the power connection line 21 on the substrate. The third insulating layer, the second insulating layer, and the first insulating layer in the eighth via V8 are etched to expose the surface of the first end of the power connection line 21, and the eighth via V8 is configured to enable the first power line formed subsequently to connect with the first end of the power connection line 21 through the via.

[0183] In the example embodiment, the ninth via V9 can be arranged in the second sub-pixel P2 and the third sub-pixel P3, and the normal projection of the ninth via V9 on the substrate is located within the normal projection of the second end of the power connection line 21 on the substrate. The third insulating layer, the second insulating layer, and the first insulating layer in the ninth via V9 are etched to expose the surface of the second end of the power connection line 21, and the ninth via V9 is configured to enable the power connection electrode formed subsequently to connect with the second end of the power connection line 21 through the via.

[0184] In the example embodiment, the tenth via V10 can be disposed between the second sub-pixel P2 and the third sub-pixel P3, the orthogonal projection of the tenth via V10 on the substrate is within the range of the orthogonal projection of the compensation connection block 22-1 on the substrate, the third insulating layer, the second insulating layer and the first insulating layer in the tenth via V10 are etched away to expose the surface of the compensation connection block 22-1, and the tenth via V10 is configured to enable the compensation signal line formed subsequently to be connected to the compensation connection block 22-1 through the via.

[0185] (6) Forming a third conductive layer pattern. In the example embodiment, forming the third conductive layer can include: on the substrate on which the aforementioned pattern is formed, depositing a third conductive thin film, and patterning the third conductive thin film by using a patterning process to form a third conductive layer disposed on the third insulating layer, as shown in FIGS. 11A and 11B, FIG. 11B is a plan view of the third conductive layer in FIG. 11A. In the example embodiment, the third conductive layer can be referred to as a source-drain metal (SD) layer.

[0186] In the example embodiment, the third conductive layer pattern of each sub-pixel in the repeating unit at least includes: a first connection electrode 51, a second connection electrode 52, a third connection electrode 53, a fourth connection electrode 54, and a fifth connection electrode 55.

[0187] In the example embodiment, the shape of the first connection electrode 51 can be a strip shape extending along the second direction Y, and the first connection electrode 51 is connected to the second gate electrode 42 and the second plate 34 through the seventh via V7 at the same time, so that the gate electrode of the second transistor T2 and the second plate 34 of the storage capacitor have the same potential. Since the second gate electrode 42 in the seventh via V7 overlaps the second plate 34, the seventh via V7 will not be over-etched to expose the shielding electrode 23, thereby effectively avoiding short circuit between the second gate electrode 42 and the second plate 34 and the shielding electrode 23, and dark spot defects can be effectively avoided.

[0188] In the example embodiment, the shape of the second connection electrode 52 can be a strip shape extending along the second direction Y, and the second connection electrode 52 is connected to the second region of the second active layer and the shielding electrode 23 through the fourth via V4 at the same time. Since the shielding electrode 23 is overlapped with the connection plate 12, and the connection plate 12 is connected to the first plate 11, the second connection electrode 52 realizes that the second electrode of the second transistor T2 and the first plate 11 of the storage capacitor have the same potential. In the example embodiment, the second connection electrode 52 can serve as a node electrode of the present disclosure.

[0189] In the example embodiment, the second connection electrode 52 includes a first sub-electrode 52-1 and a second sub-electrode 52-2. The first sub-electrode 52-1 and the second sub-electrode 52-2 can have a block shape (e.g., a rectangular shape), and the second sub-electrode 52-2 can be disposed on a side of the first sub-electrode 52-1 away from the second plate 34 and connected to the first sub-electrode 52-1. The first sub-electrode 52-1 is connected to the second region of the second active layer and the shield electrode 23 through the fourth via V4, and the second sub-electrode 52-2 is configured to be connected to the first electrode formed later.

[0190] In the example embodiment, the third connection electrode 53 can have a block shape (e.g., a rectangular shape), and the third connection electrode 53 is connected to the second region of the first active layer through the second via V2. Since the second region of the first active layer is connected to the second plate 34 through the plate connection strip 31-1, the third connection electrode 53 achieves the same potential of the second electrode of the first transistor T1 and the second plate 34 of the storage capacitor.

[0191] In the example embodiment, since the first connection electrode 51 achieves the same potential of the gate electrode of the second transistor T2 and the second plate 34 of the storage capacitor, and the third connection electrode 53 achieves the same potential of the second electrode of the first transistor T1 and the second plate 34 of the storage capacitor, the first connection electrode 51 and the third connection electrode 53 achieve the same potential of the second electrode of the first transistor T1, the gate electrode of the second transistor T2, and the second plate 34 of the storage capacitor, i.e., the potential of the first node N1 in the pixel driving circuit.

[0192] In the example embodiment, the fourth connection electrode 54 can have a strip shape extending along the second direction Y, and the fourth connection electrode 54 is connected to the second region of the third active layer and the interlayer connection electrode 24 through the sixth via V6. Since the interlayer connection electrode 24 is connected to the connection line 13, and the connection line 13 is connected to the first plate 11, the fourth connection electrode 54 achieves the same potential of the second electrode of the third transistor T3 and the first plate 11 of the storage capacitor.

[0193] In the example embodiment, since the second connection electrode 52 achieves the same potential of the second electrode of the second transistor T2 and the first plate 11 of the storage capacitor, and the fourth connection electrode 54 achieves the same potential of the second electrode of the third transistor T3 and the first plate 11 of the storage capacitor, the second connection electrode 52 and the fourth connection electrode 54 achieve the same potential of the second electrode of the second transistor T2, the second electrode of the third transistor T3, and the first plate 11 of the storage capacitor, i.e., the potential of the second node N2 in the pixel driving circuit.

[0194] In the example embodiment, the fifth connection electrode 55 can have a strip shape extending along the second direction Y, and the fifth connection electrode 55 is connected to the first region of the third active layer and the compensation connection line 22 through the fifth via V5. Since the compensation connection line 22 is configured to be connected to the compensation signal line, the fifth connection electrode 55 realizes that the compensation signal line writes the compensation signal to the first electrode of the third transistor T3 of each sub-pixel.

[0195] In the example embodiment, the third conductive layer pattern of the repeating unit can further include a power connection electrode 56, a first power line 60, and a compensation signal line 80.

[0196] In the example embodiment, the first power line 60 can have a straight line shape or a polyline shape with a main body portion extending along the second direction Y, and can be respectively arranged on a side of the first sub-pixel P1 away from the second sub-pixel P2 and a side of the fourth sub-pixel P4 away from the third sub-pixel P3. On the one hand, the first power line 60 is connected to the first region of the second active layer through the third via V3 (power via), realizing that the first power line 60 writes the first power signal to the first electrode of the second transistor T2 in the first sub-pixel P1 and the fourth sub-pixel P4. On the other hand, the first power line 60 is connected to the first end of the power connection line 21 through the eighth via V8, realizing that the first power line 60 located in the first sub-pixel P1 transmits the power signal to the second sub-pixel P2 through the power connection line 21, and realizing that the first power line 60 located in the fourth sub-pixel P4 can transmit the power signal to the third sub-pixel P3 through the power connection line 21.

[0197] In the example embodiment, the first power line 60 can be a non-equal-width straight line or a polyline, which not only facilitates the layout of the pixel structure, but also reduces the parasitic capacitance.

[0198] In the example embodiment, the power connection electrode 56 can have a strip shape extending along the second direction Y, and can be respectively arranged in the second sub-pixel P2 and the third sub-pixel P3. The first end of the power connection electrode 56 is connected to the first region of the second active layer through the third via V3 (power via), and the second end of the power connection electrode 56 is connected to the second end of the power connection line 21 through the ninth via V9. Since the first end of the power connection line 21 is connected to the first power line 60, the first power line 60 realizes that the first power signal is written to the first electrode of the second transistor T2 in the second sub-pixel P2 and the third sub-pixel P3.

[0199] In the example embodiment, the first power supply line 60 in the first sub-pixel P1 can be connected with the first area of the second active layer through the third via hole V3, and connected with the first end of the power supply connection line 21 through the eighth via hole V8. The first end of the power supply connection electrode 56 in the second sub-pixel P2 can be connected with the first area of the second active layer through the third via hole V3, and the second end of the power supply connection electrode 56 can be connected with the second end of the power supply connection line 21 through the ninth via hole V9, that is, the first power supply line 60 in the first sub-pixel P1 is connected with the first area of the second active layer in the second sub-pixel P2 through the power supply connection line 21 and the power supply connection electrode 56. The first power supply line 60 in the fourth sub-pixel P4 can be connected with the first area of the second active layer through the third via hole V3, and connected with the first end of the power supply connection line 21 through the eighth via hole V8. The first end of the power supply connection electrode 56 in the third sub-pixel P3 is connected with the first area of the second active layer through the third via hole V3, and the second end of the power supply connection electrode 56 is connected with the second end of the power supply connection line 21 through the ninth via hole V9, that is, the first power supply line 60 in the fourth sub-pixel P4 is connected with the first area of the second active layer in the third sub-pixel P3 through the power supply connection line 21 and the power supply connection electrode 56. In this way, the first power supply line 60 in the first sub-pixel P1 can provide a power supply signal to the pixel driving circuit in the first sub-pixel P1 and the second sub-pixel P2, and the first power supply line 60 in the fourth sub-pixel P4 can provide a power supply signal to the pixel driving circuit in the third sub-pixel P3 and the fourth sub-pixel P4. The present disclosure realizes writing the power supply signal into the second transistor T2 in the four sub-pixels respectively by arranging two power supply connection lines 21 extending along the first direction X and two first power supply lines 60 extending along the second direction Y in the repeating unit, and forms a one-to-two structure of the first power supply line.

[0200] In the example embodiment, the shape of the compensation signal line 80 can be a straight line or a broken line extending along the second direction Y, and the compensation signal line 80 can be arranged between the second sub-pixel P2 and the third sub-pixel P3 and connected with the compensation connection block 22-1 through the tenth via hole V10. Since the compensation connection block 22-1 is connected with the compensation connection line 22 in the first sub-pixel P1 and the second sub-pixel P2 on one hand, and connected with the compensation connection line 22 in the third sub-pixel P3 and the fourth sub-pixel P4 on the other hand, one compensation connection line 22 is connected with the first electrode of the third transistor T3 in the first sub-pixel P1 and the second sub-pixel P2 through the fifth connection electrode 55, and the other compensation connection line 22 is connected with the first electrode of the third transistor T3 in the third sub-pixel P3 and the fourth sub-pixel P4 through the fifth connection electrode 55. In this way, one compensation signal line 80 can provide a compensation signal to the pixel driving circuit in the four sub-pixels, and forms a one-to-four structure of the compensation signal line.

[0201] The present disclosure realizes that the compensation signal is written into the four sub-pixels by the third transistor T3 through the one compensation signal line 80 extending along the second direction Y and the two compensation connection lines 22 extending along the first direction X in the repeating unit, can ensure that the RC delay of the compensation signal before being written into the transistor is basically the same, and ensures the display uniformity.

[0202] In an example embodiment, the third conductive layer pattern of each sub-pixel in the repeating unit can further include a data signal line 70.

[0203] In an example embodiment, the shape of the data signal line 70 can be a polyline shape with a main body part extending along the second direction Y, and the data signal line 70 is connected with the first area of the first active layer through the first via V1, realizing that the data signal line 70 writes the data signal into the first electrode of the first transistor T1.

[0204] In an example embodiment, in the first sub-pixel P1 and the third sub-pixel P3, the data signal line 70 can be arranged on one side of the first direction X of the storage capacitor (the first electrode plate 11 and the second electrode plate 34). In the second sub-pixel P2 and the fourth sub-pixel P4, the data signal line 70 can be arranged on the side opposite to the first direction X of the storage capacitor.

[0205] In an example embodiment, in at least one sub-pixel, the data signal line 70 can include a first sub-line 70-1, a second sub-line 70-2, and a third sub-line 70-3. The shape of the first sub-line 70-1 and the second sub-line 70-2 is a straight line shape extending along the second direction Y, and the shape of the third sub-line 70-3 is a straight line shape or a polyline shape extending along an oblique direction. The third sub-line 70-3 can be arranged between the first sub-line 70-1 and the second sub-line 70-2, the first end of the third sub-line 70-3 is connected with the first sub-line 70-1, and the second end of the third sub-line 70-3 is connected with the second sub-line 70-2.

[0206] In an example embodiment, in at least one of the first sub-pixel P1 and the fourth sub-pixel P4, the first distance L1 between the first sub-line 70-1 and the first power supply line 60 can be greater than the second distance L2 between the second sub-line 70-2 and the first power supply line 60. The first distance L1 can be the distance between the edge of the first sub-line 70-1 close to the first power supply line 60 and the edge of the first power supply line 60 close to the first sub-line 70-1, which is the size of the first direction X. The second distance L2 can be the distance between the edge of the second sub-line 70-2 close to the first power supply line 60 and the edge of the first power supply line 60 close to the second sub-line 70-2, which is the size of the first direction X.

[0207] In the exemplary embodiments, the first sub-line 70-1 and the compensation signal line 80 can have a third distance L3, and the second sub-line 70-2 and the compensation signal line 80 can have a fourth distance L4 in at least one of the second sub-pixel P2 and the third sub-pixel P3, and the third distance L3 can be less than the fourth distance L4. The third distance L3 can be a distance between an edge of the first sub-line 70-1 close to the compensation signal line 80 and an edge of the compensation signal line 80 close to the first sub-line 70-1, and is a dimension in the first direction X. The fourth distance L4 can be a distance between an edge of the second sub-line 70-2 close to the compensation signal line 80 and an edge of the compensation signal line 80 close to the second sub-line 70-2, and is a dimension in the first direction X.

[0208] In the exemplary embodiments, the first distance L1 can be equal to the third distance L3.

[0209] In the exemplary embodiments, the first sub-pixel P1 and the fourth sub-pixel P4 are directly connected to the first power line 60 at the first region of the second active layer, and the second sub-pixel P2 and the third sub-pixel P3 are connected to the first power line 60 through the power connection line 21 and the power connection electrode 56, so that the layout space requirement of the second sub-pixel P2 and the third sub-pixel P3 is larger than that of the first sub-pixel P1 and the fourth sub-pixel P4. The present disclosure can effectively increase the area of the second sub-pixel P2 and the third sub-pixel P3 by arranging the data signal line 70 in the shape of a broken line and bending the broken line part away from the compensation signal line 80, so as to meet the layout space requirement of the second sub-pixel P2 and the third sub-pixel P3, and facilitate high-resolution display.

[0210] In the exemplary embodiments, the data signal line 70 can be a broken line with equal width or non-equal width, which can not only facilitate the layout of the pixel structure, but also reduce the parasitic capacitance.

[0211] In the exemplary embodiments, the third conductive layer in the first sub-pixel P1 and the second sub-pixel P2 and the third conductive layer in the third sub-pixel P3 and the fourth sub-pixel P4 can be arranged substantially symmetrically with respect to the repeat unit center line. For example, the positions and shapes of the first to fifth connection electrodes 51-55, the power connection electrode 56, the first power line 60, the data signal line 70, and the compensation signal line 80 in the first sub-pixel P1 and the fourth sub-pixel P4 can be arranged substantially symmetrically with respect to the repeat unit center line. For another example, the positions and shapes of the first to fifth connection electrodes 51-55, the power connection electrode 56, the first power line 60, the data signal line 70, and the compensation signal line 80 in the second sub-pixel P2 and the third sub-pixel P3 can be arranged substantially symmetrically with respect to the repeat unit center line.

[0212] (7) Forming a fourth insulating layer and a planar layer pattern. In an exemplary embodiment, forming the fourth insulating layer and the planar layer pattern can include: on the substrate on which the aforementioned patterns are formed, first depositing a fourth insulating thin film, then coating a planar thin film, and patterning the planar thin film and the fourth insulating thin film by using a patterning process, to form the fourth insulating layer covering the third conductive layer, and the planar layer disposed on the fourth insulating layer, the planar layer and the fourth insulating layer being provided with a plurality of through holes, as shown in FIG. 12.

[0213] In an exemplary embodiment, the plurality of through holes of each sub-pixel in the repeating unit at least includes an anode through hole YV.

[0214] In an exemplary embodiment, the orthographic projection of the anode through hole YV on the substrate is within the orthographic projection of the second sub-electrode 52-2 in the second connecting electrode 52 on the substrate, the planar layer and the fourth insulating layer in the anode through hole YV are removed to expose the surface of the second sub-electrode 52-2, and the anode through hole YV is configured to allow the first electrode formed subsequently to connect with the second sub-electrode 52-2 through the through hole.

[0215] In an exemplary embodiment, the orthographic projection of the anode through hole YV on the substrate does not overlap with the orthographic projection of the fourth through hole V4 (node through hole) on the substrate, and the anode through hole YV is located on the side of the fourth through hole V4 away from the second electrode plate 34.

[0216] In an exemplary embodiment, in at least one sub-pixel, the orthographic projection of the anode through hole YV on the display substrate plane at least partially overlaps with the orthographic projection of the second region of the second active layer on the display substrate plane.

[0217] In some other embodiments, the display substrate can include a color film layer, and on the substrate on which the aforementioned patterns are formed, first form the fourth insulating layer, then form the color film layer on the fourth insulating layer, and then coat the planar thin film, to form the fourth insulating layer covering the third conductive layer, the color film layer disposed on the fourth insulating layer, and the planar layer covering the color film layer, and the fourth insulating layer, the color film layer and the planar layer in the anode through hole are removed to expose the surface of the second connecting electrode.

[0218] (8) Forming a second transparent conductive layer pattern. In an exemplary embodiment, forming the second transparent conductive layer pattern can include: on the substrate on which the aforementioned patterns are formed, depositing a second transparent conductive thin film, and patterning the second transparent conductive thin film by using a patterning process, to form the second transparent conductive layer pattern disposed on the planar layer, as shown in FIG. 13.

[0219] In an exemplary embodiment, the second transparent conductive layer pattern of each sub-pixel in the repeating unit at least includes the first electrode 90.

[0220] In an example embodiment, the first electrode 90 can have a shape of a bar extending along the second direction Y, and a protruding portion can be provided on one side of the first electrode 90 in the second direction Y, and the protruding portion can be connected to the second sub-electrode 52-2 through the anode via hole YV. Since the second connection electrode 52 including the second sub-electrode 52-2 has the potential of the second node N2 in the pixel driving circuit, the first electrode 90 is connected to the second node N2.

[0221] In an example embodiment, in at least one of the sub-pixels, the orthogonal projection of the first electrode 90 on the substrate at least partially overlaps the orthogonal projection of the storage capacitor (the first plate 11 and the second plate 34) in the sub-pixel on the substrate.

[0222] In an example embodiment, in at least one of the sub-pixels, the orthogonal projection of the first electrode 90 on the substrate can include the orthogonal projection of the storage capacitor in the sub-pixel on the substrate.

[0223] In an example embodiment, the second transparent conductive layer in the first sub-pixel P1 and the second sub-pixel P2 and the second transparent conductive layer in the third sub-pixel P3 and the fourth sub-pixel P4 can be substantially symmetrically arranged with respect to the repeat unit center line. For example, the positions and shapes of the first electrodes 90 in the first sub-pixel P1 and the fourth sub-pixel P4 can be substantially symmetrically arranged with respect to the repeat unit center line. For another example, the positions and shapes of the first electrodes 90 in the second sub-pixel P2 and the third sub-pixel P3 can be substantially symmetrically arranged with respect to the repeat unit center line.

[0224] (9) Forming a pixel definition layer pattern. In an example embodiment, forming the pixel definition layer pattern can include: applying a pixel definition film on the substrate on which the aforementioned pattern is formed, patterning the pixel definition film by using a patterning process, and forming the pixel definition layer pattern, as shown in FIG. 14.

[0225] In an example embodiment, the pixel definition layer pattern of each sub-pixel in the repeat unit at least includes a pixel opening 90A.

[0226] In an example embodiment, the pixel opening 90A can have a shape of a bar extending along the second direction Y, the orthogonal projection of the pixel opening 90A on the substrate can be located within the range of the orthogonal projection of the first electrode 90 on the substrate, and the pixel definition film in the pixel opening 90A is removed to expose the surface of the first electrode 90.

[0227] In an example embodiment, in at least one of the sub-pixels, the orthogonal projection of the pixel opening 90A on the substrate at least partially overlaps the orthogonal projection of the storage capacitor in the sub-pixel on the substrate.

[0228] In an example embodiment, in at least one of the sub-pixels, the fourth via V4 (node via) can be located on one side of the pixel opening 90A in the second direction Y, and the orthographic projection of the fourth via V4 on the substrate does not overlap with the orthographic projection of the pixel opening 90A on the substrate.

[0229] In an example embodiment, in at least one of the sub-pixels, the anode via YV can be located on one side of the fourth via V4 in the second direction Y, i.e., the anode via YV can be located on the side of the fourth via V4 away from the pixel opening 90A, and the orthographic projection of the anode via YV on the substrate does not overlap with the orthographic projection of the pixel opening 90A on the substrate.

[0230] In an example embodiment, the shapes and areas of the pixel openings of different sub-pixels can be different. The example embodiments of the present disclosure can adapt to the transmittance of the color filter layer of different sub-pixels by designing four sub-pixels with different aperture ratios, so that the light emitting devices of the four sub-pixels can emit the same brightness at different currents, and the life of the light emitting devices of the four sub-pixels is optimized to the maximum, and the product life is guaranteed.

[0231] In an example embodiment, the shape of the pixel opening can include any one or more of the following: a triangle, a rectangle, a trapezoid, a parallelogram, a pentagon, a hexagon, a circle, and an ellipse.

[0232] In an example embodiment, the subsequent preparation process can include: forming an organic light emitting layer by using an evaporation or inkjet printing process, the organic light emitting layer being connected to the first electrode through the pixel opening, forming a second electrode on the organic light emitting layer, the second electrode being connected to the organic light emitting layer. Forming an encapsulation structure layer, which can include a first encapsulation layer, a second encapsulation layer, and a third encapsulation layer stacked together, the first encapsulation layer and the third encapsulation layer can be made of inorganic material, the second encapsulation layer can be made of organic material, and the second encapsulation layer is arranged between the first encapsulation layer and the third encapsulation layer, which can prevent external water vapor from entering the light emitting structure layer.

[0233] So far, the driving circuit layer, the light emitting structure layer arranged on the driving circuit layer, and the encapsulation structure layer arranged on the light emitting structure layer have been prepared on the substrate. In a plane perpendicular to the display substrate, the driving circuit layer can include a first transparent conductive layer, a first conductive layer, a first insulating layer, a semiconductor layer, a second insulating layer, a second conductive layer, a third insulating layer, a third conductive layer, a fourth insulating layer, and a planarization layer stacked in order on the substrate. The light emitting structure layer can include the first electrode, the pixel definition layer, the organic light emitting layer, and the second electrode, and the encapsulation structure layer can include the first encapsulation layer, the second encapsulation layer, and the third encapsulation layer stacked together.

[0234] In an example embodiment, the substrate can be a flexible substrate, or can be a rigid substrate. The rigid substrate can be one or more of, but not limited to, glass, quartz, and the flexible substrate can be one or more of, but not limited to, polyethylene terephthalate, ethylene terephthalate, polyether ether ketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fibers. In an example embodiment, the flexible substrate can include a first flexible material layer, a first inorganic material layer, a semiconductor layer, a second flexible material layer, and a second inorganic material layer stacked together, the materials of the first and second flexible material layers can be polyimide (PI), polyethylene terephthalate (PET), or a surface-treated polymer soft film, etc., the materials of the first and second inorganic material layers can be silicon nitride (SiNx) or silicon oxide (SiOx), etc., for improving the water and oxygen resistance of the substrate, and the material of the semiconductor layer can be amorphous silicon (a-si).

[0235] In an example embodiment, the first and second transparent conductive layers can employ a transparent conductive material, such as indium tin oxide (ITO) or indium zinc oxide (IZO), etc. The first, second, and third conductive layers can employ a metal material, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or an alloy material of the above-mentioned metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb), which can be a single-layer structure, or a multi-layer composite structure, such as Mo / Cu / Mo, etc. The first, second, third, and fourth insulating layers can employ any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), which can be a single layer, a multi-layer, or a composite layer. The planarization layer can employ an organic material, such as resin, etc., and the pixel definition layer can employ polyimide, acrylic, or polyethylene terephthalate.

[0236] Research shows that in a bottom-emitting OLED display device, when the pixel opening is close to the anode via hole, the first electrode (ITO) in the anode via hole and the pixel opening will form a waveguide effect, and part of the light of the light-emitting device will be emitted from the boundary of the planarization layer, causing the OLED display device to have display defects such as watermarks.

[0237] An example embodiment of the present disclosure provides a display substrate, by setting the node via hole close to the pixel opening and setting the anode via hole away from the pixel opening, not only can effectively reduce light leakage and eliminate display defects such as watermarks, but also can maximize the pixel opening, effectively improve the afterimage, and improve the display quality and display performance.

[0238] The present disclosure can effectively avoid short circuit and dark point defects by setting the second gate electrode to at least partially overlap the second plate on the substrate.

[0239] The present disclosure can effectively increase the area of the second and third sub-pixels, meet the layout space requirement of the second and third sub-pixels, and facilitate high-resolution and high-aperture-ratio display by setting the data signal line in a polyline shape and bending the polyline part away from the compensation signal line.

[0240] The present disclosure can effectively increase the capacitance of the storage capacitor and the pixel opening by adopting a transparent storage capacitor composed of a transparent first transparent conductive layer and a transparent semiconductor layer, and the light can be emitted through the transparent storage capacitor, so the storage capacitor can be arranged in the pixel opening.

[0241] The present disclosure can save the number of signal lines, reduce the occupied space, and improve the space utilization by setting the one-to-two structure of the first power line and the one-to-four structure of the compensation signal line.

[0242] The display substrate of the present disclosure adopts a 3T1C pixel driving circuit with one scanning signal line, and the scanning signal line is connected with all first transistors and all third transistors in a pixel row, which effectively reduces the number of scanning signal lines, simplifies the structure of the pixel driving circuit, reduces the occupied area of the pixel driving circuit, effectively increases the light transmission area of the light transmission region, improves the space proportion of the light transmission region, and facilitates high-resolution display and high-transparency display.

[0243] The preparation process of the present disclosure can be realized by using existing mature preparation equipment, has little improvement on the existing process, is compatible with the existing preparation process, is simple to implement, has high production efficiency, low production cost, and high yield.

[0244] The structure and its preparation process shown in the present disclosure are only exemplary, and in the exemplary embodiments, the corresponding structure can be changed, and the patterning process can be increased or reduced, which is not limited in the present disclosure.

[0245] In an exemplary embodiment, the display substrate of the present disclosure can be applied to a display device with pixel driving circuit, such as OLED, quantum dot display (QLED), light emitting diode display (Micro LED or Mini LED), or quantum dot light emitting diode display (QDLED), etc., which are not limited herein.

[0246] The present disclosure also provides a preparation method of a display substrate, for preparing the display substrate of the foregoing embodiments. In an exemplary embodiment, the display substrate includes a plurality of sub-pixels; and the preparation method includes:

[0247] forming a pixel driving circuit and a light emitting device in at least one sub-pixel; the pixel driving circuit at least includes a second transistor as a driving transistor and a node electrode, the second transistor at least includes a second active layer, the node electrode is connected with a second region of the second active layer through a node via, a first region of the second active layer is connected with a first power line; the light emitting device at least includes a first electrode and a pixel definition layer, the first electrode is connected with the node electrode through an anode via, the pixel definition layer is provided with a pixel opening exposing the first electrode; in at least one sub-pixel, a normal projection of the node via on a display substrate plane does not overlap with a normal projection of the pixel opening on the display substrate plane, the anode via is arranged on a side of the node via away from the pixel opening.

[0248] The present disclosure also provides a display device including the display substrate of the foregoing embodiments. The display device can be any product or component with display function, such as mobile phone, tablet computer, television, display, notebook computer, digital photo frame, navigator, etc.

[0249] Although the embodiments of the present disclosure are disclosed as above, it should be noted that the above embodiments are only exemplary and not restrictive. Therefore, the present disclosure is not limited to the specific embodiments shown and described herein. Various modifications, replacements or omissions can be made to the forms and details of the embodiments without departing from the scope of the present disclosure.

Claims

1. A display substrate, comprising a plurality of repeating units, at least one of the repeating units comprising a plurality of sub-pixels, at least one of the sub-pixels comprising a pixel driving circuit and a light emitting device. The pixel driving circuit at least includes a second transistor as a driving transistor and a node electrode, the second transistor at least includes a second active layer, the node electrode is connected with a second region of the second active layer through a node via, and a first region of the second active layer is connected with a first power supply line; and the light emitting device at least includes a first electrode and a pixel definition layer, the first electrode is connected with the node electrode through an anode via, and the pixel definition layer is provided with a pixel opening exposing the first electrode. In at least one of the sub-pixels, a normal projection of the node via on a display substrate plane does not overlap with a normal projection of the pixel opening on the display substrate plane, and the anode via is arranged on a side of the node via away from the pixel opening. 2.The display substrate of claim 1, wherein, The pixel driving circuit further includes a shielding electrode and a transparent storage capacitor, the storage capacitor includes a first plate and a second plate, a normal projection of the first plate on a display substrate plane at least partially overlaps with a normal projection of the second plate on the display substrate plane, a normal projection of the shielding electrode on the display substrate plane at least partially overlaps with a normal projection of the second active layer on the display substrate plane, and the shielding electrode is connected with the first plate. In at least one of the sub-pixels, the node electrode is further connected with the shielding electrode through the node via. 3.The display substrate of claim 2, wherein, The node electrode at least includes a first sub-electrode and a second sub-electrode connected with each other, the first sub-electrode is connected with the second region of the second active layer and the shielding electrode through the node via at the same time, the first electrode is connected with the second sub-electrode through an anode via, and the second sub-electrode is arranged on a side of the first sub-electrode away from the pixel opening. 4.The display substrate of claim 3, wherein, A normal projection of the second sub-electrode on a display substrate plane at least partially overlaps with a normal projection of the second region of the second active layer on the display substrate plane, and a normal projection of the anode via on the display substrate plane at least partially overlaps with a normal projection of the second region of the second active layer on the display substrate plane. 5.The display substrate of claim 2, wherein, In at least one of the sub-pixels, a normal projection of the first plate on a display substrate plane at least partially overlaps with a normal projection of the pixel opening on the display substrate plane, and a normal projection of the second plate on the display substrate plane at least partially overlaps with a normal projection of the pixel opening on the display substrate plane. 6.The display substrate of claim 2, wherein, In a direction perpendicular to the display substrate, the display substrate at least includes a first transparent conductive layer arranged on a base, a first conductive layer arranged on a side of the first transparent conductive layer away from the base, a semiconductor layer arranged on a side of the first conductive layer away from the base, and a second conductive layer arranged on a side of the semiconductor layer away from the base, the first plate is arranged in the first transparent conductive layer, the shielding electrode is arranged in the first conductive layer, the second plate and the second active layer are arranged in the semiconductor layer, and the node electrode is arranged in the second conductive layer. 7.The display substrate of claim 2, wherein, The second transistor further includes a second gate electrode, and the pixel driving circuit further includes a first connection electrode; in at least one of the sub-pixels, the first connection electrode is connected to the second plate and the second gate electrode through a first transfer via hole. 8.The display substrate of claim 7, wherein, In at least one of the sub-pixels, a projection of the second gate electrode on a display substrate plane at least partially overlaps a projection of the second plate on the display substrate plane. 9.The display substrate of claim 7, wherein, In at least one of the first transfer via holes, a projection of the second gate electrode on a display substrate plane at least partially overlaps a projection of the second plate on the display substrate plane. 10.The display substrate according to any one of claims 1 to 9, wherein At least one of the repeating units includes, in sequence along a first direction, a first sub-pixel, a second sub-pixel, a third sub-pixel, and a fourth sub-pixel; the first power supply line is in a linear or zigzag shape extending along a second direction and is arranged in the first sub-pixel and the fourth sub-pixel, respectively; the first power supply line in the first sub-pixel is connected to a first region of the second active layer in the first sub-pixel through a power supply via hole; the first power supply line in the first sub-pixel is connected to a first region of the second active layer in the second sub-pixel through a power supply connection line and a power supply connection electrode; the first power supply line in the fourth sub-pixel is connected to a first region of the second active layer in the third sub-pixel through a power supply connection line and a power supply connection electrode; and the first power supply line in the fourth sub-pixel is connected to a first region of the second active layer in the fourth sub-pixel through a power supply via hole. 11.The display substrate of claim 10, wherein, The pixel driving circuit further includes a shielding electrode, a projection of the shielding electrode on a display substrate plane at least partially overlaps a projection of the second active layer on the display substrate plane; in the first sub-pixel and the fourth sub-pixel, a projection of the power supply via hole on the display substrate plane does not overlap a projection of the shielding electrode on the display substrate plane. 12.The display substrate of claim 10, wherein, The pixel driving circuit further includes a shielding electrode, a projection of the shielding electrode on a display substrate plane at least partially overlaps a projection of the second active layer on the display substrate plane; in the second sub-pixel and the third sub-pixel, a first end of the power supply connection electrode is connected to a first region of the second active layer through a power supply via hole, a second end of the power supply connection electrode is connected to the first power supply line through the power supply connection line, and a projection of the power supply via hole on the display substrate plane at least partially overlaps a projection of the shielding electrode on the display substrate plane. 13.The display substrate of claim 10, wherein, At least one of the sub-pixels further comprises a data signal line connected to the pixel driving circuit, the data signal line has a shape of a broken line extending along the second direction, and comprises at least a first sub-line and a second sub-line in straight line shape, and a third sub-line in slant line shape, the third sub-line is arranged between the first sub-line and the second sub-line, and two ends of the third sub-line are connected to the first sub-line and the second sub-line respectively; in at least one of the first sub-pixel and the fourth sub-pixel, the first sub-line has a first distance from the first power line, the second sub-line has a second distance from the first power line, the first distance is greater than the second distance, and the first distance and the second distance are dimensions in the first direction. 14.The display substrate of claim 13, wherein, At least one of the sub-pixels further comprises a compensation signal line connected to the pixel driving circuit, the compensation signal line is arranged between the second sub-pixel and the third sub-pixel; in at least one of the second sub-pixel and the third sub-pixel, the first sub-line has a third distance from the compensation signal line, the second sub-line has a fourth distance from the compensation signal line, the third distance is less than the fourth distance, and the third distance and the fourth distance are dimensions in the first direction. 15.The display substrate of claim 14, wherein, A normal projection of the compensation signal line on a display substrate plane does not overlap a normal projection of the power connection line on the display substrate plane.

16. The display substrate according to any one of claims 1 to 9, wherein The pixel driving circuit further comprises a first transistor as a data writing transistor and a third transistor as a compensation transistor, in at least one of the sub-pixels, a gate electrode of the first transistor and a gate electrode of the third transistor are connected to the same scan signal line. 17.The display substrate of claim 16, wherein, In at least one of the repeating units, gate electrodes of a plurality of the first transistors and gate electrodes of a plurality of the third transistors are connected to the same scan signal line. 18.The display substrate of claim 16, wherein, In at least one of the repeating units, at least one via hole is arranged on the scan signal line, a normal projection of the via hole on a display substrate plane at least partially overlaps a normal projection of the first power line on the display substrate plane.

19. A display device comprising the display substrate according to any one of claims 1 to 18.

20. A manufacturing method of a display substrate, the display substrate comprising a plurality of sub-pixels; the manufacturing method comprising: forming a pixel driving circuit and a light emitting device in at least one of the sub-pixels; the pixel driving circuit comprising at least a second transistor as a driving transistor and a node electrode, the second transistor comprising at least a second active layer, the node electrode being connected to a second region of the second active layer through a node via hole, a first region of the second active layer being connected to a first power line; the light emitting device comprising at least a first electrode and a pixel definition layer, the first electrode being connected to the node electrode through an anode via hole, the pixel definition layer being provided with a pixel opening exposing the first electrode; In at least one of the sub-pixels, a normal projection of the node via on the display substrate plane does not overlap with a normal projection of the pixel opening on the display substrate plane, and the anode via is disposed on a side of the node via away from the pixel opening.

Images