Ceramic packaging substrate, semiconductor chip, and manufacturing method for ceramic packaging substrate

Abstract

The present invention relates to the technical field of semiconductor chip packaging, and specifically relates to a ceramic packaging substrate, a semiconductor chip, and a manufacturing method for the ceramic packaging substrate. The ceramic packaging substrate comprises a ceramic core board and ABF / BT composite layers. A ceramic substrate of the ceramic core board is provided with a plurality of interconnection holes, and the interconnection holes pass through the upper and lower surfaces of the ceramic substrate. Electroplated copper coating layers are provided on the surfaces of the ceramic substrate. The ABF / BT composite layers are provided on both the upper and lower sides of the ceramic core board. Each ABF / BT composite layer comprises a plurality of stacked ABF / BT layers, and a copper-clad laminate layer is provided on the outer side of each ABF / BT layer. A solder mask layer is provided on the surface of the outermost ABF / BT layer, and a surface treatment layer is provided on the outer side of the solder mask layer. The ceramic packaging substrate in the present solution has a ceramic core board at the center thereof, thereby providing advantages such as high thermal conductivity, high hardness, high flexural strength, good insulation, low dielectric loss, and resistance to high temperature and corrosion. Moreover, the ceramic packaging substrate is durable and has a prolonged service life, and the pass rate of outgoing products is improved.

Description

Ceramic packaging substrate, semiconductor chip and manufacturing method of ceramic packaging substrate TECHNICAL FIELD

[0001] The application belongs to the technical field of semiconductor chip packaging, and particularly relates to a ceramic packaging substrate, a semiconductor chip and a manufacturing method of the ceramic packaging substrate. BACKGROUND

[0002] The packaging substrate is the carrier of the chip and also the bridge connecting the chip and the PCB circuit board, and its importance is also very significant. At present, the packaging substrate in the industry is mainly ABF laminated substrate, which has excellent corrosion resistance, high temperature resistance, good heat dissipation and electrical and thermal properties. However, in the actual processing process, due to the different thermal expansion coefficients of various materials of the ABF laminated substrate, the warping amplitude of the ABF laminated substrate after processing is large.

[0003] Therefore, it is necessary to design an anti-warping ceramic packaging substrate and a manufacturing method thereof, and a semiconductor chip structure using the ceramic packaging substrate. SUMMARY

[0004] In order to solve the above problems existing in the prior art, the application provides a ceramic packaging substrate, a semiconductor chip and a manufacturing method of the ceramic packaging substrate.

[0005] The technical scheme adopted by the application is as follows:

[0006] A ceramic packaging substrate comprises a ceramic core plate and an ABF / BT composite layer.

[0007] The ceramic core plate comprises a ceramic substrate and an electroplated copper coating layer. A plurality of interconnected holes are arranged on the ceramic substrate, and the interconnected holes penetrate the upper and lower surfaces of the ceramic substrate. The electroplated copper coating layer is arranged on the upper and lower surfaces of the ceramic substrate and the hole walls of the interconnected holes. The interconnected holes are also filled with ink.

[0008] ABF / BT composite layers are arranged above and below the ceramic core plate. The ABF / BT composite layers comprise a plurality of ABF / BT layers arranged in layers. Copper clad plate layers are arranged on the outer sides of each ABF / BT layer. A plurality of communication pads are formed on the copper clad plate layers. A plurality of grooves are arranged on the copper clad plate layers, and blind holes are arranged on the ABF / BT layers at the grooves. Copper pillars are arranged in the blind holes.

[0009] A solder resist layer is arranged on the surface of the outermost ABF / BT layer, and a surface treatment layer is arranged on the outer side of the solder resist layer.

[0010] The electroplated copper coating layer, the copper clad plate layer and the surface treatment layer are metal layers, and a plurality of communication pads are arranged on each metal layer.

[0011] The interconnection pads between different copper clad plate layers and the interconnection pads between the copper clad plate layers and the electroplated copper film layers are electrically connected through corresponding copper columns.

[0012] Alternatively or additionally to the above, the ceramic substrate is 92 porcelain, 95 porcelain, or 99 porcelain, and is made of an alumina, aluminum nitride, or silicon nitride material.

[0013] Alternatively or additionally to the above, the interconnection hole is formed by laser drilling.

[0014] Alternatively or additionally to the above, the groove is a slot structure formed by mechanical drilling, and the blind hole is a hole structure formed by mechanical drilling.

[0015] A semiconductor chip, comprising a flip chip, a heat dissipation cover, and the ceramic packaging substrate described above; the lower surface of the flip chip is provided with a seed layer for external electrical connection, and the seed layer is electrically connected to the interconnection pads on the upper surface of the ceramic packaging substrate through a plurality of bumps; the heat dissipation cover covers the flip chip, and the inner top of the heat dissipation cover is in contact with the flip chip through heat dissipation glue.

[0016] Alternatively or additionally to the above, the flip chip below the heat dissipation cover is single or multiple.

[0017] Alternatively or additionally to the above, the edge of the heat dissipation cover is adhered to the upper surface of the ceramic packaging substrate through upper cover glue.

[0018] Alternatively or additionally to the above, the ceramic packaging substrate below the heat dissipation cover is also provided with electronic components, and the flip chip and the ceramic packaging substrate are provided with underfill glue; the pads on the lower surface of the ceramic packaging substrate are provided with solder balls.

[0019] A method for manufacturing a ceramic packaging substrate, comprising the following steps:

[0020] A1: preparing a ceramic substrate;

[0021] A2: drilling the ceramic core plate by laser drilling to form an interconnection hole that connects the upper and lower surfaces of the ceramic substrate;

[0022] A3: electroplating the ceramic substrate to form an electroplated copper film layer on the upper and lower surfaces of the ceramic core plate and the hole wall of the interconnection hole;

[0023] A4: filling the hole cavity of the interconnection hole with ink;

[0024] A5: processing and forming the interconnecting pads on the electroplated copper film layer, and making the interconnecting pads on the upper and lower surfaces of the electroplated copper film layer communicate through the metal part at the interconnecting hole according to the pre-designed circuit diagram; thus, the ceramic core plate is formed;

[0025] A6: forming an ABF / BT layer on the upper and lower surfaces of the ceramic core plate, or making another ABF / BT layer outside the formed ABF / BT layer;

[0026] A7: preparing a copper clad plate layer outside the ABF / BT layer made in step A6;

[0027] A8: mechanically processing grooves on the copper clad plate layer in step A7;

[0028] A9: mechanically processing and forming blind holes on the ABF / BT layer in step A6, electroplating and forming copper columns on the hole walls of the blind holes, and realizing electrical communication between different metal layers by the copper columns;

[0029] A10: performing patterned manufacturing on the surface of the copper clad plate, and forming interconnecting pads;

[0030] A11: repeating steps A6-A10 until the overlapping of the set number of ABF / BT layers is completed; setting a solder resist layer on the surface of the outermost ABF / BT layer, setting a surface treatment layer outside the solder resist layer; punching on the solder resist layer, and processing and forming interconnecting pads on the surface treatment layer, and connecting the interconnecting pads of the surface treatment layer with the interconnecting pads of the ABF / BT layer; thus, the preparation of the ceramic packaging substrate is completed.

[0031] The beneficial effects of the present application are:

[0032] 1. The ceramic packaging substrate of the present application has a ceramic substrate at the center, which has the advantages of high thermal conductivity, high hardness, high bending resistance, good insulation, small dielectric loss, high temperature resistance, corrosion resistance, and the like, and is durable, capable of prolonging the service life of the packaging substrate and improving the qualified rate of the product.

[0033] 2. The ABF / BT composite layer is arranged on both sides of the ceramic substrate in the present application, so that the ceramic packaging substrate has the structural strength of the ceramic material, and also has the advantages of ABF corrosion resistance, high temperature resistance, good heat dissipation and electrical performance; and the ceramic substrate is used as the support framework of the ABF / BT composite layer, thereby reducing the warping probability of the ceramic packaging substrate. BRIEF DESCRIPTION OF DRAWINGS

[0034] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the drawings needed in the embodiment or prior art description will be briefly introduced as follows.

[0035] Fig. 1 is a sectional view of a heat dissipation cover;

[0036] Fig. 2 is a structure view of the front and back of the heat dissipation cover;

[0037] Fig. 3 is a sectional view of a ceramic packaging substrate;

[0038] Fig. 4 is a sectional view of a single-core semiconductor chip;

[0039] Fig. 5 is a sectional view of a two-core semiconductor chip;

[0040] Fig. 6 is a sectional view of a ceramic substrate;

[0041] Fig. 7 is a structure view of Fig. 6 with an electroplated copper film layer added;

[0042] Fig. 8 is a structure view of Fig. 7 with ink added;

[0043] Fig. 9 is a structure view of Fig. 8 with an ABF / BT layer and a copper-clad plate layer added;

[0044] Fig. 10 is a structure view of Fig. 8 with multiple ABF / BT layers and multiple copper-clad plate layers added;

[0045] Fig. 11 is a structure view of Fig. 10 with a surface treatment layer and a solder resist layer added;

[0046] Fig. 12 is a structure view of Fig. 11 with a flip chip added.

[0047] In the figures: 001 - ceramic packaging substrate; 100 - ceramic core plate; 101 - ceramic substrate; 210 - electroplated copper film layer; 220 - conductive dielectric layer; 230 - blind hole; 240 - groove; 250 - surface treatment layer; 260 - seed layer; 300 - ABF / BT composite layer; 310 - interconnection hole; 320 - ABF / BT layer; 330 - solder resist layer; 410 - underfill adhesive; 420 - heat dissipation adhesive; 430 - upper cover adhesive; 510 - flip chip; 511 - electronic component; 602 - bump; 604 - tin ball; 700 - heat dissipation cover. Embodiment of the present application

[0048] The technical solutions in the embodiments will be described clearly and completely below with reference to the drawings. The described embodiments are only a part of the embodiments, and all other embodiments obtained by those skilled in the art without creative labor based on the embodiments in the present application are within the protection scope of the present application.

[0049] Embodiment 1

[0050] As shown in FIGS. 1-12, the present embodiment designs a ceramic packaging substrate 001, which comprises a ceramic core plate 100 and an ABF / BT composite layer 300.

[0051] The ceramic core plate 100 comprises a ceramic substrate 101 and a plated copper film layer 210. The ceramic substrate 101 is provided with a plurality of interconnected holes 310 formed by laser drilling, which penetrate the upper and lower surfaces of the ceramic substrate 101; the plated copper film layer 210 is arranged on the upper and lower surfaces of the ceramic substrate 101 and the hole walls of the interconnected holes 310; and the interconnected holes 310 are further filled with ink.

[0052] The ceramic substrate 101 is made of 92 porcelain, 95 porcelain or 99 porcelain, and is made of alumina, aluminum nitride or silicon nitride material. The ceramic substrate 101 has high thermal conductivity, in which the crystal of the aluminum nitride material of the ceramic substrate 101 is AIN, which has the advantages of high hardness, good insulation, high temperature resistance and corrosion resistance; the thermal conductivity (thermal conductivity coefficient) is greater than or equal to 170 W / m.k; at the same time, the dielectric loss of the aluminum nitride material of the ceramic substrate 101 is very low, about 0.0002F, and the thermal expansion coefficient is also very low (4.6-5.2 m / K), which makes it have the advantages of small dielectric loss, small energy consumption, high temperature resistance, corrosion resistance and long service life; in addition, the dielectric constant of the ceramic substrate 101 is generally 9.0F / m, which means that the quality is better. The bending strength of the ceramic substrate 101 is better, and the bending strength refers to the ability of the material to resist bending and cracking, in which the bending strength of the aluminum nitride ceramic substrate 101 is 450Mpa, which means that the aluminum nitride ceramic substrate 101 can withstand more pressure and tension.

[0053] The ABF / BT composite layer 300 is arranged above and below the ceramic core plate 100, and comprises a plurality of ABF / BT layers 320 arranged in layers, each ABF / BT layer 320 is a thin layer structure made of ABF material or BT material, and each ABF / BT layer 320 is provided with a copper-clad plate layer on the outer side; a plurality of communication pads are formed on the copper-clad plate layer; a plurality of grooves 240 are arranged on the copper-clad plate layer, and a blind hole 230 is arranged on the ABF / BT layer 320 at each groove 240; and a copper pillar is arranged in the blind hole 230.

[0054] A solder resist layer 330 is arranged on the surface of the outermost ABF / BT layer 320, and a surface treatment layer 250 is arranged on the outer side of the solder resist layer 330.

[0055] The plated copper film layer 210, the copper-clad plate layer and the surface treatment layer 250 are all metal layers, and a plurality of communication pads are arranged on each metal layer, and the communication pads of different metal layers are electrically connected through copper pillars.

[0056] The communication pads between different copper clad plate layers and the communication pads between the copper clad plate layers and the electroplated copper film layer 210 are electrically connected through corresponding copper pillars. The grooves 240 are slot structures formed by mechanical punching, and the blind holes 230 are hole structures formed by mechanical punching.

[0057] The advantages of the ceramic packaging substrate 001 in this embodiment are as follows:

[0058] 1. Combine high-performance ceramic substrate 101 (such as 92 / 95 / 99 alumina, aluminum nitride, silicon nitride) with ABF material or BT material, and fully utilize the advantages of both materials. The ceramic substrate 101 has excellent thermal conductivity, mechanical strength, and high-temperature and corrosion resistance, while the ABF material or BT material excels in electrical performance and processing convenience. This material combination not only retains the electrical performance advantages of ABF material, but also significantly improves the problems of easy warping and thermal decay.

[0059] 2. Innovation of preparation process

[0060] Laser drilling and electroplating technology: Form interconnection holes 310 through the ceramic substrate 101 by laser drilling, and electroplate the side walls of the interconnection holes 310 to form a conductive copper medium layer. This technology ensures reliable conduction between the ceramic substrate 101 and the ABF material or BT material.

[0061] Ink filling interconnection holes 310: This process step not only improves the filling reliability of the interconnection holes 310, but also enhances the conduction performance of the upper and lower surfaces.

[0062] Mechanical drilling and electroplated copper pillar blind hole 230: The copper clad plate layer forms a copper pillar blind hole 230 through mechanical drilling and electroplating, realizing the interconnection of each layer. This process further improves the electrical conductivity and structural strength of the packaging substrate.

[0063] 3. Innovation of structure design

[0064] Multi-layer dielectric layer and copper clad plate layer: An ABF layer or BT layer is formed on the upper and lower surfaces of the ceramic core plate 100, and a copper clad plate layer is prepared on the outer layer of the dielectric layer. This multi-layer structure design effectively improves the mechanical strength and electrical performance of the packaging substrate, while ensuring good heat dissipation and corrosion resistance.

[0065] Upper and lower surface conduction design: The upper and lower surfaces of the ceramic core plate 100 form grooves 240 that are in conduction with the interconnection holes 310, ensuring high conductivity and high reliability of the overall structure.

[0066] 4. Improvement of comprehensive performance

[0067] Through the innovative material combination and preparation process, the comprehensive performance of the packaging substrate is significantly improved, including thermal conductivity, mechanical strength, electrical performance and durability. The improvement of the comprehensive performance provides a more reliable and efficient solution for the packaging of high-performance chips.

[0068] 5. Solve industry pain points

[0069] The present application effectively solves the problems of large warping and thermal decay in the production and processing of existing ABF and BT boards, improves the yield and product consistency of the packaging substrate, and significantly improves the technical difficulties encountered in the packaging industry.

[0070] Embodiment 2

[0071] As shown in FIGS. 1-12, the present embodiment designs a semiconductor chip, which includes a flip chip 510, a heat dissipation cover 700 and the above-mentioned ceramic packaging substrate 001; the lower surface of the flip chip 510 is provided with a seed layer 260 for external electrical connection, and the seed layer 260 is electrically connected (usually directly welded) to the communication pad on the upper surface of the ceramic packaging substrate 001 through a plurality of bumps 602; the heat dissipation cover 700 covers the flip chip 510, and the inner top of the heat dissipation cover 700 is bonded to the flip chip 510 through the heat dissipation adhesive 420.

[0072] The flip chip 510 below the heat dissipation cover 700 is single or multiple.

[0073] The edge of the heat dissipation cover 700 is bonded to the upper surface of the ceramic packaging substrate 001 through the upper cover adhesive 430.

[0074] The electronic components 511 are also arranged on the ceramic packaging substrate 001 below the heat dissipation cover 700, and the flip chip 510 and the ceramic packaging substrate 001 are provided with the underfill adhesive 410; the solder balls 604 are arranged on the pads on the lower surface of the ceramic packaging substrate 001, and the semiconductor chip can be welded to the circuit board through the solder balls 604.

[0075] Embodiment 3

[0076] On the basis of the structure of embodiment 1 and embodiment 2, the present embodiment designs a manufacturing method of the ceramic packaging substrate 001, which includes the following steps:

[0077] A1: prepare a ceramic substrate 101;

[0078] A2: laser drilling is used to drill the ceramic core plate 100, so that the interconnection hole 310 is formed on the ceramic substrate 101 to communicate the upper and lower ceramic substrate 101;

[0079] A3: Electroplating the ceramic substrate 101 to form an electroplated copper film layer 210 on the upper and lower surfaces of the ceramic core board 100 and the hole wall of the interconnection hole 310;

[0080] A4: Filling the hole cavity of the interconnection hole 310 with ink;

[0081] A5: Processing the electroplated copper film layer 210 to form a through-hole pad, and according to the pre-designed circuit diagram, the through-hole pads on the upper and lower surfaces of the electroplated copper film layer 210 are connected through the metal part at the interconnection hole 310; thus, the ceramic core board 100 is formed;

[0082] A6: Forming an ABF / BT layer 320 on the upper and lower surfaces of the ceramic core board 100, respectively;

[0083] A7: Preparing a copper-clad plate layer on the outer side of the ABF / BT layer 320 prepared in step A6;

[0084] A8: Mechanically processing a groove 240 on the copper-clad plate layer in step A7;

[0085] A9: Mechanically processing a blind hole 230 on the ABF / BT layer in step A6, electroplating and forming a copper column on the hole wall of the blind hole 230, and realizing electrical connection between different metal layers by the copper column;

[0086] A10: Forming a through-hole pad on the surface of the copper-clad plate by patterning;

[0087] A11: Repeating steps A6-A10 until the overlap of a set number of ABF / BT layers 320 is completed; a solder resist layer 330 is arranged on the surface of the outermost ABF / BT layer 320, and a surface treatment layer 250 is arranged on the outer side of the solder resist layer 330; a through-hole pad is processed on the surface treatment layer 250, and the through-hole pad of the surface treatment layer 250 is connected with the through-hole pad of the ABF / BT layer 320 by punching on the solder resist layer 330; thus, the preparation of the ceramic packaging substrate is completed.

[0088] The above embodiments are only examples for clearly illustrating the examples, and are not limitations of the embodiments; all embodiments do not need to be exhausted, and obvious changes or variations derived therefrom are still within the protection scope of the technology.

Claims

1. A ceramic package substrate, characterized by: The ceramic core plate (100) and the ABF / BT composite layer (300) are included. The ceramic core plate (100) includes a ceramic substrate (101) and a plated copper film layer (210); a plurality of interconnected holes (310) are arranged on the ceramic substrate (101) and penetrate the upper and lower surfaces of the ceramic substrate (101); the plated copper film layer (210) is arranged on the upper and lower surfaces of the ceramic substrate (101) and the hole walls of the interconnected holes (310); and the interconnected holes (310) are further filled with ink. ABF / BT composite layers (300) are arranged above and below the ceramic core plate (100); the ABF / BT composite layer (300) includes a plurality of stacked ABF / BT layers (320); a copper-clad plate layer is arranged on the outer side of each ABF / BT layer (320); a plurality of grooves (240) are arranged on the copper-clad plate layer; blind holes (230) are arranged on the ABF / BT layer (320) at each groove (240); and a copper pillar is arranged in the blind hole (230). A solder mask layer (330) is arranged on the surface of the outermost ABF / BT layer (320); a surface treatment layer (250) is arranged on the outer side of the solder mask layer (330); and a blind hole (230) with a built-in copper pillar is arranged on the surface treatment layer (250). The plated copper film layer (210), the copper-clad plate layer, and the surface treatment layer (250) are metal layers; a plurality of communication pads are arranged on each metal layer. The communication pads of different copper-clad plate layers and the communication pads of the plated copper film layer (210) and the copper-clad plate layer are electrically connected through corresponding copper pillars.

2. The ceramic package substrate of claim 1, wherein: The ceramic substrate (101) is made of 92 porcelain, 95 porcelain, or 99 porcelain and is made of an alumina, aluminum nitride, or silicon nitride material.

3. The ceramic package substrate of claim 1, wherein: The interconnected holes (310) are formed by laser drilling.

4. The ceramic package substrate of claim 1, wherein: The grooves (240) are slot structures formed by mechanical drilling, and the blind holes (230) are hole structures formed by mechanical drilling.

5. A semiconductor chip, characterized by: The ceramic packaging substrate (001) includes a flip chip (510), a heat dissipation cover (700), and a ceramic packaging substrate (001) according to any one of claims 1-4; a seed layer (260) for external electrical connection is arranged on the lower surface of the flip chip (510); the seed layer (260) is electrically connected to the communication pads on the upper surface of the ceramic packaging substrate (001) through a plurality of bumps (602); the heat dissipation cover (700) covers the flip chip (510); and the inner top of the heat dissipation cover (700) is in contact with the flip chip (510) through heat dissipation adhesive (420).

6. The semiconductor chip of claim 5, wherein: The flip chip (510) below the heat dissipation cover (700) is a single particle or multiple particles.

7. The semiconductor chip of claim 5, wherein: The edge of the heat dissipation cover (700) is bonded to the upper surface of the ceramic packaging substrate (001) through upper cover adhesive (430).

8. The semiconductor chip of claim 5, wherein: Electronic components (511) are further arranged on the ceramic packaging substrate (001) below the heat dissipation cover (700); the bottom filling adhesive (410) is arranged between the flip chip (510) and the ceramic packaging substrate (001); and the solder balls (604) are arranged on the pads on the lower surface of the ceramic packaging substrate (001).

9. A method for manufacturing a ceramic package substrate according to any one of claims 1 to 4, characterized by: The method comprises the following steps: A1: preparing a ceramic substrate (101); A2: perforating the ceramic core plate (100) by means of laser perforation, so that the ceramic substrate (101) is formed with interconnected holes (310) connecting the upper and lower ceramic substrate (101); A3: electroplating the ceramic substrate (101), so that the upper and lower surfaces of the ceramic core plate (100) and the hole walls of the interconnected holes (310) are formed with electroplated copper film layers (210); A4: filling the hole cavities of the interconnected holes (310) with ink; A5: processing the electroplated copper film layers (210) to form interconnected pads, and according to a pre-designed circuit diagram, the interconnected pads on the upper and lower surfaces of the electroplated copper film layers (210) are connected through the metal parts at the interconnected holes (310); thus, the ceramic core plate (100) is formed; A6: forming an ABF / BT layer (320) on the upper and lower surfaces of the ceramic core plate (100), or making another ABF / BT layer (320) outside the already formed ABF / BT layer; A7: preparing a copper-clad plate layer outside the ABF / BT layer (320) made in step A6; A8: mechanically processing grooves (240) on the copper-clad plate layer in step A7; A9: mechanically processing blind holes (230) on the ABF / BT layer in step A6, electroplating the hole walls of the blind holes (230) to form copper pillars, and realizing electrical connection between different metal layers by means of the copper pillars; A10: performing patterned fabrication on the surface of the copper-clad plate and forming interconnected pads; A11: repeating steps A6-A10 until the overlapping of a set number of ABF / BT layers (320) is completed; setting a solder resist layer (330) on the surface of the outermost ABF / BT layer (320), setting a surface treatment layer (250) outside the solder resist layer (330), perforating the solder resist layer (330), processing interconnected pads on the surface treatment layer (250), and connecting the interconnected pads of the surface treatment layer (250) and the interconnected pads of the ABF / BT layer (320); thus, the preparation of the ceramic packaging substrate is completed.

Images