Package structure and manufacturing method therefor, circuit board, and electronic device

Abstract

The present application provides a package structure and a manufacturing method therefor, a circuit board, and an electronic device. The package structure comprises a stacked structure, the stacked structure comprises a dielectric layer, and the dielectric layer comprises a first dielectric layer and a second dielectric layer. The second dielectric layer is provided on at least one side of the first dielectric layer, and a power device is embedded in the first dielectric layer.

Description

Package structure and preparation method thereof, circuit board and electronic device

[0001] The present application claims priority to the Chinese patent application No. 202411111996.3, filed on August 14, 2024, and entitled "Package structure and preparation method thereof, circuit board and electronic device", the content of which is incorporated herein by reference in its entirety. TECHNICAL FIELD

[0002] The present application relates to the technical field of semiconductor packaging, in particular to a package structure and a preparation method thereof, a circuit board and an electronic device. BACKGROUND

[0003] System in package (SIP) technology is an integrated circuit packaging technology that integrates multiple devices in a single package, increasing the integration level, reducing the volume and power consumption of the device. The high integration, high efficiency and high power of the system in package power module bring blessings to the field of electric energy conversion and motor control. At present, most of the packaged power modules still adopt a ternary structure of power device-bonding wire-substrate. The working principle of this structure can be summarized as follows: the bottom of the power device is soldered to the copper-clad ceramic plate (DBC), and the surface electrode of the power device is connected to the DBC through the bonding wire. The power device and other devices are electrically connected through the bonding wire and the copper layer on the top of the DBC. This ternary structure usually has the following disadvantages, including: low working frequency of the power module, the bonding wire introduces a large parasitic inductance, which causes more serious overvoltage, parasitic oscillation and electromagnetic interference (EMI) under high-frequency current change; the packaged power module still needs to be attached to the surface of the circuit board, causing area waste and increasing product volume; in order to ensure the stability of the power module, the product weight is heavier due to the injection of potting glue in the shell.

[0004] In order to meet the development requirements of miniaturization, integration and high frequency of the packaged power module, the related technology adopts an embedded packaging technology to integrate the power device from the surface of the substrate to the inside of the substrate. TECHNICAL PROBLEM

[0005] However, the packaged power module prepared by using the embedded packaging technology generates a large amount of heat during work, which easily affects other devices arranged on the surface of the packaged power module. TECHNICAL SOLUTION

[0006] An object of the present application is to provide a new technical solution of a package structure and a preparation method thereof, a circuit board and an electronic device.

[0007] According to a first aspect of the present application, a packaging structure is provided. The packaging structure comprises a laminated structure, the laminated structure comprising a medium layer, the medium layer comprising a first medium layer and a second medium layer; at least one side of the first medium layer is provided with the second medium layer, and a power device is embedded in the first medium layer.

[0008] In some embodiments of the present application, the packaging structure further comprises a protective layer located on opposite surfaces of the laminated structure, and at least one of the protective layers is provided with a solder pad, and the second medium layer is located between the first medium layer and the protective layer provided with the solder pad.

[0009] In some embodiments of the present application, the second medium layer is inlaid with a heat insulation structure.

[0010] In some embodiments of the present application, the heat insulation structure corresponds to the power device.

[0011] In some embodiments of the present application, the heat insulation structure comprises an insulating cover layer and a heat insulation core layer, and the insulating cover layer covers the surface of the heat insulation core layer.

[0012] In some embodiments of the present application, the heat insulation core layer comprises a heat insulation material, and the heat insulation material comprises at least one of asbestos, aerogel, rock wool, vacuum board and graphite felt.

[0013] In some embodiments of the present application, the laminated structure further comprises a circuit layer, the power device is electrically connected to the circuit layer, and the solder pad is electrically connected to the circuit layer.

[0014] In some embodiments of the present application, the circuit layer comprises a first circuit layer and a second circuit layer; the first circuit layer is adjacent to the first medium layer, the power device is electrically connected to the first circuit layer, the second circuit layer is adjacent to the protective layer, and the solder pad is electrically connected to the second circuit layer.

[0015] In some embodiments of the present application, the first medium layer further embeds a heat dissipation plate, the power device is arranged on the heat dissipation plate, and a heat dissipation end surface of the heat dissipation plate protrudes out of the first medium layer.

[0016] In some embodiments of the present application, the laminated structure further comprises a first circuit layer; the first medium layer further embeds a first electrode connecting layer, and the power device is connected to the first circuit layer through the first electrode connecting layer.

[0017] In some embodiments of the present application, the first medium layer comprises a first body part and a first packaging part, the first body part and the first packaging part are arranged integrally, and the power device and the first electrode connecting layer are embedded in the first packaging part.

[0018] In some embodiments of the present application, the power device has surface electrodes, the surface electrodes include three independent sub-surface electrodes; the first electrode connecting layer includes three independent sub-electrode connecting layers; the sub-surface electrodes are connected to the sub-electrode connecting layers one by one.

[0019] In some embodiments of the present application, a heat dissipation plate is further embedded in the first dielectric layer, the heat dissipation plate includes an insulating body and conductive layers and heat conductive layers located on two opposite side surfaces of the insulating body; the power device has opposite first and second surfaces, one of the three sub-surface electrodes is distributed on the second surface, and the other two are distributed on the first surface; the sub-surface electrode located on the second surface is connected to the conductive layer, and the conductive layer is further connected to a sub-electrode connecting layer; the heat conductive layer partially extends out of the first dielectric layer.

[0020] In some embodiments of the present application, the dielectric layer further includes a third dielectric layer located on one side of the first dielectric layer, and a second device is embedded in the third dielectric layer.

[0021] In some embodiments of the present application, the laminated structure further includes a third circuit layer adjacent to the third dielectric layer and electrically connected to the second device.

[0022] In some embodiments of the present application, the second device includes at least one of a passive device and a control chip.

[0023] In some embodiments of the present application, a second electrode connecting layer is further embedded in the third dielectric layer, and the second device is connected to the third circuit layer through the second electrode connecting layer.

[0024] In some embodiments of the present application, the third dielectric layer includes a second body part and a second packaging part, the second body part and the second packaging part are integrally arranged, and the second device and the second electrode connecting layer are embedded in the second packaging part.

[0025] In some embodiments of the present application, the second dielectric layer is located between the first dielectric layer and the third dielectric layer.

[0026] In some embodiments of the present application, the packaging structure is provided with a metalized through hole, the metalized through hole penetrates through the laminated structure and is electrically connected to the circuit layer.

[0027] In some embodiments of the present application, the packaging structure further includes a conductive column, the conductive column is arranged in the laminated structure and is electrically connected to the circuit layer.

[0028] In some embodiments of the present application, the medium layer is an organic medium layer, the organic medium layer comprises resin and reinforcing material, the resin comprises at least one of epoxy resin, polytetrafluoroethylene, phenolic resin, polyphenylene ether and bismaleimide triazine resin, and the reinforcing material comprises at least one of paper base, glass cloth and metal core.

[0029] In some embodiments of the present application, the thickness of the circuit layer is 17.5 μm to 140 μm.

[0030] In some embodiments of the present application, the circuit layer comprises at least one of copper, silver and gold.

[0031] In some embodiments of the present application, the power device comprises a silicon carbide power device.

[0032] According to a second aspect of the present application, a preparation method of a packaging structure is provided. The preparation method of the packaging structure comprises:

[0033] providing a first substrate and a second substrate, the first substrate comprising a first medium sheet, and the second substrate comprising a second medium sheet;

[0034] embedding a power device in the first medium sheet of the first substrate;

[0035] stacking the first substrate and the second substrate together, performing a first hot-pressing treatment, and obtaining a packaging structure.

[0036] According to a third aspect of the present application, a circuit board is further provided. The circuit board comprises the packaging structure as described above.

[0037] According to a fourth aspect of the present application, an electronic device is further provided. The electronic device comprises the circuit board as described above. Advantages

[0038] The packaging structure provided by the embodiments of the present application embeds the power device in the first medium layer of the stacked structure, which eliminates the need for an outer shell, sealing glue and the like, reduces the volume and weight of the packaging module, and improves the degree of integration. The stacked structure further comprises a second medium layer, which is located on at least one side of the first medium layer. In this way, the second medium layer can block the heat generated by the power device from being transmitted to at least one surface of the packaging structure to some extent, thereby relieving the thermal influence of the power device on other components on the corresponding surface of the packaging structure when the power device is working.

[0039] Other features and advantages of the present application will be described in detail in the following specific embodiments. BRIEF DESCRIPTION OF DRAWINGS

[0040] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the embodiments description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without any creative effort on the basis of these drawings.

[0041] For a more complete understanding of the present application and its advantages, the following description needs to be taken in conjunction with the drawings, in which the same reference numerals represent the same parts in the following description.

[0042] Fig. 1 is a schematic diagram of a cross-sectional structure of a packaging structure provided in an exemplary embodiment of the present disclosure;

[0043] Fig. 2 is an enlarged schematic diagram of part A in Fig. 1;

[0044] Fig. 3 is an enlarged schematic diagram of part B in Fig. 1;

[0045] Fig. 4 is an enlarged schematic diagram of part C in Fig. 1;

[0046] Fig. 5 is a flowchart of a preparation method of a packaging structure provided in an exemplary embodiment of the present disclosure;

[0047] Figs. 6-10 are flowcharts of preparation of a packaging structure provided in an exemplary embodiment of the present disclosure;

[0048] Fig. 11 is a schematic diagram of a structure of an electronic device provided in an exemplary embodiment of the present disclosure.

[0049] Explanation of reference signs: 10, package structure; 1, laminated structure; 11, circuit layer; 111, first circuit layer; 112, second circuit layer; 113, third circuit layer; 12, dielectric layer; 121, first dielectric layer; 121a, first body part; 121b, first packaging part; 122, second dielectric layer; 123, third dielectric layer; 123a, second body part; 123b, second packaging part; 13, power device; 13a, first surface; 13b, second surface; 131, first electrode connecting layer; 1310, sub-electrode connecting layer; 131a, first sub-electrode connecting layer; 131b, second sub-electrode connecting layer; 131c, third sub-electrode connecting layer; 132, heat sink; 132a, insulating body; 132b, conductive layer; 132c, heat-conductive layer; 133, surface electrode; 1330, sub-surface electrode; 133a, first sub-surface electrode; 133b, second sub-surface electrode; 133c, third sub-surface electrode; 14, second device; 141, second electrode connecting layer; 15, thermal insulation structure; 151, thermal insulation core layer; 152, insulating cover layer; 16, metallized via; 17, conductive column; 2, protective layer; 2a, first protective layer; 2b, second protective layer; 21, pad; 3, first substrate; 31, first dielectric sheet; 32, metal layer; 33, first mounting groove; 34, first hole; 35, second mounting groove; 36, second hole; 37, first positioning hole; 38, first mounting hole; 301, first sub-substrate; 302, second sub-substrate; 4, second substrate; 41, second dielectric sheet; 42, second positioning hole; 43, second mounting hole; 44, third mounting groove; 100, circuit board; 1000, electronic device.

[0050] Embodiments of the present application

[0051] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by a person skilled in the art without creative labor fall within the protection scope of the present application.

[0052] In a first aspect, referring to FIGS. 1-4 and 11, the embodiments of the present application provide a package structure 10, which is used in an electronic device 1000, including but not limited to a mobile terminal, a household appliance, a smart robot, a vehicle, and the like. Taking a vehicle as an example, the vehicle includes a vehicle body and a circuit board 100 arranged on the vehicle body, and the circuit board 100 is provided with the package structure 10.

[0053] Specifically, the packaging structure 10 comprises the laminated structure 1, the laminated structure 1 comprises the dielectric layer 12, the dielectric layer 12 comprises a first dielectric layer 121 and a second dielectric layer 122; at least one side of the first dielectric layer 121 is provided with the second dielectric layer 122, and the power device 13 is embedded in the first dielectric layer 121.

[0054] The dielectric layer 12 refers to a non-conductive layer structure, and is used for electrically isolating some charged structures or charged devices in the laminated structure 1. The dielectric layer 12 can be an organic dielectric layer, which not only has good insulation, but also has the function of heat insulation. The organic dielectric layer contains resin, which can include at least one of epoxy resin, polytetrafluoroethylene, phenolic resin, polyphenylene oxide (PPO) resin and bismaleimide triazine (BT) resin. The organic dielectric layer can also contain reinforcing materials for enhancing the mechanical strength of the organic dielectric layer, which can include at least one of paper-based, glass cloth and metal core.

[0055] The dielectric layer 12 comprises the first dielectric layer 121 and the second dielectric layer 122, and the first dielectric layer 121 and the second dielectric layer 122 refer to different dielectric layers 12. In the laminated structure 1, the number of layers of the first dielectric layer 121 is at least one layer, that is, it can be one layer or multiple layers. In the laminated structure 1, the number of layers of the second dielectric layer 122 is also at least one layer, that is, it can be one layer or multiple layers. The number of layers of the first dielectric layer 121 and the number of layers of the second dielectric layer 122 can be the same or different.

[0056] At least one side of the first dielectric layer 121 is provided with the second dielectric layer 122, which can be that one side of the first dielectric layer 121 is provided with the second dielectric layer 122, or both sides of the first dielectric layer 121 are provided with the second dielectric layer 122. The first dielectric layer 121 and the second dielectric layer 122 can be adjacently arranged or spaced apart, for example, other structures such as the circuit layer 11 are arranged between the first dielectric layer 121 and the second dielectric layer 122.

[0057] The first dielectric layer 121 is a power device layer. The power device 13 is embedded in the first dielectric layer 121. Here, embedding refers to embedding an object as a whole or part into another object. The number of power devices 13 embedded in the first dielectric layer 121 can be one or multiple. The number of layers of the first dielectric layer 121 can be one layer or multiple layers.

[0058] The power device 13 is also referred to as a power electronic device or a power semiconductor device, and is an electronic component capable of processing and controlling electric energy. The main function of the power device 13 is to convert electric energy from one form to another or transmit electric energy to other devices. The power device 13 usually needs to withstand high voltage and current, and has characteristics such as high voltage resistance, large current, and low internal resistance, which enables the power device 13 to efficiently control and transmit electric energy in a circuit. Common power devices 13 include power diodes, thyristors (SCRs), insulated gate bipolar transistors (IGBTs), metal oxide semiconductor field effect transistors (MOSFETs), silicon carbide (SiC) power devices, and gallium nitride (GaN) power devices. As an example, the power device 13 is a silicon carbide power device, which has the advantages of low conduction loss, high switching frequency, and high thermal conductivity, thereby having the advantage of power module miniaturization and integration.

[0059] The second dielectric layer 122 is a heat insulation layer. The second dielectric layer 122 is located on one side of the first dielectric layer 121, so that when the power device 13 is working, the heat generated by the power device 13 is blocked by the second dielectric layer 122, thereby reducing the heat transfer to at least one side surface of the packaging structure 10, and reducing the thermal influence on other components provided on the corresponding surface of the packaging structure 10. The number of layers of the second dielectric layer 122 can be one or more. Generally, the more layers of the second dielectric layer 122, the better the heat insulation effect. Usually, one or more second dielectric layers 122 can be provided on one side of the first dielectric layer 121 to block the heat transfer of the first dielectric layer 121, or one or more second dielectric layers 122 can be provided on both sides of the first dielectric layer 121 to block the heat transfer of the first dielectric layer 121 to both sides.

[0060] The packaging structure 10 provided by the embodiment of the present application embeds the power device 13 in the first dielectric layer 121 of the laminated structure 1, which eliminates the need for an outer shell, sealing glue, and the like, reduces the volume and weight of the packaging module, and improves the degree of integration. The laminated structure 1 further includes a second dielectric layer 122 located on at least one side of the first dielectric layer 121, so that the second dielectric layer 122 can block the heat generated by the power device 13 to at least one side surface of the packaging structure 10 to a certain extent, thereby alleviating the thermal influence of the power device 13 on other components on the corresponding surface of the packaging structure 10 when the power device 13 is working.

[0061] In some embodiments, referring to FIGS. 1 and 2, the packaging structure 10 further includes a protective layer 2 located on the opposite sides of the laminated structure 1, and at least one of the protective layers 2 is provided with a solder pad 21. The second dielectric layer 122 is located between the first dielectric layer 121 and the protective layer 2 provided with the solder pad 21.

[0062] The laminated structure 1 has two opposite surfaces in the thickness direction, and a protective layer 2 is arranged on each of the two surfaces of the laminated structure 1. It can be understood that the number of the protective layer 2 in the packaging structure 10 is two. For the sake of distinction, the protective layer 2 located on one side surface of the laminated structure 1 is referred to as the first protective layer 2a, and the protective layer 2 located on the other side surface of the laminated structure 1 is referred to as the second protective layer 2b. The protective layer 2 is an insulating coating, and the protective layer 2 is used to protect the laminated structure 1 from short circuit and external erosion. As an example, the protective layer 2 is a solder resist layer, and the solder resist layer contains solder resist ink (also known as green oil).

[0063] At least one of the protective layers 2 is provided with a pad 21. The pad 21 can be arranged on the first protective layer 2a, or on the second protective layer 2b, or on both the first protective layer 2a and the second protective layer 2b. The number of the pad 21 arranged on the protective layer 2 can be one or more. The pad 21 is a basic unit of surface mount assembly, and the pad 21 can be used to mount a surface mount device. That is, by arranging the pad 21, other devices (referred to as surface mount devices or STM devices) can be continuously mounted on the packaging structure 10. Here, the surface mount device can be a power device or a non-power device, which is not limited here.

[0064] By arranging the protective layer 2, the laminated structure 1 can be protected by the protective layer 2; by arranging the pad 21 on the protective layer 2, other devices can be continuously mounted on the packaging structure 10; since the second dielectric layer 122 in the laminated structure 1 is located between the protective layer 2 provided with the pad 21 and the first dielectric layer 121, the second dielectric layer 122 can block the heat generated by the power device 13 from being transmitted to the pad 21 to a certain extent, and the heat influence of the power device 13 on the surface mount device during operation is alleviated.

[0065] In some embodiments, referring to FIGS. 1 and 2, the laminated structure 1 further includes a circuit layer 11, the power device 13 is electrically connected to the circuit layer 11, and the pad 21 is connected to the circuit layer 11.

[0066] The laminated structure 1 includes the circuit layer 11 and the dielectric layer 12, and the circuit layer 11 and the dielectric layer 12 are arranged together in a laminated manner, and the dielectric layer 12 can electrically isolate the circuit layer 11 in the laminated structure 1.

[0067] The circuit layer 11 refers to a circuitized metal layer for current transmission. The metal layer can be patterned by laser scribing or wet etching to form the circuit layer 11. The circuit layer 11 can include at least one of copper, silver, and gold. As an example, the circuit layer 11 is a copper layer, and the mass content of copper in the copper layer is higher than 99.8wt%. Copper has good electrical conductivity and thermal conductivity, and is stable in chemical properties and inexpensive. The circuit layer 11 is usually thin, and the thickness of the circuit layer 11 can be 0.5Oz, 1Oz, 2Oz, or 4Oz. Here, Oz is the thickness unit of the circuit layer 11, and 1Oz is equivalent to 35μm. That is, the thickness of the circuit layer 11 can be 17.5μm-140μm, for example, 17.5μm, 30μm, 50μm, 70μm, 90μm, 120μm, or 140μm.

[0068] By arranging the circuit layer 11, the circuit layer 11 is electrically connected with the power device 13 and the pad 21, and the circuit of the power device 13 and the pad 21 is turned on.

[0069] In some embodiments, referring to FIGS. 1 and 2, the circuit layer 11 includes a first circuit layer 111 and a second circuit layer 112. The first circuit layer 111 is adjacent to the first dielectric layer 121, and the power device 13 is electrically connected with the first circuit layer 111. The second circuit layer 112 is adjacent to the protective layer 2, and the pad 21 is electrically connected with the second circuit layer 112.

[0070] The circuit layer 11 includes the first circuit layer 111 and the second circuit layer 112, and the first circuit layer 111 and the second circuit layer 112 refer to different circuit layers 11. The number of layers of the first circuit layer 111 in the laminated structure 1 is at least one, that is, it can be one layer or multiple layers. The first circuit layer 111 is adjacent to the first dielectric layer 121, which means that the first circuit layer 111 is adjacent to and connected with the first dielectric layer 121. The first circuit layer 111 can be arranged on one side surface of the first dielectric layer 121, or the first circuit layer 111 can be arranged on both side surfaces of the first dielectric layer 121. In this way, the number of the first circuit layer 111 is related to the number of the first dielectric layer 121.

[0071] The power device 13 is embedded in the first dielectric layer 121, and the power device 13 is connected with the first circuit layer 111, so as to realize circuit conduction. Alternatively, the power device 13 is entirely embedded in the first dielectric layer 121, and the power device 13 is indirectly connected with the first circuit layer 111 through the first electrode connecting layer 131. Alternatively, the surface electrode on the power device 13 is exposed outside the first dielectric layer 121 and directly connected with the first circuit layer 111.

[0072] The second circuit layer 112 is adjacent to the second protective layer 2, and the second circuit layer 112 can be one layer or two layers. For example, the solder pad 21 can be arranged on the first protective layer 2a, and the solder pad 21 is connected to the second circuit layer 112 adjacent to the first protective layer 2a; or the solder pad 21 can be arranged on the second protective layer 2b, and the solder pad 21 is connected to the second circuit layer 112 adjacent to the second protective layer 2b; or the solder pad 21 can be arranged on both the first protective layer 2a and the second protective layer 2b, and each solder pad 21 is connected to a different second circuit layer 112.

[0073] In the packaging structure 10 provided by the embodiment of the application, the laminated structure 1 includes multiple circuit layers 11 (at least including the first circuit layer 111 and the second circuit layer 112), the power device 13 is connected to the first circuit layer 111 to realize electrical conduction, and the solder pad 21 is connected to the second circuit layer 112 in the laminated structure 1 in proximity, so that more complex electrical connection can be realized.

[0074] In some embodiments, referring to FIG. 2, the packaging structure 10 further includes the first circuit layer 111, the first electrode connecting layer 131 is also embedded in the first dielectric layer 121, and the power device 13 is connected to the first electrode connecting layer 131, and the first electrode connecting layer 131 is connected to the first circuit layer 111, that is, the power device 13 is connected to the first circuit layer 111 through the first electrode connecting layer 131, so as to realize circuit conduction.

[0075] Generally, the first electrode connecting layer 131 is mostly embedded in the first dielectric layer 121, but the first electrode connecting layer 131 still retains an end surface exposed on a side surface of the first dielectric layer 121, so as to be connected to the first circuit layer 111. As an example, the first electrode connecting layer 131 can be a copper electrode, a silver electrode or a gold electrode, etc.

[0076] The packaging structure 10 provided by the embodiment of the application embeds the first electrode connecting layer 131 in the first dielectric layer 121 of the laminated structure 1, and the power device 13 is connected to the first circuit layer 111 in the laminated structure 1 through the first electrode connecting layer 131, so that the participation of the bonding wire is cancelled, and the parasitic inductance is reduced.

[0077] In some embodiments, referring to FIG. 2, the first dielectric layer 121 includes a first body part 121a and a first packaging part 121b, and the power device 13 and the first electrode connecting layer 131 are embedded in the first packaging part 121b.

[0078] The first dielectric layer 121 includes a first body part 121a and a first encapsulation part 121b. The first body part 121a and the first encapsulation part 121b are integrally arranged, for example, the first encapsulation part 121b is inlaid in the first body part 121a. The first encapsulation part 121b is arranged through the first body part 121a. The thickness of the first encapsulation part 121b is equal to the thickness of the first body part 121a. The surface of the first encapsulation part 121b is flush with the surface of the first body part 121a. The main material of the first body part 121a and the main material of the first encapsulation part 121b can be the same or different. Optionally, the main material of the first body part 121a and the main material of the first encapsulation part 121b are different. For example, the main material of the first body part 121a includes epoxy resin, and the main material of the first encapsulation part 121b includes bismaleimide triazine resin. In this way, the first dielectric layer 121 has better performance and is cost-effective, thereby reducing the production cost of the packaging structure 10. It can be understood that the main material of the first body part 121a and the main material of the first encapsulation part 121b are both dielectric materials, for example, organic resin. In addition, the power device 13 and the first electrode connection layer 131 are embedded in the first encapsulation part 121b, which can reduce the manufacturing difficulty.

[0079] In some embodiments, the first dielectric layer 121 further embeds a heat dissipation plate 132. The power device 13 is arranged on the heat dissipation plate 132. The heat dissipation end surface of the heat dissipation plate 132 protrudes out of the first dielectric layer 121.

[0080] The packaging structure 10 further includes a heat dissipation plate 132. The heat dissipation plate 132 is used for dissipating heat of the power device 13. For example, the heat dissipation plate 132 can be an active metal brazing (AMB) ceramic substrate, a direct bond copper (DBC) ceramic substrate, or a graphite plate, etc.

[0081] Exemplarily, the power device 13, the heat sink 132 and the first electrode connecting layer 131 are all embedded in the first packaging portion 121b of the first dielectric layer 121, and the power device 13, the heat sink 132 and the first electrode connecting layer 131 can be fixed and protected by the first packaging portion 121b. In detail, the power device 13 is entirely embedded in the first packaging portion 121b, although the majority of the heat sink 132 and the first electrode connecting layer 131 are embedded in the first packaging portion 121b, the first electrode connecting layer 131 still retains an end face exposed on a side surface of the first packaging portion 121b to be connected with the first circuit layer 111, and the heat sink 132 also retains an end face (specifically, a heat dissipation end face) exposed on a side surface of the first packaging portion 121b to dissipate heat. In the first packaging portion 121b, the heat sink 132 and the first electrode connecting layer 131 are both connected with the power device 13. Among them, the power device 13 is connected with one end of the first electrode connecting layer 131, and the other end of the first electrode connecting layer 131 extends to a side surface of the first packaging portion 121b and is connected with the first circuit layer 111, so that the power device 13 is electrically connected with the first circuit layer 111 through the first electrode connecting layer 131. The power device 13 is arranged on a side surface of the heat sink 132, for example, the power device 13 is welded on the heat sink 132, and the other side surface of the heat sink 132 is exposed on the other side surface of the first packaging portion 121b and is connected with another circuit layer 11 (for example, the second circuit layer 112), and the second circuit layer 112 is adjacent to the first dielectric layer 121 in addition to being adjacent to the protective layer 2, and the power device 13 can transfer heat to the second circuit layer 112 through the heat sink 132 to dissipate heat. Here, the heat sink 132 is connected with the second circuit layer 112, and only heat transfer can be achieved between the heat sink 132 and the second circuit layer 112, and current flow cannot be achieved, that is, the heat sink 132 and the second circuit layer 112 are in thermal conduction connection. Alternatively, the second dielectric layer 122 is located on a side of the first dielectric layer 121 away from the heat sink 132.

[0082] By arranging the heat sink 132 to dissipate heat for the power device 13, the risk of thermal failure of the power device 13 is reduced.

[0083] Of course, in other embodiments, the first dielectric layer 121 can also only include the first body portion 121a, and the power device 13, the heat sink 132 and the first electrode connecting layer 131 are all embedded in the first body portion 121a.

[0084] In some embodiments, referring to FIG. 2, the power device 13 has a surface electrode 133, the surface electrode 133 includes three independent sub-surface electrodes 1330; the first electrode connecting layer 131 includes three independent sub-electrode connecting layers 1310; and the sub-surface electrodes 1330 and the sub-electrode connecting layers 1310 are connected one by one.

[0085] Specifically, taking the power device 13 as a metal-oxide-semiconductor field-effect transistor as an example, the surface electrode 133 of the power device 13 includes three independent sub-surface electrodes 1330, namely a first sub-surface electrode 133a, a second sub-surface electrode 133b and a third sub-surface electrode 133c, wherein the first sub-surface electrode 133a is a gate (G), the second sub-surface electrode 133b is a source (S), and the third sub-surface electrode 133c is a drain (D), which respectively undertake the functions of control, input and output.

[0086] The first electrode connecting layer 131 includes three independent sub-electrode connecting layers 1310, namely a first sub-electrode connecting layer 131a, a second sub-electrode connecting layer 131b and a third sub-electrode connecting layer 131c.

[0087] The sub-surface electrodes 1330 and the sub-electrode connecting layers 1310 are connected one by one, that is, the first sub-surface electrode 133a and the first sub-electrode connecting layer 131a are connected in turn, the second sub-surface electrode 133b and the second sub-electrode connecting layer 131b are connected in turn, and the third sub-surface electrode 133c and the third sub-electrode connecting layer 131c are connected in turn.

[0088] By setting multiple independent sub-electrode connecting layers 1310, different sub-surface electrodes 1330 are respectively connected with the circuit layer 11, thereby ensuring the stability and reliability of the power device 13.

[0089] In some embodiments, referring to FIG. 2, the heat sink 132 includes an insulating body 132a and a conductive layer 132b and a heat-conductive layer 132c located on the two opposite surfaces of the insulating body 132a; the power device 13 has a first surface 13a and a second surface 13b opposite to each other, one of the three sub-surface electrodes 1330 is distributed on the second surface 13b, and the other two are distributed on the first surface 13a; the sub-surface electrode 1330 located on the second surface is connected with the conductive layer 132b, and the conductive layer 132b is also connected with a sub-electrode connecting layer 1310; the heat-conductive layer 132c partially extends out of the first dielectric layer 121.

[0090] Specifically, the heat dissipation plate 132 includes an insulating body 132a, an electrically conductive layer 132b and a thermally conductive layer 132c, which constitute a sandwich structure, i.e. the insulating body 132a is in the middle, the electrically conductive layer 132b and the thermally conductive layer 132c are respectively located on both sides of the insulating body 132a, and the insulating body 132a is spaced apart from the electrically conductive layer 132b and the thermally conductive layer 132c, so that the electrically conductive layer 132b and the thermally conductive layer 132c cannot be electrically connected. In this way, the electrically conductive layer 132b and the thermally conductive layer 132c can both be set as metal layers, because metal has good electrical conductivity, thermal conductivity and molding effect. Optionally, the insulating body 132a is a ceramic sheet. Taking the DBC ceramic substrate as an example, the DBC ceramic substrate has a copper-ceramic-copper three-layer structure, wherein the ceramic in the middle is the insulating body 132a, and the copper layers on both sides are the electrically conductive layer 132b and the thermally conductive layer 132c respectively. Optionally, the thermally conductive layer 132c is connected with the second circuit layer 112.

[0091] When the heat dissipation plate 132 is connected with the power device 13, the electrically conductive layer 132b on the heat dissipation plate 132 is connected with the power device 13 to realize electrical conduction, and the thermally conductive layer 132c on the heat dissipation plate 132 partially extends out of the first packaging portion 121b, which is beneficial to dissipate heat.

[0092] The power device 13 has two opposite surfaces, i.e. a first surface 13a and a second surface 13b, wherein the second surface 13b faces the heat dissipation plate 132. Generally, the heat dissipation plate 132 is larger than the power device 13, i.e. the top surface area of the electrically conductive layer 132b in the heat dissipation plate 132 is larger than the surface area of the second surface 13b of the power device 13.

[0093] The surface electrode 133 on the power device 13 includes a first sub-surface electrode 133a, a second sub-surface electrode 133b and a third sub-surface electrode 133c, the first sub-surface electrode 133a and the second sub-surface electrode 133b are spaced apart and distributed on the first surface 13a of the power device 13, and the third sub-surface electrode 133c is independently distributed on the second surface 13b of the power device 13.

[0094] The first electrode connecting layer 131 includes a first sub-electrode connecting layer 131a, a second sub-electrode connecting layer 131b and a third sub-electrode connecting layer 131c, wherein the first sub-electrode connecting layer 131a and the second sub-electrode connecting layer 131b are opposite to the first surface 13a of the power device 13, and the third sub-electrode connecting layer 131c is staggered with the power device 13, and the third sub-electrode connecting layer 131c is arranged on the conductive layer 132b of the heat dissipation plate 132, and the third sub-electrode connecting layer 131c is electrically connected with the third sub-surface electrode 133c through the conductive layer 132b. In this way, the first sub-electrode connecting layer 131a, the second sub-electrode connecting layer 131b and the third sub-electrode connecting layer 131c are all located on one side of the heat dissipation plate 132 and all extend away from the heat dissipation plate 132, so that the first sub-electrode connecting layer 131a, the second sub-electrode connecting layer 131b and the third sub-electrode connecting layer 131c are all connected with the same circuit layer 11 on one side of the first dielectric layer 121, that is, the first circuit layer 111.

[0095] By the above arrangement, the three sub-electrode connecting layers 1310 can be led out on the same side of the first dielectric layer 121, and the three sub-electrode connecting layers 1310 are connected with the same circuit layer 11.

[0096] In some embodiments, referring to FIG. 3, the second dielectric layer 122 is inlaid with the heat insulation structure 15.

[0097] The heat insulation structure 15 inlaid in the second dielectric layer 122 can be that the heat insulation structure 15 penetrates through the second dielectric layer 122, or that three sides of the heat insulation structure 15 are surrounded by the second dielectric layer 122, or that the heat insulation structure 15 is entirely surrounded by the second dielectric layer 122. The number of the heat insulation structure 15 in the second dielectric layer 122 can be one or more.

[0098] By arranging the heat insulation structure 15 in the second dielectric layer 122, the heat insulation structure 15 can better block the propagation of heat, thereby improving the heat insulation effect of the second dielectric layer 122.

[0099] In some embodiments, referring to FIG. 1, the position of the heat insulation structure 15 in the second dielectric layer 122 corresponds to the position of the power device 13 in the first dielectric layer 121. Alternatively, in the radial direction, the size of the heat insulation structure 15 is greater than the size of the power device 13.

[0100] By arranging the heat insulation structure 15 to correspond to the power device 13, the heat insulation structure 15 can effectively block the propagation of heat, thereby improving the heat insulation effect of the second dielectric layer 122.

[0101] In some embodiments, the thermal insulation structure 15 at least includes a thermal insulation core layer 151, which includes a thermal insulation material with a high thermal resistance value to prevent heat transfer. As an example, the thermal insulation material includes at least one of asbestos, aerogel, rock wool, vacuum board, and graphite felt.

[0102] In some embodiments, the thermal insulation structure 15 includes the thermal insulation core layer 151 and an insulating cover layer 152.

[0103] The thermal insulation structure 15 can further include the insulating cover layer 152, which covers the surface of the thermal insulation core layer 151. The insulating cover layer 152 can cover one side surface of the thermal insulation core layer 151, both side surfaces, or even completely cover the thermal insulation core layer 151. When the thermal insulation structure 15 is arranged through the second medium layer 122, the insulating cover layer 152 can be used to completely cover the thermal insulation core layer 151, which can effectively prevent the circuit layer 11 on both sides of the second medium layer 122 from being conducted through the thermal insulation structure 15. The insulating cover layer 152 includes an insulating medium. As an example, the insulating medium includes resin.

[0104] In some embodiments, referring to FIG. 4, the medium layer 12 further includes a third medium layer 123, which is located on one side of the first medium layer 121, and the second device 14 is embedded in the third medium layer 123.

[0105] That is, in addition to including the first medium layer 121 and the second medium layer 122, the laminated structure 1 can further include the third medium layer 123, which is located on one side of the first medium layer 121. The number of the third medium layer 123 can be one or multiple. The third medium layer 123 can be distributed in various positions in the laminated structure 1. As an example, the laminated structure 1 includes three medium layers 12, i.e., the first medium layer 121, the second medium layer 122, and the third medium layer 123. The third medium layer 123 can be located between the first medium layer 121 and the second medium layer 122, the first medium layer 121 can be located between the third medium layer 123 and the second medium layer 122, or the second medium layer 122 can be located between the first medium layer 121 and the third medium layer 123.

[0106] The second device 14 embedded in the third medium layer 123 refers to other devices other than power devices. Optionally, the second device 14 includes at least one of a passive device and a control chip. As an example, the passive device includes at least one of a temperature control element, a temperature sensing element, a strain gauge, a resistor, and a capacitor. The control chip includes a processor. The number of the second device 14 in the third medium layer 123 can be one or multiple.

[0107] For more clearly distinguishing the power device 13 and the second device 14, the power device 13 is taken as a power chip and the second device 14 is taken as a current control chip as an example for description, wherein the power chip is a switching device capable of controlling on-off of a large current, and the current control chip is capable of controlling magnitude and direction of an output current according to an input signal, and does not flow a large current itself. In some cases, the current control chip can be used as a driving chip of the power chip.

[0108] By arranging the third dielectric layer 123 in the laminated structure 1 and embedding the second device 14 in the third dielectric layer 123, different second devices 14 have different functions, so that the third dielectric layer 123 can be functionalized by introducing different second devices 14, thereby expanding the use of the packaging structure 10.

[0109] In addition, since the power device 13 generates a large amount of heat during operation, the power device 13 is arranged in the first dielectric layer 121 to facilitate heat management (including heat dissipation and heat insulation), and the second device 14 is arranged in the third dielectric layer 123, which is used as a functional layer.

[0110] In some embodiments, the number of second devices 14 is multiple, and the third dielectric layer 123 includes multiple sub-layers arranged in a stack, and the multiple second devices 14 can be arranged in different sub-layers, respectively. Here, the sub-layers of the third dielectric layer 123 can be directly connected.

[0111] In some embodiments, the laminated structure 1 further includes a third circuit layer 113 adjacent to the third dielectric layer 123, and the second device 14 is electrically connected to the third circuit layer 113.

[0112] Generally, the third circuit layer 113 to which the second device 14 is connected is not the same circuit layer 11 as the first circuit layer 111 to which the power device 13 is connected.

[0113] By embedding the second device 14 in the third dielectric layer 123 and connecting the second device 14 to the third circuit layer 113, electrical conduction is achieved.

[0114] In some embodiments, referring to FIG. 4, a second electrode connecting layer 141 is also embedded in the third dielectric layer 123, the second device 14 is connected to the second electrode connecting layer 141, and the second device 14 is connected to the third circuit layer 113 through the second electrode connecting layer 141.

[0115] The packaging structure 10 further includes a second electrode connecting layer 141 for electrically connecting the second device 14 to the nearest circuit layer 11, i.e., the third circuit layer 113. As an example, the second electrode connecting layer 141 can be a copper electrode, a silver electrode, or a gold electrode, etc.

[0116] The second electrode connecting layer 141 is arranged to electrically connect the second device 14 and the third circuit layer 113, and can effectively reduce the parasitic inductance compared with a bonding wire.

[0117] In some embodiments, referring to FIG. 4, the third dielectric layer 123 includes a second body part 123a and a second packaging part 123b, and the second device 14 and the second electrode connecting layer 141 are embedded in the second packaging part 123b.

[0118] The third dielectric layer 123 includes the second body part 123a and the second packaging part 123b, and the second body part 123a and the second packaging part 123b are integrally arranged, for example, the second packaging part 123b is inlaid in the second body part 123a. The second packaging part 123b is arranged through the second body part 123a, the thickness of the second packaging part 123b is equal to the thickness of the second body part 123a, and the surface of the second packaging part 123b is flush with the surface of the second body part 123a. The main material of the second body part 123a and the main material of the second packaging part 123b can be the same or different.

[0119] Specifically, the second device 14 and the second electrode connecting layer 141 are both embedded in the second packaging part 123b, and the second device 14 and the second electrode connecting layer 141 can be fixed and protected by the second packaging part 123b. In detail, the second device 14 is entirely embedded in the second packaging part 123b, and most of the second electrode connecting layer 141 is embedded in the second packaging part 123b, and the second electrode connecting layer 141 still retains an end face exposed on one side surface of the second packaging part 123b to be connected with the third circuit layer 113. In the second packaging part 123b, the second electrode connecting layer 141 is connected with the second device 14, so that the second device 14 is electrically connected with the circuit layer 11 through the second electrode connecting layer 141.

[0120] By arranging the third dielectric layer 123 to include the second body part 123a and the second packaging part 123b, and embedding the second device 14 and the second electrode connecting layer 141 by the second packaging part 123b, it is beneficial to control the cost and manufacturing difficulty of the packaging structure 10.

[0121] Of course, in other embodiments, the third dielectric layer 123 can only include the second body part 123a, and the second device 14 and the second electrode connecting layer 141 are both embedded in the second body part 123a.

[0122] In some embodiments, referring to FIG. 1, the second dielectric layer 122 is located between the first dielectric layer 121 and the third dielectric layer 123.

[0123] In this way, the second dielectric layer 122 can better separate the first dielectric layer 121 from the third dielectric layer 123, reducing the thermal impact of heat propagation on the second device 14 when the power device 13 is working.

[0124] In some embodiments, please refer to FIG1, the package structure 10 is provided with a metallized via 16, which penetrates the stacked structure 1 and is electrically connected to the circuit layer 11.

[0125] The metallized via 16, also known as a PTH (Plating Through Hole), refers to a hole with conductive metal on its inner side, such as copper foil on the inner side. The metallized via 16 penetrates the stacked structure 1, that is, it penetrates both the circuit layer 11 and the dielectric layer 12. The metallized via 16 is electrically connected to the circuit layer 11. For example, the circuit layer 11 includes a first circuit layer 111, a second circuit layer 112, and a third circuit layer 113. The metallized via 16 is electrically connected to all three circuit layers, and electrical connections between different circuit layers 11 can be achieved through the metallized via 16.

[0126] By utilizing metallized vias 16 as pathways for interlayer circuit connections, electrical connections between circuit layers 11 in the stacked structure 1 can be achieved.

[0127] In some embodiments, referring to FIG1, the encapsulation structure 10 further includes conductive pillars 17, which pass through the stacked structure 1 and are electrically connected to the circuit layer 11.

[0128] The conductive post 17 is a metal post. For example, the conductive post 17 is a copper post. The conductive post 17 passes through the laminated structure 1, that is, it passes through the circuit layer 11 and the dielectric layer 12. The conductive post 17 has a large cross-sectional area, resulting in a smaller interlayer resistance than the metallized via 16, and can carry a larger overcurrent. Simultaneously, the copper post penetrates between layers, and the high thermal conductivity of metal results in a small overcurrent temperature rise, providing a heat dissipation channel for the heat generated by the components in the laminated structure 1. The conductive post 17 is electrically connected to the circuit layer 11. For example, the circuit layer 11 includes a first circuit layer 111, a second circuit layer 112, and a third circuit layer 113. The conductive post 17 is electrically connected to all three circuit layers, thus enabling electrical connection between different circuit layers 11 via the conductive post 17.

[0129] By inserting conductive pillars 17 through the stacked structure 1, the conductive pillars 17 can not only serve as a path for conducting large currents between layers, but also as a heat dissipation channel, thereby improving the heat dissipation effect of the encapsulation structure 10.

[0130] Secondly, referring to Figure 5, this application embodiment also provides a method for preparing the encapsulation structure 10, including:

[0131] S1, providing a first substrate 3 and a second substrate 4, the first substrate 3 comprising a first dielectric sheet 31, and the second substrate 4 comprising a second dielectric sheet 41;

[0132] S2, embedding a power device 13 in the first dielectric sheet 31 of the first substrate 3;

[0133] S3, stacking the first substrate 3 and the second substrate 4 together, and performing a first heat pressing treatment to obtain a packaging structure 10.

[0134] The packaging structure 10 provided by the embodiment of the present application has a simple preparation method and is easy to manufacture. The packaging structure 10 obtained by embedding the power device 13 in the first dielectric sheet 31 of the layer structure 1 eliminates the need for an outer shell, sealing glue and the like, reduces the volume and weight of the packaging module, and improves the degree of integration. The first substrate 3 and the second substrate 4 are stacked together in the packaging structure 10, and the second dielectric sheet 41 is located on one side of the first dielectric sheet 31. In this way, the second dielectric sheet 41 can block the heat generated by the power device 13 from being transmitted to at least one side surface of the packaging structure 10, thereby relieving the thermal influence of the power device 13 on the components on the corresponding surface of the packaging structure 10 when the power device 13 is working.

[0135] In some embodiments, referring to FIGS. 5 to 10, the embodiment of the present application provides a preparation method of a packaging structure 10, comprising:

[0136] S1, providing a first substrate 3 and a second substrate 4, the first substrate 3 comprising a first dielectric sheet 31, and the second substrate 4 comprising a second dielectric sheet 41;

[0137] S2, embedding a power device 13 in the first dielectric sheet 31 of the first substrate 3, connecting the power device 13 with the metal layer 32 on one side surface of the first dielectric sheet 31, and etching the metal layer 32 connected with the power device 13 into a first circuit layer 111;

[0138] S31, stacking the first substrate 3 and the second substrate 4 together, and performing a first heat pressing treatment to obtain a layer structure 1, at least one side surface of the layer structure 1 being a metal layer 32, and the second dielectric sheet 41 being located between the metal layer 32 on one side surface of the layer structure 1 and the first dielectric sheet 31;

[0139] S32, etching the metal layer 32 on the surface of the layer structure 1 into a patterned second circuit layer 112;

[0140] S33, arranging a protective layer 2 on the opposite two side surfaces of the layer structure 1, respectively;

[0141] S34, at least on the protection layer 2 adjacent to the second circuit layer 112, a pad 21 is arranged, and a packaging structure 10 is obtained.

[0142] Specifically, in step S1, the first substrate 3 and the second substrate 4 are provided, wherein the number of the first substrate 3 can be one or multiple, and the number of the second substrate 4 can be one or multiple, and the number of the first substrate 3 and the second substrate 4 finally affects the structure of the obtained packaging structure 10.

[0143] The first substrate 3 and the second substrate 4 can be self-made or purchased.

[0144] The first substrate 3 includes a first dielectric sheet 31, and at least one side surface of the first dielectric sheet 31 is provided with a metal layer 32. It can be understood that the first substrate 3 is a multi-layer structure. As an example, the first substrate 3 can be a sandwich structure of "metal layer-first dielectric sheet-metal layer"; the first substrate 3 can also be a double-layer structure of "first dielectric sheet-metal layer".

[0145] The second substrate 4 includes a second dielectric sheet 41, and at most one side surface of the second dielectric sheet 41 is provided with a metal layer 32. As an example, the second substrate 4 can be a double-layer structure of "second dielectric sheet-metal layer", or a single-layer structure including only the second dielectric sheet.

[0146] The first dielectric sheet 31 contains a non-conductive dielectric material. Optionally, the dielectric material includes a resin, which can include at least one of an epoxy resin, a polytetrafluoroethylene, a phenol resin, a polyphenylene oxide (PPO) resin, and a bismaleimide triazine (BT) resin. The first dielectric sheet 31 can also contain a reinforcing material for enhancing the mechanical strength of the first dielectric sheet 31, and the reinforcing material can include at least one of a paper base, a glass cloth, and a metal core. As an example, the first substrate 3 can be a double-sided copper-clad plate.

[0147] The second dielectric sheet 41 is similar to the first dielectric sheet 31, and the second dielectric sheet 41 also contains a non-conductive dielectric material such as a resin. The second dielectric sheet 41 can also contain a reinforcing material. As an example, the first dielectric sheet 31 and the second dielectric sheet 41 are both semi-cured sheets (also known as PP sheets).

[0148] Referring to FIG. 6, in step S2, the power device 13 is embedded in the first substrate 3. When the number of the first substrate 3 is multiple, the power device 13 can be embedded in one of the first substrates 3, or in several of the first substrates 3, or in all of the first substrates 3. Moreover, the number of the power device 13 embedded in a single first substrate 3 can be one or multiple.

[0149] Referring to FIG. 9, in step S31, when the laminated structure 1 is prepared, the laminated structure 1 can be made to have at least one side surface of the laminated structure 1 as the metal layer 32, and the second dielectric sheet 41 between the metal layer 32 on the side surface of the laminated structure 1 and the first dielectric sheet 31 by adjusting the number, configuration and / or stacking order of the first substrate 3 and the second substrate 4.

[0150] Here, the laminated structure 1 can have one side surface as the metal layer 32, or both side surfaces of the laminated structure 1 as the metal layer 32. The second dielectric sheet 41 is between the metal layer 32 on the side surface of the laminated structure 1 and the first dielectric sheet 31, and when both side surfaces of the laminated structure 1 are the metal layer 32 and the number of the second dielectric sheet 41 is only one, the second dielectric sheet 41 can be arranged between the metal layer 32 on one side of the laminated structure 1 and the first dielectric sheet 31, and the metal layer 32 on the other side of the laminated structure 1 can also be adjacent to the first dielectric sheet 31. In this case, at least the pad 21 on one side of the laminated structure 1 can be further spaced apart from the first dielectric sheet 31.

[0151] For example, a first substrate 3 configured as "metal layer-first dielectric sheet-metal layer" and a second substrate 4 configured as "second dielectric sheet-metal layer" are stacked in sequence to obtain a laminated structure 1 configured as "metal layer-first dielectric sheet-metal layer-second dielectric sheet-metal layer".

[0152] For example, a first substrate 3 configured as "first dielectric sheet-metal layer" and a second substrate 4 configured as "second dielectric sheet-metal layer" are stacked in sequence to obtain a laminated structure 1 configured as "first dielectric sheet-metal layer-second dielectric sheet-metal layer".

[0153] When the number of the first substrate 3 is more than one, at least one of the first substrates 3 has the power device 13 embedded therein. Thus, when the first substrate 3 is stacked in preparing the laminated structure 1, the first circuit layer 111 on the first substrate 3 can be arranged inwardly, or the first circuit layer 111 on the first substrate 3 can be arranged outwardly.

[0154] For example, a first substrate 3 configured as "first circuit layer-first dielectric sheet-metal layer", a second substrate 4 configured as "second dielectric sheet", and a first substrate 3 configured as "metal layer-first dielectric sheet-metal layer" are stacked in sequence to obtain a laminated structure 1 configured as "first circuit layer-first dielectric sheet-metal layer-second dielectric sheet-metal layer-first dielectric sheet-metal layer".

[0155] As an example, a piece of second substrate 4 configured as "metal layer-second dielectric sheet" and a piece of first substrate 3 configured as "first circuit layer-first dielectric sheet-metal layer" are stacked together in sequence, a laminated structure 1 configured as "metal layer-second dielectric sheet-first circuit layer-first dielectric sheet-metal layer" can be obtained.

[0156] That is, the first circuit layer 111 in the laminated structure 1 can be located on the surface of the laminated structure 1 or inside the laminated structure 1. Optionally, the first circuit layer 111 is located inside the laminated structure 1, which can reduce the damage to the fine circuit on the first circuit layer 111 in the process of pressing in the first heat pressing process.

[0157] As an example, the metal layer 32 on the surface of the laminated structure 1 is etched into the second circuit layer 112 in step S32. If the laminated structure 1 has a metal layer 32 on one side surface, one second circuit layer 112 can be obtained by etching. If the laminated structure 1 has a metal layer 32 on both side surfaces, two second circuit layers 112 can be obtained by etching. As an example, the metal layer 32 can be etched into the second circuit layer 112 by wet etching.

[0158] As an example, the laminated structure 1 has a structure of "first circuit layer-first dielectric sheet-metal layer-second dielectric sheet-metal layer-first dielectric sheet-metal layer", and after etching the metal layer 32 on the surface, a laminated structure 1 with a structure of "first circuit layer-first dielectric sheet-metal layer-second dielectric sheet-metal layer-first dielectric sheet-second circuit layer" can be obtained.

[0159] As an example, the metal layer 32 on the surface of the laminated structure 1 is etched into the second circuit layer 112 in step S32. If the laminated structure 1 has a metal layer 32 on one side surface, one second circuit layer 112 can be obtained by etching. If the laminated structure 1 has a metal layer 32 on both side surfaces, two second circuit layers 112 can be obtained by etching. As an example, the metal layer 32 can be etched into the second circuit layer 112 by wet etching.

[0160] As an example, the metal layer 32 on the surface of the laminated structure 1 is etched into the second circuit layer 112 in step S32. If the laminated structure 1 has a metal layer 32 on one side surface, one second circuit layer 112 can be obtained by etching. If the laminated structure 1 has a metal layer 32 on both side surfaces, two second circuit layers 112 can be obtained by etching. As an example, the metal layer 32 can be etched into the second circuit layer 112 by wet etching.

[0161] The preparation method of the packaging structure 10 provided by the embodiments of the present application is simple in process, beneficial for manufacturing, and the prepared packaging structure 10 is obtained by embedding the power device 13 in the first dielectric sheet 31 of the laminated structure 1, and connecting the power device 13 with the first circuit layer 111 in the laminated structure 1, which omits the shell, sealing glue and the like, reduces the volume and weight of the packaging module, and improves the integration degree. The packaging structure 10 further comprises a protective layer 2, and the solder pad 21 is arranged on the protective layer 2, and other components can be continuously attached on the surface of the packaging structure 10 by using the solder pad 21, and the second dielectric sheet 41 in the laminated structure 1 is located between the solder pad 21 and the first dielectric sheet 31, so that the second dielectric sheet 41 can block the heat generated by the power device 13 from being transmitted to the solder pad 21, and the thermal influence of the power device 13 on the surface-mounted components during operation is alleviated.

[0162] In some embodiments, the two side surfaces of the first dielectric sheet 31 are provided with the metal layer 32, and the two side surfaces of the second dielectric sheet 41 are not provided with the metal layer 32, that is, the first substrate 3 comprises the first dielectric sheet 31 and the metal layer 32, and the second substrate 4 only comprises the second dielectric sheet 41. The number of the first substrate 3 is one more than the number of the second substrate 4. It can be understood that the number of the first substrate 3 is multiple, that is, at least two, and the number of the second substrate 4 is at least one, that is, the number of the second dielectric sheet 41 can be one or multiple.

[0163] The first substrate 3 comprises the first dielectric sheet 31 and the metal layer 32 which are laminated, and the metal layer 32 is located on the two opposite side surfaces of the first dielectric sheet 31. That is, the first substrate 3 is a sandwich structure of "metal layer-first dielectric sheet-metal layer", the first dielectric sheet 31 is located in the middle, the metal layer 32 is located on the two sides, and the first dielectric sheet 31 separates the two metal layers 32.

[0164] Hereinafter, the first substrate 3 comprises the first dielectric sheet 31 and the metal layer 32 on the two sides, and the second substrate 4 only comprises the second dielectric sheet 41.

[0165] In some embodiments, the first substrate 3 is prepared, and the preparation of the first substrate 3 comprises the following steps:

[0166] S11, providing a metal foil, and pre-treating the metal foil. The metal foil is used to form the metal layer 32. Optionally, the metal foil includes at least one of a copper foil, a silver foil, and a gold foil. As an example, the metal foil is a copper foil, and the mass content of copper in the copper foil is higher than 99.8wt%. Copper has good electrical conductivity and thermal conductivity, and is stable in chemical properties and inexpensive. The copper foil is usually thin, and as an example, the thickness of the copper foil can be 0.5Oz, 1Oz, 2Oz, or 4Oz. The pre-treatment of the metal foil includes, but is not limited to, at least one of cutting, degreasing, pickling, washing, pre-impregnation, brown oxidation, and black oxidation. As an example, the pre-treatment of the metal foil includes cutting, and the size of the metal foil after cutting is slightly larger than the size of the first dielectric sheet 31, so as to ensure that the metal foil can completely cover one side surface of the first dielectric sheet 31.

[0167] S12, providing the first dielectric sheet 31, and attaching the metal foil to both side surfaces of the first dielectric sheet 31 and combining the metal foil with the first dielectric sheet 31 through a second hot-pressing process. As an example, the second hot-pressing process can include a vacuum lamination process, i.e., using a vacuum laminator to press the upper and lower metal foils and the first dielectric sheet 31 together under vacuum conditions. Then, the excess part of the glue overflow can be cut off.

[0168] In some embodiments, step S2 specifically includes embedding the power device 13 in the first dielectric sheet 31 of at least one first substrate 3. In order to distinguish, the first substrate 3 used for embedding the power device 13 is referred to as a first sub-substrate 301. That is, at least one first substrate 3 in the plurality of first substrates 3 is the first sub-substrate 301. One power device 13 or a plurality of power devices 13 can be embedded in the first dielectric sheet 31.

[0169] In some embodiments, referring to FIG. 6, the process of embedding the power device 13 in the first dielectric sheet 31 of the first substrate 3 (specifically, the first sub-substrate 301) includes the following steps:

[0170] S211, providing the power device 13. As an example, the power device 13 includes at least one of a power diode, a thyristor (SCR), an insulated gate bipolar transistor (IGBT), a metal oxide semiconductor field effect transistor (MOSFET), a silicon carbide (SiC) power device, and a gallium nitride (GaN) power device.

[0171] S212, please refer to FIG. 6(a) and FIG. 6(b), a first mounting groove 33 is formed on the first substrate 3, the first mounting groove 33 extends into the first dielectric sheet 31 at least. As an example, the first substrate 3 can be partially thinned along the thickness direction of the first substrate 3 by laser etching or mechanical processing to obtain the first mounting groove 33. As an example, the first mounting groove 33 can be obtained by slotting. Since the metal layer 32 is thin, in order to ensure that the first mounting groove 33 has sufficient depth to accommodate the power device 13, the first mounting groove 33 will at least partially extend into the first dielectric sheet 31, that is, at least part of the first dielectric sheet 31 will be etched. The first mounting groove 33 can extend through the first dielectric sheet 31 or not, but the first mounting groove 33 at least extends through the metal layer 32 on one side of the first dielectric sheet 31.

[0172] S213, please refer to FIG. 6(c) and FIG. 6(d), the power device 13 is placed in the first mounting groove 33, and a dielectric material is backfilled in the first mounting groove 33 to obtain a first packaging portion 121b, and the power device 13 is embedded in the first packaging portion 121b. The dielectric material backfilled in the first mounting groove 33 and the dielectric material in the first dielectric sheet 31 can be the same or different. The dielectric material commonly used to backfill the first mounting groove 33 is liquid, so that the dielectric material can better coat the power device 13, and then a solidifying agent, heating or light can be used to solidify the dielectric material to form the first packaging portion 121b, and the power device 13 is embedded in the first packaging portion 121b. As an example, the dielectric material includes epoxy resin. Optionally, the top surface of the first packaging portion 121b is flush or substantially flush with the surface of the first dielectric sheet 31.

[0173] S214, please refer to FIG. 6 (e) and FIG. 6 (f), a first hole 34 is opened on the first packaging part 121b to expose the power device 13, a metal layer is deposited in the first hole 34 to form a first electrode connecting layer 131, and the metal layer 32 on the surface of the first packaging part 121b is restored, the first electrode connecting layer 131 is electrically connected with the power device 13 and the metal layer 32. As an example, the first hole 34 can be obtained by etching the first packaging part 121b by laser etching, the depth of the first hole 34 is determined by the exposed part of the power device 13, which is referred to as the power device 13. The exposed part of the power device 13 is the surface electrode 133. The metal layer is filled in the first hole 34 by metal deposition, thereby forming a metal deposition layer filling the first hole 34, which is the first electrode connecting layer 131, and the first electrode connecting layer 131 is electrically connected with the power device 13. Since the metal layer 32 on one side of the first dielectric sheet 31 has been etched away when the first mounting groove 33 is opened, the surface of the first packaging part 121b formed later no longer has the metal layer 32, and therefore the metal layer 32 on the surface of the first packaging part 121b needs to be restored.

[0174] It can be understood that in the first substrate 3 after the power device 13 is buried, the power device 13 is connected with the first electrode connecting layer 131 and both are located in the first dielectric sheet 31, and the first electrode connecting layer 131 is also connected with the metal layer 32 on one side of the first dielectric sheet 31.

[0175] Optionally, in order to dissipate heat for the power device 13, a heat sink 132 is also buried in the first dielectric sheet 31 of the first substrate 3, and the step S2 further comprises:

[0176] In step S211, the heat sink 132 is additionally provided, and the power device 13 is arranged on the heat sink 132. For example, the power device 13 is welded on the heat sink 132.

[0177] In step S212, the first mounting groove 33 is arranged to penetrate the first dielectric sheet 31, so that the bottom wall of the first mounting groove 33 is the metal layer 32, which is the metal layer 32 on the side of the first substrate 3 away from the opening of the first mounting groove 33.

[0178] In step S213, the power device 13 and the heat sink 132 are placed in the first mounting groove 33 together, and the heat sink 132 is located on the metal layer 32, and then the first packaging part 121b is arranged in the first mounting groove 33, the heat sink 132 is also buried in the first packaging part 121b, and the heat sink 132 is in thermal connection with the metal layer 32.

[0179] With reference to FIGS. 2 and 6, the process of embedding the power device 13 and the heat sink 132 into the first substrate 3 will be described in more detail below, taking the power device 13 as a metal-oxide-semiconductor field-effect transistor as an example.

[0180] In detail, the first surface 13a of the power device 13 is provided with a first sub-surface electrode 133a and a second sub-surface electrode 133b at intervals, and the second surface 13b of the power device 13 is provided with a third sub-surface electrode 133c.

[0181] The heat sink 132 is provided, and the area of the heat sink 132 is greater than the area of the power device 13. The heat sink 132 includes an insulating body 132a and an electrically-conductive layer 132b and a thermally-conductive layer 132c on the two side surfaces of the insulating body 132a. The heat sink 132 and the power device 13 are thermally compressed together by vacuum hot pressing, so that the third sub-surface electrode 133c is connected together with the electrically-conductive layer 132b on the heat sink 132.

[0182] The heat sink 132 and the power device 13 that are thermally compressed together are placed into the first mounting groove 33, and the thermally-conductive layer 132c of the heat sink 132 is in contact with the metal layer 32 of the bottom wall of the first mounting groove 33 to achieve thermally-conductive connection. Then, the first packaging portion 121b is arranged in the first mounting groove 33.

[0183] The first packaging portion 121b is etched to obtain three first holes 34 that respectively conduct the first sub-surface electrode 133a, the second sub-surface electrode 133b, and the electrically-conductive layer 132b. Metal is deposited in the three first holes 34 to obtain three sub-electrode connecting layers 1310, namely, a first sub-electrode connecting layer 131a, a second sub-electrode connecting layer 131b, and a third sub-electrode connecting layer 131c. Finally, a layer of metal is deposited on the surface of the first packaging portion 121b to restore the metal layer 32. The first sub-electrode connecting layer 131a directly connects the metal layer 32 and the first sub-surface electrode 133a, the second sub-electrode connecting layer 131b directly connects the metal layer 32 and the second sub-surface electrode 133b, and the third sub-electrode connecting layer 131c directly connects the metal layer 32 and the electrically-conductive layer 132b.

[0184] S215、Please refer to FIG. 6(h), the metal layer 32 connected with the power device 13 is etched into the first circuit layer 111. That is, before the first substrate 3 and the second substrate 4 are stacked into the laminated structure 1, the metal layer 32 connected with the power device 13 on the first substrate 3 needs to be etched into the patterned circuit layer 11 (i.e. the first circuit layer 111) in advance, especially when the circuit layer 11 is arranged towards the second substrate 4 in the laminated structure 1, because the circuit layer 11 towards the second substrate 4 in the laminated structure 1 will be blocked, and if the metal layer 32 is not etched in advance, it cannot be patterned. As an example, the wet etching method can be used to etch away the excess part of the metal layer 32 and obtain the patterned circuit layer 11, and the process of wet etching includes: film pasting, developing exposure, etching and film stripping.

[0185] In order to improve the alignment effect of the first substrate 3 and the second dielectric sheet 41 in the laminated structure 1, optionally, please refer to FIG. 6(g), step S2 further includes passing the first positioning hole 37 and the first mounting hole 38 through the first substrate 3 (specifically the first sub substrate 301), the first positioning hole 37 can be used to assist the alignment when preparing the laminated structure 1, and the first mounting hole 38 can be used to pass the conductive column 17. Generally, the first positioning hole 37 is arranged on the invalid area of the edge of the first substrate 3, and the invalid area can be cut off after the preparation of the packaging structure 10.

[0186] In some embodiments, step S2 further includes: embedding the second device 14 in the first dielectric sheet 31 of at least one first substrate 3, and the first substrate 3 embedding the second device 14 is different from the first substrate 3 embedding the power device 13. In order to distinguish, the first substrate 3 embedding the second device 14 is referred to as the second sub substrate 302. That is, at least one of the plurality of first substrates 3 is the second sub substrate 302. The second sub substrate 302 is not the same as the first sub substrate 301. One second device 14 or a plurality of second devices 14 can be embedded in the first dielectric sheet 31.

[0187] In some embodiments, please refer to FIG. 7, the process of embedding the second device 14 in the first dielectric sheet 31 of the first substrate 3 (specifically the second sub substrate 302) includes the following steps:

[0188] S221, providing a second device 14. The second device 14 refers to other devices other than the power device. Optionally, the second device 14 includes at least one of a passive device and a control chip. As an example, the passive device includes at least one of a temperature control element, a temperature sensing element, a strain gauge, a resistor and a capacitor. The control chip includes a processor.

[0189] S222, please refer to Fig. 7(a) and Fig. 7(b), a second mounting groove 35 is formed on the first substrate 3, the second mounting groove 35 extends into the first dielectric sheet 31 at least. As an example, the first substrate 3 can be partially thinned along the thickness direction of the first substrate 3 by means of laser etching or mechanical processing to obtain the second mounting groove 35. As an example, the second mounting groove 35 can be prepared by means of slotting. Since the metal layer 32 is thin, in order to ensure that the second mounting groove 35 has sufficient depth to accommodate the second device 14, the second mounting groove 35 will extend into the first dielectric sheet 31 at least, i.e. at least part of the first dielectric sheet 31 will be etched away. The second mounting groove 35 can or can not extend through the first dielectric sheet 31, but the second mounting groove 35 extends through the metal layer 32 on one side of the first dielectric sheet 31 at least.

[0190] S223, please refer to Fig. 7(c) and Fig. 7(d), the second device 14 is placed in the second mounting groove 35, and a dielectric material is backfilled in the second mounting groove 35 to obtain a second encapsulation part 123b, the second device 14 is embedded in the second encapsulation part 123b. The dielectric material backfilled in the second mounting groove 35 can be the same dielectric material as that in the first dielectric sheet 31 or a different dielectric material. The dielectric material used to backfill the second mounting groove 35 is usually liquid, so that the dielectric material can better coat the second device 14, and then a solidifying agent can be added, or the dielectric material can be heated or irradiated to solidify the dielectric material to form the second encapsulation part 123b, and the second device 14 is embedded in the second encapsulation part 123b. As an example, the dielectric material includes epoxy resin. Optionally, the top surface of the second encapsulation part 123b is flush with or substantially flush with the surface of the first dielectric sheet 31.

[0191] S224, please refer to FIG. 7 (e) and FIG. 7 (f), a second hole 36 is opened on the second packaging part 123b to expose the second device 14, a metal layer 32 is deposited in the second packaging part 123b to form a second electrode connecting layer 141, and the surface of the second packaging part 123b is recovered with the metal layer 32, and the second electrode connecting layer 141 is electrically connected with the second device 14 and the metal layer 32. As an example, the second packaging part 123b can be etched by laser etching to obtain the second hole 36, and the depth of the second hole 36 is determined according to the exposure of the second device 14, which means the electrical connecting part of the second device 14 is exposed. The second hole 36 is filled with metal by metal deposition, so as to form a metal deposition layer filling the second hole 36, and the metal deposition layer is the second electrode connecting layer 141, which is electrically connected with the second device 14. Since part of the metal layer 32 on one side of the first dielectric sheet 31 has been etched away when the second mounting groove 35 is opened, the surface of the second packaging part 123b formed later does not have the metal layer 32, and therefore the metal layer 32 needs to be recovered on the surface of the second packaging part 123b. Alternatively, the metal layer 32 can also be recovered on the surface of the second packaging part 123b by metal deposition, and the recovered metal layer 32 is also electrically connected with the second electrode connecting layer 141.

[0192] S225, please refer to FIG. 7 (h), the metal layer 32 connected with the second electrode connecting layer 141 is etched to form a third circuit layer 113. That is, before the first substrate 3 and the second substrate 4 are stacked into the layer stack structure 1, the metal layer 32 on the first substrate 3 connected with the second device 14 needs to be etched into a patterned circuit layer 11 (i.e. the third circuit layer 113), especially when the circuit layer 11 is arranged towards the second substrate 4 in the layer stack structure 1. If the metal layer 32 is not etched in advance, it cannot be patterned. As an example, the metal layer 32 can be etched by wet etching to remove the excess part and obtain the patterned circuit layer 11, and the process of wet etching includes film pasting, developing exposure, etching and film stripping.

[0193] In order to improve the alignment effect of the first substrate 3 and the second dielectric sheet 41 in the layer stack structure 1, optionally, please refer to FIG. 7 (g), step S2 further includes a first positioning hole 37 and a first mounting hole 38 passing through the first substrate 3 (specifically the second sub substrate 302), the first positioning hole 37 can be used for assisting alignment when preparing the layer stack structure 1, and the first mounting hole 38 can be used for passing through the conductive column 17. Generally, the first positioning hole 37 is arranged on the invalid area of the edge of the first substrate 3, and the invalid area can be cut off after the preparation of the packaging structure 10.

[0194] In some embodiments, the method for preparing the package structure 10 further comprises: disposing the thermal insulation structure 15 in the at least one second dielectric sheet 41 before preparing the laminated structure 1. The number of the thermal insulation structure 15 disposed in one second dielectric sheet 41 can be one or more. When the number of the second dielectric sheets 41 is more than one, the thermal insulation structure 15 can be disposed in one or several of the second dielectric sheets 41, or the thermal insulation structure 15 can be disposed in each of the second dielectric sheets 41.

[0195] Specifically, referring to FIG. 8, the process of disposing the thermal insulation structure 15 in the second dielectric sheet 41 comprises:

[0196] S231, referring to FIG. 8(a) and FIG. 8(b), a third mounting groove 44 is formed on the second dielectric sheet 41. As an example, the third mounting groove 44 can be formed by locally thinning the second dielectric sheet 41 along the thickness direction of the second dielectric sheet 41 through laser etching or mechanical processing. As an example, the third mounting groove 44 can be formed by slotting. Optionally, the depth of the third mounting groove 44 is less than the thickness of the second dielectric sheet 41. Of course, in some embodiments, the depth of the third mounting groove 44 is equal to the thickness of the second dielectric sheet 41, i.e., the third mounting groove 44 penetrates the second dielectric sheet 41.

[0197] S232, referring to FIG. 8(d), the third mounting groove 44 is filled with a thermal insulation material to obtain a thermal insulation core layer 151. As an example, the thermal insulation material comprises at least one of asbestos, aerogel, rock wool, vacuum board and graphite felt.

[0198] S233, referring to FIG. 8(c) and FIG. 8(e), an insulating medium is filled in the third mounting groove 44, and the insulating medium is solidified to obtain an insulating cover layer 152, and the thermal insulation structure 15 comprises the thermal insulation core layer 151 and the insulating cover layer 152. As an example, the insulating medium comprises resin.

[0199] It should be noted that when the depth of the third mounting groove 44 is less than the thickness of the second dielectric sheet 41, the third mounting groove 44 can be formed first, and then the thermal insulation material is filled in the third mounting groove 44, and then the insulating medium is filled in the third mounting groove 44 until the surface of the insulating medium is flush with the surface of the second dielectric sheet 41. In this way, the thermal insulation structure 15 obtained after solidification comprises the thermal insulation core layer 151 and the insulating cover layer 152, and the insulating cover layer 152 covers one side surface of the thermal insulation core layer 151.

[0200] When the depth of the third mounting groove 44 is equal to the thickness of the second dielectric sheet 41, the third mounting groove 44 is a through groove, and the insulating medium can be added into the third mounting groove 44 from the other end of the third mounting groove 44 after the one end of the third mounting groove 44 is sealed by a tape (see FIG. 8(c)). After the insulating medium is cured, the thermal insulation material is added (see FIG. 8(d)). Finally, the insulating medium is added until the surface of the insulating medium is flush with the surface of the second dielectric sheet 41 (see FIG. 8(d)). Thus, the thermal insulation structure 15 obtained after curing includes the thermal insulation core layer 151 and the insulating cover layer 152, and the insulating cover layer 152 includes two layers, which respectively cover the two side surfaces of the thermal insulation core layer 151.

[0201] In some cases, the thermal insulation material can be shaped and fixed before being added into the third mounting groove 44, so that the size of the thermal insulation core layer 151 in the radial direction and the axial direction is smaller than the size of the third mounting groove 44 in the radial direction and the axial direction. Thus, the thermal insulation core layer 151 can be completely wrapped by the insulating cover layer 152 in the thermal insulation structure 15 obtained.

[0202] In order to improve the alignment effect of the first substrate 3 and the second dielectric sheet 41 in the laminated structure 1, the step S2 can further include penetrating the second positioning hole 42 and the second mounting hole 43 in the second dielectric sheet 41. The second positioning hole 42 can be used for assisting alignment when the laminated structure 1 is prepared, and the second mounting hole 43 can be used for penetrating the conductive column 17. Generally, the second positioning hole 42 is arranged on the invalid area of the edge of the second dielectric sheet 41, and the invalid area can be cut off after the packaging structure 10 is prepared.

[0203] In some embodiments, the step of stacking the first substrate 3 and the second substrate 4 together includes: alternately stacking the first substrate 3 and the second substrate 4 together.

[0204] Referring to FIG. 9, the step S31 includes the following sub-steps:

[0205] S311, please see Figure 9 (a) and Figure 9 (b), the first substrate 3 and the second substrate 4 are alternately stacked together, and the second substrate 4 is located between the two first substrates 3, and the first circuit layer 111 and the third circuit layer 113 in the first substrate 3 are both towards the second substrate 4, obtaining a pre-laminated structure. As known from the foregoing, the first substrate 3 is at least two, and the second substrate 4 is at least one. As an example, two first substrates 3 and one second substrate 4 (i.e. the second dielectric sheet 41) are stacked together, and the second dielectric sheet 41 is clamped between the two first substrates 3. During the stacking process, the circuit layers 11 (first circuit layer 111 and third circuit layer 113 respectively) on the two first substrates 3 are kept towards the second dielectric sheet 41, while the unpatterned metal layer 32 on the two first substrates 3 serves as the surface layer of the laminated structure 1. When the second dielectric sheet 41 is provided with the heat insulation structure 15, the heat insulation structure 15 is kept corresponding to the power device 13 in the first substrate 3 as much as possible.

[0206] Optionally, the first positioning hole 37 is provided on the first substrate 3, and the second positioning hole 42 is provided on the second substrate 4. The first substrate 3 and the second substrate 4 are positioned by using the first positioning hole 37 and the second positioning hole 42, so as to improve the alignment effect of the first substrate 3 and the second substrate 4.

[0207] Optionally, the first mounting hole 38 is provided on the first substrate 3, and the second mounting hole 43 is provided on the second dielectric sheet 41. The first mounting hole 38 is aligned with the second mounting hole 43, and the conductive column 17 is penetrated into the first mounting hole 38 and the second mounting hole 43. Optionally, the conductive column 17 is electrically connected with the first circuit layer 111, the second circuit layer 112 and the third circuit layer 113. The conductive column 17 is a metal column, and the conductive column 17 penetrates through the laminated structure 1. The conductive column 17 can not only serve as a conductive channel, but also serve as a heat dissipation channel, so as to improve the current carrying capacity and heat dissipation capacity of the packaging structure 10.

[0208] S312, the pre-laminated structure is subjected to first heat pressing treatment to obtain the laminated structure 1. In the pre-laminated structure, the first substrate 3 and the second substrate 4 are only stacked one by one, and have not yet been combined together, and further treatment is needed to combine the first substrate 3 and the second dielectric sheet 41 together. Specifically, the pre-laminated structure is subjected to first heat pressing treatment to obtain the laminated structure 1. As an example, the first heat pressing treatment is vacuum lamination treatment.

[0209] S313、Please refer to (c) of FIG. 9, a through hole is formed on the laminated structure 1, and the through hole is metallized to obtain a metallized through hole 16. The metallization method includes but is not limited to electroplating. Optionally, the metallized through hole 16 is electrically connected with the first circuit layer 111, the second circuit layer 112 and the third circuit layer 113. The metallized through hole 16 can realize electrical connection between the multi-layer circuit layers 11 of the laminated structure 1.

[0210] In a third aspect, referring to FIG. 1, the application also provides a circuit board 100, wherein the circuit board 100 is provided with the packaging structure 10.

[0211] In a fourth aspect, referring to FIG. 1, the application also provides an electronic device 1000, wherein the electronic device 1000 comprises the circuit board 100.

[0212] In the description of the application, the terms "first", "second" are only for the purpose of description, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Therefore, the features defined with "first", "second" can explicitly or implicitly include one or more features. In the description of the application, the meaning of "multiple" is two or more, unless otherwise specifically limited.

[0213] In the above embodiments, the description of each embodiment is focused on, and the parts not described in detail in a certain embodiment can be referred to the related description of other embodiments.

[0214] The embodiments, implementation manners and related technical features of the application can be combined or replaced with each other without conflict.

[0215] The above is only the preferred embodiment of the application, and does not limit the application in any form. Although the description of each embodiment in the application is focused on, and the parts not described in detail in a certain embodiment can be referred to the related content of other embodiments, any simple modification, equivalent change and modification of the above embodiments according to the technical essence of the application still belong to the scope of the technical solution of the application.

Claims

1. A packaging structure (10) comprising a laminated structure (1), the laminated structure (1) comprising a medium layer (12), the medium layer (12) comprising a first medium layer (121) and a second medium layer (122), one side of at least the first medium layer (121) being provided with the second medium layer (122), and a power device (13) being embedded in the first medium layer (121).

2. The package structure (10) according to claim 1, wherein The packaging structure (10) further comprises a protective layer (2) located on opposite surfaces of the laminated structure (1), at least one of the protective layers (2) being provided with a pad (21), and the second medium layer (122) being located between the first medium layer (121) and the protective layer (2) provided with the pad (21).

3. The package structure (10) of claim 1, wherein, The second medium layer (122) is inlaid with a heat insulation structure (15).

4. The package structure (10) according to claim 3, wherein The heat insulation structure (15) corresponds to the power device (13).

5. The package structure (10) according to claim 3, wherein The heat insulation structure (15) comprises an insulating core layer (151) and an insulating cover layer (152), and the insulating cover layer (152) covers the surface of the insulating core layer (151).

6. The package structure (10) according to claim 5, wherein The insulating core layer (151) comprises an insulating material, and the insulating material comprises at least one of asbestos, aerogel, rock wool, vacuum board and graphite felt.

7. The package structure (10) according to claim 2, wherein The laminated structure (1) further comprises a circuit layer (11), the power device (13) is electrically connected to the circuit layer (11), and the pad (21) is electrically connected to the circuit layer (11).

8. The package structure (10) according to claim 7, wherein The circuit layer (11) comprises a first circuit layer (111) and a second circuit layer (112), the first circuit layer (111) is adjacent to the first medium layer (121), the power device (13) is electrically connected to the first circuit layer (111), the second circuit layer (112) is adjacent to the protective layer (2), and the pad (21) is electrically connected to the second circuit layer (112).

9. The package structure (10) according to any one of claims 1 to 8, wherein The first medium layer (121) further embeds a heat dissipation plate (132), the power device (13) is arranged on the heat dissipation plate (132), and a heat dissipation end surface of the heat dissipation plate (132) protrudes out of the first medium layer (121).

10. The package structure (10) according to any one of claims 1 to 8, wherein The laminated structure (1) further comprises a first circuit layer (111); the first medium layer (121) further embeds a first electrode connecting layer (131), and the power device (13) is connected to the first circuit layer (111) through the first electrode connecting layer (131).

11. The package structure (10) according to claim 10, wherein The first medium layer (121) comprises a first body portion (121a) and a first packaging portion (121b), the first body portion (121a) and the first packaging portion (121b) are arranged integrally, and the power device (13) and the first electrode connecting layer (131) are embedded in the first packaging portion (121b).

12. The package structure (10) according to claim 10, wherein The power device (13) has surface electrodes (133), the surface electrodes (133) include three independent sub-surface electrodes (1330); the first electrode connecting layer (131) includes three independent sub-electrode connecting layers (1310); the sub-surface electrodes (1330) are connected with the sub-electrode connecting layers (1310) one by one.

13. The package structure (10) according to claim 12, wherein The first medium layer (121) is further embedded with a heat dissipation plate (132), the heat dissipation plate (132) includes an insulating body (132a) and conductive layers (132b) and heat conductive layers (132c) located on the two side surfaces of the insulating body (132a); the power device (13) has a first surface (13a) and a second surface (13b) opposite to each other, one of the three sub-surface electrodes (1330) is distributed on the second surface (13b), and the other two are distributed on the first surface (13a) with a spacing; the sub-surface electrode (1330) located on the second surface (13b) is connected with the conductive layer (132b), and the conductive layer (132b) is further connected with a sub-electrode connecting layer (1310); the heat conductive layer (132c) partially extends out of the first medium layer (121).

14. The package structure (10) according to any one of claims 1 to 8, wherein, The medium layer (12) further includes a third medium layer (123), the third medium layer (123) is located on one side of the first medium layer (121), and a second device (14) is embedded in the third medium layer (123).

15. The package structure (10) according to claim 14, wherein The laminated structure (1) further includes a third circuit layer (113), the third circuit layer (113) is adjacent to the third medium layer (123) and is electrically connected with the second device (14).

16. The package structure (10) according to claim 14, wherein The second device (14) includes at least one of a passive device and a control chip.

17. The package structure (10) according to claim 15, wherein The third medium layer (123) is further embedded with a second electrode connecting layer (141), and the second device (14) is connected with the third circuit layer (113) through the second electrode connecting layer (141).

18. The package structure (10) according to claim 17, wherein The third medium layer (123) includes a second body part (123a) and a second packaging part (123b), the second body part (123a) and the second packaging part (123b) are integrally arranged, and the second device (14) and the second electrode connecting layer (141) are embedded in the second packaging part (123b).

19. The package structure (10) of claim 14, wherein, The second medium layer (122) is located between the first medium layer (121) and the third medium layer (123).

20. The package structure (10) according to claim 7 or 8, wherein The packaging structure (10) is provided with a metalized via hole (16) penetrating through the laminated structure (1) and electrically connected with the circuit layer (11); and / or, the packaging structure (10) further includes a conductive column (17) penetrating in the laminated structure (1) and electrically connected with the circuit layer (11).

21. The package structure (10) according to claim 7 or 8, wherein The medium layer (12) is an organic medium layer (12), the organic medium layer (12) comprises a resin and a reinforcing material, the resin comprises at least one of an epoxy resin, polytetrafluoroethylene, a phenolic resin, a polyphenyl ether and a bismaleimide triazine resin, and the reinforcing material comprises at least one of a paper base, a glass cloth and a metal core; and / or, the thickness of the circuit layer (11) is 17.5 μm to 140 μm; and / or, the circuit layer (11) comprises at least one of copper, silver and gold; and / or, the power device comprises a silicon carbide power device.

22. A method for manufacturing a packaging structure (10), comprising: providing a first substrate (3) and a second substrate (4), the first substrate (3) comprising a first medium sheet (31), and the second substrate (4) comprising a second medium sheet (41); embedding a power device (13) in the first medium sheet (31) of the first substrate (3); stacking the first substrate (3) and the second substrate (4) together, and performing a first hot-pressing treatment to obtain the packaging structure (10).

23. A circuit board (100), comprising the packaging structure (10) according to any one of claims 1 to 21 or manufactured by the method according to claim 22.

24. An electronic device (1000), comprising the circuit board (100) according to claim 23.

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