Micro-display device

Abstract

The present invention relates to a micro-display device. The micro-display device comprises a drive wafer, and a display device layer provided on the drive wafer, wherein the display device layer comprises a sub-pixel, and a first ohmic contact layer is provided on the surface of the sub-pixel that is away from the drive wafer; and the first ohmic contact layer of the sub-pixel in at least one display device layer is electrically connected to a transparent conductive layer, the transparent conductive layer covers the first ohmic contact layer of the sub-pixel, the first ohmic contact layer is provided with an exposed region, an upper surface of the first ohmic contact layer is completely exposed to form the exposed region, and the exposed region is in contact with the transparent conductive layer. The present invention effectively improves the photoelectric performance and reliability of display devices.

Description

Micro display device

[0001] Priority Information: This application claims priority to Chinese Patent Application No. 2024111264098, filed on August 16, 2024, the entire contents of which are incorporated herein by reference. TECHNICAL FIELD

[0002] The present application relates to the technical field of semiconductor, in particular to a micro display device. BACKGROUND

[0003] In the field of LED micro display, the micro display device is mainly composed of a driving wafer (with driving circuit) and pixels stacked above the driving wafer to control the pixels to emit light by the driving wafer. The top surface of each pixel needs to be electrically connected with the top conductive layer. In the traditional structure, a notch is etched above the top surface of the pixel, and the contact between the top surface of the pixel and the top conductive layer is realized by using the notch. This structure is relatively complex, and the electrical contact area between the top surface of the pixel and the top conductive layer is small. As the injected current increases, the smaller the electrical contact area, the greater the current density, which causes the resistance value of the conductive layer to be higher, thereby increasing the heat of the display device and reducing the photoelectric performance, and reducing the reliability of the display device. SUMMARY

[0004] Therefore, the technical problem to be solved by the present application is to improve the reliability of the micro display device in the prior art.

[0005] To solve the above technical problems, the present application provides a micro display device, which comprises a driving wafer and a display device layer arranged above the driving wafer.

[0006] The display device layer comprises sub-pixels, and the first ohmic contact layer is arranged on one side of the sub-pixel away from the driving wafer.

[0007] At least one first ohmic contact layer of the sub-pixel in the display device layer is electrically connected with a transparent conductive layer, the transparent conductive layer is arranged on the first ohmic contact layer of the sub-pixel, the first ohmic contact layer has an exposed area, the upper surface of the first ohmic contact layer is completely exposed to form the exposed area, and the exposed area is in contact with the transparent conductive layer.

[0008] In an embodiment of the present application, at least one first ohmic contact layer of the sub-pixel in the display device layer is electrically connected with a transparent conductive layer, the upper surface and at least part of the sidewall of the first ohmic contact layer are exposed to form the exposed area, and the exposed area is in contact with the transparent conductive layer.

[0009] In one embodiment of the present application, in the same layer of the display device layer, the transparent conductive layer comprises contact sections and non-contact sections, the contact sections are in contact with the exposed regions of the same layer of sub-pixels, the sections other than the contact sections in the transparent conductive layer are non-contact sections, and the non-contact sections are located at the upper portions of the same layer of sub-pixels.

[0010] In one embodiment of the present application, in the same layer of the display device layer, the transparent conductive layer comprises contact sections and non-contact sections, the contact sections are in contact with the exposed regions of the same layer of sub-pixels, the sections other than the contact sections in the transparent conductive layer are non-contact sections, and the non-contact sections are partially located at the sidewalls of the corresponding sub-pixels of the same layer, and a fourth insulating layer is arranged between the non-contact sections at the sidewalls of the sub-pixels and the sidewalls of the sub-pixels.

[0011] In one embodiment of the present application, one side of the fourth insulating layer is in contact with the sidewalls of the sub-pixels, and the other side is in contact with the non-contact sections.

[0012] In one embodiment of the present application, in one layer of the display device layer, the periphery of the sub-pixel is surrounded by a metal fence, the metal fence is located between the non-contact sections at the sidewalls of the sub-pixels and the sidewalls of the sub-pixels, the fourth insulating layer is arranged between the metal fence and the sidewalls of the sub-pixels, and a fifth insulating layer is further arranged between the metal fence and the non-contact sections at the sidewalls of the sub-pixels.

[0013] In one embodiment of the present application, the metal fence is formed at the upper portion of a metal bonding layer, one end of the sub-pixel close to the driving wafer is provided with a second ohmic contact layer and connected to the metal bonding layer through the second ohmic contact layer, and the second ohmic contact layer is located inside the metal fence.

[0014] In one embodiment of the present application, the sub-pixel comprises a second ohmic contact layer, an active layer and a first ohmic contact layer arranged in the direction away from the driving wafer, and the lowest point of the exposed region of the sub-pixel is not lower than the upper surface of the active layer.

[0015] In one embodiment of the present application, in the display device layer where the metal fence is located, the upper surface of the metal fence is lower than the upper surface of the first ohmic contact layer of the sub-pixel and higher than the upper surface of the second ohmic contact layer.

[0016] In one embodiment of the present application, in the display device layer where the metal fence is located, the upper surface of the metal fence is not lower than the upper surface of the active layer.

[0017] In one embodiment of the present application, a layer is provided between the lower surface of the active layer of the sub-pixel and the upper surface of the second ohmic contact layer, the layer extending at least partially under the fourth insulating layer.

[0018] In one embodiment of the present application, in the display device layer in which the metal fence is located, the metal fence is not in contact with the transparent conductive layer, and the minimum distance between the metal fence and the transparent conductive layer at the periphery of each sub-pixel is not less than 5 nm.

[0019] In one embodiment of the present application, an insulating medium is provided between the upper surface of the metal fence at the periphery of the sub-pixel and the transparent conductive layer above, the insulating medium having an insulating bend.

[0020] In one embodiment of the present application, a plurality of sub-pixels in the same display device layer share one transparent conductive layer, or each sub-pixel independently uses the transparent conductive layer.

[0021] In one embodiment of the present application, a metal reinforcing structure is further provided on the transparent conductive layer; a plurality of sub-pixels in the same display device layer are provided with one metal reinforcing structure at the periphery, or each sub-pixel in the same display device layer is independently provided with a metal reinforcing structure at the periphery.

[0022] In one embodiment of the present application, in the same display device layer, a metal reinforcing structure is provided between two adjacent sub-pixels, the metal reinforcing structure comprising a metal side wall, and the metal side wall is attached to a non-contact section of the transparent conductive layer at the side wall of at least one of the two adjacent sub-pixels.

[0023] In one embodiment of the present application, the metal reinforcing structure comprises two oppositely arranged metal side walls, one of the metal side walls being attached to a non-contact section of the transparent conductive layer at the side wall of one of the two adjacent sub-pixels, and the other metal side wall being attached to a non-contact section of the transparent conductive layer at the side wall of the other of the two adjacent sub-pixels.

[0024] In one embodiment of the present application, the two oppositely arranged metal side walls of the metal reinforcing structure are connected by a metal connecting portion.

[0025] In one embodiment of the present application, the upper part of the metal side wall at the periphery of the sub-pixel forms a metal bend, which bends towards the axis direction of the same sub-pixel.

[0026] In one embodiment of the present application, the highest point of the metal side wall at the periphery of the sub-pixel is higher than the upper surface of the metal fence at the periphery of the same sub-pixel.

[0027] In one embodiment of the present application, the highest point of the metal sidewall of the sub-pixel periphery is not lower than the upper surface of the first ohmic contact layer of the same sub-pixel.

[0028] In one embodiment of the present application, a lens is further included, and a plurality of the lenses are arranged on the upper portion of one of the display device layers, such that each of the lenses covers at least one of the sub-pixels in the same display device layer.

[0029] In one embodiment of the present application, the bottom surface of the lens is not lower than the upper surface of the first ohmic contact layer of the corresponding sub-pixel in the display device layer connected with the lens.

[0030] In one embodiment of the present application, the bottom surface of the lens is lower than the upper surface of the metal fence of the corresponding sub-pixel periphery in the display device layer connected with the lens.

[0031] In one embodiment of the present application, a plurality of the lenses are arranged on the upper portion of one of the display device layers, and adjacent two of the lenses are separated from each other to be arranged independently, or are connected with each other to form an integrated structure.

[0032] In one embodiment of the present application, the lens comprises a curved portion and a flat portion, and the flat portion is arranged at the bottom end of the curved portion.

[0033] In one embodiment of the present application, each of the sub-pixels in the display device layer connected with the lens corresponds to one lens, and the axis of each of the lenses is offset relative to the axis of the corresponding sub-pixel.

[0034] The above technical solution of the present application has the following advantages compared with the prior art:

[0035] The micro display device of the present application can effectively increase the electrical contact area of the sub-pixel and the transparent conductive layer, improve the photoelectric efficiency of the display device, reduce the power consumption of the display device, and effectively improve the photoelectric performance and reliability of the device. BRIEF DESCRIPTION OF DRAWINGS

[0036] In order to make the content of the present application more easily understood, the present application will be further described in detail below according to specific embodiments of the present application and in conjunction with the accompanying drawings.

[0037] FIG. 1 is a structural schematic diagram of a micro display device with a single display device layer according to an embodiment of the present application;

[0038] FIG. 2 is a structural schematic diagram of a micro display device with a single display device layer according to an embodiment of the present application;

[0039] FIG. 3 is a structural schematic diagram of a micro display device with a double display device layer according to an embodiment of the present application;

[0040] Figure 4 is a structural schematic diagram of a micro display device with double display device layers according to an embodiment of the present application;

[0041] Figure 5 is a structural schematic diagram of a micro display device with double display device layers according to an embodiment of the present application;

[0042] Figure 6 is a structural schematic diagram of a micro display device with double display device layers according to an embodiment of the present application;

[0043] Figure 7 is a structural schematic diagram of a micro display device with triple display device layers according to an embodiment of the present application;

[0044] Figure 8 is a structural schematic diagram of a micro display device with triple display device layers according to an embodiment of the present application;

[0045] Figure 9 is a schematic diagram of a single layer pixelation preparation process according to an embodiment of the present application;

[0046] Figure 10 is a schematic diagram of a double layer pixelation preparation process according to an embodiment of the present application;

[0047] Figure 11 is a schematic diagram of an electrical connection process for a micro display device with double display device layers according to an embodiment of the present application;

[0048] Figure 12 is a schematic diagram of an electrical connection process for a micro display device with double display device layers according to an embodiment of the present application;

[0049] Figure 13 is a schematic diagram of an electrical connection process for a micro display device with double display device layers according to an embodiment of the present application;

[0050] Figure 14 is a schematic diagram of an electrical connection process for a micro display device with double display device layers according to an embodiment of the present application;

[0051] Figure 15 is a schematic diagram of a triple layer pixelation preparation process according to an embodiment of the present application;

[0052] Figure 16 is a structural schematic diagram of a micro display device with one display device layer according to an embodiment of the present application;

[0053] Figure 17 is a partial enlarged view of M1 in Figure 16;

[0054] Figure 18 is a preparation schematic diagram of the micro display device shown in Figure 16;

[0055] Figure 19 is a structural schematic diagram of a first micro display device with a metal reinforcing structure according to an embodiment of the present application;

[0056] Fig. 20 is a structural schematic diagram of a second micro display device with a metal reinforcing structure according to an embodiment of the present application;

[0057] Fig. 21 is a structural schematic diagram of a first micro display device with a lens structure according to an embodiment of the present application;

[0058] Fig. 22 is a structural schematic diagram of a second micro display device with a lens structure according to an embodiment of the present application;

[0059] Fig. 23 is a structural schematic diagram of a third micro display device with a lens structure according to an embodiment of the present application;

[0060] Fig. 24 is a structural schematic diagram of a fourth micro display device with a lens structure according to an embodiment of the present application;

[0061] Fig. 25 is a structural schematic diagram of a fifth micro display device with a lens structure according to an embodiment of the present application;

[0062] Fig. 26 is a structural schematic diagram of a micro display device according to an embodiment of the present application;

[0063] Fig. 27 is a partial enlarged view of M2 in Fig. 26;

[0064] Fig. 28 is a structural schematic diagram of a micro display device according to an embodiment of the present application;

[0065] Fig. 29 is a partial enlarged view of M3 in Fig. 26;

[0066] Fig. 30 is a structural schematic diagram of a micro display device according to an embodiment of the present application;

[0067] Fig. 31 is a structural schematic diagram of another micro display device according to an embodiment of the present application;

[0068] Fig. 32 is a structural schematic diagram of a micro display device without a metal fence according to an embodiment of the present application;

[0069] Description of the drawings: 100, drive wafer; 110, anode contact; 200, first display device layer; 210, first sub-pixel; 2101, active layer; 220, first insulating layer; 300, second display device layer; 310, second sub-pixel; 320, second insulating layer; 400, third display device layer; 410, third sub-pixel; 420, third insulating layer; 500, transparent conductive layer; 501, contact section; 502, non-contact section; 600, opening; 700, metal reinforcing structure; 701, metal side wall; 7011, metal bending part; 702, metal connecting part; 800, via hole interconnection metal; 910, metal bonding layer; 920, first ohmic contact layer; 930, second ohmic contact layer; 940, layer body part; 940, first layer color compound; 950, second layer color compound; 960, third layer color compound; 1000, fourth insulating layer; 1100, fifth insulating layer; 1200, metal fence; 1300, lens; 1301, curved part; 1302, flat part; 1400, etching stop layer; 1500, exposed area; 1600, insulating medium; 1601, insulating bending part; DETAILED DESCRIPTION

[0070] The present application will be further described with reference to the drawings and specific examples, so that those skilled in the art can better understand the present application and implement it. It is obvious that the described examples are only a part of the embodiments of the present disclosure, not all. The following description of at least one exemplary embodiment is actually only illustrative, but not as any limitation on the present disclosure and its application or use.

[0071] In the description of the present application, it should be understood that the terms "vertical", "upper", "lower", "top", "side", "inner", "outer" and the like indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the present application. In addition, the terms "first", "second" are only for the purpose of description, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, the features limited by "first", "second" can be explicitly or implicitly included one or more features. In the description of the present application, unless otherwise stated, the meaning of "a plurality of" is two or more.

[0072] In the description of the present application, it should be noted that unless otherwise explicitly specified and limited, the terms "mounting", "connection", "linking" should be understood in a broad sense, for example, it can be fixed connection, or detachable connection, or integral connection; it can be mechanical connection, or electrical connection; it can be direct connection, or indirect connection through intermediate medium, or internal connection of two elements. For those skilled in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.

[0073] It should be noted that each layer of color compound layer in the present application refers to a layer structure with a certain thickness prepared from compound semiconductor material (i.e. compound wafer material). Compound semiconductor generally refers to a compound formed by two or more elements, including crystalline inorganic compounds (such as III-V, II-VI compound semiconductors) and oxide semiconductors, etc. The compound semiconductors involved in the present application are mainly light emitting diode epitaxial materials, such as InGaN ternary material system or AlGaInP quaternary material system, etc.

[0074] The related structure of the LED display device of the present application will be further described below in combination with the following specific embodiments.

[0075] Embodiment one

[0076] Referring to FIGS. 1-15, the present embodiment provides a stacked integrated micro display device.

[0077] The above micro display device comprises: a driving wafer 100, one or more display device layers arranged above the driving wafer 100; each display device layer comprises sub-pixels and an insulating layer, the first ohmic contact layer of the sub-pixels is away from the driving wafer 100, and the projection of the sub-pixels in any display device layer on the driving wafer 100 does not coincide with the projection of the sub-pixels in the remaining display device layers on the driving wafer 100; the insulating layer in at least one display device layer is filled in the display device layer, and the top height of the insulating layer around the sub-pixels is not higher than the top height of the first ohmic contact layer of the sub-pixels in the same layer, so that the first ohmic contact layer of the sub-pixels is exposed to the upper surface and / or part of the side wall compared with the surrounding insulating layer in the same layer; the first ohmic contact layer of the sub-pixels in any display device layer is connected by common cathode through a transparent conductive layer 500, and the transparent conductive layer 500 is arranged on the first ohmic contact layer of the sub-pixels in each display device layer.

[0078] In the embodiments of the present application, a micro display device having single-layer or multi-layer display device layers is provided, at least one sub-pixel and an insulating layer are arranged in each display device layer, and the insulating layer in each display device layer is used for insulating protection of the sub-pixel in the layer. In the case of multi-layer display device layers, the projection of the sub-pixels included in any display device layer on the driving wafer 100 does not coincide with the projection of the sub-pixels included in the remaining display device layers, so as to reduce the interference problem caused by multi-layer stacked display. In addition, in the case of multi-layer display device layers, different display device layers can be designed to emit light of different wavelengths, so as to realize colorized display.

[0079] In the embodiments of the present application, at least one display device layer in the micro display device is designed in the following structure: the insulating layer is filled in the display device layer, and the top height of the insulating layer around the sub-pixel is designed to be not higher than the top height of the first ohmic contact layer of the sub-pixel in the same layer. Specifically, in one case, the top height of the insulating layer around the sub-pixel is flush with the first ohmic contact layer of the sub-pixel in the same layer, so as to expose the upper surface of the first ohmic contact layer of the sub-pixel to be in contact with the transparent conductive layer 500. In another case, the top height of the insulating layer around the sub-pixel is lower than the first ohmic contact layer of the sub-pixel in the same layer, so as to expose the upper surface and part of the sidewall of the first ohmic contact layer of the sub-pixel to be in contact with the transparent conductive layer 500, thereby further increasing the N-face current injection area. Especially in the case of smaller size of the sub-pixel, the increase of the N-face current injection area is more obvious, and the power consumption advantage is more obvious.

[0080] It can be understood that the first ohmic contact layer and the second ohmic contact layer in the present application can be designed as P-type ohmic contact layer and N-type ohmic contact layer respectively, or can be designed as N-type ohmic contact layer and P-type ohmic contact layer respectively.

[0081] In an embodiment, as shown in FIG. 1 and FIG. 2, the micro display device has a single-layer display device layer, i.e., a first display device layer 200. In the first display device layer 200, the upper surface and part of the sidewall of the first ohmic contact layer of the first sub-pixel 210 are exposed to be in contact with the transparent conductive layer 500.

[0082] In an embodiment, as shown in FIG. 3, the micro display device has double-layer display device layers, i.e., a first display device layer 200 and a second display device layer 300. In the first display device layer 200, the upper surface and part of the sidewall of the first ohmic contact layer of the first sub-pixel 210 are exposed to be in contact with the transparent conductive layer 500.

[0083] In one embodiment, as shown in FIG. 4, the micro-display device has two display device layers: a first display device layer 200 and a second display device layer 300. In the first display device layer 200, the upper surface and part of the sidewall of the first ohmic contact layer of the first sub-pixel 210 are exposed. In the second display device layer 300, the upper surface of the first ohmic contact layer of the second sub-pixel 310 is exposed and in contact with the transparent conductive layer 500.

[0084] In one embodiment, as shown in FIG. 5 and FIG. 6, the micro-display device has two display device layers: a first display device layer 200 and a second display device layer 300. In the first display device layer 200, the upper surface and part of the sidewall of the first ohmic contact layer of the first sub-pixel 210 are exposed. In the second display device layer 300, the upper surface and part of the sidewall of the first ohmic contact layer of the second sub-pixel 310 are exposed and in contact with the transparent conductive layer 500.

[0085] In one embodiment, as shown in FIG. 7, the micro-display device has three display device layers: a first display device layer 200, a second display device layer 300 and a third display device layer 400. In the three display device layers, the upper surface and part of the sidewall of the first ohmic contact layer of the corresponding sub-pixel are exposed and in contact with the transparent conductive layer 500.

[0086] In one embodiment, as shown in FIG. 8, the micro-display device has three display device layers: a first display device layer 200, a second display device layer 300 and a third display device layer 400. In the first display device layer 200 and the second display device layer 300, the upper surface and part of the sidewall of the first ohmic contact layer of the corresponding sub-pixel are exposed. In the third display device layer 400, the upper surface of the first ohmic contact layer of the corresponding sub-pixel is exposed and in contact with the transparent conductive layer 500.

[0087] In one embodiment, as shown in FIG. 9, the micro-display device has three display device layers: a first display device layer 200, a second display device layer 300 and a third display device layer 400. In the three display device layers, the upper surface and part of the sidewall of the first ohmic contact layer of the corresponding sub-pixel are exposed and in contact with the transparent conductive layer 500. In one embodiment, as shown in FIG. 10, the micro-display device has three display device layers: a first display device layer 200, a second display device layer 300 and a third display device layer 400. In the three display device layers, the upper surface and part of the sidewall of the first ohmic contact layer of the corresponding sub-pixel are exposed and in contact with the transparent conductive layer 500.

[0088] Further, part of the damaged layer of the first ohmic contact layer can be removed. In order to fully expose the upper surface of each sub-pixel and achieve good ohmic contact, a certain thickness of the damaged layer can be removed by etching. In this design, the top height of the sub-pixel in the current display device layer can be slightly lower than the bottom height of the metal bonding layer in the previous display device layer. In addition, good ohmic contact can also be achieved by certain surface activation, which is not limited in the present application.

[0089] Specifically, the sub-pixel is made of a compound wafer material, and the structures of some compound wafers are shown in Table 1. In some practical applications, the film layers of the compound wafer are more complex, or there is cross use of materials. The typical main materials include P layer material, N layer material, and MQW quantum well sandwiched between the two, and other functional layers.

[0090] Table 1: Film layer material table of compound wafer

[0091] The transparent conductive layer 500 can be a combination of one or more of ITO (Indium Tin Oxide) film, AZO (Antimony doped Zinc Oxide) film, ATO (Antimony doped Tin Oxide) film, and FTO (Fluorine doped Tin Oxide) film, or a single layer or stack of metal-doped ITO formed by annealing after plating thin Al, Au, or Ag on the ITO surface, to enhance the current transmission capacity of the common cathode.

[0092] The insulating layer material can include a single film layer of silicon oxide, silicon nitride, aluminum oxide, boron nitride, or a stack of two or more materials.

[0093] In one possible implementation, the top height of the insulating layer around the sub-pixel in at least one display device layer is not higher than the top height of the first ohmic contact layer of the sub-pixel in the same layer, and not lower than the bottom height of the first ohmic contact layer of the sub-pixel in the same layer.

[0094] In this implementation, when the first ohmic contact layer of the sub-pixel is exposed, the height of the insulating layer around the sub-pixel is further designed to be not lower than the bottom height of the first ohmic contact layer of the sub-pixel, to avoid leakage problems of the device.

[0095] In one possible implementation, as shown in FIGS. 4 to 8, the number of display device layers is at least two; in the insulating layer filled by at least one display device layer above the i-th display device layer, an opening 600 aligned with a region of the i-th sub-pixel in the i-th display device layer is provided to expose the first ohmic contact layer of the i-th sub-pixel; and the transparent conductive layer 500 is attached to the surface of the opening 600 to connect with the first ohmic contact layer of the i-th sub-pixel.

[0096] In the present embodiment, in the case that the micro display device comprises multiple display device layers, if the upper display device layer of the current display device layer is designed to be filled with an insulating layer as a whole, the first ohmic contact layer of the sub-pixel in the current display device layer is exposed by means of opening the insulating layer of the upper device layer to form an opening 600, and correspondingly, the transparent conductive layer 500 is in N-face contact with the sub-pixel in the current display device layer through the opening 600.

[0097] It can be understood that the number of layers of the upper display device layer can be one or more, and the opening 600 penetrates the insulating layer of one or more upper display device layers, and the opening 600 can have only one step surface and be formed by one etching operation. For example, referring to FIG. 7, the micro display device has three display device layers, the third insulating layer 420 is filled in the third display device layer 400 as a whole, and the second insulating layer 320 is filled in the second display device layer 300 as a whole, so that the corresponding opening 600 is opened for the first sub-pixel 210 in the third insulating layer 420 and the second insulating layer 320, and the corresponding opening 600 is opened for the second sub-pixel 310 in the third insulating layer 420. Referring to FIG. 4, the micro display device has two display device layers, and the second insulating layer 320 is filled in the second display device layer 300 as a whole, so that the corresponding opening 600 is opened for the first sub-pixel 210 in the second insulating layer 320.

[0098] Further, the opening 600 gradually increases in size in the direction away from the driving wafer, thereby facilitating process implementation. For example, referring to FIGS. 4 to 8, the opening 600 is used to expose the first sub-pixel 210 or the second sub-pixel 310, the size of the top of the opening 600 is obviously larger than the size of the bottom of the opening 600, and the size of the bottom of the opening 600 can be greater than or equal to the size of the upper surface of the first ohmic contact layer of the first sub-pixel 210 or the second sub-pixel 310.

[0099] Further, in the design that the number of layers of the display device layer is at least two, the insulating layer in the top display device layer is attached to the sidewall of the same layer sub-pixel. By designing the insulating layer in the top display device layer to be attached to the sidewall of the same layer sub-pixel instead of being filled in the display device layer as a whole, the thickness of the insulating layer filled as a whole in the micro display device layer can be reduced, thereby facilitating the exposure of the N-face of the sub-pixel in the lower display device layer. For example, referring to FIG. 8, the micro display device has three display device layers, and the third insulating layer 420 is designed to be attached to the sidewall of the third sub-pixel 410, thereby facilitating the opening of the corresponding opening 600 for the first sub-pixel 210 and exposing the first sub-pixel 210 through the opening 600. Referring to FIG. 6, the micro display device has two display device layers, and the second insulating layer 320 is designed to be attached to the sidewall of the second sub-pixel 310, thereby facilitating the direct exposure of the first sub-pixel 210 in the first insulating layer 220.

[0100] In a possible implementation, the transparent conductive layer 500 is provided with a metal reinforcing structure 700, and a projection of the metal reinforcing structure 700 on the driving wafer does not coincide with the second ohmic contact layer in the sub-pixel in any display device layer.

[0101] In the implementation, as shown in FIGS. 3-6, by preparing the metal reinforcing structure 700 on the transparent conductive layer 500, current spreading and the improvement of the light-emitting angle and brightness can be achieved. The metal reinforcing structure 700 can be a single layer or a stack of Ni, Al, Ti, Au, or the like.

[0102] Further, the metal reinforcing structure 700 is provided in units of parent pixels or sub-pixels. The parent pixel is a pixel unit formed by arranging a plurality of sub-pixels, and the specific arrangement of the parent pixel is not limited in the application. For example, the sub-pixels in each display device layer can be set to be ≥1, and the sub-pixels in the three display device layers can be freely combined to form a parent pixel, such as one sub-pixel in each display device layer to form a parent pixel; two sub-pixels in the first display device layer 200 and one sub-pixel in each of the other two display device layers to form a parent pixel; two sub-pixels in the third display device layer 400 and one sub-pixel in each of the other two display device layers to form a parent pixel, and the like.

[0103] In a possible implementation, as shown in FIGS. 1-8, the driving wafer 100 includes an anode contact 110; the sub-pixel in any display device layer includes, in a direction away from the driving wafer 100, a metal bonding layer, a second ohmic contact layer, an active layer, and a first ohmic contact layer; the projection position of the sub-pixel in any display device layer on the underlying display device layer is provided with a metal bonding layer; and the sub-pixel in any display device layer is anodically connected to the anode contact 110 in the driving wafer 100 through the metal bonding layer in the underlying display device layer.

[0104] In the implementation, the driving wafer 100 is provided with a plurality of anode contacts 110, and each display device layer has one or more anode contacts corresponding to the sub-pixel. Each display device layer is anodically connected to the corresponding anode contact 110 in the driving wafer 100, specifically, the projection position of the sub-pixel in each display device layer on the underlying display device layer is provided with a metal bonding layer, and the sub-pixel in each display device layer is anodically connected to the corresponding anode contact 110 in the driving wafer 100 through the metal bonding layer in the underlying display device layer.

[0105] Further, in addition to the top display device layer, the other display device layers also include the through-hole interconnection metal structure 800 penetrating the display device layer, the bottom of the through-hole interconnection metal structure 800 is connected with the metal bonding layer in the display device layer, and the top is connected with the metal bonding layer in the upper display device layer.

[0106] The through-hole interconnection metal structure 800 can include a metal seed layer and a corresponding adhesion layer or barrier layer, the metal seed layer can be Al, Cu, W, etc., and the adhesion layer or barrier layer can be Ti, TiN, Ti / Cu, TaN / Cu, etc.

[0107] For example, as shown in FIG. 7 and FIG. 8, the first display device layer 200 is provided with the metal bonding layer and the through-hole interconnection metal structure 800 stacked in the direction away from the driving wafer, the metal bonding layer is connected with the anode contact 110 in the driving wafer 100, the bottom of the second sub-pixel 310 in the second display device layer 300 is connected with the top of the through-hole interconnection metal structure 800 in the first display device layer 200, so that the second sub-pixel 310 completes the anode connection through the through-hole interconnection metal structure 800 and the metal bonding layer in the first display device layer 200. Further, the second display device layer 300 is also provided with the metal bonding layer and the through-hole interconnection metal structure 800 stacked in the direction away from the driving wafer, the bottom of the third sub-pixel 410 in the third display device layer 400 is connected with the top of the through-hole interconnection metal structure 800 in the second display device layer, and the first display device layer 200 is also provided with the corresponding through-hole interconnection metal structure 800 in the vertical direction, so that the third sub-pixel completes the anode connection through the through-hole interconnection metal structure 800 and the metal bonding layer in the first display device layer 200 and the second display device layer 300.

[0108] The sub-pixels in each display device layer are color compound, the color compound layer can be set first, and then the color compound layer is pixelated etched to obtain each sub-pixel.

[0109] Further, the related size of the micro display device can be set as follows: the thickness of the metal bonding layer B1 / B2 / B3 is designed to be in the range of 10 nm to 1.5 um, and the metal bonding layer is prepared in the direction of thinness and without voids or gaps, and the optimal design thickness is different for different bonding metal methods; the thickness of the second ohmic contact layer is in the range of 5 nm to 300 nm; the thickness of the first / second / third layer of color compound epitaxial layer A1 / A2 / A3 is designed to be in the range of 0.2 um to 5 um, and the optimal design thickness is different for different compound patterning sizes; the thickness T1 of the transparent conductive layer is in the range of 10 nm to 500 nm, and in addition to considering current spreading and transmittance, the thicker the current spreading is, the lower the transmittance is; the thickness n of the metal reinforcing structure 700 is designed to be in the range of 100 nm to 5000 nm,

[0110] In summary, the embodiment of the present application provides a stacked integrated micro display device, which includes one or more display device layers, and the insulating layer in at least one of the display device layers is filled in the display device layer, and the top height of the insulating layer around the sub-pixel is not higher than the top height of the first ohmic contact layer of the sub-pixel in the same layer, so that the first ohmic contact layer of the sub-pixel is exposed to the upper surface and / or part of the side wall compared with the surrounding insulating layer in the same layer, and the first ohmic contact layer of the sub-pixel in any display device layer is connected to the common cathode through the transparent conductive layer, and the transparent conductive layer is arranged on the first ohmic contact layer of the sub-pixel in each display device layer, thereby greatly increasing the contact area between the transparent conductive layer and the epitaxial layer, increasing the current injection area, reducing the resistance, improving the photoelectric efficiency of the device, and realizing the preparation of high-brightness pixel units.

[0111] Next, the preparation method of the micro display device corresponding to the structure described in the above embodiment is described. The preparation method of the micro display device can include the following steps:

[0112] Step S1: preparing a driving wafer.

[0113] Step S2: bonding one or more display device layers on the driving wafer, any display device layer including a sub-pixel and an insulating layer, the first ohmic contact layer being on the side of the sub-pixel away from the driving wafer, and the projection of the sub-pixel included in any display device layer on the driving wafer not coinciding with the projection of the sub-pixel included in the remaining display device layer, the insulating layer in at least one of the display device layers being filled in the display device layer, and the top height of the insulating layer around the sub-pixel being not higher than the top height of the first ohmic contact layer of the sub-pixel in the same layer, so that the first ohmic contact layer of the sub-pixel is exposed to the upper surface and / or part of the side wall compared with the surrounding insulating layer in the same layer.

[0114] Wherein, before the preparation of the transparent conductive layer, the following step can also be performed: removing the damaged layer of the first ohmic contact layer, thereby achieving a good ohmic contact.

[0115] If the number of display device layers is one layer, and the display device layer only includes the first display device layer, step S2 specifically includes:

[0116] (1) Bonding the first layer of color compound to the driving wafer, and pixelizing the first layer of color compound to form a first sub-pixel.

[0117] It can be understood that each layer of color compound layer refers to a layer structure with a certain thickness prepared from a compound semiconductor material (i.e. a compound wafer material). After pixelizing (e.g. etching) the color compound layer, a sub-pixel can be obtained, and the obtained sub-pixel is also a compound semiconductor material.

[0118] Wherein, the preparation process of the first sub-pixel can be as shown in FIG. 9, including:

[0119] Step 1: Selecting the first layer of color compound 940 and preparing a second ohmic contact layer 930.

[0120] Specifically, a contact material is prepared on the P contact surface or the N contact surface of the first layer of color compound 940 to form the second ohmic contact layer 930. The contact material can be a transparent conductive thin film such as ITO, IZO, IGZO, AZO, or a metal alloy thin film such as AuBe, AnZn, and the thickness ranges from 1 nm to 300 nm.

[0121] Step 2: Bonding the first layer of color compound 940 to the wafer.

[0122] Specifically, a bonding structure is prepared on the first layer of color compound 940 and the driving wafer 100, respectively, and the first layer of color compound 940 and the driving wafer 100 are bonded and integrated through wafer-level bonding to form a metal bonding layer 910.

[0123] The bonding structure can be a conductive material, and the main bonding material can be one or more of Ni, Sn combination, Au, Sn combination, Cu, Sn combination, Au, In combination, Au, Au combination, Al, Al combination, Cu, Cu combination, ITO, ITO combination, etc. The bonding material and the wafer can include an adhesion layer (such as Cr, Ti, Ni, etc.) and a barrier depletion layer (such as Ni, Pt, Cu, etc.). The bonding structure on the compound and the driving wafer can be symmetrical or asymmetrical.

[0124] In an embodiment, symmetric metal bonding is used, i.e. the compound and the bonding structure on the driving wafer are the same, and the bonding structure is Cr (10 nm, adhesion layer) / Pt (50 nm, barrier depletion layer) / Au (100 nm) / Sn (150 nm) / Au (50 nm). After high-temperature thermal compression bonding, the compound and the driving wafer are integrated by bonding.

[0125] Step 3: Pixelated preparation.

[0126] The substrate and related structure of the first layer color compound 940 integrated by bonding are removed, and the first ohmic contact layer 920 is exposed. After the first ohmic contact layer 920 is exposed, the first layer color compound is patterned and pixelated by a semiconductor lithography and etching process. The second ohmic contact layer 930 is used as an etching stop layer, and the first sub-pixel 210 corresponds to the anode contact in the driving wafer 100, which can be one-to-one or one-to-many. Then, the second ohmic contact layer 930, the metal bonding layer 910, etc. are isolated by further patterning and etching, and the sub-pixel is realized independently.

[0127] (2) The first sub-pixel is filled with insulating medium to form a first insulating layer, and the upper surface and / or part of the sidewall of the first sub-pixel are exposed in the first insulating layer.

[0128] Specifically, based on the third step in the above, the first insulating layer is formed by filling the insulating medium, and the insulating medium includes silicon oxide, silicon nitride, SiC, SiCN, PSG, BPSG, polyimide, etc. Then, the upper surface and / or part of the sidewall of the first sub-pixel are exposed in the first insulating layer by planarization and / or etching.

[0129] In an embodiment, as shown in FIG. 1 and FIG. 2, the upper surface and sidewall of the first ohmic contact layer of the first sub-pixel are exposed by planarization and etching technology.

[0130] If the number of layers of the display device layer is 2, and the display device layer includes a first display device layer 200 and a second display device layer 300, step S2 specifically includes:

[0131] (1) For the first display device layer 200, the first layer color compound 940 is bonded and integrated onto the driving wafer, and the first layer color compound 940 is pixelated and prepared to form the first sub-pixel 210. The first sub-pixel 210 is filled with insulating medium to form a first insulating layer 220, and the first insulating layer 220 is planarized to expose the upper surface of the first sub-pixel 210. A via interconnection metal structure corresponding to the second sub-pixel 310 is prepared in the first insulating layer 220.

[0132] The preparation process of the first display device layer can be similar to the first to third steps above, and further includes the following steps as shown in FIG. 10:

[0133] Step 4: filling the insulating substance and planarization.

[0134] Specifically, the insulating medium is filled to form the first insulating layer 220, and the insulating medium includes silicon oxide, silicon nitride, SiC, SiCN, PSG, BPSG, polyimide, etc. Then, planarization is performed, which can be executed by CMP, etching or a combination of both, and the planarization is stopped at the upper surface of the first sub-pixel 210.

[0135] Step 5: preparation of through-hole interconnection metal.

[0136] Specifically, the through-hole structure is prepared in the first insulating layer 220, and the through-hole metal is filled to form the through-hole interconnection metal 800.

[0137] In an embodiment, the through-hole interconnection metal structure corresponding to the second sub-pixel is prepared in the first insulating layer, including: opening the color compound in the first insulating layer and backfilling the metal to form the through-hole interconnection metal structure penetrating the color compound.

[0138] (2.1) For the second display device layer 300, the second layer of color compound 950 is bonded and integrated onto the first display device layer 200, and the second layer of color compound 950 is prepared by pixelization to form the second sub-pixel 310; the insulating medium is deposited on the sidewall of the second sub-pixel 310 to form the second insulating layer 320.

[0139] As shown in FIG. 10, the first display device layer prepared by completing the fifth step is defined as a new driving wafer, and the first to third steps are repeated to stack and complete the pixelization of the double layers.

[0140] Further, the insulating layer is prepared, and after being patterned, the epitaxial surface of the second sub-pixel is etched to expose the second insulating layer of the sidewall of the second sub-pixel. The second insulating layer can be prepared by plasma deposition, sputtering, atomic layer deposition, etc., and the thickness range is 1 nm to 500 nm.

[0141] In an embodiment, as shown in FIG. 11, after the preparation of the second insulating layer is completed, a certain thickness of the first insulating layer is further removed by means of patterned etching to expose the sidewall surface of the first sub-pixel, and then the preparation of the electrical connection structure and the further preparation of the metal reinforcing structure are carried out. The transparent conductive layer can cover the upper surface and the sidewall surface of the first ohmic contact layer of the first sub-pixel. This scheme can continue to increase the N-face current injection area, especially in smaller pixel sizes, the increase in the N-face current injection area is more obvious, and the power consumption advantage is more obvious.

[0142] (2.2) For the second display device layer, the second layer of color system compound 950 is bonded and integrated onto the first display device layer 200, and the second layer of color system compound 950 is pixelated to form the second sub-pixel 310. The second sub-pixel 310 is filled with insulating medium to form the second insulating layer 320, and the upper surface and / or part of the sidewall of the second sub-pixel 310 are exposed in the second insulating layer. The area in the second insulating layer aligned with the first sub-pixel is patterned and etched to form an opening to expose the upper surface and / or part of the sidewall of the first sub-pixel.

[0143] As shown in FIG. 10, the first display device layer prepared in the fifth step is defined as a new driving wafer, and the first step to the third step are repeated to stack and complete the pixelation preparation of the double layers.

[0144] Further, the insulating medium is filled, and then the upper surface and / or part of the sidewall of the second sub-pixel are exposed by planarization and / or etching technology, and then the upper surface and / or part of the sidewall of the first sub-pixel are patterned and etched.

[0145] In an embodiment, as shown in FIG. 12, the upper surface of the second sub-pixel 310 is exposed by planarization of the second display device layer 300, and then the upper surface and the sidewall of the first sub-pixel 210 are patterned and etched, and then the electrical connection is carried out.

[0146] In an embodiment, as shown in FIG. 13, the upper surface and the sidewall of the second sub-pixel 310 are exposed by planarization technology and / or etching technology of the second display device layer 300, and then the upper surface and the sidewall of the first sub-pixel 210 are patterned and etched, and then the electrical connection is carried out.

[0147] In an embodiment, as shown in FIG. 14, the upper surface and the sidewall of the first sub-pixel 210 and the second sub-pixel 310 are exposed by planarization of the second display device layer 300, and then the electrical connection is carried out.

[0148] If the number of display device layers is three, the display device layers include the first display device layer 200, the second display device layer 300, and the third display device layer 400, step S2 specifically includes:

[0149] (1) For the first display device layer 200, the first layer color compound 940 is bonded and integrated onto the driving wafer, and the first layer color compound 940 is pixelated to form the first sub-pixel 210; the first sub-pixel 210 is filled with insulating medium to form the first insulating layer 220, and the first insulating layer 220 is planarized to expose the upper surface of the first sub-pixel 210; the via interconnection metal structure corresponding to the second sub-pixel 310 and the third sub-pixel 410 is prepared in the first insulating layer 220.

[0150] The preparation process of the first display device layer can be similar to the first to fifth steps described above, and will not be repeated here.

[0151] In an embodiment, the via interconnection metal structure corresponding to the second sub-pixel and the third sub-pixel is prepared in the first insulating layer, including: opening and metal backfilling the color compound in the first insulating layer to form the via interconnection metal structure penetrating the color compound.

[0152] (2) For the second display device layer 300, the second layer color compound 950 is bonded and integrated onto the first display device layer 200, and the second layer color compound 950 is pixelated to form the second sub-pixel 310; the second sub-pixel 310 is filled with insulating medium to form the second insulating layer 320, and the second insulating layer 320 is planarized to expose the upper surface of the second sub-pixel 310; the via interconnection metal structure corresponding to the third sub-pixel 410 is prepared in the second insulating layer 320.

[0153] The first display device layer prepared in the fifth step is defined as a new driving wafer, and the first to third steps are repeated to stack to complete the pixelation preparation of the double layers. Then, the insulating medium is filled, and then the upper surface of the second sub-pixel is exposed by planarization, and the via interconnection metal structure is prepared.

[0154] In an embodiment, the via interconnection metal structure corresponding to the third sub-pixel is prepared in the second insulating layer, including: opening and metal backfilling the color compound in the second insulating layer to form the via interconnection metal structure penetrating the color compound.

[0155] (3.1) For the third display device layer 400, the third layer color compound 960 is bonded and integrated onto the second display device layer 300, and the third layer color compound 960 is pixelated to form the third sub-pixel 410; the insulating medium is deposited on the sidewall of the third sub-pixel 410 to form the third insulating layer 420; the region in the second insulating layer 320 aligned with the first sub-pixel 210 is patterned and etched to form the opening 600 to expose the upper surface and / or part of the sidewall of the first sub-pixel 210.

[0156] As shown in FIG. 15, the prepared second display device layer is defined as a new driving wafer, and the first step to the third step are repeated to stack and complete the pixelation preparation of three layers.

[0157] Further, the insulating layer is prepared, and after patterning and etching, the epitaxial surface of the third sub-pixel is exposed to form the third insulating layer of the sidewall of the third sub-pixel. The third insulating layer can be prepared by plasma deposition, sputtering, atomic layer deposition, etc., and the thickness range is 1 nm to 500 nm.

[0158] (3.2) For the third display device layer 400, the third layer color compound 960 is bonded and integrated onto the second display device layer 300, and the third layer color compound 960 is pixelated to form the third sub-pixel 410; the insulating medium is filled in the third sub-pixel 410 to form the third insulating layer 420, and the upper surface and / or part of the sidewall of the third sub-pixel 410 is exposed in the third insulating layer 420; the region in the third insulating layer 420 aligned with the second sub-pixel 310 is patterned and etched to form the opening 600 to expose the upper surface and / or part of the sidewall of the second sub-pixel 310, and the region in the third insulating layer 420 and the second insulating layer 320 aligned with the first sub-pixel 210 is patterned and etched to form the opening 600 to expose the upper surface and / or part of the sidewall of the first sub-pixel 210.

[0159] As shown in FIG. 15, the prepared second display device layer is defined as a new driving wafer, and the first step to the third step are repeated to stack and complete the pixelation preparation of three layers.

[0160] Further, the insulating medium is filled, and then the upper surface and / or part of the sidewall of the third sub-pixel 410 are exposed by planarization and / or etching technology, and the upper surface and / or part of the sidewall of the first sub-pixel 210 and the second sub-pixel 310 are exposed by patterned etching.

[0161] In an embodiment, the third display device layer 400 is planarized to expose the upper surface of the third sub-pixel 410, and then the upper surface and the sidewall of the second sub-pixel 310 and the first sub-pixel 210 are patterned and etched, and then electrical connection is performed.

[0162] In an embodiment, the third display device layer 400 is subjected to a planarization technique and / or an etching technique to expose the upper surface and sidewall of the third sub-pixel 410, and then the upper surface and sidewall of the second sub-pixel 310 and the first sub-pixel 210 are etched by patterning, and then electrical connection is performed.

[0163] In an embodiment, the second display device layer 300 is subjected to planarization, and a certain thickness of insulating layer material is left above the third sub-pixel 410, and then the upper surface and sidewall of the first sub-pixel 210, the second sub-pixel 310 and the third sub-pixel 410 are exposed by patterning, and then electrical connection is performed.

[0164] It can be understood that in the above embodiment, the upper surface of each sub-pixel can be roughened to increase the light extraction rate. Light emitted from the compound into the air is from a high refractive index to a low refractive index medium, and there is a total reflection phenomenon. Taking the GaN system as an example, the light generated by the active region in the emission process is incident from the optically dense medium GaN (refractive index n=2.4) to the optically sparse medium air (n=1), and the critical angle of total reflection is about 24.5°. That is, a large part of the emitted light with an angle greater than 24.5° with the GaN / air interface undergoes total reflection at the interface and returns to the compound. This part of the light returning to the compound will be collected to the bottom again due to reflection, and the light extraction efficiency will be reduced again. By roughening the surface, the total reflection interface can be reduced, the light extraction rate can be increased, and the brightness can be improved.

[0165] Step S3: preparing a transparent conductive layer 500, the first ohmic contact layer of the sub-pixel in any display device layer is connected to a common cathode through the transparent conductive layer, and the transparent conductive layer 500 is disposed on the first ohmic contact layer of the sub-pixel in each display device layer.

[0166] Specifically, after the exposure of the upper surface of the sub-pixel in each display device layer is completed, electrical connection is performed, and a transparent conductive film is deposited by sputtering, evaporation or the like to form a transparent conductive layer.

[0167] Further, after step S3, it further includes: disposing a metal reinforcing structure 700 on the transparent conductive layer 500, and the projection of the metal reinforcing structure 700 on the driving wafer 100 does not coincide with the second ohmic contact layer 930 in the sub-pixel in any display device layer.

[0168] Specifically, the metal reinforcing structure 700 is prepared on the transparent conductive layer 500, which can be realized by patterning evaporation, sputtering, or by plating and etching.

[0169] In an embodiment, the metal enhanced structure is realized by patterning and plating a Ni, Al, Ti, Au stack, which realizes better current spreading, and the cavity formed by the structure can constrain light emission distribution and improve brightness.

[0170] In summary, the preparation method of the micro display device provided in the embodiment integrates one or more display device layers on the driving wafer, at least one of the display device layers is filled with an insulating layer, and the top of the insulating layer around the sub-pixel is not higher than the top of the first ohmic contact layer of the sub-pixel in the same layer, so that the first ohmic contact layer of the sub-pixel in any display device layer is connected to the common cathode through the transparent conductive layer, the transparent conductive layer can be arranged on the first ohmic contact layer of the sub-pixel in each display device layer, thereby greatly increasing the contact area between the transparent conductive layer and the epitaxial layer, increasing the current injection area, reducing the resistance, improving the photoelectric efficiency of the device, and realizing the preparation of a high-brightness pixel unit.

[0171] Embodiment Two

[0172] The LED display device in the embodiment has a Z direction and an X direction, which are perpendicular to each other, wherein the Z direction is the stacking direction of the display device layers, and can also be understood as the direction away from / close to the driving backplane, wherein the "height" or "up, down" or "top, bottom" are along the Z direction.

[0173] Referring to FIGS. 16-17, the embodiment provides a micro display device, which includes a driving wafer 100 and a display device layer arranged on the driving wafer 100; the display device layer includes a sub-pixel, and the sub-pixel is provided with a first ohmic contact layer 920 away from one side of the driving wafer 100.

[0174] The first ohmic contact layer 920 of the sub-pixel in at least one of the display device layers is electrically connected to the transparent conductive layer 500, the transparent conductive layer 500 is arranged on the first ohmic contact layer 920 of the sub-pixel, the entire upper surface b1 and at least part of the sidewall b2 of the first ohmic contact layer 920 are exposed to form an exposed area 1500, the exposed area 1500 and the transparent conductive layer 500 are in contact to realize the electrical connection of the top end of the sub-pixel.

[0175] For example, as shown in the structure of FIG. 16, only one display device layer is arranged, which is a first display device layer 200, the first display device layer 200 is connected to the driving wafer 100, and three first sub-pixels 210 are arranged in the first display device layer 200, the entire upper surface and part of the sidewall of each first sub-pixel 210 are exposed and directly in contact with the transparent conductive layer 500.

[0176] It can be understood that the first ohmic contact layer 920 in the embodiment can be a P-type ohmic contact layer or an N-type ohmic contact layer.

[0177] The transparent conductive layer 500 can be a combination of one or more of an ITO (Indium Tin Oxide) film, an AZO (Antimony doped Zinc Oxide) film, an ATO (Antimony doped Tin Oxide) film, and an FTO (Fluorine doped Tin Oxide) film, or a single layer or a stack of metal-doped ITO formed by annealing after plating thin Al, Au, or Ag on the ITO surface to enhance the current transmission capacity of the common cathode.

[0178] The driving wafer 100 is an element having a driving circuit, and the sub-pixel is a light-emitting element, so that the sub-pixel can be driven to emit light by electrical connection of the driving wafer 100 and the sub-pixel, and each sub-pixel can be independently driven to emit light.

[0179] The driving wafer 100 includes, but is not limited to, a CMOS (Complementary Metal Oxide Semiconductor) driving backplane or a TFT glass substrate.

[0180] The top end and the bottom end of the sub-pixel are two ends with opposite polarities, for example, the top end is the end where the N-type ohmic contact layer is located (or the end where the P-type ohmic contact layer is located-anode), and the bottom end is the end where the P-type ohmic contact layer is located (or the end where the N-type ohmic contact layer is located-cathode), which need to be connected to electrode terminals with different polarities, respectively.

[0181] In the above structure, the entire upper surface of the first ohmic contact layer of the sub-pixel is exposed, and the sidewall is also exposed, which greatly increases the exposed area compared with only exposing a small part of the upper surface, and the exposed area is used as an electrical contact area and an electrical contact of the transparent conductive layer, thereby effectively increasing the electrical contact area and enhancing the current spreading. Especially in the case of designing the sub-pixel to be smaller in size, the current injection area increases more obviously, the power consumption advantage is more obvious, and it is also more beneficial to heat dissipation, which ultimately reduces the power consumption and increases the photoelectric performance and reliability of the device.

[0182] In addition, the sub-pixel is a compound semiconductor material, which is a light-dense medium, the transparent conductive layer 500 is also a light-dense medium, and the insulating medium layer (for example, SiO2) is a light-lean medium. In the conventional pixel structure, only a small part of the upper surface of the first ohmic contact layer 920 is exposed in the optical transmission path, and the upper surface of the first ohmic contact layer 920 is covered with the insulating medium layer. That is, when the light emitted by the sub-pixel is transmitted through the upper surface and the sidewall of the sub-pixel, the transmission mode is from the compound (light-dense medium) to the insulating medium (light-lean medium) to the transparent conductive layer (light-dense medium) to the lens (light-lean medium, which can be SiO2). That is, the optical transmission mode is from the light-dense medium to the light-lean medium to the light-dense medium to the light-lean medium. In the embodiment, when the light emitted by the sub-pixel is transmitted through the upper surface and the sidewall of the sub-pixel, the transmission mode is from the compound (light-dense medium) to the transparent conductive layer (light-dense medium) to the lens (light-lean medium). That is, the optical transmission mode is from the light-dense medium to the light-lean medium, which can effectively reduce the loss of light and effectively improve the extraction rate of light.

[0183] In the embodiment, as shown in FIG. 17, in the same layer of the display device layer: the transparent conductive layer 500 includes a contact section 501 and a non-contact section 502. The contact section 501 is the section of the transparent conductive layer 500 that is in contact with the exposed section 1500 of the same layer of the sub-pixel. The section of the transparent conductive layer 500 other than the contact section 501 is the non-contact section 502.

[0184] In the embodiment, as shown in FIG. 17, in the same layer of the display device layer: the transparent conductive layer 500 includes a contact section 501 and a non-contact section 502. The contact section 501 is the section of the transparent conductive layer 500 that is in contact with the exposed section 1500 of the same layer of the sub-pixel. The section of the transparent conductive layer 500 other than the contact section 501 is the non-contact section 502.

[0185] It can be understood that the non-contact section 502 of the transparent conductive layer 500 includes not only the vertical part at the sidewall of the sub-pixel, but also the horizontal part at the bottom of the sub-pixel.

[0186] Further, the fourth insulating layer 1000 is in contact with the sidewall of the sub-pixel.

[0187] In the embodiment, the sub-pixel is provided with the first ohmic contact layer 920 away from one end of the driving wafer 100 and the second ohmic contact layer 930 close to one end of the driving wafer 100. The polarities of the first ohmic contact layer 920 and the second ohmic contact layer 930 are opposite. It can be understood that the first ohmic contact layer 920 and the second ohmic contact layer 930 in the application can be designed as a P-type ohmic contact layer and an N-type ohmic contact layer, respectively, or an N-type ohmic contact layer and a P-type ohmic contact layer, respectively.

[0188] The driving wafer 100 is provided with an electrode contact corresponding to the sub-pixel, the first ohmic contact layer 920 of the sub-pixel is used to electrically connect with the transparent conductive layer 500, and the second ohmic contact layer 930 is used to electrically connect with the corresponding electrode contact, so as to realize the electrical connection between the sub-pixel and the driving wafer 100.

[0189] For example, the first ohmic contact layer 920 at the top end of the sub-pixel is an N-type ohmic contact layer, the second ohmic contact layer 930 at the bottom end is a P-type ohmic contact layer, the driving wafer 100 is provided with an anode contact 110 corresponding to the sub-pixel, and then the transparent conductive layer 500 is a cathode connection layer. The top end of the sub-pixel is connected to the transparent conductive layer 500 through the N-type ohmic contact layer to realize cathode connection, and the bottom end is electrically connected to the corresponding anode contact 110 through the P-type ohmic contact layer to realize anode connection.

[0190] In some embodiments, in a display device layer of a certain layer: as shown in FIGS. 16-17, the periphery of the sub-pixel is surrounded by a metal fence 1200, which is a metal material and is a conductive material;

[0191] The metal fence 1200 is located between the non-contact section 502 at the side wall of the sub-pixel and the fourth insulating layer 1000, and a fifth insulating layer 1100 is further arranged between the metal fence 1200 and the non-contact section 502 at the side wall of the sub-pixel, so as to realize the insulation and isolation between the transparent conductive layer 500 and the metal fence 1200.

[0192] In the above structure, the metal fence 1200 at the periphery of the sub-pixel can increase the heat conduction capacity of the device layer. When the display device is working, the transparent conductive layer 500 will generate high heat due to resistance, and the metal fence 1200 can accelerate the export of these heat, thereby reducing the heat accumulation problem of the pixel unit and enhancing the heat dissipation effect, thereby greatly reducing the working temperature of the device and more conducive to ensuring the long-term stable operation of the device.

[0193] Further, the metal fence 1200 is formed on the upper part of the metal bonding layer 910, one end of the sub-pixel close to the driving wafer 100 is provided with the second ohmic contact layer 930 and connected to the metal bonding layer 910 through the second ohmic contact layer 930, and the second ohmic contact layer 930 is located inside the metal fence 1200.

[0194] The metal bonding layer 910 is electrically connected with the corresponding anode contact 110 on the driving wafer 100. Through the above arrangement, the bottom end of the sub-pixel is finally electrically connected to the anode contact 110 through the metal bonding layer 910 to realize anode connection, and the top end is connected to the transparent conductive layer 500 to realize cathode connection.

[0195] Exemplarily, the driving wafer 100 is provided with a first display device layer 200, and the first display device layer 200 has a plurality of first sub-pixels 210, each of the first sub-pixels 210 corresponds to an anode contact 110 on the driving wafer 100 in one-to-one correspondence, and the bottom end of each of the first sub-pixels 210 is electrically connected to the corresponding anode contact 110 through a metal bonding layer 910.

[0196] In other ways, a plurality of anode contacts 110 can also correspond to one first sub-pixel 210.

[0197] In the specific preparation, when the metal bonding layer 910 around the sub-pixel is etched, the metal fence 1200 is sputtered on the upper part of the metal bonding layer, and the metal bonding layer 910 and the metal fence 1200 are both metal materials and conductive materials.

[0198] In some embodiments, the sub-pixel includes a second ohmic contact layer 930, an active layer 2101 and a first ohmic contact layer 920 arranged in a direction away from the driving wafer 100; wherein the active layer 2101 can adopt an active quantum well for emitting light.

[0199] As shown in FIG. 17, the lowest point of the exposed area 1500 of the sub-pixel is not lower than the upper surface b4 of the active layer 2101, so as to avoid short circuit of the sub-pixel, increase the current transmission area, and reduce the resistance and power consumption of the device.

[0200] In some embodiments, as shown in FIG. 17, in the display device layer where the metal fence 1200 is located, the upper surface b3 of the metal fence 1200 is lower than the upper surface b1 of the first ohmic contact layer 920 of the sub-pixel and higher than the upper surface of the second ohmic contact layer 930.

[0201] Further, in the display device layer where the metal fence 1200 is located, the upper surface b3 of the metal fence 1200 is not lower than the upper surface b4 of the active layer 2101. The light emitted from the active layer 2101 of the sub-pixel is emitted from above, and part of the light is emitted in the direction of the sidewall. Through the above height setting, part of the light emitted in the sidewall direction can be reflected by the metal fence 1200 and emitted in the obliquely upper direction, which can effectively reduce the light crosstalk problem between the adjacent pixels in the X direction, and also make most of the light emitted by the sub-pixel can be emitted from the upper part (directly above and obliquely above) of the sub-pixel, greatly improving the emission intensity and enhancing the light efficiency; as shown in FIG. 16, the arrow direction is the light emission direction of the sub-pixel.

[0202] In some embodiments, in the display device layer where the metal fence 1200 is located: the metal fence 1200 and the peripheral transparent conductive layer 500 are not in contact, and the minimum spacing therebetween is not less than 5 nm, so as to ensure that the metal fence 1200 and the transparent conductive layer 500 are not in contact, thereby effectively ensuring the insulation isolation effect therebetween.

[0203] It can be understood that the above-mentioned "minimum spacing" can be vertical spacing or horizontal spacing.

[0204] Further, in the display device layer where the metal fence 1200 is located: the vertical spacing (Z direction) between the metal fence 1200 of each sub-pixel and the peripheral transparent conductive layer 500 is not less than 5 nm, and the horizontal spacing (X direction) between the metal fence 1200 and the peripheral transparent conductive layer 500 is not less than 5 nm, so as to ensure that the metal fence 1200 and the transparent conductive layer 500 are not in contact, thereby effectively ensuring the insulation isolation effect therebetween.

[0205] For example, a display device layer is provided, in which the vertical spacing between the upper surface of the metal fence 1200 and the lower surface of the transparent conductive layer 500 located above is H2, and the horizontal spacing between the outer sidewall of the metal fence 1200 and the transparent conductive layer 500 at the peripheral sidewall is H1, then H2≥5 nm, and H1≥5 nm.

[0206] In the specific preparation, the thickness of the fifth insulating layer 1100 can be uniform or non-uniform.

[0207] In the specific arrangement, the smaller the spacing between the metal fence 1200 and the peripheral transparent conductive layer 500, the stronger the heat conduction ability, and the temperature of the device is effectively reduced. However, if the spacing is too small, the insulation isolation effect of the two cannot be effectively ensured, and short circuit risk is caused.

[0208] When the fifth insulating layer 1100 is provided between the metal fence 1200 and the peripheral transparent conductive layer 500, the fifth insulating layer 1100 can be selected to have strong insulation ability, so as to thin the thickness of the fifth insulating layer 1100, thereby reducing the spacing between the metal fence 1200 and the peripheral transparent conductive layer 500.

[0209] In some embodiments, as shown in FIG. 31, the upper surface b3 of the metal fence 1200 surrounding the first sub-pixel 210 and the transparent conductive layer 500 located above have an insulating medium 1600, and the insulating medium 1600 has an insulating bending portion 1601, and the bending shape of the insulating bending portion 1601 can be L-shaped, arc-shaped or other shapes, which are not limited here.

[0210] It can be understood that the above-mentioned insulating medium 1600 can be formed by the fourth insulating layer 1000 and / or the fifth insulating layer 1100.

[0211] In some modes, the non-contact section 502 of the transparent conductive layer 500 can also be provided with a bending part at the end connected to the contact section, which can be consistent with the bending direction of the insulating bending part 1601.

[0212] In some preferred embodiments, as shown in FIG. 16, multiple sub-pixels in the same display device layer share one transparent conductive layer 500, and if the transparent conductive layer 500 is connected to the cathode end (N-type ohmic contact layer) of the sub-pixel, then the transparent conductive layer 500 is a common cathode layer.

[0213] In other modes, each sub-pixel can also independently use a corresponding transparent conductive layer 500, that is, the transparent conductive layer and the sub-pixel are one-to-one.

[0214] The preparation process of the micro display device of the present embodiment will be described in detail taking a micro display device with only one display device layer as an example: first, bond the first layer of color compound 940 to the driving wafer 100, and perform pixelization preparation on the first layer of color compound 940 to form the first sub-pixel 210; then deposit the fourth insulating layer 1000 outside the first sub-pixel 210, and then perform image etching on the device layer, as shown in g1 stage of FIG. 18, etch and remove the metal bonding layer 910 between adjacent sub-pixels, so that each first sub-pixel 210 is independently separated from each other. When etching the metal bonding layer 910, a metal fence 1200 can be sputtered on the upper part of the metal bonding layer 910; then, as shown in g2 stage of FIG. 18, deposit the fifth insulating layer 1100 on the surface of the device layer; then perform etching treatment, as shown in g3 stage of FIG. 18, to expose the upper surface b1 and at least part of the side wall b2 of the first ohmic contact layer 920 of the first sub-pixel 210 to form an exposed area 1500, and then, as shown in g4 stage of FIG. 18, deposit the transparent conductive layer 500, so that the transparent conductive layer 500 is deposited on the first ohmic contact layer 920 of the first sub-pixel 210, and the transparent conductive layer 500 is in contact with the exposed area 1500.

[0215] In some modes, an etching barrier layer 1400 can also be provided on the upper surface of the color compound before pixelization preparation, so as to avoid damaging the top surface of the sub-pixel during pixelization preparation.

[0216] The micro display device of the above embodiment can increase the electrical contact area between the sub-pixel and the transparent conductive layer 500, enhance the current spreading, thereby reducing the power consumption of the device, and the metal fence 1200 arranged at the periphery of the sub-pixel can effectively increase the heat conduction capacity of the device, thereby reducing the heat accumulation problem of the pixel during operation, greatly reducing the temperature of the device, and facilitating the long-term stable operation of the device.

[0217] Embodiment Three

[0218] As shown in FIGS. 19-29, the main difference between the present embodiment and Embodiment Two is that in the present embodiment, the transparent conductive layer 500 is further provided with a metal reinforcing structure 700, which is a metal conductive structure and can enhance the current spreading and improve the conductive capacity of the transparent conductive layer 500.

[0219] In some preferred embodiments, as shown in FIGS. 19-20, multiple sub-pixels in the same display device layer share one transparent conductive layer 500, and if the transparent conductive layer 500 is connected to the cathode end (N-type ohmic contact layer) of the sub-pixel, then the transparent conductive layer 500 is a common cathode layer.

[0220] In some embodiments, as shown in FIG. 19, one metal reinforcing structure 700 is arranged at the periphery of multiple sub-pixels in the same display device layer, or as shown in FIG. 20, one metal reinforcing structure 700 is arranged at the periphery of each sub-pixel in the same display device layer. That is, the metal reinforcing structure 700 can be shared by multiple sub-pixels or used independently by each sub-pixel.

[0221] The single-pixel exclusive mode has better current transmission capacity, and the multiple-pixel shared mode is more suitable for reducing the size of the pixel, especially for small-size display devices.

[0222] In some embodiments, as shown in FIGS. 26-29, in the same display device layer: a metal reinforcing structure 700 is arranged between two adjacent sub-pixels, the metal reinforcing structure 700 includes a metal side wall 701, and the metal side wall 701 is attached to the non-contact section 502 of the transparent conductive layer 500 at the side wall of at least one of the two adjacent sub-pixels. That is, the metal side wall 701 is attached to the non-contact section 502 at the side wall of the sub-pixel, and this structure can adjust the direction of the outgoing light of the sub-pixel through the metal side wall 701 of the metal reinforcing structure 700, thereby adjusting the light-emitting curve and the light-emitting angle.

[0223] When the light emitted by the sub-pixel is emitted towards the side wall direction, there is a part of light rays emitted via the side wall area above the metal fence 1200, which, after passing through the transparent conductive layer 500, is incident at the metal side wall 701 of the metal reinforcing structure 700, so as to be reflected back by the metal side wall 701 to change the light path direction, thereby achieving the adjustment of the light emitting angle of the sub-pixel and achieving the effect of enhancing the light emitting effect.

[0224] The above structure can adopt the following two forms when being specifically arranged.

[0225] The first form: as shown in FIGS. 26-27, only the non-contact section 502 of the transparent conductive layer 500 at the side wall of one of the two adjacent sub-pixels is attached with the metal side wall 701, and the non-contact section 502 of the side wall of the other sub-pixel does not need to be provided with the metal side wall 701, at this time, the metal reinforcing structure 700 can only include one metal side wall 701.

[0226] In this way, the metal side walls 701 at the periphery of different sub-pixels can be located at the same side (left side or right side), or the metal side walls 701 at the periphery of some sub-pixels can be located at the left side, and the metal side walls 701 at the periphery of other sub-pixels can be located at the right side, which is flexibly arranged according to the requirements of the light emitting curve.

[0227] The second form: as shown in FIGS. 28-29, the metal reinforcing structure 700 includes two oppositely arranged metal side walls 701, one metal side wall 701 is attached to the non-contact section 502 of the transparent conductive layer 500 at the side wall of one of the two adjacent sub-pixels, and the other metal side wall 701 is attached to the non-contact section 502 of the transparent conductive layer 500 at the side wall of the other of the two adjacent sub-pixels.

[0228] The two oppositely arranged metal side walls 701 in the above metal reinforcing structure 700 can be symmetrically arranged or asymmetrically arranged.

[0229] Further, as shown in FIG. 29, the two oppositely arranged metal side walls 701 of the metal reinforcing structure are connected through a metal connecting part 702. The metal connecting part 702 is attached to the horizontal section of the non-contact section 502 of the transparent conductive layer 500.

[0230] In some embodiments, as shown in FIGS. 27 and 29, the upper part of the metal side wall 701 at the periphery of the sub-pixel forms a metal bending part 7011, which is bent towards the axis direction of the sub-pixel, so as to better adjust the light emitting direction of the sub-pixel. For example, referring to FIG. 26, the metal bending part 7011 of the metal side wall at the periphery of the first sub-pixel 210 located at the leftmost side in the display device layer is bent towards the axis O1-O1 direction of the sub-pixel.

[0231] It can be understood that the metal bending part 7011 can be L-shaped, or arc-shaped or other shapes, and the application does not limit the bending shape thereof.

[0232] In some embodiments, as shown in FIGS. 27 and 29, the highest point b5 of the metal side wall 701 of the sub-pixel periphery is higher than the upper surface b3 of the metal fence 1200 of the same sub-pixel periphery. This mode can effectively adjust the light path of the light emitted via the side wall area above the metal fence 1200, so that this part can be transmitted to the metal side wall 701 and reflected back via the metal side wall 701, so that the light emission of the sub-pixel is more concentrated, which has a light condensing effect.

[0233] Further, the highest point b5 of the metal side wall 701 of the sub-pixel periphery is not lower than the upper surface b1 of the first ohmic contact layer 920 of the sub-pixel, so as to better adjust the light emission direction and also prevent the light crosstalk phenomenon between pixels.

[0234] In some embodiments, as shown in FIG. 21, the above-mentioned metal reinforcing structure 700 can also not have a metal side wall 701, but only have a metal connecting part 702.

[0235] Embodiment Four

[0236] Referring to FIGS. 21-29, the main difference between the present embodiment and Embodiment Three is that the present embodiment further comprises a lens 1300, and the lens 1300 is arranged on the upper part of a certain layer of display device layer, so that each lens 1300 covers at least one sub-pixel in the same layer of display device layer, that is, one lens 1300 can correspond to multiple sub-pixels, or the sub-pixel and the lens 1300 can be one-to-one.

[0237] The one-to-one correspondence between the sub-pixel and the lens 1300 can better guarantee the light emission effect of each sub-pixel; the multiple sub-pixels sharing one lens 1300 can be more conducive to reducing the size of the pixel, and is particularly suitable for small-size display devices.

[0238] In the specific arrangement, the above-mentioned lens 1300 can be arranged on the upper part of the uppermost layer of display device layer.

[0239] Through the arrangement of the lens 1300, the light emission effect can be enhanced and the light emission brightness can be improved.

[0240] The lens 1300 can be made of an insulating material.

[0241] For example, the lens 1300 can be made of one or more of silicon dioxide, silicon nitride, aluminum oxide, silicate glass, PMMA, silicone material or SU8, etc.

[0242] The height of the bottom surface of the lens 1300 can be set in the following ways:

[0243] The first way: the bottom surface j1 of the lens 1300 is not lower than the upper surface b1 of the first ohmic contact layer 920 of the corresponding sub-pixel in the display device layer connected with the lens 1300. That is, the bottom surface of the lens 1300 is above or flush with the first ohmic contact layer 920 of the top surface of the sub-pixel.

[0244] The second way: as shown in FIG. 21, the bottom surface j1 of the lens 1300 is lower than the upper surface b1 of the first ohmic contact layer 920 of the corresponding sub-pixel in the display device layer connected with the lens 1300.

[0245] Further, the bottom surface j1 of the lens 1300 is lower than the upper surface b3 of the metal fence 1200 of the periphery of the corresponding sub-pixel in the display device layer connected with the lens 1300; this way can make the light emitted above the metal fence 1200 be focused via the lens 1300, reduce the light-emitting angle of the pixel, and also well reduce the light crosstalk phenomenon between the pixels, which is beneficial to reducing the loss of light energy.

[0246] In some embodiments, in the display device layer connected with the lens 1300: each sub-pixel corresponds to one lens 1300, and a metal reinforcing structure 700 is arranged between adjacent two sub-pixels, the metal reinforcing structure 700 includes a metal connecting part 702, and the bottom surface of the lens 1300 is not lower than the upper surface of the metal connecting part 702 of the periphery of the corresponding sub-pixel. For example, as shown in FIG. 22, the bottom surface j1 of the lens 1300 is higher than the upper surface of the metal connecting part 702 of the periphery of the corresponding sub-pixel, or as shown in FIG. 21, the bottom surface j1 of the lens 1300 is flush with the upper surface of the metal connecting part 702 of the periphery of the corresponding sub-pixel.

[0247] Further, as shown in FIGS. 26-30, when the metal reinforcing structure 700 has a metal side wall 701, and the metal side wall 701 is attached to the non-contact section 502 of the transparent conductive layer 500 at the side wall of the sub-pixel, the metal side wall 701 of the periphery of each sub-pixel is covered by the corresponding lens 1300.

[0248] In some embodiments, a plurality of lenses 1300 are arranged on the upper part of a certain layer of the display device layer. As shown in FIG. 23, adjacent two lenses 1300 are separated from each other to be independently arranged; or as shown in FIGS. 22 and 24, adjacent two lenses 1300 are interconnected to form an integrated structure.

[0249] In some embodiments, as shown in FIG. 24, the lens 1300 includes a curved part 1301 and a flat part 1302, and the bottom end of the curved part 1301 is provided with the flat part 1302, so as to be more conducive to preparation.

[0250] In some embodiments, as shown in FIG. 25, in the display device layer connected with the lens 1300, each sub-pixel corresponds to one lens 1300, and the axis of each lens 1300 is offset relative to the axis of the corresponding sub-pixel.

[0251] The offset arrangement of the lens 1300 and the axis of the corresponding sub-pixel can change the light-emitting curve or light-emitting angle of the sub-pixel through the offset amount of the axis, so as to achieve the effect that the light-emitting effect is controllable.

[0252] In the specific design, each lens 1300 can be offset in the same direction (left or right), or the offset directions of different lenses 1300 can be different.

[0253] Embodiment Five

[0254] Referring to FIGS. 1-2, the main difference between the present embodiment and embodiment two is that in the same layer of the display device layer, the transparent conductive layer 500 includes a contact section 501 and a non-contact section 502, the contact section 501 is the section of the transparent conductive layer 500 that contacts the exposed area 1500 of the sub-pixel in the same layer, and the section of the transparent conductive layer 500 other than the contact section 501 is the non-contact section 502, wherein the non-contact section 502 is arranged close to the upper region of the sub-pixel in the same layer.

[0255] For example, referring to FIGS. 1-2, in the present embodiment, the upper part of the first display device layer 200 is provided with the transparent conductive layer 500, the non-contact section 502 of the transparent conductive layer 500 is located in the upper region of the first sub-pixel in the same layer, and the transparent conductive layer 500 is arranged on the first ohmic contact layer 920 of the first sub-pixel 210. Specifically, the upper surface b1 and at least part of the side wall b2 of the first ohmic contact layer 920 of the first sub-pixel 210 are exposed to form the exposed area 1500, and the exposed area 1500 and the contact section 501 of the transparent conductive layer are in contact to realize the electrical connection between them.

[0256] Embodiment Six

[0257] In the present embodiment, the sub-pixel includes a second ohmic contact layer 930, an active layer 2101, and a first ohmic contact layer 920 arranged in a direction away from the driving wafer;

[0258] As shown in FIG. 30, the lower surface of the active layer 2101 of the first sub-pixel 210 and the upper surface of the second ohmic contact layer 930 have a layer body part 940, and the layer body part 940 at least partially extends below the fourth insulating layer. That is, the fourth insulating layer 1000 and the second ohmic contact layer 930 are separated by a part of the layer body part, and this part of the layer body part does not need to be etched and removed.

[0259] The layer body can be a compound semiconductor material.

[0260] Embodiment Seven

[0261] In this embodiment, a first ohmic contact layer 920 of a sub-pixel in a display device layer is electrically connected to a transparent conductive layer 500, the transparent conductive layer 500 is disposed on the first ohmic contact layer 920 of the sub-pixel, and the first ohmic contact layer 920 has an exposed area 1500.

[0262] The main difference between this embodiment and Embodiment Two is that only the upper surface of the first ohmic contact layer 920 of the sub-pixel is fully exposed to form the exposed area 1500, and the sidewall of the sub-pixel is not exposed, so that the exposed area 1500 is in contact with the transparent conductive layer 500 to achieve electrical connection.

[0263] Further, as shown in FIG. 31, the sidewall of the first sub-pixel 210 is covered by the insulating layer, and only the upper surface of the first ohmic contact layer is in contact with the transparent conductive layer 500.

[0264] In some embodiments, as shown in FIG. 31, there is an insulating medium 1600 between the upper surface b3 of the metal fence 1200 around the first sub-pixel 210 and the transparent conductive layer 500 above, and the insulating medium 1600 has an insulating bending portion 1601.

[0265] The insulating bending portion 1101 described above also extends to be in contact with the sidewall of the first sub-pixel 210, so that the sidewall of the first sub-pixel is fully covered by the insulating layer, at this time, the sidewall of the first sub-pixel 210 is completely isolated from the transparent conductive layer 500, so that only the upper surface of the first ohmic contact layer 920 is in contact with the transparent conductive layer 500 to achieve electrical connection.

[0266] In the above structure, the entire upper surface of the first ohmic contact layer of the sub-pixel is exposed, which greatly increases the exposed area compared to only exposing a small part of the upper surface, and the exposed area is used as an electrical contact area and is in electrical contact with the transparent conductive layer, thereby effectively increasing the electrical contact area and enhancing the current spreading. Especially in the case of designing the sub-pixel to be smaller in size, the current injection area increases more obviously, and the power consumption advantage is more obvious. At the same time, it is also more beneficial to heat dissipation, and finally reduces the power consumption, increases the photoelectric performance and reliability of the device.

[0267] Embodiment Eight

[0268] The main difference between this embodiment and Embodiment Two is that no metal fence 1200 is provided in this embodiment.

[0269] In the embodiment, in the same display device layer, the transparent conductive layer 500 includes a contact section 501 and a non-contact section 502, the contact section 501 is a section of the transparent conductive layer 500 that contacts the exposed section 1500 of the sub-pixel in the same layer, and the section of the transparent conductive layer 500 other than the contact section 501 is the non-contact section 502;

[0270] The non-contact section 502 in the transparent conductive layer 500 is partially located at the sidewall of the corresponding sub-pixel in the same layer, and the non-contact section 502 at the sidewall of the sub-pixel and the sidewall of the sub-pixel are provided with an insulating layer to realize the insulation and isolation of the non-contact section 502 and the sidewall of the sub-pixel.

[0271] The one side of the insulating layer is fitted with the sidewall of the sub-pixel, and the other side is fitted with the non-contact section 502, that is, the one side of the insulating layer is directly fitted with the non-contact section 502 of the transparent conductive layer 500, and there is no metal fence between them.

[0272] For example, as shown in FIG. 8, in the third display device layer, the non-contact section 502 at the sidewall of the sub-pixel and the sidewall of the sub-pixel are provided with a third insulating layer 420, one side of the third insulating layer 420 is directly fitted with the sidewall of the sub-pixel, and the other side is directly fitted with the non-contact section 502.

[0273] Alternatively, as shown in FIG. 32, the non-contact section 502 at the sidewall of the sub-pixel and the sidewall of the sub-pixel are provided with a fourth insulating layer 1000, one side of the fourth insulating layer 1000 is directly fitted with the sidewall of the sub-pixel, and the other side is directly fitted with the non-contact section 502.

[0274] All the optional technical solutions described above can be combined to form optional embodiments of the present application, that is, any number of embodiments can be combined to meet the needs of different application scenarios, which are all within the protection scope of the present application and will not be described one by one here.

[0275] It should be noted that the above embodiments are only examples for clear illustration, and are not limitations on the embodiments. Based on the above description, other different forms of changes or variations can be made by those skilled in the art. Here, it is not necessary and impossible to exhaust all the embodiments. The obvious changes or variations derived therefrom are still within the protection scope of the present application.

Claims

1. A microdisplay device, characterized by: The micro display device comprises a driving wafer and a display device layer disposed on the driving wafer; The display device layer comprises sub-pixels, and a first ohmic contact layer is disposed on a side of the sub-pixels away from the driving wafer; At least one first ohmic contact layer of the sub-pixels in the display device layer is electrically connected with a transparent conductive layer, the transparent conductive layer is disposed on the first ohmic contact layer of the sub-pixels, the first ohmic contact layer has an exposed area, the upper surface of the first ohmic contact layer is completely exposed to form the exposed area, and the exposed area is in contact with the transparent conductive layer.

2. The microdisplay device of claim 1, wherein: At least one first ohmic contact layer of the sub-pixels in the display device layer is electrically connected with a transparent conductive layer, the upper surface and at least part of the sidewall of the first ohmic contact layer are exposed to form the exposed area, and the exposed area is in contact with the transparent conductive layer.

3. The microdisplay device of claim 1, wherein: In the same layer of the display device layer, the transparent conductive layer comprises a contact section and a non-contact section, the contact section is in contact with the exposed area of the sub-pixel in the same layer, and the section other than the contact section in the transparent conductive layer is the non-contact section, and the non-contact section is located in the upper part of the sub-pixel in the same layer.

4. The microdisplay device of claim 1, wherein: In the same layer of the display device layer, the transparent conductive layer comprises a contact section and a non-contact section, the contact section is in contact with the exposed area of the sub-pixel in the same layer, and the section other than the contact section in the transparent conductive layer is the non-contact section, and the non-contact section is partially located at the sidewall of the corresponding sub-pixel in the same layer, and a fourth insulating layer is disposed between the non-contact section at the sidewall of the sub-pixel and the sidewall of the sub-pixel.

5. The microdisplay device of claim 4, wherein: One side of the fourth insulating layer is in contact with the sidewall of the sub-pixel, and the other side is in contact with the non-contact section.

6. The microdisplay device of claim 4, wherein: In one layer of the display device layer, the periphery of the sub-pixel is surrounded by a metal fence, the metal fence is located between the non-contact section at the sidewall of the sub-pixel and the sidewall of the sub-pixel, the fourth insulating layer is disposed between the metal fence and the sidewall of the sub-pixel, and a fifth insulating layer is further disposed between the metal fence and the non-contact section at the sidewall of the sub-pixel.

7. The microdisplay device of claim 6, wherein: The metal fence is formed in the upper part of a metal bonding layer, one end of the sub-pixel close to the driving wafer is provided with a second ohmic contact layer and connected to the metal bonding layer through the second ohmic contact layer, and the second ohmic contact layer is located in the interior of the metal fence.

8. The microdisplay device of claim 7, wherein: The sub-pixel comprises a second ohmic contact layer, an active layer and a first ohmic contact layer disposed in the direction away from the driving wafer, and the lowest point of the exposed area of the sub-pixel is not lower than the upper surface of the active layer.

9. The microdisplay device of claim 7, wherein: In the display device layer where the metal fence is located, the upper surface of the metal fence is lower than the upper surface of the first ohmic contact layer of the sub-pixel and higher than the upper surface of the second ohmic contact layer.

10. The microdisplay device of claim 9, wherein: In the display device layer where the metal fence is located, the upper surface of the metal fence is not lower than the upper surface of the active layer.

11. The microdisplay device according to claim 8, characterized in that: The sub-pixel has a layer body part between the lower surface of the active layer and the upper surface of the second ohmic contact layer, and the layer body part at least partially extends below the fourth insulating layer.

12. The microdisplay device of claim 6, wherein: In the display device layer where the metal fence is located, the metal fence is not in contact with the transparent conductive layer, and the minimum distance between the metal fence at the periphery of each sub-pixel and the transparent conductive layer is not less than 5 nm.

13. The microdisplay device of claim 6, wherein: An insulating medium is arranged between the upper surface of the metal fence at the periphery of the sub-pixel and the transparent conductive layer above, and the insulating medium has an insulating bending portion.

14. The microdisplay device of claim 1, wherein: The transparent conductive layer is shared by multiple sub-pixels in the same display device layer or is used independently by each sub-pixel.

15. The microdisplay device of claim 1, wherein: A metal reinforcing structure is further arranged on the transparent conductive layer, and one metal reinforcing structure is arranged at the periphery of multiple sub-pixels in the same display device layer, or one metal reinforcing structure is arranged at the periphery of each sub-pixel in the same display device layer.

16. The microdisplay device of claim 6, wherein: In the same display device layer, the metal reinforcing structure is arranged between two adjacent sub-pixels, and the metal reinforcing structure includes a metal side wall, and the metal side wall is attached to a non-contact section of the transparent conductive layer at the side wall of at least one of the two adjacent sub-pixels.

17. The microdisplay device of claim 16, wherein: The metal reinforcing structure includes two oppositely arranged metal side walls, one of which is attached to a non-contact section of the transparent conductive layer at the side wall of one of the two adjacent sub-pixels, and the other is attached to a non-contact section of the transparent conductive layer at the side wall of the other of the two adjacent sub-pixels.

18. The microdisplay device of claim 17, wherein: The two oppositely arranged metal side walls of the metal reinforcing structure are connected by a metal connecting portion.

19. The microdisplay device of claim 16, wherein: The upper part of the metal side wall at the periphery of the sub-pixel forms a metal bending portion, which bends towards the axis direction of the sub-pixel.

20. The microdisplay device of claim 16, wherein: The highest point of the metal side wall at the periphery of the sub-pixel is higher than the upper surface of the metal fence at the periphery of the same sub-pixel.

21. The microdisplay device of claim 20, wherein: The highest point of the metal side wall at the periphery of the sub-pixel is not lower than the upper surface of the first ohmic contact layer of the same sub-pixel.

22. The microdisplay device of claim 6, wherein: A lens is further included, and the lens is arranged on the upper part of one of the display device layers, so that each lens covers at least one sub-pixel in the same display device layer.

23. The microdisplay device of claim 22, wherein: The bottom surface of the lens is not lower than the upper surface of the first ohmic contact layer of the corresponding sub-pixel in the display device layer connected with the lens.

24. The microdisplay device of claim 22, wherein: The bottom surface of the lens is lower than the upper surface of the metal fence at the periphery of the corresponding sub-pixel in the display device layer connected with the lens.

25. The microdisplay device of claim 22, wherein: Multiple lenses are arranged on the upper part of one of the display device layers, and adjacent two lenses are separated from each other to be arranged independently; or adjacent two lenses are interconnected to form an integrated structure.

26. The microdisplay device of claim 22, wherein: The lens includes a curved portion and a flat portion, and the flat portion is arranged at the bottom end of the curved portion.

27. The microdisplay device of claim 22, wherein: In the display device layer connected with the lens, each sub-pixel corresponds to one lens, and the axis of each lens is offset relative to the axis of the corresponding sub-pixel.

Images