Shielded gate trench-type transistor and manufacturing method therefor

Abstract

The present invention provides a shielded gate trench-type transistor and a manufacturing method therefor. An inter-gate dielectric layer comprises a first inter-gate dielectric layer located on a shielded gate structure and a second inter-gate dielectric layer located on the first inter-gate dielectric layer, the first inter-gate dielectric layer is denser than the second inter-gate dielectric layer, and the two ends of the inter-gate dielectric layer protrudes from a middle portion. In this way, the two sides of the bottom of a control gate electrode are relatively smooth, and a control gate dielectric layer clamped between the bottom of the control gate electrode and the sidewall of a trench is also relatively thick, thereby avoiding the breakdown of the gate dielectric layer, and improving the performance of a device.

Description

Shield gate trench transistor and manufacturing method thereof

[0001] Cross-reference to related applications

[0002] This application claims priority to application number 202411116737.X, filed on August 14, 2024, entitled "Shield Gate Trench Transistor and Manufacturing Method Thereof", and incorporates the content thereof by reference in its entirety for all purposes. TECHNICAL FIELD

[0003] The present application relates to the technical field of semiconductor manufacturing, in particular to a shield gate trench transistor and a manufacturing method thereof. BACKGROUND

[0004] Shield Gate Trench (SGT) transistors have low specific on-resistance, low Miller capacitance, low power loss, small parasitic capacitance, high switching speed, and good high-frequency characteristics, and have occupied an increasingly large market share in medium and low voltage application fields below 250V. However, the existing shield gate trench transistors are prone to gate dielectric layer breakdown, which seriously affects the performance of the device. Therefore, the technical personnel in the field have been working hard to solve this problem. SUMMARY

[0005] The purpose of the present application is to provide a shield gate trench transistor and a manufacturing method thereof to solve the problem of the existing shield gate trench transistor that is prone to gate dielectric layer breakdown, which seriously affects the performance of the device.

[0006] In order to solve the above technical problems, the present application provides a shield gate trench transistor, which comprises:

[0007] a semiconductor substrate, wherein a trench is formed in the semiconductor substrate;

[0008] a shield gate structure located in the trench, the shield gate structure comprising a shield gate dielectric layer and a shield gate electrode located in the shield gate dielectric layer;

[0009] a gate-to-gate dielectric layer located in the trench, the gate-to-gate dielectric layer comprising a first gate-to-gate dielectric layer located on the shield gate structure and a second gate-to-gate dielectric layer located on the first gate-to-gate dielectric layer, the first gate-to-gate dielectric layer being denser than the second gate-to-gate dielectric layer, and the gate-to-gate dielectric layer being in a shape of two ends protruding from the middle; and

[0010] a control gate structure located in the trench, the control gate structure comprising a control gate dielectric layer located on the gate-to-gate dielectric layer and a control gate electrode located in the control gate dielectric layer.

[0011] Optionally, in the shielding gate trench transistor, a surface of the gate dielectric layer is a circular arc surface.

[0012] Optionally, in the shielding gate trench transistor, the first gate dielectric layer and the second gate dielectric layer are made of the same material but formed by different processes.

[0013] Optionally, in the shielding gate trench transistor, the shielding gate trench transistor further comprises:

[0014] a well region in the semiconductor substrate on both sides of the trench;

[0015] a source region in the well region;

[0016] an interlayer dielectric layer on the semiconductor substrate and covering the control gate structure; and,

[0017] a conductive layer on the semiconductor substrate and connected to the source region.

[0018] The present application also provides a manufacturing method of a shielding gate trench transistor, the manufacturing method of the shielding gate trench transistor comprising:

[0019] providing a semiconductor substrate;

[0020] forming a trench in the semiconductor substrate;

[0021] forming a shielding gate structure in the trench, the shielding gate structure comprising a shielding gate dielectric layer and a shielding gate electrode in the shielding gate dielectric layer;

[0022] forming a gate dielectric layer in the trench, the gate dielectric layer comprising a first gate dielectric layer on the shielding gate structure and a second gate dielectric layer on the first gate dielectric layer, the first gate dielectric layer being denser than the second gate dielectric layer, the gate dielectric layer being in a shape of two ends protruding from a middle part; and,

[0023] forming a control gate structure in the trench, the control gate structure comprising a control gate dielectric layer on the gate dielectric layer and a control gate electrode in the control gate dielectric layer.

[0024] Optionally, in the manufacturing method of the shielding gate trench transistor, forming the gate dielectric layer in the trench comprises:

[0025] forming a first dielectric material layer in the trench by using a first film forming process;

[0026] forming a second dielectric material layer on the first dielectric material layer by using a second film forming process, wherein the first dielectric material layer is denser than the second dielectric material layer; and,

[0027] etching the first dielectric material layer and the second dielectric material layer to form the inter-gate dielectric layer.

[0028] Optionally, in the method of manufacturing the shielded-gate trench transistor, after forming the first dielectric material layer in the trench by the first film-forming process, the method further comprises:

[0029] performing an annealing process on the first dielectric material layer.

[0030] Optionally, in the method of manufacturing the shielded-gate trench transistor, the first film-forming process is a high-density plasma process, and the second film-forming process is a chemical vapor deposition process.

[0031] Optionally, in the method of manufacturing the shielded-gate trench transistor, the first dielectric material layer and the second dielectric material layer are made of the same material.

[0032] Optionally, in the method of manufacturing the shielded-gate trench transistor, the method of manufacturing the shielded-gate trench transistor further comprises:

[0033] performing a first ion implantation process on the semiconductor substrate to form a well region in the semiconductor substrate on both sides of the trench;

[0034] performing a second ion implantation process on the well region to form a source region in the well region;

[0035] forming an interlayer dielectric layer on the semiconductor substrate, the interlayer dielectric layer covering the control gate structure; and,

[0036] forming a conductive layer on the semiconductor substrate, the conductive layer being connected to the source region.

[0037] Optionally, in the method of manufacturing the shielded-gate trench transistor, the first dielectric material layer covers the shielded gate structure and the sidewall exposed by the trench.

[0038] Optionally, in the method of manufacturing the shielded-gate trench transistor, the control gate dielectric layer is formed by a thermal oxidation process or a deposition process, and the control gate dielectric layer extends to cover the surface of the semiconductor substrate.

[0039] Optionally, in the method of manufacturing the shielded-gate trench transistor, the control gate electrode is made of polysilicon.

[0040] The inventors have found that in the prior art shield gate trench transistor, the surface of the gate dielectric layer is relatively flat, so that the bottom of the control gate electrode is relatively sharp and the control gate dielectric layer sandwiched between the bottom of the control gate electrode and the trench sidewall is relatively thin, which results in easy breakdown of the gate dielectric layer and seriously affects the performance of the device.

[0041] Therefore, in the shield gate trench transistor and the manufacturing method thereof provided by the present application, the gate dielectric layer comprises a first gate dielectric layer on the shield gate structure and a second gate dielectric layer on the first gate dielectric layer, the first gate dielectric layer is denser than the second gate dielectric layer, and the gate dielectric layer is in a shape of two ends protruding from the middle, so that the bottom of the control gate electrode is relatively smooth and the control gate dielectric layer sandwiched between the bottom of the control gate electrode and the trench sidewall is relatively thick, which avoids the breakdown of the gate dielectric layer and improves the performance of the device. BRIEF DESCRIPTION OF DRAWINGS

[0042] FIGS. 1 to 14 are structural schematic diagrams of devices formed by the manufacturing method of the shield gate trench transistor according to the embodiments of the present application.

[0043] In the drawings, the reference signs are explained as follows: 100-semiconductor substrate; 101-silicon substrate; 102-silicon epitaxial layer; 110-mask layer; 120-trench; 130-shield gate structure; 131-shield gate dielectric layer; 131a-shield gate dielectric material layer; 132-shield gate electrode; 140-gate dielectric layer; 141-first gate dielectric layer; 141a-first dielectric material layer; 142-second gate dielectric layer; 142a-second dielectric material layer; 150-control gate structure; 151-control gate dielectric layer; 152-control gate electrode; 160-well region; 170-source region; 180-interlayer dielectric layer; 190-conductive layer. DETAILED DESCRIPTION

[0044] The shield gate trench transistor and the manufacturing method thereof provided by the present application are further described in detail below in combination with the drawings and specific embodiments. The advantages and features of the present application will be more apparent according to the following description. It should be noted that the drawings are very simplified and use non-precise proportions, which are only used to facilitate and clarify the purpose of assisting the description of the embodiments of the present application.

[0045] The terms used in the present application are merely for the purpose of describing particular embodiments and are not intended to limit the present application. Unless otherwise defined in the application file, technical terms or scientific terms used in the present application should be understood as the common meanings to those skilled in the art. The terms "first", "second" and similar terms used in the description and the claims of the present application do not denote any order, quantity or importance, but are used to distinguish different components. Similarly, the terms "one" or "a" or similar terms do not denote a quantity restriction, but mean at least one. "Plural" or "several" means two or more. Unless otherwise indicated, "upper", "lower", and similar terms are used for convenience only and are not intended to be limiting as to a particular position or spatial orientation. "Include" or "comprise" and similar terms are meant to be inclusive and not exclusive, and do not exclude other elements or components. "Connected" or "coupled" and similar terms are not limited to physical or mechanical connections or linkages, and can include electrical connections or linkages, whether direct or indirect. The singular forms "a", "an", and "the" used in the present application and the appended claims are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "and / or", as used herein, refer to and encompass any or all possible combinations of one or more of the associated listed items.

[0046] The core idea of the present application is to provide a shielded gate trench transistor and a manufacturing method thereof, wherein the gate dielectric layer comprises a first gate dielectric layer on the shielded gate structure and a second gate dielectric layer on the first gate dielectric layer, the first gate dielectric layer is denser than the second gate dielectric layer, and the gate dielectric layer is in a shape of two ends protruding from the middle, thereby making the bottom of the control gate electrode smoother on both sides and the control gate dielectric layer held between the control gate electrode and the trench sidewall thicker, so that the gate dielectric layer breakdown can be avoided and the device performance is improved.

[0047] Specifically, refer to FIGS. 1 to 14, which are structural schematic diagrams of devices formed by the manufacturing method of the shielded gate trench transistor according to the embodiments of the present application.

[0048] As shown in FIG. 1, a semiconductor substrate 100 is provided, in the embodiments of the present application, the semiconductor substrate 100 comprises a silicon substrate 101 and a silicon epitaxial layer 102 formed on the silicon substrate 101; in other embodiments of the present application, the semiconductor substrate 100 can also comprise other structures and / or materials, for example, the semiconductor substrate 100 can be a silicon carbide substrate, etc.

[0049] Then, as shown in FIG. 2, a mask layer 110 is formed on the semiconductor substrate 100. In the embodiment of the present application, the mask layer 110 is a hard mask layer of ONO structure (oxide layer-nitride layer-oxide layer); in other embodiments of the present application, the mask layer 110 can also be of other materials. Then, the mask layer 110 is patterned to form an opening (not shown in the figure) exposing part of the semiconductor substrate 100 in the mask layer 110.

[0050] Referring to FIG. 3, in the embodiment of the present application, the semiconductor substrate 100 is etched with the mask layer 110 as a mask to form a trench 120 in the semiconductor substrate 100. Specifically, the trench 120 can be formed by dry or wet etching process.

[0051] Then, as shown in FIGS. 4-6, a shield gate structure 130 is formed in the trench 120, which includes a shield gate dielectric layer 131 and a shield gate electrode 132 in the shield gate dielectric layer 131.

[0052] Specifically, as shown in FIG. 4, in the embodiment of the present application, a shield gate dielectric material layer 131a is first formed in the trench 120, which covers the surface of the trench 120 and also extends to cover the surface of the mask layer 110. Specifically, the shield gate dielectric material layer 131a can be formed by deposition process or oxidation process.

[0053] Then, as shown in FIG. 5, a shield gate electrode 132 is formed in the shield gate dielectric material layer 131a, and in the embodiment of the present application, the shield gate electrode 132 is of polysilicon. Specifically, a shield gate electrode material layer (not shown in the figure) can be first deposited in the shield gate dielectric material layer 131a; then, the shield gate electrode material layer is etched to form the shield gate electrode 132.

[0054] As shown in FIG. 6, then, part of the shield gate dielectric material layer 131a is removed to form a shield gate dielectric layer 131, thereby forming the shield gate structure 130. Specifically, the shield gate dielectric material layer 131a exposed by the shield gate electrode 132 can be removed by etching process to form the shield gate dielectric layer 131.

[0055] Referring to FIGS. 7-9, in the embodiment of the present application, then, an inter-gate dielectric layer 140 is formed in the trench 120, the inter-gate dielectric layer 140 includes a first inter-gate dielectric layer 141 on the shielding gate structure 130 and a second inter-gate dielectric layer 142 on the first inter-gate dielectric layer 141, the first inter-gate dielectric layer 141 is denser than the second inter-gate dielectric layer 142, and the inter-gate dielectric layer 140 is in a shape of two ends protruding from the middle.

[0056] Specifically, as shown in FIG. 7, a first dielectric material layer 141a is formed in the trench 120 by a first film forming process. The first dielectric material layer 141a covers the shielding gate structure 130 and the sidewall of the trench 120 exposed, and further extends to cover the mask layer 110.

[0057] In the embodiment of the present application, the first film forming process is a high-density plasma process to form the high-density first dielectric material layer 141a. In other embodiments of the present application, the first film forming process can also be other film forming processes, here, only the first dielectric material layer 141a formed is denser than the second dielectric material layer / second inter-gate dielectric layer formed subsequently. Further, an annealing process is performed on the first dielectric material layer 141a to improve the density of the first dielectric material layer 141a.

[0058] Then, as shown in FIG. 8, a second dielectric material layer 142a is formed on the first dielectric material layer 141a by a second film forming process, and the first dielectric material layer 141a is denser than the second dielectric material layer 142a. In the embodiment of the present application, the second film forming process is a chemical vapor deposition process, and in other embodiments of the present application, the second film forming process can also be other film forming processes, here, only the first dielectric material layer 141a is denser than the second dielectric material layer 142a. Further, in the embodiment of the present application, the density of the first dielectric material layer 141a is improved by performing an annealing process on the first dielectric material layer 141a, thus, the second film forming process can also be the same as the first film forming process. In the embodiment of the present application, the first dielectric material layer 141a and the second dielectric material layer 142a are of the same material, both of which are silicon oxide, and in other embodiments of the present application, the materials of the two can be different.

[0059] As shown in Figure 9, then, the first dielectric material layer 141a and the second dielectric material layer 142a are etched to form a first inter-gate dielectric layer 141 and a second inter-gate dielectric layer 142 on the first inter-gate dielectric layer 141, thereby obtaining the inter-gate dielectric layer 140. In the embodiment of the present application, the mask layer 110 is also removed to expose the surface of the semiconductor substrate 100.

[0060] Here, since the first dielectric material layer 141a is denser than the second dielectric material layer 142a, when the first dielectric material layer 141a and the second dielectric material layer 142a are etched, the second dielectric material layer 142a is easier to be etched than the first dielectric material layer 141a, so that the inter-gate dielectric layer 140 formed is in a shape of two ends protruding from the middle. Further, the surface of the inter-gate dielectric layer 140 is in a circular arc shape.

[0061] As shown in Figure 10, in the embodiment of the present application, then, a control gate structure 150 is formed in the trench 120, the control gate structure 150 including a control gate dielectric layer 151 on the inter-gate dielectric layer 140 and a control gate electrode 152 in the control gate dielectric layer 151.

[0062] Specifically, the control gate dielectric layer 151 can be first formed in the trench 120, for example, by a thermal oxidation process or a deposition process, and the control gate dielectric layer 151 can extend to cover the surface of the semiconductor substrate 100; then, the control gate electrode 152 is filled in the trench 120, where the material of the control gate electrode 152 is polysilicon.

[0063] Please refer to Figure 11, in the embodiment of the present application, then, a first ion implantation process is performed on the semiconductor substrate 100 to form a well region 160 in the semiconductor substrate 100 on both sides of the trench 120. Specifically, a P-type ion implantation process is performed on the semiconductor substrate 100 to form a P-well in the semiconductor substrate 100 on both sides of the trench 120.

[0064] As shown in Figure 12, a second ion implantation process is performed on the well region 160 to form a source region 170 in the well region 160. Specifically, an N-type ion implantation process is performed on the well region 160 to form an N-type source region 170 in the well region 160.

[0065] In the embodiment of the present application, then, as shown in Figure 13, an interlayer dielectric layer 180 is formed on the semiconductor substrate 100, and the interlayer dielectric layer 180 covers the control gate structure 150.

[0066] Then, as shown in Fig. 14, a conductive layer 190 is formed on the semiconductor substrate 100, and the conductive layer 190 is connected with the source region 170. Specifically, an etching process can be performed on the interlayer dielectric layer 180 to form a conductive socket (not shown in the figure) which exposes the source region 170, and the conductive socket can extend into the well region 160; then, the conductive layer 190 is filled in the conductive socket, and the material of the conductive layer 190 can be metal, and further, the conductive layer 190 can also cover the interlayer dielectric layer 180.

[0067] In the embodiments of the present application, a shielded gate trench transistor is obtained correspondingly, please continue to refer to Fig. 14, the shielded gate trench transistor comprises: a semiconductor substrate 100, the semiconductor substrate 100 is formed with a trench 120; a shielded gate structure 130 located in the trench 120, the shielded gate structure 130 comprises a shielded gate dielectric layer 131 and a shielded gate electrode 132 located in the shielded gate dielectric layer 131; a gate dielectric layer 140 located in the trench 120, the gate dielectric layer 140 comprises a first gate dielectric layer 141 located on the shielded gate structure 130 and a second gate dielectric layer 142 located on the first gate dielectric layer 141, the first gate dielectric layer 141 is denser than the second gate dielectric layer 142, and the gate dielectric layer 140 is in a shape of two ends protruding from the middle; and a control gate structure 150 located in the trench 120, the control gate structure 150 comprises a control gate dielectric layer 151 located on the gate dielectric layer 140 and a control gate electrode 152 located in the control gate dielectric layer 151.

[0068] In the shielded gate trench transistor and the manufacturing method thereof provided by the present application, the gate dielectric layer 140 comprises a first gate dielectric layer 141 located on the shielded gate structure 130 and a second gate dielectric layer 142 located on the first gate dielectric layer 141, the first gate dielectric layer 141 is denser than the second gate dielectric layer 142, and the gate dielectric layer 140 is in a shape of two ends protruding from the middle, thereby making the bottom sides of the control gate electrode 152 more smooth and the control gate dielectric layer 151 clamped between the bottom sides of the control gate electrode 152 and the sidewalls of the trench 120 thicker, so that the gate dielectric layer breakdown can be avoided, and the device performance is improved.

[0069] Further, the surface of the gate dielectric layer 140 is in a circular arc shape. The materials of the first gate dielectric layer 141 and the second gate dielectric layer 142 can be the same or different, and the forming processes thereof can also be the same or different. Optionally, the materials of the first gate dielectric layer 141 and the second gate dielectric layer 142 are the same, and both are oxide layers, and the forming processes thereof are different, so that the first gate dielectric layer 141 is denser than the second gate dielectric layer 142.

[0070] In the embodiments of the present application, the shielded gate trench transistor further comprises: a well region 160 in the semiconductor substrate 100 on both sides of the trench 120; a source region 170 in the well region 160; an interlayer dielectric layer 180 on the semiconductor substrate 100 and covering the control gate structure 150; and a conductive layer 190 on the semiconductor substrate 100 and connected with the source region 170.

[0071] In this application, the mention of "one embodiment", "some embodiments" means that the features, structures or characteristics described in connection with the embodiment are contained in at least one embodiment, at least some embodiments of the present application. Therefore, the appearance of the phrase "in one embodiment", "in some embodiments" in various places in the present application does not necessarily refer to the same or some embodiments. In addition, in one or more embodiments, the features, structures or characteristics can be combined in any suitable combination and / or sub-combination.

[0072] Although some specific embodiments of the present application have been described in detail through examples, those skilled in the art should understand that the above examples are only for illustration, not for limiting the scope of the present application. The embodiments of the present application can be combined in any combination without departing from the spirit and scope of the present application. Those skilled in the art should also understand that various modifications can be made to the embodiments without departing from the scope and spirit of the present application. The scope of the present application is defined by the appended claims.

Claims

1. A shielded gate trench transistor, characterized by, The shield gate trench transistor comprises: a semiconductor substrate, wherein a trench is formed in the semiconductor substrate; a shield gate structure in the trench, the shield gate structure comprising a shield gate dielectric layer and a shield gate electrode in the shield gate dielectric layer; a gate dielectric layer in the trench, the gate dielectric layer comprising a first gate dielectric layer on the shield gate structure and a second gate dielectric layer on the first gate dielectric layer, the first gate dielectric layer being denser than the second gate dielectric layer, the gate dielectric layer being in a shape of two ends protruding from a middle part; and a control gate structure in the trench, the control gate structure comprising a control gate dielectric layer on the gate dielectric layer and a control gate electrode in the control gate dielectric layer.

2. The shielded gate trench transistor of claim 1, wherein, A surface of the gate dielectric layer is in a circular arc shape.

3. The shielded gate trench transistor of claim 1, wherein, The first gate dielectric layer and the second gate dielectric layer are made of the same material but formed by different processes.

4. The shielded gate trench transistor of any one of claims 1 to 3, wherein, The shield gate trench transistor further comprises: a well region in the semiconductor substrate on both sides of the trench; a source region in the well region; an interlayer dielectric layer on the semiconductor substrate and covering the control gate structure; and a conductive layer on the semiconductor substrate and connected to the source region.

5. A manufacturing method of a shielded gate trench transistor, characterized by, The method for manufacturing the shield gate trench transistor comprises: providing a semiconductor substrate; forming a trench in the semiconductor substrate; forming a shield gate structure in the trench, the shield gate structure comprising a shield gate dielectric layer and a shield gate electrode in the shield gate dielectric layer; forming a gate dielectric layer in the trench, the gate dielectric layer comprising a first gate dielectric layer on the shield gate structure and a second gate dielectric layer on the first gate dielectric layer, the first gate dielectric layer being denser than the second gate dielectric layer, the gate dielectric layer being in a shape of two ends protruding from a middle part; and forming a control gate structure in the trench, the control gate structure comprising a control gate dielectric layer on the gate dielectric layer and a control gate electrode in the control gate dielectric layer.

6. The manufacturing method of a shielded gate trench transistor according to claim 5, wherein The forming of the gate dielectric layer in the trench comprises: forming a first dielectric material layer in the trench by using a first film forming process; forming a second dielectric material layer on the first dielectric material layer by using a second film forming process, wherein the first dielectric material layer is denser than the second dielectric material layer; and etching the first dielectric material layer and the second dielectric material layer to form the gate dielectric layer.

7. The manufacturing method of a shielded gate trench transistor according to claim 6, wherein After the forming of the first dielectric material layer in the trench by using the first film forming process, the forming of the gate dielectric layer in the trench further comprises: performing an annealing process on the first dielectric material layer.

8. The manufacturing method of a shielded gate trench transistor according to claim 6, wherein The first film forming process is a high-density plasma process, and the second film forming process is a chemical vapor deposition process.

9. The manufacturing method of a shielded gate trench transistor according to claim 6, wherein The first dielectric material layer and the second dielectric material layer are made of the same material.

10. The manufacturing method of the shielded gate trench transistor according to any one of claims 5 to 9, wherein The method for manufacturing the shield gate trench transistor further comprises: performing a first ion implantation process on the semiconductor substrate to form a well region in the semiconductor substrate on both sides of the trench; performing a second ion implantation process on the well region to form a source region in the well region; forming an interlayer dielectric layer on the semiconductor substrate, the interlayer dielectric layer covering the control gate structure; and forming a conductive layer on the semiconductor substrate, the conductive layer being connected with the source region.

11. The manufacturing method of a shielded gate trench transistor according to claim 6, wherein The first dielectric material layer covers the shielding gate structure and the sidewall exposed by the trench.

12. The manufacturing method of a shielded gate trench transistor according to claim 5, wherein The control gate dielectric layer is formed by a thermal oxidation process or a deposition process, and the control gate dielectric layer extends to cover the surface of the semiconductor substrate.

13. The manufacturing method of a shielded gate trench transistor according to claim 5, wherein The material of the control gate electrode is polysilicon.

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