Parallel poling of electro-optic devices

Abstract

A method includes providing a plurality of devices, each of the plurality of devices including one or more slot waveguides, a first contact pad, a second contact pad, and organic electro-optic (OEO) material provided within the one or more slot waveguides; forming a first temporary circuit element including a conductive material, the first temporary circuit element being coupled to the first contact pad of each of the plurality of devices; forming a second temporary circuit element including a conductive material, the second temporary circuit element being coupled to the second contact pad of each of the plurality of devices; applying a direct current (DC) voltage across each of the plurality of devices using the first and second temporary circuit elements to apply an electric poling field across the OEO material of each of the plurality of devices during a thermal cycle to effect electric field poling of the OEO material; and removing the first and second temporary circuit elements.

Description

PATENTAttorney Docket No.: 797AA0004PCPARALLEL POLING OF ELECTRO-OPTIC DEVICESCROSS-REFERENCES TO RELATED APPLICATIONS

[0001] The present invention claims priority to U.S. Provisional Application No. 63 / 682,491, filed August 13, 2024, which is incorporated by reference herein for all purposes.BACKGROUND

[0002] The present disclosure relates to systems and methods for parallel poling of organic electro-optic devices, and more particularly to techniques for simultaneously applying electric fields to multiple devices during fabrication using circuit elements.

[0003] The application of DC and low-frequency AC electric fields to organic materials during fabrication processes provides significant benefits to device performance and stability. In organic photovoltaics, organic light-emitting diodes (LEDs), and organic field-effect transistors (FETs), applying electric fields during annealing steps results in improved device characteristics. In organic electro-optic materials, dipole alignment represents a fundamental requirement for device operation and is achieved through the application of electric fields during fabrication in a process known as "poling."

[0004] Electric field poling of organic electro-optic materials has emerged as a significant bottleneck in the fabrication of hybrid organic electro-optic modulators for integrated photonics platforms. This process represents a substantial challenge for scaling such technologies to high-volume manufacturing environments. Existing poling techniques generally rely on die or wafer probers using multi-contact DC probes to make independent contact to every' modulator, requiring two contacts per device on a given die, and performing poling on isolated dies one at a time. Even when poling cycle times can be maintained at relatively short durations of approximately five minutes, this approach adds considerable time and cost to fabrication compared to wafer-level processes.

[0005] The physical limitations of probe cards impose additional constraints on both the number of devices that can be processed simultaneously and their relative positions, whether poling is performed at the die or wafer level. These limitations become particularly problematic when considering the scaling requirements for high-volume manufacturing of hybrid organic electro-optic devices on integrated photonics platforms.PATENTAttorney Docket No.: 797AA0004PCSUMMARY

[0006] Embodiments of the present disclosure relate to systems and methods for parallel poling of organic electro-optic devices, and more particularly to techniques for simultaneously applying electric fields to multiple devices during fabrication using circuit elements.

[0007] In an embodiment, a method includes providing a plurality of devices, each of the plurality of devices including one or more slot waveguides, a first contact pad, a second contact pad, and organic electro-optic (OEO) material provided within the one or more slot waveguides; forming a first temporary circuit element including a conductive material, the first temporary circuit element being coupled to the first contact pad of each of the plurality of devices; forming a second temporary circuit element including a conductive material, the second temporary circuit element being coupled to the second contact pad of each of the plurality of devices; applying a direct current (DC) voltage across each of the plurality7of devices using the first and second temporary7circuit elements to apply an electric poling field across the OEO material of each of the plurality of devices during a thermal cycle to effect electric field poling of the OEO material; and removing the first and second temporary circuit elements.

[0008] In an embodiment, the plurality7of the devices are provided on a wafer. The first temporary circuit element and the second temporary circuit element are formed by an ink-jet printing process or an aerosol-jet printing process.

[0009] In an embodiment, the first temporary circuit element and the second temporary circuit element are removed by a washing process that uses water, an organic solvent, or both.

[0010] In an embodiment, the first temporary circuit element and the second temporary circuit element are removed using a liquid-phase etchant.

[0011] In an embodiment, the first temporary circuit element and the second temporary circuit element are removed using a vapor etchant, a plasma etchant, or both.

[0012] In an embodiment, the first temporary circuit element and the second temporary circuit element are removed using chemical mechanical planarization (CMP).

[0013] In an embodiment, the DC voltage is greater than 10V.PATENTAttorney Docket No.: 797AA0004PC

[0014] In an embodiment, the plurality of devices includes at least one of a polymer modulator, a silicon-organic hybrid modulator, a plasmonic-organic hybrid modulator, a silicon nitride-organic hybrid modulator, a modulator containing a semiconductor compound, a Mach-Zehnder modulator, a ring resonator modulator (RRM), a modulator in a racetrack resonator, a modulator in a plasmonic mixer, an IQ modulator, or a combination thereof.

[0015] In an embodiment, the semiconductor compound is a III-V semiconductor compound including InP, GaAs, or GaN, or a combination thereof.

[0016] In an embodiment, the OEO material includes chromophores exhibiting hyperpolarizability'.

[0017] In another embodiment, a poling circuit includes a first temporary circuit element including a conductive material; a second temporary’ circuit element including the conductive material; and a plurality of devices disposed on a substrate, each of the plurality of devices including: one or more slot waveguides, a first contact pad coupled to the first temporary' circuit element, a second contact pad coupled to the second temporary' circuit element, and organic electro-optic (OEO) material provided within the one or more slot waveguides; and wherein the first and second temporary circuit elements are configured to provide a direct current (DC) electric voltage across each device of the plurality devices to apply an electric poling field across the OEO material associated with each device of the plurality of devices during a thermal cycle to effect electric field poling of the OEO material.

[0018] In an embodiment, the conductive material is formed by one of ink-jet or aerosol-jet printing process.

[0019] In an embodiment, the conductive material comprises a conducting polymer, the conductive material including poly(3,4-ethylenedioxide):poly(styrene sulfonate)PEDOT:PSS.

[0020] In an embodiment, the conductive material comprises gold, or silver nanoparticles, or transparent conducting oxide (TCO) nanoparticles.

[0021] In an embodiment, the conductive material includes material that can be removed using a washing process that uses water or an organic solvent, or both.

[0022] In an embodiment, the conductive material includes material that can be removed using a liquid- phase etchant, or that can be removed using one of a vapor etchant or a plasma etchant, or can be removed using chemical mechanical planarization (CMP).PATENTAttorney Docket No.: 797AA0004PC

[0023] In an embodiment, the plurality of device includes a polymer modulator, a siliconorganic hybrid modulator, a plasmonic-organic hybrid modulator, a silicon nitride-organic hybrid modulator, a modulator containing a semiconductor compound, a Mach-Zehnder modulator, a ring resonator modulator (RRM), a modulator in a racetrack resonator, a modulator in a plasmonic mixer, an IQ modulator, or a combination thereof.

[0024] In yet another embodiment, a poling system for organic electro-optic devices includes a substrate; a plurality of organic electro-optic devices disposed on the substrate, each device including a first contact pad, a second contact pad, at least one optical waveguide, and organic electro-optic material disposed within the optical waveguide; a first temporary circuit element including printed conductive material electrically connecting the first contact pad of each device in the plurality of devices; and a second temporary circuit element including printed conductive material electrically connecting the second contact pad of each device in the plurality of devices, wherein the first and second temporary' circuit elements are configured to enable simultaneous application of a poling voltage across the organic electro-optic material of each device in the plurality of devices during a thermal cycle to effect electric field poling of the OEO material. The substrate may be a wafer.BRIEF DESCRIPTION OF THE DRAWINGS

[0025] In the accompanying figures like reference numerals refer to identical or functionally similar elements throughout the separate views, together with the detailed description below, and are incorporated in and form part of the specification to further illustrate embodiments of concepts that include the claimed invention and explain various principles and advantages of those embodiments.

[0026] Figure 1 illustrates a photonic device assembly according to an embodiment.

[0027] Figure 2 illustrates a photonic device assembly with temporary' poling circuits when seen in a top plan view according to an embodiment.

[0028] Figure 3 illustrates a photonic device assembly with temporary poling circuits after electric field poling has been performed according to an embodiment.

[0029] Figure 4 illustrates a photonic integrated circuit after removal of temporary poling circuits according to an embodiment.PATENTAttorney Docket No.: 797AA0004PCDETAILED DESCRIPTION

[0030] The present disclosure relates to photonic integrated circuits, and more specifically to systems and methods for parallel poling of organic electro-optic devices. The disclosed techniques include simultaneously applying electric fields to multiple devices during fabrication using circuit elements. The circuit elements may be temporary elements and may be formed using a printing process. This approach enables efficient, high-volume manufacturing in comparison to conventional single-device poling methods.

[0031] In an embodiment, organic electro-optic (OEO) devices include Silicon-Organic Hybrid (SOH) modulators. Plasmonic-Organic Hybrid (POH) modulators, Slot Waveguide EO modulators, and Photonic Crystal Organic EO modulators.

[0032] Figure 1 illustrates a photonic device assembly 100 according to an embodiment. The photonic assembly 100 is in a state prior to electric field poling and is a precursor to a photonic integrated circuit. The assembly includes a plurality of modulator 102 and a substrate 104. In this initial configuration, the organic electro-optic (OEO) material within each modulator 102 contains chromophores with randomly oriented dipole moments, resulting in a centrosymmetric arrangement that exhibits substantially no net electro-optic effect. In an embodiment, the substrate 104 may be a wafer, e.g., 300 mm wafer. In another embodiment, the substrate 104 may be a die.

[0033] Figure 2 illustrates a photonic device assembly 200 when seen in a top plan view according to an embodiment. The assembly 200 a plurality of modulators 202 including a slot waveguide 204 filled with OEO material 206. A first contact pad 208 positioned at a first side of the modulator, and a second contact pad 210 positioned at a second side of the modulator.

[0034] A first temporary' circuit element 212 and a second temporary' circuit element 214 electrically coupled to the plurality' of the modulators 202, where the first temporary circuit element 212 is coupled to the modulators 202 via the first contact pads 208 and the second temporary circuit element 214 is coupled to the modulators 202 via the second contact pads. The first and second temporary circuit elements 212 and 214 are configured to enable parallel poling of the plurality' of modulators 202.

[0035] In an embodiment, the first temporary circuit element 212 and second temporary circuit element 214 are electrically isolated from each other to form independent electrical pathways. The first temporary circuit element 212 is coupled to a voltage source andPATENTAttorney Docket No.: 797AA0004PC configured to apply a poling voltage Vdd. while the second temporary circuit element 214 is coupled to ground potential. This configuration enables simultaneous application of a direct current (DC) electric field across the OEO material in each of the plurality of modulators 202 through an electrical connection to each temporary circuit element, rather than requiring individual electrical connections to each modulator. The temporary circuit elements 212. 214 may be formed using conductive materials such as PEDOTPSS, silver nanoparticle ink, gold, transparent conducting oxide nanoparticles, or other suitable conductive materials deposited by printing processes including inkjet printing or aerosol-jet printing.

[0036] Figure 3 illustrates a photonic device assembly 300 after electric field poling has been performed according to an embodiment. The assembly 300 (or photonic integrated circuit) includes a plurality of modulators 302, each modulator having altered OEO material 304 with aligned dipole moments.

[0037] In an embodiment, during the poling process, the OEO material is heated to above its glass transition temperature while the poling voltage Vdd is applied between a first temporary circuit element 306 and a grounded second temporary circuit element 308. The applied electric field causes the randomly oriented chromophore dipoles within the OEO material to reorient and align in a preferred direction corresponding to the applied field direction. The photonic integrated circuit 300 is then cooled to below the glass transition temperature while maintaining the applied electric field, thereby locking the induced dipole alignment into place and creating a non-centrosymmetric arrangement of chromophores. This non-centrosymmetric alignment enables the OEO material to exhibit a strong electro-optic effect via the Pockels effect, making each modulator 302 functional for high-speed electrooptic modulation. The aligned dipole configuration remains stable after the electric field is removed, providing permanent electro-optic functionality to each modulator 302.

[0038] Figure 4 illustrates a photonic integrated circuit 400 according to an embodiment. The first temporary circuit element and second temporary circuit element (not shown) have been removed after the poling. The circuit 400 includes a plurality of poled modulators 402 on the substrate 404. The temporary circuit elements are removed using methods appropriate for the specific conductive material employed, such as water washing for PEDOT:PSS materials, water and isopropanol washing, chemical mechanical planarization for silver-based materials, aqueous etchants for gold materials, or vapor phase etching techniques. The removal process is selected to effectively eliminate the temporary circuit elements whilePATENTAttorney Docket No.: 797AA0004PC preserving the integrity of the OEO material and the poled dipole alignment achieved during the poling process.

[0039] The resulting photonic integrated circuit 400, as shown in figure 4, comprises a plurality of functional electro-optic modulators 402 with aligned dipole moments in their OEO material 406. Each modulator 102 may be used in connection with applications such as optical communications. LiDAR systems, or optical computing platforms.

[0040] Embodiments of the present disclosure enable arbitrary numbers and positions of devices to be poled simultaneously whether at the die or wafer level. Such techniques can be used to enable high-volume manufacturing of hybrid organic electro-optic devices on integrated photonics platforms in a fast and cost-efficient manner. Further, the described poling can be used in other applications where such poling is needed or desired.

[0041] Organic electro-optic (OEO) materials, when integrated into hybrid device architectures such as silicon-organic hybrid (SOH) and plasmonic organic hybrid (POH) devices, enable exceptional electro-optic modulation performance. These materials achieve substantial electro-optic modulation efficiencies with VTIL values of 0.5 Vmm or less, electro-optic modulation bandwidths exceeding 500+ GHz. and electro-optic modulation energy efficiencies down to femtojoule per bit levels. These properties result from their very large Pockels Effect coefficients ( q reaching up to 1100 pm / V and the unique electronic displacement mechanism underlying their Pockels Effect. These characteristics make hybrid organic electro-optic modulators in integrated photonics platforms particularly attractive for numerous applications including datacom, millimeter-wave and microwave photonics, quantum computing / networking, and hybrid electronic-photonic computing for artificial intelligence and machine learning processing.

[0042] The Pockels Effect represents a second-order nonlinear process, arising from the x(2)nonlinearity, that produces a linear change in the refractive index of a material in response to an applied electric field. For a material to possess a non-zero / J2’. the material will exhibit non-centrosymmetry. Unlike inorganic electro-optic materials, which derive their “ / r2)nonlinearity from acentric crystal lattices and atomic distortions therein, OEO materials derive their / (2)nonlinearity from organic nonlinear optical chromophores (dye molecules) which exhibit microscopic second order nonlinearity called hyperpolarizability (b).PATENTAttorney Docket No.: 797AA0004PC

[0043] Chromophores generally consist of electron-rich donor moieties, connected via n- conjugated bridges to electron-poor acceptor moieties, creating an anharmonic potential energy well for electrons which gives rise to the hyperpolarizability. These chromophores are inherently highly dipolar in nature, with dipole moments reaching 30 Debye or greater. These chromophores can be doped into inert polymer hosts, covalently attached to polymers via side chains, or possess sufficient side-chains to enable formation of neat organic glasses.

[0044] To achieve noncentrosymmetric alignment of the chromophores, the material is heated to the glass transition temperature (Tg), where local molecular motion becomes possible. Under such conditions and with the application of a large electric field (-100 V / pm). the dipoles reorient in response to the field. The material is then cooled back down under the field to well below (typically at least 20 °C below) the Tgto lock the induced order into place before the field is removed. The dipole reorientation in response to the applied, large electric field is due to the strong dipole moments of the chromophores which thermodynamically favor centrosymmetric packing due to dipole-dipole interactions. This process, called electric field poling, constitutes one of the steps in making OEO-based devices. It is also one of the challenges for high-volume manufacturing (HVM) of such devices, due in part to the time-consuming nature of the process, as well as the added constraints it places on device design, layout, and processing.

[0045] In a conventional process, electric field poling is typically performed on a single modulator at a time, making this process unsuitable for high-volume manufacturing of OEO devices. Using DC multi-contact probes parallel poling of up to eight devices on a die simultaneously, using either a single source-measure unit (SMU) to supply a common voltage to all devices, or an eight-channel SMU to independently source voltage and measure current for all devices, has been demonstrated, but physical limitations in multi-contact probes place constraints on the number and layout of devices that can be physically addressed on a given die or wafer.

[0046] Embodiments of the present disclosure provide systems and methods for enabling simultaneous poling for nearly arbitrary numbers of devices on a die or w afer. In addition to enhancing the number of addressable devices, the embodiments of the present disclosure provide additional freedom in the layout of such devices, which may have benefits for the RF performance of such devices. An embodiment of the present disclosure may be implemented at the w afer level, for example, a system and a method that may be used in a wafer, where thePATENTAttorney Docket No.: 797AA0004PC system is capable of contacting over 300,000 devices on a 300 mm wafer. In another implementation, the system may be capable of making 500,000 contacts or 750,000 contacts or more.

[0047] Embodiments of the present disclosure provide systems and methods for enabling simultaneous poling, or other low-frequency electric field treatments of any numbers of devices at the die and wafer level by utilizing temporary circuit elements that can be formed with various geometries and subsequently removed after processing.[004S] The systems and methods include forming temporary circuit elements to enable parallel connection of devices on a die or wafer, performing poling and optional crosslinking, or other stabilization techniques on a plurality of devices coupled to the temporary circuit elements, and removing the temporary circuit elements to allow each device to operate independently, while minimizing RF losses or other undesirable parasitic electrical effects due to extraneous circuit elements.

[0049] In an embodiment, the temporary circuit elements (e.g., the first and second temporary circuits disclosed above in connection with figure 2) are fabricated by depositing conductive paths of materials such as poly(3,4-ethylenedioxide):poly(styrene sulfonate) [PEDOT:PSS], an organic semiconductor that can be formulated to achieve high conductivity. The printing process enables facile deposition of temporary' circuit elements connecting device contact pads on die or wafer with nearly arbitrary' geometries without requiring additional patterning steps.

[0050] In embodiments, temporary circuit elements are fabricated by depositing conductive paths using printing techniques.

[0051] The conductive material may comprise poly(3,4-ethylenedioxide):poly(styrene sulfonate) [PEDOT:PSS], an organic semiconductor that can be formulated to achieve high conductivities. Suitable formulations include aqueous dispersions of PEDOTPSS conductive polymer, such as the product sold under Clevios™ PH 1000. These formulations are largely aqueous-based, making them relatively benign from environmental and chemical compatibility standpoints.

[0052] The traces can be printed as heavily as required to achieve the necessary sheet resistance, as transparency of the material is not relevant for the described printing process. While PEDOTPSS material is typically used in applications where transparency is desired,PATENTAttorney Docket No.: 797AA0004PC such transparency requirements typically result in sheet resistance values that may be too high for use in conventional applications. However, for the poling process described herein, the primary role of the temporary circuit elements is to provide voltage, with minimal current carrying capacity ty pically in the picoampere to microampere range, so the sheet resistance of the conductive traces need not be particularly low. A sheet resistance of less than about 200 / cm2may be desirable for certain implementations.

[0053] The printing process enables facile deposition of temporary circuit elements connecting device contact pads on die or wafer with nearly arbitrary geometries, without requiring additional patterning steps. In embodiments, the linewidths of the temporary circuit elements may be equal to or greater than about 10 pm. In other embodiments, the linewidths may range from about 50 pm to about 100 pm.

[0054] In an embodiment, temporary circuit elements may be fabricated using inkjet printing, aerosol-jet printing, screen printing, or the like. The printing methods that may be used allow for direct, maskless patterning of conductive traces that connect first contact pads of multiple devices via a first temporary circuit element and second contact pads via a second temporary circuit element.

[0055] The printed temporary circuit elements can be formed using various conductive materials including poly(3,4-ethylenedioxide):poly(styrene sulfonate) [PEDOT:PSS], silver nanoparticle inks, gold nanoparticle inks, transparent conducting oxide nanoparticles, carbonbased inks, or other suitable conductive materials. The printing process parameters such as drop spacing, print speed, substrate temperature, and curing conditions can be optimized for each material system to achieve the desired sheet resistance and electrical performance for the poling application.

[0056] In an embodiment, the temporary' circuit elements can be fabricated using conventional photolithographic and physical vapor deposition techniques, such as sputtering or evaporation. Conductive materials such as aluminum, copper, or gold can be deposited with photolithographic patterning to form the temporary' circuit elements, and then removed using suitable liquid or vapor-phase etchants, or via CMP, after poling.

[0057] In another embodiment, temporary circuit elements are formed using selective electroplating techniques. A patterned mask layer, such as photoresist or a hard mask, is applied to define the areas where conductive material is to be deposited. A seed layer may bePATENTAttorney Docket No.: 797AA0004PC deposited prior to mask patterning to provide electrical continuity for the electroplating process. Conductive materials such as copper, nickel, or gold are then electroplated into the openings in the mask to form the temporary circuit traces. After poling, the temporary circuits can be removed using suitable liquid or vapor-phase etchants, or via CMP.

[0058] In another embodiment, temporary circuit elements are formed using conductive adhesives or pastes. Conductive adhesive materials containing metal particles, carbon fillers, or conductive polymers are applied in predetermined patterns using dispensing techniques such as syringe dispensing, pneumatic dispensing, or automated dispensing systems. After poling, the temporary' circuit elements could be removed using CMP.

[0059] In another embodiment, temporary circuit elements are fabricated using stencil printing techniques, including screen printing. A metal stencil or screen with openings corresponding to the desired circuit pattern is positioned over the wafer or die surface. A conductive material, including PEDOT:PSS, colloidal silver, or other conductive formulations, would be deposited through the stencil or screen to form the temporary circuit elements. After poling, the temporary circuit elements could be removed via washing with water and / or solvents, liquid or vapor-phase etching, or CMP.

[0060] In an embodiment, the temporary' circuit elements include a first temporary circuit element and a second temporary' circuit element, that are deposited to couple contact pads of multiple devices together. First contact pads of a plurality of devices on a die or wafer are coupled together via the first temporary circuit element, which forms a first conductive path in a first circuit. Similarly, second contact pads of the plurality of devices are interconnected together via the second temporary circuit element, which forms a second conductive path in a second circuit, such that the first and second circuits are isolated from each other.

[0061] The poling voltage can then be applied between the first and second circuits using a single DC probe for each circuit, while effectively applying the poling voltage across all devices simultaneously. This configuration dramatically reduces the complexity and time requirements compared to individual device poling.

[0062] The plurality' of devices that can be processed using the disclosed methods includes various ty pes of electro-optic modulators. These include polymer modulators, silicon-organic hybrid modulators, plasmonic-organic hybrid modulators, silicon nitride-organic hybrid modulators, and modulators containing semiconductor compounds. The devices may bePATENTAttorney Docket No.: 797AA0004PC configured as Mach-Zehnder modulators, ring resonator modulators (RRM), modulators in racetrack resonators, modulators in plasmonic mixers, IQ modulators, or combinations thereof. For semiconductor compound-containing devices, the semiconductor compound may be a III-V semiconductor compound including InP, GaAs, or GaN.

[0063] In embodiments, the first and second temporary circuits provide a DC voltage across each of the plurality of devices to apply an electric poling field across OEO material provided within one or more slot waveguides of each device. The poling voltage may be applied as a positive voltage to the first temporary' circuit element and a ground voltage to the second temporary' circuit element, though the polarity may be reversed. Alternatively, positive and negative voltages may be applied to the first and second temporary circuit elements respectively to establish the desired poling voltage across each device.

[0064] In an embodiment, for hybrid OEO devices, the designation of positive and negative terminals is generally arbitrary', as these devices typically do not have specific polarity requirements and poling can generally be applied in either direction across a given device. While phase shifters are typically two-terminal devices. Mach-Zehnder modulators (MZMs) are typically three-terminal ground-signal-ground (G-S-G) devices, where the poling voltage is applied between the two ground terminals. The described poling systems and methods can be adapted for such device configurations.

[0065] In implementations where it may not be desirable to create single positive and negative circuits, at the die or wafer level due to integrated circuit layout requirements, such as photonic integrated circuit (PIC) layout constraints, two or more separate positive circuits and two or more separate negative circuits can be constructed. Custom DC multi-contact probes can then be used to contact multiple independent poling circuits, each containing multiple devices.

[0066] This approach could result in separate poling circuits for portions of a wafer, or separate poling circuits for each die on a wafer, or multiple poling circuits on each die. With approximately 300,000 contacts possible from a 300 mm wafer prober, up to approximately 50-100 unique poling circuits are possible on a given die, each of which may have many individual devices.

[0067] Independent SMU channels may be used to address each of the poling circuits, to provide independent voltage supply to each circuit. Alternatively, some or all of the positivePATENTAttorney Docket No.: 797AA0004PC and negative circuits can be shorted together at the multi-contact probe pinout to use a common SMU for poling some or all the independent temporary circuits. The use of independent SMU channels for unique poling circuits enables the application of different poling voltages for different groups of devices, which is useful when multiple types of devices with different geometries are present on a die or wafer.

[0068] After deposition of the PEDOT:PSS temporary circuit elements of a poling circuit, a drying step is performed to remove or evaporate residual water and cosolvents. The poling process may then be performed on the plurality of devices of the poling circuit. The details of the poling and optional crosslinking process depend on the specific OEO material being used, and the systems and methods described herein can be adapted to perform such poling with alterations of parameters based on the OEO material being processed, while avoiding detrimental impacts to the performance of temporary poling circuitry.

[0069] After poling is complete, the PEDOT:PSS temporary circuit elements can be removed using various methods. Due to the aqueous nature of the PEDOT:PSS material used to construct the temporary circuit elements, water can be used to substantially remove the temporary circuit elements from the die or wafer. However, while PEDOT:PSS is generally formulated in aqueous solutions, it exists in the form of a suspension rather than a true solution, and a portion of the temporary PEDOT:PSS circuit elements may remain after water treatment.

[0070] The remaining PEDOTPSS material can be removed, if necessary, with a mild solvent that will not have significant detrimental effects on the OEO materials, wafer, or die, such as isopropanol (IP A). A single treatment using a combination of water and a solvent can be used to remove the PEDOT:PSS, such as a water:IPA blend. The treatment can be applied as either a wash or under mild sonication treatment that provides agitation to assist with removal of the PEDOTPSS temporary circuit elements from the die or wafer. OEO materials are generally resilient to the described water, solvent, and water-solvent treatments, so removal of the PEDOT:PSS using such methods is unlikely to damage, degrade, or otherwise adversely impact any exposed OEO material on the die or wafer.

[0071] In embodiments, the deposited OEO material can be protected to allow the use of stronger or more aggressive solvents for removal of the PEDOT:PSS temporary circuit elements, such as chloroform or N-methylpyrrolidone. The OEO material can be protectedPATENTAttorney Docket No.: 797AA0004PC via thin film encapsulation prior to deposition of the temporary circuit elements. With such thin film encapsulation, alternative methods for removal of the PEDOTPSS temporary circuit elements can be used, such as UV-ozone, oxygen plasma, or other vapor phase etching techniques. The use of aggressive species may attack, degrade, and substantially or entirely remove the PEDOTPSS temporary circuit elements. With the OEO materials protected by encapsulation or other suitable techniques, the use of such aggressive species will have little or no detrimental effects on the OEO material or device performance.

[0072] In alternative embodiments, the temporary' circuit elements can be fabricated by depositing conductive traces of silver. Silver ink products, some of which are based on colloidal silver, may be used to print or deposit the temporary circuit elements. The printing geometries applicable to PEDOTPSS inks are also applicable to the application of silver ink to form temporary circuit elements.

[0073] One difference between the use of PEDOTPSS and silver ink temporary circuit elements is that different removal techniques may be used after poling is complete. The use of water, solvent, solvent-water combinations, or aggressive species such as ozone or oxygen plasma treatments may not fully remove the silver traces from the die or wafer. While alternative vapor phase etch processes may be used to remove the temporary circuit elements, an alternative approach involves the use of chemical mechanical planarization (CMP). CMP can remove the silver traces through a combination of physical and chemical processes. When using CMP to remove silver traces, the OEO material can be protected with one or more hard thin-film encapsulation layers, such as oxides that would be removed at a slower rate than the silver traces during the CMP process.

[0074] In other embodiments, the temporary' circuit elements can be fabricated by printing conductive traces of nanoparticle inks. These conductive nanoparticle inks may include stabilized noble metal nanoparticles, transparent conducting oxide (TCO) nanoparticles, or other nanoparticles suitable for creating conductive traces to form temporary circuit elements. Some conductive nanoparticle inks have similar properties to colloidal silver ink products discussed above.

[0075] Some nanoparticle inks may be less optimized for forming conductive traces and may not achieve the low resistivity’ of traces formed using colloidal silver inks due to inefficient coupling between nanoparticles. Additionally, some nanoparticle inks may havePATENTAttorney Docket No.: 797AA0004PC reliability' concerns, as the nanoparticles may not readily coalesce into dense solid networks that are resilient to chemical or mechanical disruption. As a result, temporary conductive traces formed using nanoparticle inks may have sheet resistance values greater than those of temporary' traces formed using colloidal silver inks.

[0076] However, this is unlikely to have detrimental impacts on the poling process, as the temporary traces formed using nanoparticle inks can support the moderate voltages less than 100 V and low currents approximately picoampere to microampere generally required for poling operations. Furthermore, the weak adhesion properties of nanoparticle inks can be exploited for facile removal of the temporary' circuit elements after poling.

[0077] The parameters of the removal processes and techniques can be based, at least partially, on the properties of the nanoparticle ink used to form the temporary conductive traces. Example removal processes include washing with water, IPA, other mild solvents, or combinations thereof to remove the nanoparticle ink from the die or wafer. Mild sonication or mechanical agitation can be used to assist with removal of the nanoparticle ink temporary' conductive traces. The conditions created by sonication or mechanical agitation are less aggressive than those created by CMP processes for removal of printed silver traces, which simplifies the overall poling process.

[0078] In alternative embodiments, the temporary' circuit elements can be fabricated from gold. The gold material may be deposited on a die or wafer including a plurality' of devices using physical vapor deposition (PVD), sputter coating, or similar methods. The deposited gold material may be patterned to form the temporary circuit elements. In some implementations, the OEO materials on the die or wafer can be optionally protected from photolithography patterning processes using thin film encapsulation prior to gold deposition and patterning. In other implementations, when the OEO materials have sufficient resistance to substantially prevent damage during photolithography patterning processes, it may be unnecessary to protect the OEO material.

[0079] After the poling process is complete, the temporary gold circuit elements can be removed with an aqueous gold etchant solution that is compatible with the OEO materials, such as an aqueous solution based on potassium iodide and iodine. Alternatively, other OEO compatible solutions can be used to remove the gold temporary circuit elements.PATENTAttorney Docket No.: 797AA0004PC

[0080] In some cases, it may be desirable to have special contact pads fabricated on the chip specifically for the DC probes to facilitate good electrical contact to the temporary electrical circuits. This can also simplify the poling process, as consistent and fixed locations on the dies or wafers can be established as the contact points for the applied DC probes, allowing the contact action to be more easily repeatable.

[0081] In the foregoing detailed description, illustrative embodiments have been described by way of example. It will be understood by those skilled in the art that various changes in form and detail may be made without departing from the scope of the present disclosure. The drawings and description are intended to be illustrative, not limiting. Like reference numerals refer to like elements throughout the specification.

[0082] Unless explicitly stated otherwise, the terms "comprise," "comprising," and similar terms are used in an inclusive sense, meaning "including but not limited to." As used herein, the terms "connected," "coupled," and their variants refer to any direct or indirect connection or coupling between elements, which may be physical, logical, or a combination thereof.

[0083] The examples described herein are not intended to be exhaustive or to limit the disclosed subject matter to the precise forms described. Other implementations and variations will be apparent to those skilled in art. Steps or blocks described as occurring in a particular sequence may, in alternative implementations, be performed in a different order or in parallel. Numerical values and ranges provided are illustrative and may be varied in other embodiments.

[0084] The features and methods described herein may be applied to other systems, not necessarily limited to those explicitly described. Elements from different embodiments may be combined to form additional implementations.

[0085] Any patents, patent applications, and other references cited herein, including those listed in any accompanying documents, are incorporated by reference in their entirety. Aspects of the present technology may be adapted, as needed, in view of such references to provide further implementations.

[0086] The scope of the present disclosure is defined solely by the appended claims and their legal equivalents. Nothing in the foregoing description is intended to limit the scope of the claims, and the specific embodiments described are merely illustrative of selected forms of the invention.

Claims

PATENTAttorney Docket No.: 797AA0004PCWHAT IS CLAIMED IS:1 . A method comprising: providing a plurality of devices, each of the plurality of devices including one or more slot waveguides, a first contact pad, a second contact pad, and organic electro-optic (OEO) material provided within the one or more slot waveguides; forming a first temporary circuit element including a conductive material, the first temporary circuit element being coupled to the first contact pad of each of the plurality of devices; forming a second temporary circuit element including a conductive material, the second temporary circuit element being coupled to the second contact pad of each of the plurality of devices; applying a direct current (DC) voltage across each of the plurality of devices using the first and second temporary circuit elements to apply an electric poling field across the OEO material of each of the plurality of devices during a thermal cycle to effect electric field poling of the OEO material; and removing the first and second temporary circuit elements.

2. The method of claim 1. wherein the plurality of the devices are provided on a wafer.

3. The method of claim 1, wherein the first temporary circuit element and the second temporary circuit element are formed by an ink-jet printing process or an aerosol-jet printing process.

4. The method of claim 1, wherein the first temporary circuit element and the second temporary circuit element are removed by a washing process that uses water, an organic solvent, or both.

5. The method of claim 1, wherein the first temporary circuit element and the second temporary' circuit element are removed using a liquid-phase etchant.PATENTAttorney Docket No.: 797AA0004PC6. The method of claim 1. wherein the first temporary circuit element and the second temporary circuit element are removed using a vapor etchant, a plasma etchant, or both.

7. The method of claim 1. wherein the first temporary circuit element and the second temporary circuit element are removed using chemical mechanical planarization (CMP).

8. The method of claim 1. wherein the DC voltage is greater than 10V.

9. The method of claim 1, wherein the plurality of devices includes at least one of a polymer modulator, a silicon-organic hybrid modulator, a plasmonic-organic hybrid modulator, a silicon nitride-organic hybrid modulator, a modulator containing a semiconductor compound, a Mach-Zehnder modulator, a ring resonator modulator (RRM), a modulator in a racetrack resonator, a modulator in a plasmonic mixer, an IQ modulator, or a combination thereof.

10. The method of claim 8, wherein the semiconductor compound is III-V semiconductor compound including InP, GaAs, or GaN, or a combination thereof.

11. The method of claim 1, wherein the OEO material includes chromophores exhibiting hyperpolarizability7.

12. A poling circuit, comprising: a first temporary circuit element including a conductive material; a second temporary circuit element including the conductive material; and a plurality of devices disposed on a substrate, each of the plurality of devices including: one or more slot waveguides, a first contact pad coupled to the first temporary circuit element, a second contact pad coupled to the second temporary circuit element, and organic electro-optic (OEO) material provided within the one or more slot waveguides; andPATENTAttorney Docket No.: 797AA0004PC wherein the first and second temporary circuit elements are configured to provide a direct current (DC) electric voltage across each device of the plurality devices to apply an electric poling field across the OEO material associated with each device of the plurality of devices.

13. The circuit of claim 12. wherein the conductive material is formed by one of ink-jet or aerosol-jet printing process.

14. The circuit of claim 12, wherein the conductive material comprises a conducting polymer, the conductive material including poly (3,4- ethylenedioxide):poly(styrene sulfonate)PEDOT:PSS.

15. The circuit of claim 12, wherein the conductive material comprises gold, or silver nanoparticles, or transparent conducting oxide (TCO) nanoparticles.

16. The circuit of claim 12, wherein the conductive material includes material that can be removed using a washing process that uses water or an organic solvent, or both.

17. The circuit of claim 12, wherein the conductive material includes material that can be removed using a liquid- phase etchant, or that can be removed using one of a vapor etchant or a plasma etchant, or can be removed using chemical mechanical planarization (CMP).

18. The circuit of claim 12, wherein the plurality’ of device includes a polymer modulator, a silicon-organic hybrid modulator, a plasmonic-organic hybrid modulator, a silicon nitride-organic hybrid modulator, a modulator containing a semiconductor compound, a Mach-Zehnder modulator, a ring resonator modulator (RRM), a modulator in a racetrack resonator, a modulator in a plasmonic mixer, an IQ modulator, or a combination thereof.

19. A poling system for organic electro-optic devices, the system comprising: a substrate; a plurality of organic electro-optic devices disposed on the substrate, each device including a first contact pad, a second contact pad, at least one optical waveguide, and organic electro-optic material disposed within or around the optical waveguide; a first temporary circuit element including printed conductive material electrically connecting the first contact pad of each device in the plurality' of devices; andPATENTAttorney Docket No.: 797AA0004PC a second temporary circuit element including printed conductive material electrically connecting the second contact pad of each device in the plurality of devices, wherein the first and second temporary' circuit elements are configured to enable simultaneous application of a poling voltage across the organic electro-optic material of each device in the plurality of devices during a thermal cycle to effect electric field poling of the OEO material.

20. The poling system of claim 19, wherein the substrate is a wafer.

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